CY_BLE_DEFAULT_RCB_CTRL_FREQ (reference) in projects: hal_infineon-3.5.0

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Searched refs:CY_BLE_DEFAULT_RCB_CTRL_FREQ (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
D	cy_ble_clk.c	`101 #define CY_BLE_DEFAULT_RCB_CTRL_FREQ (4000000UL) /* Default RCB clock is 4 … macro 309 if(periClkFreqHz > CY_BLE_DEFAULT_RCB_CTRL_FREQ) in Cy_BLE_EcoConfigure() 311 rcbDivider = (periClkFreqHz / CY_BLE_DEFAULT_RCB_CTRL_FREQ) - 1U; in Cy_BLE_EcoConfigure()`
/hal_infineon-3.5.0/bless/
D	cy_ble_clk.c	`101 #define CY_BLE_DEFAULT_RCB_CTRL_FREQ (4000000UL) /* Default RCB clock is 4 … macro 309 if(periClkFreqHz > CY_BLE_DEFAULT_RCB_CTRL_FREQ) in Cy_BLE_EcoConfigure() 311 rcbDivider = (periClkFreqHz / CY_BLE_DEFAULT_RCB_CTRL_FREQ) - 1U; in Cy_BLE_EcoConfigure()`

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