CPUSS_TRIM_RAM_ULP (reference) in projects: hal_infineon-3.5.0

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/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
D	cy_syspm.c	`188 #define CPUSS_TRIM_RAM_ULP (0x00006012U) macro 2218 (CPUSS_TRIM_RAM_ULP & CPUSS_TRIM_RAM_CTL_RM_Msk); in SetReadMarginTrimUlp() 2278 (CPUSS_TRIM_RAM_ULP & CPUSS_TRIM_RAM_CTL_WA_Msk); in SetWriteAssistTrimUlp()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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Zephyr-Core-3.5.0
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