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Searched refs:CPUSS_TRIM_RAM_CTL_WC_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
Dcy_syspm.c222 #define CPUSS_TRIM_RAM_CTL_WC_MASK (0x3UL << 10U) macro
2327 uint32_t trimRamCheckVal = (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK); in IsVoltageChangePossible()
2338 CPUSS_TRIM_RAM_CTL &= ~CPUSS_TRIM_RAM_CTL_WC_MASK; in IsVoltageChangePossible()
2339 CPUSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & CPUSS_TRIM_RAM_CTL_WC_MASK); in IsVoltageChangePossible()
2341 retVal = (trimRamCheckVal != (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK)); in IsVoltageChangePossible()
Dcy_syspm_v2.c124 #define CPUSS_TRIM_RAM_CTL_WC_MASK (0x3UL << 10U) macro
2062 uint32_t trimRamCheckVal = (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK); in IsVoltageChangePossible()
2064 CPUSS_TRIM_RAM_CTL &= ~CPUSS_TRIM_RAM_CTL_WC_MASK; in IsVoltageChangePossible()
2065 CPUSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & CPUSS_TRIM_RAM_CTL_WC_MASK); in IsVoltageChangePossible()
2067 retVal = (trimRamCheckVal != (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK)); in IsVoltageChangePossible()