Searched refs:CPUSS_RAM2_CTL0 (Results 1 – 6 of 6) sorted by relevance
456 CPUSS_RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates); in Cy_SysLib_SetWaitStates()457 CPUSS_RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM2_CTL0, CPUSS_RAM2_CTL0_FAST_WS, 0UL); in Cy_SysLib_SetWaitStates()
27 #define CPUSS_RAM2_CTL0 0x402013a0 macro117 ldr r1, =CPUSS_RAM2_CTL0
35 CPUSS_RAM2_CTL0 EQU 0x402013a0 define120 LDR r1, =CPUSS_RAM2_CTL0
56 CPUSS_RAM2_CTL0 EQU 0x402013a0 define183 LDR r1, =CPUSS_RAM2_CTL0
431 #define CPUSS_RAM2_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_devi… macro
503 #define CPUSS_RAM2_CTL0 ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_CTL0)) macro
