Home
last modified time | relevance | path

Searched refs:CPUSS_MEM_CLOCK_CTL (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h451 #define CPUSS_MEM_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->MEM_CLOCK_CTL) macro
484 #define CPUSS_MEM_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->MEM_CLOCK_CTL) macro
/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
Dcy_sysclk_v2.c468 CY_REG32_CLR_SET(CPUSS_MEM_CLOCK_CTL, CPUSS_MEM_CLOCK_CTL_INT_DIV, divider); in Cy_SysClk_ClkMemSetDivider()
474 return ((uint8_t)_FLD2VAL(CPUSS_MEM_CLOCK_CTL_INT_DIV, CPUSS_MEM_CLOCK_CTL)); in Cy_SysClk_ClkMemGetDivider()