Searched refs:CPUSS_DW0_CH_NR (Results 1 – 12 of 12) sorted by relevance
43 #define _CYHAL_DMA_DW_NUM_CHANNELS (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)45 #define _CYHAL_DMA_DW_NUM_CHANNELS (CPUSS_DW0_CH_NR)53 #define CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ CPUSS_DW0_CH_NR147 …_cyhal_dma_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num… in _cyhal_dma_dw_set_obj()153 …_cyhal_dma_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num… in _cyhal_dma_dw_free_obj()159 return _cyhal_dma_dw_config_structs[block * CPUSS_DW0_CH_NR + channel]; in _cyhal_dma_dw_get_obj()173 #if (CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ != CPUSS_DW0_CH_NR) in _cyhal_dma_dw_get_block_from_irqn()175 …_t)(_CYHAL_DMA_GET_CPUSS_IRQN(0, CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ) + CPUSS_DW0_CH_NR - CYHAL_DMA_D… in _cyhal_dma_dw_get_block_from_irqn()204 #if (CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ != CPUSS_DW0_CH_NR) in _cyhal_dma_dw_get_channel_from_irqn()206 …_t)(_CYHAL_DMA_GET_CPUSS_IRQN(0, CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ) + CPUSS_DW0_CH_NR - CYHAL_DMA_D… in _cyhal_dma_dw_get_channel_from_irqn()[all …]
259 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)263 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)265 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR)272 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR)274 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)1188 CPUSS_DW0_CH_NR,
715 #define CPUSS_DW0_CH_NR 16u macro
718 #define CPUSS_DW0_CH_NR 16u macro
282 #define CY_DW0_CH_NR CPUSS_DW0_CH_NR
1753 #define CPUSS_DW0_CH_NR 16u macro
1447 #define CPUSS_DW0_CH_NR 29u macro
1413 #define CPUSS_DW0_CH_NR 30u macro
1922 #define CPUSS_DW0_CH_NR 29u macro
2128 #define CPUSS_DW0_CH_NR 100u macro
2710 #define CPUSS_DW0_CH_NR 143u macro
1027 #define CY_DW0_CH_NR CPUSS_DW0_CH_NR
