1 /***************************************************************************//** 2 * \file cyip_cpuss.h 3 * 4 * \brief 5 * CPUSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CPUSS_H_ 28 #define _CYIP_CPUSS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CPUSS 34 *******************************************************************************/ 35 36 #define CPUSS_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief CPU subsystem (CPUSS) (CPUSS) 40 */ 41 typedef struct { 42 __IOM uint32_t CM0_CTL; /*!< 0x00000000 CM0+ control */ 43 __IM uint32_t RESERVED; 44 __IM uint32_t CM0_STATUS; /*!< 0x00000008 CM0+ status */ 45 __IM uint32_t RESERVED1; 46 __IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00000010 CM0+ clock control */ 47 __IM uint32_t RESERVED2[3]; 48 __IOM uint32_t CM0_INT_CTL0; /*!< 0x00000020 CM0+ interrupt control 0 */ 49 __IOM uint32_t CM0_INT_CTL1; /*!< 0x00000024 CM0+ interrupt control 1 */ 50 __IOM uint32_t CM0_INT_CTL2; /*!< 0x00000028 CM0+ interrupt control 2 */ 51 __IOM uint32_t CM0_INT_CTL3; /*!< 0x0000002C CM0+ interrupt control 3 */ 52 __IOM uint32_t CM0_INT_CTL4; /*!< 0x00000030 CM0+ interrupt control 4 */ 53 __IOM uint32_t CM0_INT_CTL5; /*!< 0x00000034 CM0+ interrupt control 5 */ 54 __IOM uint32_t CM0_INT_CTL6; /*!< 0x00000038 CM0+ interrupt control 6 */ 55 __IOM uint32_t CM0_INT_CTL7; /*!< 0x0000003C CM0+ interrupt control 7 */ 56 __IM uint32_t RESERVED3[16]; 57 __IOM uint32_t CM4_PWR_CTL; /*!< 0x00000080 CM4 power control */ 58 __IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00000084 CM4 power control */ 59 __IM uint32_t CM4_STATUS; /*!< 0x00000088 CM4 status */ 60 __IM uint32_t RESERVED4; 61 __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000090 CM4 clock control */ 62 __IM uint32_t RESERVED5[3]; 63 __IOM uint32_t CM4_NMI_CTL; /*!< 0x000000A0 CM4 NMI control */ 64 __IM uint32_t RESERVED6[23]; 65 __IOM uint32_t RAM0_CTL0; /*!< 0x00000100 RAM 0 control 0 */ 66 __IM uint32_t RESERVED7[15]; 67 __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00000140 RAM 0 power control */ 68 __IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */ 69 __IM uint32_t RESERVED8[3]; 70 __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */ 71 __IM uint32_t RESERVED9[3]; 72 __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */ 73 __IM uint32_t RESERVED10[3]; 74 __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */ 75 __IM uint32_t RESERVED11[3]; 76 __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000001C0 Power up delay used for all SRAM power domains */ 77 __IM uint32_t RESERVED12[3]; 78 __IOM uint32_t ROM_CTL; /*!< 0x000001D0 ROM control */ 79 __IM uint32_t RESERVED13[7]; 80 __IOM uint32_t UDB_PWR_CTL; /*!< 0x000001F0 UDB power control */ 81 __IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x000001F4 UDB power control */ 82 __IM uint32_t RESERVED14[4]; 83 __IM uint32_t DP_STATUS; /*!< 0x00000208 Debug port status */ 84 __IM uint32_t RESERVED15[5]; 85 __IOM uint32_t BUFF_CTL; /*!< 0x00000220 Buffer control */ 86 __IM uint32_t RESERVED16[3]; 87 __IOM uint32_t DDFT_CTL; /*!< 0x00000230 DDFT control */ 88 __IM uint32_t RESERVED17[3]; 89 __IOM uint32_t SYSTICK_CTL; /*!< 0x00000240 SysTick timer control */ 90 __IM uint32_t RESERVED18[27]; 91 __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x000002B0 CM0+ vector table base */ 92 __IM uint32_t RESERVED19[3]; 93 __IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x000002C0 CM4 vector table base */ 94 __IM uint32_t RESERVED20[23]; 95 __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00000320 CM0+ protection context 0 handler */ 96 __IM uint32_t RESERVED21[55]; 97 __IM uint32_t IDENTITY; /*!< 0x00000400 Identity */ 98 __IM uint32_t RESERVED22[63]; 99 __IOM uint32_t PROTECTION; /*!< 0x00000500 Protection status */ 100 __IM uint32_t RESERVED23[7]; 101 __IOM uint32_t CM0_NMI_CTL; /*!< 0x00000520 CM0+ NMI control */ 102 __IM uint32_t RESERVED24[7]; 103 __IOM uint32_t AP_CTL; /*!< 0x00000540 Access port control */ 104 __IM uint32_t RESERVED25[23]; 105 __IM uint32_t MBIST_STAT; /*!< 0x000005A0 Memory BIST status */ 106 __IM uint32_t RESERVED26[14999]; 107 __IOM uint32_t TRIM_ROM_CTL; /*!< 0x0000F000 ROM trim control */ 108 __IOM uint32_t TRIM_RAM_CTL; /*!< 0x0000F004 RAM trim control */ 109 } CPUSS_V1_Type; /*!< Size = 61448 (0xF008) */ 110 111 112 /* CPUSS.CM0_CTL */ 113 #define CPUSS_CM0_CTL_SLV_STALL_Pos 0UL 114 #define CPUSS_CM0_CTL_SLV_STALL_Msk 0x1UL 115 #define CPUSS_CM0_CTL_ENABLED_Pos 1UL 116 #define CPUSS_CM0_CTL_ENABLED_Msk 0x2UL 117 #define CPUSS_CM0_CTL_VECTKEYSTAT_Pos 16UL 118 #define CPUSS_CM0_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 119 /* CPUSS.CM0_STATUS */ 120 #define CPUSS_CM0_STATUS_SLEEPING_Pos 0UL 121 #define CPUSS_CM0_STATUS_SLEEPING_Msk 0x1UL 122 #define CPUSS_CM0_STATUS_SLEEPDEEP_Pos 1UL 123 #define CPUSS_CM0_STATUS_SLEEPDEEP_Msk 0x2UL 124 /* CPUSS.CM0_CLOCK_CTL */ 125 #define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos 8UL 126 #define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk 0xFF00UL 127 #define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Pos 24UL 128 #define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Msk 0xFF000000UL 129 /* CPUSS.CM0_INT_CTL0 */ 130 #define CPUSS_CM0_INT_CTL0_MUX0_SEL_Pos 0UL 131 #define CPUSS_CM0_INT_CTL0_MUX0_SEL_Msk 0xFFUL 132 #define CPUSS_CM0_INT_CTL0_MUX1_SEL_Pos 8UL 133 #define CPUSS_CM0_INT_CTL0_MUX1_SEL_Msk 0xFF00UL 134 #define CPUSS_CM0_INT_CTL0_MUX2_SEL_Pos 16UL 135 #define CPUSS_CM0_INT_CTL0_MUX2_SEL_Msk 0xFF0000UL 136 #define CPUSS_CM0_INT_CTL0_MUX3_SEL_Pos 24UL 137 #define CPUSS_CM0_INT_CTL0_MUX3_SEL_Msk 0xFF000000UL 138 /* CPUSS.CM0_INT_CTL1 */ 139 #define CPUSS_CM0_INT_CTL1_MUX0_SEL_Pos 0UL 140 #define CPUSS_CM0_INT_CTL1_MUX0_SEL_Msk 0xFFUL 141 #define CPUSS_CM0_INT_CTL1_MUX1_SEL_Pos 8UL 142 #define CPUSS_CM0_INT_CTL1_MUX1_SEL_Msk 0xFF00UL 143 #define CPUSS_CM0_INT_CTL1_MUX2_SEL_Pos 16UL 144 #define CPUSS_CM0_INT_CTL1_MUX2_SEL_Msk 0xFF0000UL 145 #define CPUSS_CM0_INT_CTL1_MUX3_SEL_Pos 24UL 146 #define CPUSS_CM0_INT_CTL1_MUX3_SEL_Msk 0xFF000000UL 147 /* CPUSS.CM0_INT_CTL2 */ 148 #define CPUSS_CM0_INT_CTL2_MUX0_SEL_Pos 0UL 149 #define CPUSS_CM0_INT_CTL2_MUX0_SEL_Msk 0xFFUL 150 #define CPUSS_CM0_INT_CTL2_MUX1_SEL_Pos 8UL 151 #define CPUSS_CM0_INT_CTL2_MUX1_SEL_Msk 0xFF00UL 152 #define CPUSS_CM0_INT_CTL2_MUX2_SEL_Pos 16UL 153 #define CPUSS_CM0_INT_CTL2_MUX2_SEL_Msk 0xFF0000UL 154 #define CPUSS_CM0_INT_CTL2_MUX3_SEL_Pos 24UL 155 #define CPUSS_CM0_INT_CTL2_MUX3_SEL_Msk 0xFF000000UL 156 /* CPUSS.CM0_INT_CTL3 */ 157 #define CPUSS_CM0_INT_CTL3_MUX0_SEL_Pos 0UL 158 #define CPUSS_CM0_INT_CTL3_MUX0_SEL_Msk 0xFFUL 159 #define CPUSS_CM0_INT_CTL3_MUX1_SEL_Pos 8UL 160 #define CPUSS_CM0_INT_CTL3_MUX1_SEL_Msk 0xFF00UL 161 #define CPUSS_CM0_INT_CTL3_MUX2_SEL_Pos 16UL 162 #define CPUSS_CM0_INT_CTL3_MUX2_SEL_Msk 0xFF0000UL 163 #define CPUSS_CM0_INT_CTL3_MUX3_SEL_Pos 24UL 164 #define CPUSS_CM0_INT_CTL3_MUX3_SEL_Msk 0xFF000000UL 165 /* CPUSS.CM0_INT_CTL4 */ 166 #define CPUSS_CM0_INT_CTL4_MUX0_SEL_Pos 0UL 167 #define CPUSS_CM0_INT_CTL4_MUX0_SEL_Msk 0xFFUL 168 #define CPUSS_CM0_INT_CTL4_MUX1_SEL_Pos 8UL 169 #define CPUSS_CM0_INT_CTL4_MUX1_SEL_Msk 0xFF00UL 170 #define CPUSS_CM0_INT_CTL4_MUX2_SEL_Pos 16UL 171 #define CPUSS_CM0_INT_CTL4_MUX2_SEL_Msk 0xFF0000UL 172 #define CPUSS_CM0_INT_CTL4_MUX3_SEL_Pos 24UL 173 #define CPUSS_CM0_INT_CTL4_MUX3_SEL_Msk 0xFF000000UL 174 /* CPUSS.CM0_INT_CTL5 */ 175 #define CPUSS_CM0_INT_CTL5_MUX0_SEL_Pos 0UL 176 #define CPUSS_CM0_INT_CTL5_MUX0_SEL_Msk 0xFFUL 177 #define CPUSS_CM0_INT_CTL5_MUX1_SEL_Pos 8UL 178 #define CPUSS_CM0_INT_CTL5_MUX1_SEL_Msk 0xFF00UL 179 #define CPUSS_CM0_INT_CTL5_MUX2_SEL_Pos 16UL 180 #define CPUSS_CM0_INT_CTL5_MUX2_SEL_Msk 0xFF0000UL 181 #define CPUSS_CM0_INT_CTL5_MUX3_SEL_Pos 24UL 182 #define CPUSS_CM0_INT_CTL5_MUX3_SEL_Msk 0xFF000000UL 183 /* CPUSS.CM0_INT_CTL6 */ 184 #define CPUSS_CM0_INT_CTL6_MUX0_SEL_Pos 0UL 185 #define CPUSS_CM0_INT_CTL6_MUX0_SEL_Msk 0xFFUL 186 #define CPUSS_CM0_INT_CTL6_MUX1_SEL_Pos 8UL 187 #define CPUSS_CM0_INT_CTL6_MUX1_SEL_Msk 0xFF00UL 188 #define CPUSS_CM0_INT_CTL6_MUX2_SEL_Pos 16UL 189 #define CPUSS_CM0_INT_CTL6_MUX2_SEL_Msk 0xFF0000UL 190 #define CPUSS_CM0_INT_CTL6_MUX3_SEL_Pos 24UL 191 #define CPUSS_CM0_INT_CTL6_MUX3_SEL_Msk 0xFF000000UL 192 /* CPUSS.CM0_INT_CTL7 */ 193 #define CPUSS_CM0_INT_CTL7_MUX0_SEL_Pos 0UL 194 #define CPUSS_CM0_INT_CTL7_MUX0_SEL_Msk 0xFFUL 195 #define CPUSS_CM0_INT_CTL7_MUX1_SEL_Pos 8UL 196 #define CPUSS_CM0_INT_CTL7_MUX1_SEL_Msk 0xFF00UL 197 #define CPUSS_CM0_INT_CTL7_MUX2_SEL_Pos 16UL 198 #define CPUSS_CM0_INT_CTL7_MUX2_SEL_Msk 0xFF0000UL 199 #define CPUSS_CM0_INT_CTL7_MUX3_SEL_Pos 24UL 200 #define CPUSS_CM0_INT_CTL7_MUX3_SEL_Msk 0xFF000000UL 201 /* CPUSS.CM4_PWR_CTL */ 202 #define CPUSS_CM4_PWR_CTL_PWR_MODE_Pos 0UL 203 #define CPUSS_CM4_PWR_CTL_PWR_MODE_Msk 0x3UL 204 #define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Pos 16UL 205 #define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 206 /* CPUSS.CM4_PWR_DELAY_CTL */ 207 #define CPUSS_CM4_PWR_DELAY_CTL_UP_Pos 0UL 208 #define CPUSS_CM4_PWR_DELAY_CTL_UP_Msk 0x3FFUL 209 /* CPUSS.CM4_STATUS */ 210 #define CPUSS_CM4_STATUS_SLEEPING_Pos 0UL 211 #define CPUSS_CM4_STATUS_SLEEPING_Msk 0x1UL 212 #define CPUSS_CM4_STATUS_SLEEPDEEP_Pos 1UL 213 #define CPUSS_CM4_STATUS_SLEEPDEEP_Msk 0x2UL 214 #define CPUSS_CM4_STATUS_PWR_DONE_Pos 4UL 215 #define CPUSS_CM4_STATUS_PWR_DONE_Msk 0x10UL 216 /* CPUSS.CM4_CLOCK_CTL */ 217 #define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Pos 8UL 218 #define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Msk 0xFF00UL 219 /* CPUSS.CM4_NMI_CTL */ 220 #define CPUSS_CM4_NMI_CTL_MUX0_SEL_Pos 0UL 221 #define CPUSS_CM4_NMI_CTL_MUX0_SEL_Msk 0xFFUL 222 /* CPUSS.RAM0_CTL0 */ 223 #define CPUSS_RAM0_CTL0_SLOW_WS_Pos 0UL 224 #define CPUSS_RAM0_CTL0_SLOW_WS_Msk 0x3UL 225 #define CPUSS_RAM0_CTL0_FAST_WS_Pos 8UL 226 #define CPUSS_RAM0_CTL0_FAST_WS_Msk 0x300UL 227 /* CPUSS.RAM0_PWR_MACRO_CTL */ 228 #define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 0UL 229 #define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 0x3UL 230 #define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 16UL 231 #define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 232 /* CPUSS.RAM1_CTL0 */ 233 #define CPUSS_RAM1_CTL0_SLOW_WS_Pos 0UL 234 #define CPUSS_RAM1_CTL0_SLOW_WS_Msk 0x3UL 235 #define CPUSS_RAM1_CTL0_FAST_WS_Pos 8UL 236 #define CPUSS_RAM1_CTL0_FAST_WS_Msk 0x300UL 237 /* CPUSS.RAM1_PWR_CTL */ 238 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos 0UL 239 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Msk 0x3UL 240 #define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Pos 16UL 241 #define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 242 /* CPUSS.RAM2_CTL0 */ 243 #define CPUSS_RAM2_CTL0_SLOW_WS_Pos 0UL 244 #define CPUSS_RAM2_CTL0_SLOW_WS_Msk 0x3UL 245 #define CPUSS_RAM2_CTL0_FAST_WS_Pos 8UL 246 #define CPUSS_RAM2_CTL0_FAST_WS_Msk 0x300UL 247 /* CPUSS.RAM2_PWR_CTL */ 248 #define CPUSS_RAM2_PWR_CTL_PWR_MODE_Pos 0UL 249 #define CPUSS_RAM2_PWR_CTL_PWR_MODE_Msk 0x3UL 250 #define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Pos 16UL 251 #define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 252 /* CPUSS.RAM_PWR_DELAY_CTL */ 253 #define CPUSS_RAM_PWR_DELAY_CTL_UP_Pos 0UL 254 #define CPUSS_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL 255 /* CPUSS.ROM_CTL */ 256 #define CPUSS_ROM_CTL_SLOW_WS_Pos 0UL 257 #define CPUSS_ROM_CTL_SLOW_WS_Msk 0x3UL 258 #define CPUSS_ROM_CTL_FAST_WS_Pos 8UL 259 #define CPUSS_ROM_CTL_FAST_WS_Msk 0x300UL 260 /* CPUSS.UDB_PWR_CTL */ 261 #define CPUSS_UDB_PWR_CTL_PWR_MODE_Pos 0UL 262 #define CPUSS_UDB_PWR_CTL_PWR_MODE_Msk 0x3UL 263 #define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Pos 16UL 264 #define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 265 /* CPUSS.UDB_PWR_DELAY_CTL */ 266 #define CPUSS_UDB_PWR_DELAY_CTL_UP_Pos 0UL 267 #define CPUSS_UDB_PWR_DELAY_CTL_UP_Msk 0x3FFUL 268 /* CPUSS.DP_STATUS */ 269 #define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos 0UL 270 #define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL 271 #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL 272 #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL 273 #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL 274 #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL 275 /* CPUSS.BUFF_CTL */ 276 #define CPUSS_BUFF_CTL_WRITE_BUFF_Pos 0UL 277 #define CPUSS_BUFF_CTL_WRITE_BUFF_Msk 0x1UL 278 /* CPUSS.DDFT_CTL */ 279 #define CPUSS_DDFT_CTL_DDFT_OUT0_SEL_Pos 0UL 280 #define CPUSS_DDFT_CTL_DDFT_OUT0_SEL_Msk 0x1FUL 281 #define CPUSS_DDFT_CTL_DDFT_OUT1_SEL_Pos 8UL 282 #define CPUSS_DDFT_CTL_DDFT_OUT1_SEL_Msk 0x1F00UL 283 /* CPUSS.SYSTICK_CTL */ 284 #define CPUSS_SYSTICK_CTL_TENMS_Pos 0UL 285 #define CPUSS_SYSTICK_CTL_TENMS_Msk 0xFFFFFFUL 286 #define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos 24UL 287 #define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Msk 0x3000000UL 288 #define CPUSS_SYSTICK_CTL_SKEW_Pos 30UL 289 #define CPUSS_SYSTICK_CTL_SKEW_Msk 0x40000000UL 290 #define CPUSS_SYSTICK_CTL_NOREF_Pos 31UL 291 #define CPUSS_SYSTICK_CTL_NOREF_Msk 0x80000000UL 292 /* CPUSS.CM0_VECTOR_TABLE_BASE */ 293 #define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 8UL 294 #define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 0xFFFFFF00UL 295 /* CPUSS.CM4_VECTOR_TABLE_BASE */ 296 #define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Pos 10UL 297 #define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Msk 0xFFFFFC00UL 298 /* CPUSS.CM0_PC0_HANDLER */ 299 #define CPUSS_CM0_PC0_HANDLER_ADDR_Pos 0UL 300 #define CPUSS_CM0_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL 301 /* CPUSS.IDENTITY */ 302 #define CPUSS_IDENTITY_P_Pos 0UL 303 #define CPUSS_IDENTITY_P_Msk 0x1UL 304 #define CPUSS_IDENTITY_NS_Pos 1UL 305 #define CPUSS_IDENTITY_NS_Msk 0x2UL 306 #define CPUSS_IDENTITY_PC_Pos 4UL 307 #define CPUSS_IDENTITY_PC_Msk 0xF0UL 308 #define CPUSS_IDENTITY_MS_Pos 8UL 309 #define CPUSS_IDENTITY_MS_Msk 0xF00UL 310 /* CPUSS.PROTECTION */ 311 #define CPUSS_PROTECTION_STATE_Pos 0UL 312 #define CPUSS_PROTECTION_STATE_Msk 0x7UL 313 /* CPUSS.CM0_NMI_CTL */ 314 #define CPUSS_CM0_NMI_CTL_MUX0_SEL_Pos 0UL 315 #define CPUSS_CM0_NMI_CTL_MUX0_SEL_Msk 0xFFUL 316 /* CPUSS.AP_CTL */ 317 #define CPUSS_AP_CTL_CM0_ENABLE_Pos 0UL 318 #define CPUSS_AP_CTL_CM0_ENABLE_Msk 0x1UL 319 #define CPUSS_AP_CTL_CM4_ENABLE_Pos 1UL 320 #define CPUSS_AP_CTL_CM4_ENABLE_Msk 0x2UL 321 #define CPUSS_AP_CTL_SYS_ENABLE_Pos 2UL 322 #define CPUSS_AP_CTL_SYS_ENABLE_Msk 0x4UL 323 #define CPUSS_AP_CTL_CM0_DISABLE_Pos 16UL 324 #define CPUSS_AP_CTL_CM0_DISABLE_Msk 0x10000UL 325 #define CPUSS_AP_CTL_CM4_DISABLE_Pos 17UL 326 #define CPUSS_AP_CTL_CM4_DISABLE_Msk 0x20000UL 327 #define CPUSS_AP_CTL_SYS_DISABLE_Pos 18UL 328 #define CPUSS_AP_CTL_SYS_DISABLE_Msk 0x40000UL 329 /* CPUSS.MBIST_STAT */ 330 #define CPUSS_MBIST_STAT_SFP_READY_Pos 0UL 331 #define CPUSS_MBIST_STAT_SFP_READY_Msk 0x1UL 332 #define CPUSS_MBIST_STAT_SFP_FAIL_Pos 1UL 333 #define CPUSS_MBIST_STAT_SFP_FAIL_Msk 0x2UL 334 /* CPUSS.TRIM_ROM_CTL */ 335 #define CPUSS_TRIM_ROM_CTL_RM_Pos 0UL 336 #define CPUSS_TRIM_ROM_CTL_RM_Msk 0xFUL 337 #define CPUSS_TRIM_ROM_CTL_RME_Pos 4UL 338 #define CPUSS_TRIM_ROM_CTL_RME_Msk 0x10UL 339 /* CPUSS.TRIM_RAM_CTL */ 340 #define CPUSS_TRIM_RAM_CTL_RM_Pos 0UL 341 #define CPUSS_TRIM_RAM_CTL_RM_Msk 0xFUL 342 #define CPUSS_TRIM_RAM_CTL_RME_Pos 4UL 343 #define CPUSS_TRIM_RAM_CTL_RME_Msk 0x10UL 344 #define CPUSS_TRIM_RAM_CTL_WPULSE_Pos 5UL 345 #define CPUSS_TRIM_RAM_CTL_WPULSE_Msk 0xE0UL 346 #define CPUSS_TRIM_RAM_CTL_RA_Pos 8UL 347 #define CPUSS_TRIM_RAM_CTL_RA_Msk 0x300UL 348 #define CPUSS_TRIM_RAM_CTL_WA_Pos 12UL 349 #define CPUSS_TRIM_RAM_CTL_WA_Msk 0x7000UL 350 351 352 #endif /* _CYIP_CPUSS_H_ */ 353 354 355 /* [] END OF FILE */ 356
