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Searched refs:CM7_1_SYSTEM_INT_CTL (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
Dcy_sysint.c507 …CPUSS->CM7_1_SYSTEM_INT_CTL[sysIntSrc] &= (uint32_t) ~CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_VALID_Msk; in Cy_SysInt_DisableSystemInt()
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h140 __IOM uint32_t CM7_1_SYSTEM_INT_CTL[1023]; /*!< 0x0000C000 CM7 1 system interrupt control */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h512 #define CPUSS_CM7_1_SYSTEM_INT_CTL (((CPUSS_Type *)(CPUSS_BASE))->CM7_1_SYSTEM_INT_CTL)