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Searched refs:CM7_1_STATUS (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-3.5.0/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/
Dsystem_cm0plus.c473 while((CPUSS->CM7_1_STATUS & CPUSS_CM7_1_STATUS_PWR_DONE_Msk) == 0UL) in Cy_SysEnableCM7()
512 while((CPUSS->CM7_1_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) in Cy_SysDisableCM7()
576 while((CPUSS->CM7_1_STATUS & CPUSS_CM7_1_STATUS_PWR_DONE_Msk) == 0UL) in Cy_SysResetCM7()
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_flashc.h91 __IOM uint32_t CM7_1_STATUS; /*!< 0x00000560 CM7 #1 interface status */ member
Dcyip_cpuss.h58 __IM uint32_t CM7_1_STATUS; /*!< 0x00000404 CM7 1status */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h378 #define FLASHC_CM7_1_STATUS (((FLASHC_Type *)(FLASHC))->CM7_1_STATUS)
474 #define CPUSS_CM7_1_STATUS ((((CPUSS_Type *)(CPUSS_BASE))->CM7_1_STATUS))