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Searched refs:CM7_0_CTL (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-3.5.0/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM7/
Dstartup_cm7.c356 CPUSS->CM7_0_CTL &= ~(0xB); in Reset_Handler()
/hal_infineon-3.5.0/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/
Dsystem_cm0plus.c460 CPUSS->CM7_0_CTL &= ~(0x1 << CPUSS_CM7_0_CTL_CPU_WAIT_Pos); in Cy_SysEnableCM7()
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h45 __IOM uint32_t CM7_0_CTL; /*!< 0x0000000C CM7 0 control */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h470 #define CPUSS_CM7_0_CTL (((CPUSS_Type*) CPUSS_BASE)->CM7_0_CTL)