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Searched refs:CM4_CLOCK_CTL (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/
Dcy_device.c132 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V1_Type, CM4_CLOCK_CTL),
249 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
365 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
481 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h61 __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000090 CM4 clock control */ member
Dcyip_cpuss_v2.h44 __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000008 CM4 clock control */ member