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Searched refs:CM0_INT5_STATUS (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss_v2.h72 __IM uint32_t CM0_INT5_STATUS; /*!< 0x00001114 CM0+ interrupt 5 status */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h79 __IM uint32_t CM0_INT5_STATUS; /*!< 0x00001114 CM0+ interrupt 5 status */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h490 #define CPUSS_CM0_INT5_STATUS ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT5_STATUS))