Home
last modified time | relevance | path

Searched refs:CLOCK_CTL (Results 1 – 13 of 13) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_peri_v2.h45 __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ member
76 __IOM uint32_t CLOCK_CTL[256]; /*!< 0x00000C00 Clock control */ member
Dcyip_peri.h48 __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ member
122 __IOM uint32_t CLOCK_CTL[128]; /*!< 0x00000C00 Clock control register */ member
Dcyip_pdm.h44 __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ member
Dcyip_i2s.h44 __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_peri_pclk.h45 __IOM uint32_t CLOCK_CTL[256]; /*!< 0x00000C00 Clock control */ member
Dcyip_peri.h45 __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ member
Dcyip_pdm.h71 __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_peri_pclk_v3.h45 __IOM uint32_t CLOCK_CTL[256]; /*!< 0x00000C00 Clock control */ member
Dcyip_peri_v3.h45 __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ member
Dcyip_i2s_v2.h44 __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h825 #define PERI_CLOCK_CTL ((CY_PERI_BASE)->CLOCK_CTL)
933 #define REG_I2S_CLOCK_CTL(base) (((I2S_V1_Type*)(base))->CLOCK_CTL)
961 #define PDM_PCM_CLOCK_CTL(base) (((PDM_V1_Type*)(base))->CLOCK_CTL)
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1280 … ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL[periNum]
1454 …I_GR_CLOCK_CTL(instNum, grNum) ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL
1608 #define REG_I2S_CLOCK_CTL(base) (((I2S_Type*)(base))->CLOCK_CTL)
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h1094 … ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL[periNum]
1273 …I_GR_CLOCK_CTL(instNum, grNum) ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL
1746 #define PDM_PCM_CLOCK_CTL(base) (((PDM_Type*)(base))->CLOCK_CTL)