1 /***************************************************************************//** 2 * \file cy_crypto_common.h 3 * \version 2.90 4 * 5 * \brief 6 * This file provides common constants and parameters 7 * for the Crypto driver. 8 * 9 ******************************************************************************** 10 * \copyright 11 * Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or 12 * an affiliate of Cypress Semiconductor Corporation. 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 29 #if !defined (CY_CRYPTO_COMMON_H) 30 #define CY_CRYPTO_COMMON_H 31 32 #include "cy_device.h" 33 #include "cy_device_headers.h" 34 35 #if defined (CY_IP_MXCRYPTO) 36 37 #include "cy_crypto_config.h" 38 #include "cy_syslib.h" 39 40 #if defined(__cplusplus) 41 extern "C" { 42 #endif 43 44 #include <stddef.h> 45 #include <stdbool.h> 46 #include "cy_sysint.h" 47 48 /** Driver major version */ 49 #define CY_CRYPTO_DRV_VERSION_MAJOR 2 50 51 /** Driver minor version */ 52 #define CY_CRYPTO_DRV_VERSION_MINOR 90 53 54 55 /* Enable SHA functionality */ 56 #if !defined(CPUSS_CRYPTO_SHA) && (defined(CPUSS_CRYPTO_SHA1) || defined(CPUSS_CRYPTO_SHA2)) 57 #define CPUSS_CRYPTO_SHA (1) 58 59 #if defined(CPUSS_CRYPTO_SHA2) && !defined(CPUSS_CRYPTO_SHA256) 60 #define CPUSS_CRYPTO_SHA256 (1) 61 #endif 62 63 #if defined(CPUSS_CRYPTO_SHA2) && !defined(CPUSS_CRYPTO_SHA512) 64 #define CPUSS_CRYPTO_SHA512 (1) 65 #endif 66 #endif 67 68 #if !defined(CPUSS_CRYPTO_STR) 69 #define CPUSS_CRYPTO_STR (1) 70 #endif 71 72 #if !defined(CPUSS_CRYPTO_CHACHA) && defined(CY_CRYPTO_CFG_HW_V1_ENABLE) 73 #define CPUSS_CRYPTO_CHACHA (0) 74 #endif 75 76 #if !defined(CPUSS_CRYPTO_GCM) && defined(CY_CRYPTO_CFG_HW_V1_ENABLE) 77 #define CPUSS_CRYPTO_GCM (0) 78 #endif 79 80 /** \cond INTERNAL */ 81 82 /* The width of the Crypto hardware registers values in bits. */ 83 #define CY_CRYPTO_HW_REGS_WIDTH (32UL) 84 85 /* Calculates the actual size in bytes of the bits value */ 86 #define CY_CRYPTO_BYTE_SIZE_OF_BITS(x) (uint32_t)(((uint32_t)(x) + 7U) >> 3U) 87 88 /* Calculates the actual size in 32-bit words of the bits value */ 89 #define CY_CRYPTO_WORD_SIZE_OF_BITS(x) (uint32_t)(((uint32_t)(x) + 31U) >> 5U) 90 91 /** \endcond */ 92 93 /** 94 * \addtogroup group_crypto_cli_srv_macros 95 * \{ 96 */ 97 98 /** Defines Crypto_Sync blocking execution type parameter */ 99 #define CY_CRYPTO_SYNC_BLOCKING (true) 100 101 /** Defines Crypto_Sync non-blocking execution type parameter */ 102 #define CY_CRYPTO_SYNC_NON_BLOCKING (false) 103 104 /** Defines the Crypto DES block size (in bytes). */ 105 #define CY_CRYPTO_DES_BLOCK_SIZE (8u) 106 107 /** Defines the Crypto DES key size (in bytes) */ 108 #define CY_CRYPTO_DES_KEY_SIZE (CY_CRYPTO_DES_BLOCK_SIZE) 109 110 /** Defines the Crypto TDES key size (in bytes) */ 111 #define CY_CRYPTO_TDES_KEY_SIZE (24u) 112 113 114 #if defined(CY_CRYPTO_CFG_AES_C) 115 116 /** Defines the Crypto AES block size (in bytes) */ 117 #define CY_CRYPTO_AES_BLOCK_SIZE (16u) 118 119 /** Defines the Crypto AES_128 key maximum size (in bytes) */ 120 #define CY_CRYPTO_AES_128_KEY_SIZE (16u) 121 122 /** Defines the Crypto AES_192 key maximum size (in bytes) */ 123 #define CY_CRYPTO_AES_192_KEY_SIZE (24u) 124 125 /** Defines the Crypto AES_256 key maximum size (in bytes) */ 126 #define CY_CRYPTO_AES_256_KEY_SIZE (32u) 127 128 /** Defines the Crypto AES key maximum size (in bytes) */ 129 #define CY_CRYPTO_AES_MAX_KEY_SIZE (CY_CRYPTO_AES_256_KEY_SIZE) 130 131 /** Defines the Crypto AES_256 key maximum size (in four-byte words) */ 132 #define CY_CRYPTO_AES_MAX_KEY_SIZE_U32 (uint32_t)(CY_CRYPTO_AES_MAX_KEY_SIZE / 4UL) 133 134 /** Defines size of the AES block, in four-byte words */ 135 #define CY_CRYPTO_AES_BLOCK_SIZE_U32 (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE / 4UL) 136 137 /** Defines the Crypto AES GCM IV size (in bytes) */ 138 #define CY_CRYPTO_AES_GCM_IV_SIZE (12u) 139 140 #endif /* defined(CY_CRYPTO_CFG_AES_C) */ 141 142 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 143 144 /* Defines for the SHA algorithm */ 145 /** Block size for the SHA256 mode (in bytes) */ 146 #define CY_CRYPTO_SHA256_BLOCK_SIZE (64u) 147 /** Pad size for the SHA256 mode (in bytes) */ 148 #define CY_CRYPTO_SHA256_PAD_SIZE (56uL) 149 150 /** Block size for the SHA512 mode (in bytes) */ 151 #define CY_CRYPTO_SHA512_BLOCK_SIZE (128u) 152 /** Pad size for the SHA512 mode (in bytes) */ 153 #define CY_CRYPTO_SHA512_PAD_SIZE (112uL) 154 155 #if defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) 156 /** Hash size for the SHA384 mode (in bytes) */ 157 #define CY_CRYPTO_SHA384_DIGEST_SIZE (48u) 158 /** Hash size for the SHA512 mode (in bytes) */ 159 #define CY_CRYPTO_SHA512_DIGEST_SIZE (64u) 160 /** Hash size for the SHA512_224 mode (in bytes) */ 161 #define CY_CRYPTO_SHA512_224_DIGEST_SIZE (28u) 162 /** Hash size for the SHA512_256 mode (in bytes) */ 163 #define CY_CRYPTO_SHA512_256_DIGEST_SIZE (32u) 164 165 /** \cond INTERNAL */ 166 /** Internal hash size for the SHA512_256 mode (in bytes) */ 167 #define CY_CRYPTO_SHA512_HASH_SIZE (64u) 168 /** Internal round mem size for the SHA512_256 mode (in bytes) */ 169 #define CY_CRYPTO_SHA512_ROUND_MEM_SIZE (640uL) 170 /** \endcond */ 171 #endif 172 #if defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) 173 /** Hash size for the SHA224 mode (in bytes) */ 174 #define CY_CRYPTO_SHA224_DIGEST_SIZE (28u) 175 /** Hash size for the SHA256 mode (in bytes) */ 176 #define CY_CRYPTO_SHA256_DIGEST_SIZE (32u) 177 178 /** \cond INTERNAL */ 179 /** Internal hash size for the SHA256 mode (in bytes) */ 180 #define CY_CRYPTO_SHA256_HASH_SIZE (32u) 181 /** Internal round mem size for the SHA256 mode (in bytes) */ 182 #define CY_CRYPTO_SHA256_ROUND_MEM_SIZE (256uL) 183 /** \endcond */ 184 #endif 185 #if defined(CY_CRYPTO_CFG_SHA1_ENABLED) 186 /** Hash size for the SHA1 mode (in bytes) */ 187 #define CY_CRYPTO_SHA1_DIGEST_SIZE (20u) 188 /** Block size for the SHA1 mode (in bytes) */ 189 #define CY_CRYPTO_SHA1_BLOCK_SIZE (64u) 190 191 /** \cond INTERNAL */ 192 /** Internal hash size for the SHA1 mode (in bytes) */ 193 #define CY_CRYPTO_SHA1_HASH_SIZE (20u) 194 /** Internal round mem size for the SHA1 mode (in bytes) */ 195 #define CY_CRYPTO_SHA1_ROUND_MEM_SIZE (320uL) 196 /** \endcond */ 197 #endif 198 199 /** \cond INTERNAL */ 200 #if defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) 201 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (CY_CRYPTO_SHA512_DIGEST_SIZE) 202 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (CY_CRYPTO_SHA512_BLOCK_SIZE) 203 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (CY_CRYPTO_SHA512_HASH_SIZE) 204 #elif defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) 205 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (CY_CRYPTO_SHA256_DIGEST_SIZE) 206 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (CY_CRYPTO_SHA256_BLOCK_SIZE) 207 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (CY_CRYPTO_SHA256_HASH_SIZE) 208 #elif defined(CY_CRYPTO_CFG_SHA1_ENABLED) 209 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (CY_CRYPTO_SHA1_DIGEST_SIZE) 210 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (CY_CRYPTO_SHA1_BLOCK_SIZE) 211 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (CY_CRYPTO_SHA1_HASH_SIZE) 212 #else 213 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (0u) 214 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (0u) 215 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (0u) 216 #endif 217 218 #if defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) 219 #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (CY_CRYPTO_SHA512_ROUND_MEM_SIZE) 220 #elif defined(CY_CRYPTO_CFG_SHA1_ENABLED) 221 #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (CY_CRYPTO_SHA1_ROUND_MEM_SIZE) 222 #elif defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) 223 #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (CY_CRYPTO_SHA256_ROUND_MEM_SIZE) 224 #else 225 #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (0u) 226 #endif 227 /** \endcond */ 228 229 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 230 231 232 #if (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_RSA_C) 233 234 /** \cond INTERNAL */ 235 /** Processed message size for the RSA 1024Bit mode (in bytes) */ 236 #define CY_CRYPTO_RSA1024_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(1024u) 237 /** Processed message size for the RSA 1536Bit mode (in bytes) */ 238 #define CY_CRYPTO_RSA1536_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(1536u) 239 /** Processed message size for the RSA 2048Bit mode (in bytes) */ 240 #define CY_CRYPTO_RSA2048_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(2048u) 241 /** Processed message size for the RSA 3072Bit mode (in bytes) */ 242 #define CY_CRYPTO_RSA3072_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(3072u) 243 /** Processed message size for the RSA 4096Bit mode (in bytes) */ 244 #define CY_CRYPTO_RSA4096_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(4096u) 245 /** \endcond */ 246 247 /** 248 * \addtogroup group_crypto_data_structures 249 * \{ 250 */ 251 252 /** 253 * All fields for the context structure are internal. Firmware never reads or 254 * writes these values. Firmware allocates the structure and provides the 255 * address of the structure to the driver in the function calls. Firmware must 256 * ensure that the defined instance of this structure remains in scope 257 * while the drive is in use. 258 * 259 * The driver uses this structure to store and manipulate the RSA public key and 260 * additional coefficients to accelerate RSA calculation. 261 * 262 * RSA key contained from two fields: 263 * - n - modulus part of the key 264 * - e - exponent part of the key. 265 * 266 * Other fields are accelerating coefficients and can be calculated by 267 * \ref Cy_Crypto_Rsa_CalcCoefs. 268 * 269 * \note The <b>modulus</b> and <b>exponent</b> values in the 270 * \ref cy_stc_crypto_rsa_pub_key_t must also be in little-endian order.<br> 271 * Use \ref Cy_Crypto_InvertEndianness function to convert to or from 272 * little-endian order. 273 */ 274 typedef struct 275 { 276 /** \cond INTERNAL */ 277 /** The pointer to the modulus part of public key. */ 278 uint8_t *moduloPtr; 279 /** The modulus length, in bits, maximum supported size is 2048Bit */ 280 uint32_t moduloLength; 281 282 /** The pointer to the exponent part of public key */ 283 uint8_t *pubExpPtr; 284 /** The exponent length, in bits, maximum supported size is 256Bit */ 285 uint32_t pubExpLength; 286 287 /** The pointer to the Barrett coefficient. Memory for it should be 288 allocated by user with size moduloLength + 1. */ 289 uint8_t *barretCoefPtr; 290 291 /** The pointer to the binary inverse of the modulo. Memory for it 292 should be allocated by user with size moduloLength. */ 293 uint8_t *inverseModuloPtr; 294 295 /** The pointer to the (2^moduloLength mod modulo). Memory for it should 296 be allocated by user with size moduloLength */ 297 uint8_t *rBarPtr; 298 /** \endcond */ 299 } cy_stc_crypto_rsa_pub_key_t; 300 301 /** \} group_crypto_data_structures */ 302 303 #endif /* (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_RSA_C) */ 304 305 /** Crypto Driver PDL ID */ 306 #define CY_CRYPTO_ID CY_PDL_DRV_ID(0x0Cu) 307 308 /** \} group_crypto_cli_srv_macros */ 309 310 /** 311 * \addtogroup group_crypto_config_structure 312 * \{ 313 The Crypto initialization configuration. 314 * \note Should be the same for the Crypto Server and Crypto Client initialization. 315 */ 316 317 /** The Crypto user callback function type. 318 Callback is called at the end of Crypto calculation. */ 319 typedef void (*cy_crypto_callback_ptr_t)(void); 320 321 /** The Crypto configuration structure. */ 322 typedef struct 323 { 324 /** Defines the IPC channel used for client-server data exchange */ 325 uint32_t ipcChannel; 326 327 /** Specifies the IPC notifier channel (IPC interrupt structure number) 328 to notify server that data for the operation is prepared */ 329 uint32_t acquireNotifierChannel; 330 331 /** Specifies the IPC notifier channel (IPC interrupt structure number) 332 to notify client that operation is complete and data is valid */ 333 uint32_t releaseNotifierChannel; 334 335 /** Specifies the release notifier interrupt configuration. It used for 336 internal purposes and user doesn't fill it. */ 337 cy_stc_sysint_t releaseNotifierConfig; 338 339 /** User callback function. 340 If this field is NOT NULL, it called when Crypto operation 341 is complete. */ 342 cy_crypto_callback_ptr_t userCompleteCallback; 343 344 /** Server-side user IRQ handler function, called when data for the 345 operation is prepared to process. 346 - If this field is NULL, server will use own interrupt handler 347 to get data. 348 - If this field is not NULL, server will call this interrupt handler. 349 This interrupt handler must call the 350 \ref Cy_Crypto_Server_GetDataHandler to get data to process. 351 352 Note: In the second case user should process data separately and 353 clear interrupt by calling \ref Cy_Crypto_Server_Process. 354 This model is used in the 355 multitasking environment. */ 356 cy_israddress userGetDataHandler; 357 358 /** Server-side user IRQ handler function, called when a Crypto hardware 359 error occurs (interrupt was raised). 360 - If this field is NULL - server will use own interrupt handler 361 for error processing. 362 - If this field is not NULL - server will call this interrupt handler. 363 This interrupt handler must call the 364 \ref Cy_Crypto_Server_ErrorHandler to clear the interrupt. */ 365 cy_israddress userErrorHandler; 366 367 /** Specifies the prepared data notifier interrupt configuration. It used 368 for internal purposes and user doesn't fill it. */ 369 cy_stc_sysint_t acquireNotifierConfig; 370 371 /** Specifies the hardware error processing interrupt configuration. It used 372 for internal purposes and user doesn't fill it. */ 373 cy_stc_sysint_t cryptoErrorIntrConfig; 374 375 } cy_stc_crypto_config_t; 376 377 /** \} group_crypto_config_structure */ 378 379 /** 380 * \addtogroup group_crypto_cli_data_structures 381 * \{ 382 */ 383 384 /** Structure for storing a description of a Crypto hardware error */ 385 typedef struct 386 { 387 /** 388 Captures error description information for one of obtained hardware error: 389 - for <b>INSTR_OPC_ERROR</b>: - violating the instruction. 390 - for <b>INSTR_CC_ERROR</b> : - violating the instruction condition code. 391 - for <b>BUS_ERROR</b> : - violating the transfer address. */ 392 uint32_t errorStatus0; 393 394 /** 395 [31] - "1" - Indicates that hardware error has occurred and 396 ERROR_STATUS0 and ERROR_STATUS1 captured valid error-information. 397 [26..24] - The error source: 398 - "0": <b>INSTR_OPC_ERROR</b> - an instruction decoder error. 399 - "1": <b>INSTR_CC_ERROR</b> - an instruction condition code-error. 400 - "2": <b>BUS_ERROR</b> - a bus master interface AHB-Lite bus-error. 401 - [5..4] - violating the transfer, the size attribute 402 - "0": an 8-bit transfer; 403 - "1": 16 bits transfer; 404 - "2": 32-bit transfer. 405 - [0] - violating the transfer, read the attribute 406 - "3": <b>TR_AP_DETECT_ERROR</b> - True Random Generator error. 407 */ 408 uint32_t errorStatus1; 409 } cy_stc_crypto_hw_error_t; 410 411 /** \} group_crypto_cli_data_structures */ 412 413 414 /** The Crypto library functionality level. */ 415 typedef enum 416 { 417 CY_CRYPTO_NO_LIBRARY = 0x00u, 418 CY_CRYPTO_BASE_LIBRARY = 0x01u, 419 CY_CRYPTO_EXTRA_LIBRARY = 0x02u, 420 CY_CRYPTO_FULL_LIBRARY = 0x03u, 421 } cy_en_crypto_lib_info_t; 422 423 424 /** 425 * \addtogroup group_crypto_enums 426 * \{ 427 */ 428 429 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) 430 /** The key length options for the AES method. */ 431 typedef enum 432 { 433 CY_CRYPTO_KEY_AES_128 = 0x00u, /**< The AES key size is 128 bits */ 434 CY_CRYPTO_KEY_AES_192 = 0x01u, /**< The AES key size is 192 bits */ 435 CY_CRYPTO_KEY_AES_256 = 0x02u /**< The AES key size is 256 bits */ 436 } cy_en_crypto_aes_key_length_t; 437 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) */ 438 439 /** Defines the direction of the Crypto methods */ 440 typedef enum 441 { 442 /** The forward mode, plain text will be encrypted into cipher text */ 443 CY_CRYPTO_ENCRYPT = 0x00u, 444 /** The reverse mode, cipher text will be decrypted into plain text */ 445 CY_CRYPTO_DECRYPT = 0x01u 446 } cy_en_crypto_dir_mode_t; 447 448 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 449 /** Defines modes of SHA method */ 450 typedef enum 451 { 452 #if (CPUSS_CRYPTO_SHA1 == 1) && defined(CY_CRYPTO_CFG_SHA1_ENABLED) 453 CY_CRYPTO_MODE_SHA1 = 0x00u, /**< Sets the SHA1 mode */ 454 #endif /* (CPUSS_CRYPTO_SHA1 == 1) && defined(CY_CRYPTO_CFG_SHA1_ENABLED) */ 455 456 #if (CPUSS_CRYPTO_SHA256 == 1) && defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) 457 CY_CRYPTO_MODE_SHA224 = 0x01u, /**< Sets the SHA224 mode */ 458 CY_CRYPTO_MODE_SHA256 = 0x02u, /**< Sets the SHA256 mode */ 459 #endif /* (CPUSS_CRYPTO_SHA256 == 1) && defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) */ 460 461 #if (CPUSS_CRYPTO_SHA512 == 1) && defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) 462 CY_CRYPTO_MODE_SHA384 = 0x03u, /**< Sets the SHA384 mode */ 463 CY_CRYPTO_MODE_SHA512 = 0x04u, /**< Sets the SHA512 mode */ 464 CY_CRYPTO_MODE_SHA512_256 = 0x05u, /**< Sets the SHA512/256 mode */ 465 CY_CRYPTO_MODE_SHA512_224 = 0x06u, /**< Sets the SHA512/224 mode */ 466 #endif /* (CPUSS_CRYPTO_SHA512 == 1) && defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) */ 467 CY_CRYPTO_MODE_SHA_NONE = 0x07u, /**< Sets the SHA None mode */ 468 469 470 } cy_en_crypto_sha_mode_t; 471 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 472 473 #if defined(CY_CRYPTO_CFG_RSA_C) && defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) 474 /** Signature verification status */ 475 typedef enum 476 { 477 CY_CRYPTO_RSA_VERIFY_SUCCESS = 0x00u, /**< PKCS1-v1.5 verify SUCCESS */ 478 CY_CRYPTO_RSA_VERIFY_FAIL = 0x01u /**< PKCS1-v1.5 verify FAILED */ 479 } cy_en_crypto_rsa_ver_result_t; 480 #endif /* defined(CY_CRYPTO_CFG_RSA_C) && defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) */ 481 482 /** Errors of the Crypto block */ 483 typedef enum 484 { 485 /** Operation completed successfully. */ 486 CY_CRYPTO_SUCCESS = 0x00u, 487 488 /** A hardware error occurred, detailed information is in stc_crypto_hw_error_t. */ 489 CY_CRYPTO_HW_ERROR = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x01u, 490 491 /** The size of input data is not multiple of 16. */ 492 CY_CRYPTO_SIZE_NOT_X16 = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x02u, 493 494 /** The key for the DES method is weak. */ 495 CY_CRYPTO_DES_WEAK_KEY = CY_CRYPTO_ID | CY_PDL_STATUS_WARNING | 0x03u, 496 497 /** Communication between the client and server via IPC is broken. */ 498 CY_CRYPTO_COMM_FAIL = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x04u, 499 500 /** The Crypto server is not started. */ 501 CY_CRYPTO_SERVER_NOT_STARTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x06u, 502 503 /** The Crypto server in process state. */ 504 CY_CRYPTO_SERVER_BUSY = CY_CRYPTO_ID | CY_PDL_STATUS_INFO | 0x07u, 505 506 /** The Crypto driver is not initialized. */ 507 CY_CRYPTO_NOT_INITIALIZED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x08u, 508 509 /** The Crypto hardware is not enabled. */ 510 CY_CRYPTO_HW_NOT_ENABLED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x09u, 511 512 /** The Crypto operation is not supported. */ 513 CY_CRYPTO_NOT_SUPPORTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x0Au, 514 515 /** The Crypto operation parameters are incorrect. */ 516 CY_CRYPTO_BAD_PARAMS = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x0Bu, 517 518 /** TRNG generated is not a healthy random number. */ 519 CY_CRYPTO_TRNG_UNHEALTHY = CY_CRYPTO_ID | CY_PDL_STATUS_WARNING | 0x0Cu 520 521 } cy_en_crypto_status_t; 522 523 /** \} group_crypto_enums */ 524 525 /** 526 * \addtogroup group_crypto_lld_asymmetric_enums 527 * \{ 528 */ 529 530 #if (CPUSS_CRYPTO_VU == 1) && defined (CY_CRYPTO_CFG_ECP_C) 531 /** List of supported elliptic curve IDs */ 532 typedef enum { 533 CY_CRYPTO_ECC_ECP_NONE = 0, 534 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP192R1_ENABLED) 535 CY_CRYPTO_ECC_ECP_SECP192R1, 536 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP192R1_ENABLED) */ 537 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP224R1_ENABLED) 538 CY_CRYPTO_ECC_ECP_SECP224R1, 539 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP224R1_ENABLED) */ 540 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP256R1_ENABLED) 541 CY_CRYPTO_ECC_ECP_SECP256R1, 542 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP256R1_ENABLED) */ 543 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP384R1_ENABLED) 544 CY_CRYPTO_ECC_ECP_SECP384R1, 545 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP384R1_ENABLED) */ 546 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP521R1_ENABLED) 547 CY_CRYPTO_ECC_ECP_SECP521R1, 548 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP521R1_ENABLED) */ 549 /* Count of supported curves */ 550 CY_CRYPTO_ECC_ECP_CURVES_CNT 551 } cy_en_crypto_ecc_curve_id_t; 552 553 #endif /* (CPUSS_CRYPTO_VU == 1) && defined (CY_CRYPTO_CFG_ECP_C) */ 554 555 /** \} group_crypto_lld_asymmetric_enums */ 556 557 /** \cond INTERNAL */ 558 559 /** Instruction to communicate between Client and Server */ 560 typedef enum 561 { 562 CY_CRYPTO_INSTR_UNKNOWN = 0x00u, 563 CY_CRYPTO_INSTR_ENABLE = 0x01u, 564 CY_CRYPTO_INSTR_DISABLE = 0x02u, 565 566 #if (CPUSS_CRYPTO_PR == 1) && defined(CY_CRYPTO_CFG_PRNG_C) 567 CY_CRYPTO_INSTR_PRNG_INIT = 0x03u, 568 CY_CRYPTO_INSTR_PRNG = 0x04u, 569 #endif /* (CPUSS_CRYPTO_PR == 1) && defined(CY_CRYPTO_CFG_PRNG_C) */ 570 571 #if (CPUSS_CRYPTO_TR == 1) && defined(CY_CRYPTO_CFG_TRNG_C) 572 CY_CRYPTO_INSTR_TRNG_INIT = 0x05u, 573 CY_CRYPTO_INSTR_TRNG = 0x06u, 574 #endif /* (CPUSS_CRYPTO_TR == 1) && defined(CY_CRYPTO_CFG_TRNG_C) */ 575 576 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) 577 CY_CRYPTO_INSTR_AES_INIT = 0x07u, 578 CY_CRYPTO_INSTR_AES_ECB = 0x08u, 579 580 #if defined(CY_CRYPTO_CFG_CIPHER_MODE_CBC) 581 CY_CRYPTO_INSTR_AES_CBC = 0x09u, 582 #endif /* defined(CY_CRYPTO_CFG_CIPHER_MODE_CBC) */ 583 #if defined(CY_CRYPTO_CFG_CIPHER_MODE_CFB) 584 CY_CRYPTO_INSTR_AES_CFB = 0x0Au, 585 #endif /* defined(CY_CRYPTO_CFG_CIPHER_MODE_CFB) */ 586 #if defined(CY_CRYPTO_CFG_CIPHER_MODE_CTR) 587 CY_CRYPTO_INSTR_AES_CTR = 0x0Bu, 588 #endif /* defined(CY_CRYPTO_CFG_CIPHER_MODE_CTR) */ 589 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) */ 590 591 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_CMAC_C) 592 CY_CRYPTO_INSTR_CMAC = 0x0Cu, 593 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_CMAC_C) */ 594 595 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 596 CY_CRYPTO_INSTR_SHA = 0x0Du, 597 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 598 599 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_HMAC_C) 600 CY_CRYPTO_INSTR_HMAC = 0x0Eu, 601 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_HMAC_C) */ 602 603 #if (CPUSS_CRYPTO_STR == 1) 604 CY_CRYPTO_INSTR_MEM_CPY = 0x0Fu, 605 CY_CRYPTO_INSTR_MEM_SET = 0x10u, 606 CY_CRYPTO_INSTR_MEM_CMP = 0x11u, 607 CY_CRYPTO_INSTR_MEM_XOR = 0x12u, 608 #endif /* #if (CPUSS_CRYPTO_STR == 1) */ 609 610 #if (CPUSS_CRYPTO_CRC == 1) && defined(CY_CRYPTO_CFG_CRC_C) 611 CY_CRYPTO_INSTR_CRC_INIT = 0x13u, 612 CY_CRYPTO_INSTR_CRC = 0x14u, 613 #endif /* (CPUSS_CRYPTO_CRC == 1) && defined(CY_CRYPTO_CFG_CRC_C) */ 614 615 #if (CPUSS_CRYPTO_DES == 1) && defined(CY_CRYPTO_CFG_DES_C) 616 CY_CRYPTO_INSTR_DES = 0x15u, 617 CY_CRYPTO_INSTR_3DES = 0x16u, 618 #endif /* (CPUSS_CRYPTO_DES == 1) && defined(CY_CRYPTO_CFG_DES_C) */ 619 620 #if (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_RSA_C) 621 CY_CRYPTO_INSTR_RSA_PROC = 0x17u, 622 CY_CRYPTO_INSTR_RSA_COEF = 0x18u, 623 624 #if defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) 625 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 626 CY_CRYPTO_INSTR_RSA_VER = 0x19u, 627 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 628 #endif /* defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) */ 629 630 #endif /* (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_RSA_C) */ 631 632 CY_CRYPTO_INSTR_SRV_INFO = 0x55u, 633 634 #if (CPUSS_CRYPTO_VU == 1) 635 #if defined(CY_CRYPTO_CFG_RSA_C) 636 CY_CRYPTO_INSTR_MEMBUF_SET = 0x56u, 637 CY_CRYPTO_INSTR_MEMBUF_ADDR = 0x57u, 638 CY_CRYPTO_INSTR_MEMBUF_SIZE = 0x58u, 639 #endif /* defined(CY_CRYPTO_CFG_RSA_C) */ 640 641 #if defined(CY_CRYPTO_CFG_ECP_C) 642 CY_CRYPTO_INSTR_ECC_GET_DP = 0x59u, 643 CY_CRYPTO_INSTR_ECC_ECP_MUL = 0x5Au, 644 #endif /* defined(CY_CRYPTO_CFG_ECP_C) */ 645 646 #if defined(CY_CRYPTO_CFG_ECDSA_GENKEY_C) 647 CY_CRYPTO_INSTR_ECP_GEN_PRIK = 0x5Bu, 648 CY_CRYPTO_INSTR_ECP_GEN_PUBK = 0x5Cu, 649 #endif /* defined(CY_CRYPTO_CFG_ECDSA_GENKEY_C) */ 650 651 #if defined(CY_CRYPTO_CFG_ECDSA_SIGN_C) 652 CY_CRYPTO_INSTR_ECDSA_SIGN = 0x5Du, 653 #endif /* defined(CY_CRYPTO_CFG_ECDSA_SIGN_C) */ 654 655 #if defined(CY_CRYPTO_CFG_ECDSA_VERIFY_C) 656 CY_CRYPTO_INSTR_ECDSA_VER = 0x5Eu 657 #endif /* defined(CY_CRYPTO_CFG_ECDSA_VERIFY_C) */ 658 #endif /* #if (CPUSS_CRYPTO_VU == 1) */ 659 660 } cy_en_crypto_comm_instr_t; 661 662 /** \endcond */ 663 664 /** 665 * \addtogroup group_crypto_data_structures 666 * \{ 667 */ 668 669 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) 670 671 /** The structure for storing the AES state. 672 * All fields for this structure are internal. Firmware never reads or 673 * writes these values. Firmware allocates the structure and provides the 674 * address of the structure to the driver in the function calls. Firmware must 675 * ensure that the defined instance of this structure remains in scope 676 * while the drive is in use. 677 */ 678 679 /* The structure to define used memory buffers */ 680 typedef struct 681 { 682 /** \cond INTERNAL */ 683 uint32_t key[CY_CRYPTO_AES_MAX_KEY_SIZE_U32]; 684 uint32_t keyInv[CY_CRYPTO_AES_MAX_KEY_SIZE_U32]; 685 uint32_t block0[CY_CRYPTO_AES_BLOCK_SIZE_U32]; 686 uint32_t block1[CY_CRYPTO_AES_BLOCK_SIZE_U32]; 687 uint32_t block2[CY_CRYPTO_AES_BLOCK_SIZE_U32]; 688 /** \endcond */ 689 } cy_stc_crypto_aes_buffers_t; 690 691 typedef struct 692 { 693 /** \cond INTERNAL */ 694 /** AES key length */ 695 cy_en_crypto_aes_key_length_t keyLength; 696 /** Pointer to AES work buffers */ 697 cy_stc_crypto_aes_buffers_t *buffers; 698 /** AES processed block index (for CMAC, SHA operations) */ 699 uint32_t blockIdx; 700 /** \endcond */ 701 } cy_stc_crypto_aes_state_t; 702 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) */ 703 704 #if (CPUSS_CRYPTO_GCM == 1u) && defined(CY_CRYPTO_CFG_GCM_C) 705 706 /** The structure for storing the AES GCM state. 707 * All fields for this structure are internal. Firmware never reads or 708 * writes these values. Firmware allocates the structure and provides the 709 * address of the structure to the driver in the function calls. Firmware must 710 * ensure that the defined instance of this structure remains in scope 711 * while the drive is in use. 712 */ 713 714 /* The structure to define used memory buffers */ 715 typedef struct 716 { 717 /** \cond INTERNAL */ 718 /** AES ECB buffer */ 719 cy_stc_crypto_aes_buffers_t aes_buffer; 720 /** AES GCM Hash Subkey */ 721 uint8_t h[CY_CRYPTO_AES_BLOCK_SIZE]; 722 /** AES GCM Initial Counter BLock*/ 723 uint8_t icb[CY_CRYPTO_AES_BLOCK_SIZE]; 724 /** AES GCM Counter Block */ 725 uint8_t cb[CY_CRYPTO_AES_BLOCK_SIZE]; 726 /** AES GCM Ghash buffer Block */ 727 uint8_t y[CY_CRYPTO_AES_BLOCK_SIZE]; 728 /** AES GCM temp buffer for AAD data */ 729 uint8_t temp[CY_CRYPTO_AES_BLOCK_SIZE]; 730 /** AES GCM aes data buffer*/ 731 uint8_t aes_data[CY_CRYPTO_AES_BLOCK_SIZE]; 732 /** \endcond */ 733 } cy_stc_crypto_aes_gcm_buffers_t; 734 735 typedef struct cy_stc_crypto_aes_gcm_state 736 { 737 /** \cond INTERNAL */ 738 /** AES GCM hash key pointer */ 739 uint8_t *h; 740 /**AES GCM Initial Counter block */ 741 uint8_t *icb; 742 /** AES GCM Counter block */ 743 uint8_t *cb; 744 /** Pointer to ghash buffer */ 745 uint8_t *y; 746 /** pointer to temp buffer*/ 747 uint8_t *temp; 748 /**Pointer to hold the last AES block*/ 749 uint8_t *aes_data; 750 /** AES GCM total data processed*/ 751 uint32_t data_size; 752 /** AES GCM total AAD data processed*/ 753 uint32_t aad_size; 754 /** AES GCM partial AAD data processed flag*/ 755 bool partial_aad_processed; 756 /**Mode of the AES GCM operation */ 757 cy_en_crypto_dir_mode_t mode; 758 /**Pointer to the AES buffer*/ 759 cy_stc_crypto_aes_buffers_t *aes_buffer; 760 /**AES state*/ 761 cy_stc_crypto_aes_state_t aesState; 762 /** \endcond */ 763 } cy_stc_crypto_aes_gcm_state_t; 764 765 #endif /* (CPUSS_CRYPTO_GCM == 1) && defined(CY_CRYPTO_CFG_GCM_C)*/ 766 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 767 768 /** The structure for storing the SHA state. 769 * All fields for the context structure are internal. Firmware never reads or 770 * writes these values. Firmware allocates the structure and provides the 771 * address of the structure to the driver in the function calls. Firmware must 772 * ensure that the defined instance of this structure remains in scope 773 * while the drive is in use. 774 */ 775 typedef struct 776 { 777 /** \cond INTERNAL */ 778 uint32_t mode; 779 uint32_t modeHw; 780 uint8_t *block; 781 uint32_t blockSize; 782 uint8_t *hash; 783 uint32_t hashSize; 784 uint8_t *roundMem; 785 uint32_t roundMemSize; 786 uint32_t messageSize; 787 uint32_t digestSize; 788 uint32_t blockIdx; 789 uint8_t const *initialHash; 790 /** \endcond */ 791 } cy_stc_crypto_sha_state_t; 792 793 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 794 795 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_HMAC_C) 796 797 /** The structure for storing the HMAC state. 798 * All fields for the context structure are internal. Firmware never reads or 799 * writes these values. Firmware allocates the structure and provides the 800 * address of the structure to the driver in the function calls. Firmware must 801 * ensure that the defined instance of this structure remains in scope 802 * while the drive is in use. 803 */ 804 805 typedef struct 806 { 807 /** \cond INTERNAL */ 808 /* Pointer to store the ipad */ 809 uint8_t *ipad; 810 811 /* Pointer to store the opad */ 812 uint8_t *opad; 813 814 /* Pointer to store the key */ 815 uint8_t *m0Key; 816 817 /* Pointer to store the sha buffer */ 818 void* sha_buffer; 819 820 /* Hash state*/ 821 cy_stc_crypto_sha_state_t hashState; 822 /** \endcond */ 823 } cy_stc_crypto_hmac_state_t; 824 825 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_HMAC_C) */ 826 827 #if (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_ECP_C) 828 /** A point on a ECC curve */ 829 typedef struct { 830 /** The x co-ordinate */ 831 void *x; 832 /** The y co-ordinate */ 833 void *y; 834 } cy_stc_crypto_ecc_point; 835 836 /** An ECC key type */ 837 typedef enum cy_en_crypto_ecc_key_type { 838 PK_PUBLIC = 0u, 839 PK_PRIVATE = 1u 840 } cy_en_crypto_ecc_key_type_t; 841 842 /** An ECC key */ 843 typedef struct { 844 /** Type of key, PK_PRIVATE or PK_PUBLIC */ 845 cy_en_crypto_ecc_key_type_t type; 846 /** See \ref cy_en_crypto_ecc_curve_id_t */ 847 cy_en_crypto_ecc_curve_id_t curveID; 848 /** The public key */ 849 cy_stc_crypto_ecc_point pubkey; 850 /** The private key */ 851 void *k; 852 } cy_stc_crypto_ecc_key; 853 #endif /* (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_ECP_C) */ 854 855 /** \} group_crypto_data_structures */ 856 857 /************************************************************* 858 * Structures used for communication between Client and Server 859 ***************************************************************/ 860 861 /** 862 * \addtogroup group_crypto_srv_data_structures 863 * \{ 864 */ 865 866 /** The structure for storing the crypto server context. 867 * All fields for the context structure are internal. Firmware never reads or 868 * writes these values. Firmware allocates the structure and provides the 869 * address of the structure to the driver in the function calls. Firmware must 870 * ensure that the defined instance of this structure remains in scope 871 * while the drive is in use. 872 */ 873 typedef struct 874 { 875 /** \cond INTERNAL */ 876 /** IPC communication channel number */ 877 uint32_t ipcChannel; 878 /** IPC acquire interrupt channel number */ 879 uint32_t acquireNotifierChannel; 880 /** IPC release interrupt channel number */ 881 cy_israddress getDataHandlerPtr; 882 /** Crypto hardware errors interrupt handler */ 883 cy_israddress errorHandlerPtr; 884 /** Acquire notifier interrupt configuration */ 885 cy_stc_sysint_t acquireNotifierConfig; 886 /** Crypto hardware errors interrupt configuration */ 887 cy_stc_sysint_t cryptoErrorIntrConfig; 888 /** Hardware error occurrence flag */ 889 bool isHwErrorOccured; 890 /** Hardware processing errors */ 891 cy_stc_crypto_hw_error_t hwErrorStatus; 892 /** \endcond */ 893 } cy_stc_crypto_server_context_t; 894 895 /** \} group_crypto_srv_data_structures */ 896 897 /** 898 * \addtogroup group_crypto_cli_data_structures 899 * \{ 900 */ 901 902 /** The structure for storing the crypto client context. 903 * All fields for the context structure are internal. Firmware never reads or 904 * writes these values. Firmware allocates the structure and provides the 905 * address of the structure to the driver in the function calls. Firmware must 906 * ensure that the defined instance of this structure remains in scope 907 * while the drive is in use. 908 */ 909 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) 910 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) typedef struct 911 #else 912 typedef struct 913 #endif 914 { 915 /** \cond INTERNAL */ 916 /** Operation instruction code */ 917 cy_en_crypto_comm_instr_t instr; 918 /** Response from executed crypto function */ 919 cy_en_crypto_status_t resp; 920 /** Hardware processing errors */ 921 cy_stc_crypto_hw_error_t hwErrorStatus; 922 /** IPC communication channel number */ 923 uint32_t ipcChannel; 924 /** IPC acquire interrupt channel number */ 925 uint32_t acquireNotifierChannel; 926 /** IPC release interrupt channel number */ 927 uint32_t releaseNotifierChannel; 928 /** User callback for Crypto HW calculation complete event */ 929 cy_crypto_callback_ptr_t userCompleteCallback; 930 /** Release notifier interrupt configuration */ 931 cy_stc_sysint_t releaseNotifierConfig; 932 /** Pointer to the crypto function specific context data */ 933 void *xdata; 934 /** \endcond */ 935 } cy_stc_crypto_context_t; 936 937 938 #if (CPUSS_CRYPTO_DES == 1) && defined(CY_CRYPTO_CFG_DES_C) 939 /** The structure for storing the DES context. 940 * All fields for the context structure are internal. Firmware never reads or 941 * writes these values. Firmware allocates the structure and provides the 942 * address of the structure to the driver in the function calls. Firmware must 943 * ensure that the defined instance of this structure remains in scope 944 * while the drive is in use. 945 */ 946 typedef struct 947 { 948 /** \cond INTERNAL */ 949 /** Operation direction (Encrypt / Decrypt) */ 950 cy_en_crypto_dir_mode_t dirMode; 951 /** Pointer to key data */ 952 uint32_t *key; 953 /** Pointer to data destination block */ 954 uint32_t *dst; 955 /** Pointer to data source block */ 956 uint32_t *src; 957 /** \endcond */ 958 } cy_stc_crypto_context_des_t; 959 #endif /* (CPUSS_CRYPTO_DES == 1) && defined(CY_CRYPTO_CFG_DES_C) */ 960 961 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) 962 /** The structure for storing the AES context. 963 * All fields for the context structure are internal. Firmware never reads or 964 * writes these values. Firmware allocates the structure and provides the 965 * address of the structure to the driver in the function calls. Firmware must 966 * ensure that the defined instance of this structure remains in scope 967 * while the drive is in use. 968 */ 969 typedef struct 970 { 971 /** \cond INTERNAL */ 972 /** AES state data */ 973 cy_stc_crypto_aes_state_t aesState; 974 /** Operation direction (Encrypt / Decrypt) */ 975 cy_en_crypto_dir_mode_t dirMode; 976 /** AES key length */ 977 cy_en_crypto_aes_key_length_t keyLength; 978 /** Pointer to AES key */ 979 uint32_t *key; 980 /** Operation data size */ 981 uint32_t srcSize; 982 /** Size of the last non-complete block (for CTR mode only) */ 983 uint32_t *srcOffset; 984 /** Initialization vector, in the CTR mode is used as nonceCounter */ 985 uint32_t *ivPtr; 986 /** AES processed block pointer (for CTR mode only) */ 987 uint32_t *streamBlock; 988 /** Pointer to data destination block */ 989 uint32_t *dst; 990 /** Pointer to data source block */ 991 uint32_t *src; 992 /** \endcond */ 993 } cy_stc_crypto_context_aes_t; 994 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) */ 995 996 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 997 /** The structure for storing the SHA context. 998 * All fields for the context structure are internal. Firmware never reads or 999 * writes these values. Firmware allocates the structure and provides the 1000 * address of the structure to the driver in the function calls. Firmware must 1001 * ensure that the defined instance of this structure remains in scope 1002 * while the drive is in use. 1003 */ 1004 typedef struct 1005 { 1006 /** \cond INTERNAL */ 1007 /** Pointer to data source block */ 1008 uint32_t *message; 1009 /** Operation data size */ 1010 uint32_t messageSize; 1011 /** Pointer to data destination block */ 1012 uint32_t *dst; 1013 /** SHA mode */ 1014 cy_en_crypto_sha_mode_t mode; 1015 /** Pointer to key data (for HMAC only) */ 1016 uint32_t *key; 1017 /** Key data length (for HMAC only) */ 1018 uint32_t keyLength; 1019 /** \endcond */ 1020 } cy_stc_crypto_context_sha_t; 1021 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 1022 1023 #if (CPUSS_CRYPTO_PR == 1) && defined(CY_CRYPTO_CFG_PRNG_C) 1024 /** The structure for storing the PRNG context. 1025 * All fields for the context structure are internal. Firmware never reads or 1026 * writes these values. Firmware allocates the structure and provides the 1027 * address of the structure to the driver in the function calls. Firmware must 1028 * ensure that the defined instance of this structure remains in scope 1029 * while the drive is in use. 1030 */ 1031 typedef struct 1032 { 1033 /** \cond INTERNAL */ 1034 uint32_t lfsr32InitState; /**< lfsr32 initialization data */ 1035 uint32_t lfsr31InitState; /**< lfsr31 initialization data */ 1036 uint32_t lfsr29InitState; /**< lfsr29 initialization data */ 1037 uint32_t max; /**< Maximum of the generated value */ 1038 uint32_t *prngNum; /**< Pointer to generated value */ 1039 /** \endcond */ 1040 } cy_stc_crypto_context_prng_t; 1041 #endif /* (CPUSS_CRYPTO_PR == 1) && defined(CY_CRYPTO_CFG_PRNG_C) */ 1042 1043 #if (CPUSS_CRYPTO_TR == 1) && defined(CY_CRYPTO_CFG_TRNG_C) 1044 /** \cond INTERNAL */ 1045 #define CY_CRYPTO_TR_RO_ENABLE (1U) 1046 #define CY_CRYPTO_TR_RO_DISABLE (0U) 1047 /** \endcond */ 1048 1049 /** \cond INTERNAL */ 1050 typedef enum 1051 { 1052 /** "Selection of the ring oscillator (RO) source: */ 1053 CY_CRYPTO_TR_SRC_RO11 = 0, /**< "0": fixed RO 11 bit. */ 1054 CY_CRYPTO_TR_SRC_RO15, /**< "1": fixed RO 15 bit. */ 1055 CY_CRYPTO_TR_SRC_GARO15, /**< "2": fixed Galois RO 15 bit. */ 1056 CY_CRYPTO_TR_SRC_GARO31, /**< "3": flexible Galois RO 31 bit. */ 1057 CY_CRYPTO_TR_SRC_FIRO15, /**< "4": fixed Fibonacci RO 15 bit. */ 1058 CY_CRYPTO_TR_SRC_FIRO31 /**< "5": flexible Fibonacci RO 31 bit. */ 1059 } cy_en_crypto_trng_ro_sel_t; 1060 /** \endcond */ 1061 1062 /****************************************** 1063 * Configuration structure 1064 ******************************************/ 1065 /** \cond INTERNAL */ 1066 typedef enum 1067 { 1068 /** "Selection of the bitstream: */ 1069 CY_CRYPTO_TRMON_BS_DAS = 0, /**< "0": DAS bitstream. */ 1070 CY_CRYPTO_TRMON_BS_RED, /**< "1": RED bitstream. */ 1071 CY_CRYPTO_TRMON_BS_TR, /**< "2": TR bitstream. */ 1072 CY_CRYPTO_TRMON_BS_UNDEF /**< "3": Undefined. */ 1073 } cy_en_crypto_trng_bs_sel_t; 1074 /** \endcond */ 1075 1076 /** The structure for storing the TRNG configuration. 1077 */ 1078 typedef struct 1079 { 1080 /** \cond INTERNAL */ 1081 /** 1082 * "Specifies the clock divider that is used to sample oscillator data. 1083 * This clock divider is wrt. "clk_sys". 1084 * "0": sample clock is "clk_sys". 1085 * "1": sample clock is "clk_sys"/2. 1086 * 1087 * "255": sample clock is "clk_sys"/256. */ 1088 uint8_t sampleClockDiv; 1089 /** 1090 * "Specifies the clock divider that is used to produce reduced bits. 1091 * "0": 1 reduced bit is produced for each sample. 1092 * "1": 1 reduced bit is produced for each 2 samples. 1093 * 1094 * "255": 1 reduced bit is produced for each 256 samples. */ 1095 uint8_t reducedClockDiv; 1096 /** 1097 * Specifies an initialization delay: number of removed/dropped samples 1098 * before reduced bits are generated. This field should be programmed 1099 * in the range [1, 255]. After starting the oscillators, 1100 * at least the first 2 samples should be removed/dropped to clear the state 1101 * of internal synchronizers. In addition, it is advised to drop 1102 * at least the second 2 samples from the oscillators (to circumvent 1103 * the semi-predictable oscillator startup behavior). 1104 * 1105 * This result in the default field value of "3". 1106 * Field encoding is as follows: 1107 * "0": 1 sample is dropped. 1108 * "1": 2 samples are dropped. 1109 * 1110 * "255": 256 samples are dropped. 1111 * 1112 * The TR_INITIALIZED interrupt cause is set to '1', when 1113 * the initialization delay is passed. */ 1114 uint8_t initDelay; 1115 /** 1116 * "Specifies if the "von Neumann corrector" is disabled or enabled: 1117 * '0': disabled. 1118 * '1': enabled. 1119 * The "von Neumann corrector" post-processes the reduced bits 1120 * to remove a '0' or '1' bias. The corrector operates on reduced bit pairs 1121 * ("oldest bit, newest bit"): 1122 * "00": no bit is produced. 1123 * "01": '0' bit is produced (oldest bit). 1124 * "10": '1' bit is produced (oldest bit). 1125 * "11": no bit is produced. 1126 * Note that the corrector produces bits at a random pace and at a frequency 1127 * that is 1/4 of the reduced bit frequency (reduced bits are processed 1128 * in pairs, and half of the pairs do NOT produce a bit). */ 1129 bool vnCorrectorEnable; 1130 /** 1131 * Specifies if TRNG functionality is stopped on an adaptive proportion 1132 * test detection (when HW sets INTR.TR_AP_DETECT to '1'): 1133 * '0': Functionality is NOT stopped. 1134 * '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). */ 1135 bool stopOnAPDetect; 1136 /** 1137 * Specifies if TRNG functionality is stopped on a repetition 1138 * count test detection (when HW sets INTR.TR_RC_DETECT to '1'): 1139 * '0': Functionality is NOT stopped. 1140 * '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). */ 1141 bool stopOnRCDetect; 1142 1143 /** 1144 * FW sets this field to '1' to enable the ring oscillator with 11 inverters. 1145 */ 1146 bool ro11Enable; 1147 /** 1148 * FW sets this field to '1' to enable the ring oscillator with 15 inverters. 1149 */ 1150 bool ro15Enable; 1151 /** 1152 * FW sets this field to '1' to enable the fixed Galois ring oscillator 1153 * with 15 inverters. */ 1154 bool garo15Enable; 1155 /** 1156 * FW sets this field to '1' to enable the programmable Galois ring 1157 * oscillator with up to 31 inverters. The TR_GARO_CTL register specifies 1158 * the programmable polynomial. */ 1159 bool garo31Enable; 1160 /** 1161 * FW sets this field to '1' to enable the fixed Fibonacci ring oscillator 1162 * with 15 inverters. */ 1163 bool firo15Enable; 1164 /** 1165 * FW sets this field to '1' to enable the programmable Fibonacci ring 1166 * oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies 1167 * the programmable polynomial. */ 1168 bool firo31Enable; 1169 1170 /** 1171 * Polynomial for programmable Galois ring oscillator. 1172 * The polynomial is represented WITHOUT 1173 * the high order bit (this bit is always assumed '1'). 1174 * The polynomial should be aligned such that the more 1175 * significant bits (bit 30 and down) contain the polynomial 1176 * and the less significant bits (bit 0 and up) contain padding '0's. */ 1177 uint32_t garo31Poly; 1178 1179 /** 1180 * Polynomial for programmable Fibonacci ring oscillator. 1181 * The polynomial is represented WITHOUT 1182 * the high order bit (this bit is always assumed '1'). 1183 * The polynomial should be aligned such that the more 1184 * significant bits (bit 30 and down) contain the polynomial 1185 * and the less significant bits (bit 0 and up) contain padding '0's. */ 1186 uint32_t firo31Poly; 1187 1188 /** 1189 * Selection of the bitstream: 1190 * "0": DAS bitstream. 1191 * "1": RED bitstream. 1192 * "2": TR bitstream. 1193 * "3": Undefined. */ 1194 cy_en_crypto_trng_bs_sel_t monBitStreamSelect; 1195 1196 /** 1197 * Cutoff count (legal range is [1, 255]): 1198 * "0": Illegal. 1199 * "1": 1 repetition. 1200 * .. 1201 * "255": 255 repetitions. */ 1202 uint8_t monCutoffCount8; 1203 1204 /** 1205 * Cutoff count (legal range is [1, 65535]). 1206 * "0": Illegal. 1207 * "1": 1 occurrence. 1208 * ... 1209 * "65535": 65535 occurrences. */ 1210 uint16_t monCutoffCount16; 1211 /** 1212 * Window size (minus 1) : 1213 * "0": 1 bit. 1214 * ... 1215 * "65535": 65536 bits. */ 1216 uint16_t monWindowSize; 1217 /** \endcond */ 1218 } cy_stc_crypto_trng_config_t; 1219 1220 /** The structure for storing the TRNG context. 1221 * All fields for the context structure are internal. Firmware never reads or 1222 * writes these values. Firmware allocates the structure and provides the 1223 * address of the structure to the driver in the function calls. Firmware must 1224 * ensure that the defined instance of this structure remains in scope 1225 * while the drive is in use. 1226 */ 1227 typedef struct 1228 { 1229 /** \cond INTERNAL */ 1230 /** 1231 The polynomial for the programmable Galois ring oscillator (TR_GARO_CTL). 1232 The polynomial is represented WITHOUT the high order bit (this bit is 1233 always assumed '1'). 1234 The polynomial should be aligned so that more significant bits 1235 (bit 30 and down) contain the polynomial and less significant bits 1236 (bit 0 and up) contain padding '0's. */ 1237 uint32_t GAROPol; 1238 1239 /** 1240 The polynomial for the programmable Fibonacci ring oscillator(TR_FIRO_CTL). 1241 The polynomial is represented WITHOUT the high order bit (this bit is 1242 always assumed '1'). 1243 The polynomial should be aligned so that more significant bits 1244 (bit 30 and down) contain the polynomial and less significant bits 1245 (bit 0 and up) contain padding '0's. */ 1246 uint32_t FIROPol; 1247 /** Maximum of the generated value */ 1248 uint32_t max; 1249 /** Pointer to generated value */ 1250 uint32_t *trngNum; 1251 /** \endcond */ 1252 } cy_stc_crypto_context_trng_t; 1253 #endif /* (CPUSS_CRYPTO_TR == 1) && defined(CY_CRYPTO_CFG_TRNG_C) */ 1254 1255 #if (CPUSS_CRYPTO_STR == 1) 1256 /** The structure for storing the string context. 1257 * All fields for the context structure are internal. Firmware never reads or 1258 * writes these values. Firmware allocates the structure and provides the 1259 * address of the structure to the driver in the function calls. Firmware must 1260 * ensure that the defined instance of this structure remains in scope 1261 * while the drive is in use. 1262 */ 1263 typedef struct 1264 { 1265 /** \cond INTERNAL */ 1266 void const *src0; /**< Pointer to 1-st string source */ 1267 void const *src1; /**< Pointer to 2-nd string source */ 1268 void *dst; /**< Pointer to string destination */ 1269 uint32_t dataSize; /**< Operation data size */ 1270 uint32_t data; /**< Operation data value (for memory setting) */ 1271 /** \endcond */ 1272 } cy_stc_crypto_context_str_t; 1273 #endif /* #if (CPUSS_CRYPTO_STR == 1) */ 1274 1275 #if (CPUSS_CRYPTO_CRC == 1) && defined(CY_CRYPTO_CFG_CRC_C) 1276 /** The structure for storing the CRC context. 1277 * All fields for the context structure are internal. Firmware never reads or 1278 * writes these values. Firmware allocates the structure and provides the 1279 * address of the structure to the driver in the function calls. Firmware must 1280 * ensure that the defined instance of this structure remains in scope 1281 * while the drive is in use. 1282 */ 1283 typedef struct 1284 { 1285 /** \cond INTERNAL */ 1286 void* data; /**< Pointer to data source block */ 1287 uint32_t dataSize; /**< Operation data size */ 1288 uint32_t *crc; /**< Pointer to CRC destination variable */ 1289 uint32_t polynomial; /**< Polynomial for CRC calculate */ 1290 uint32_t lfsrInitState; /**< CRC calculation initial value */ 1291 uint32_t dataReverse; /**< Input data reverse flag */ 1292 uint32_t dataXor; /**< Input data XOR flag */ 1293 uint32_t remReverse; /**< Output data reverse flag */ 1294 uint32_t remXor; /**< Output data XOR flag */ 1295 /** \endcond */ 1296 } cy_stc_crypto_context_crc_t; 1297 #endif /* (CPUSS_CRYPTO_CRC == 1) && defined(CY_CRYPTO_CFG_CRC_C) */ 1298 1299 #if (CPUSS_CRYPTO_VU == 1) 1300 #if defined(CY_CRYPTO_CFG_RSA_C) 1301 /** The structure for storing the RSA context. 1302 * All fields for the context structure are internal. Firmware never reads or 1303 * writes these values. Firmware allocates the structure and provides the 1304 * address of the structure to the driver in function calls. Firmware must 1305 * ensure that the defined instance of this structure remains in scope 1306 * while the drive is in use. 1307 */ 1308 typedef struct 1309 { 1310 /** \cond INTERNAL */ 1311 /** Pointer to key data */ 1312 cy_stc_crypto_rsa_pub_key_t const *key; 1313 /** Pointer to data source block */ 1314 uint32_t const *message; 1315 /** Operation data size */ 1316 uint32_t messageSize; 1317 /** Pointer to data destination block */ 1318 uint32_t *result; 1319 /** \endcond */ 1320 } cy_stc_crypto_context_rsa_t; 1321 1322 #if defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) && (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 1323 /** The structure for storing the RSA verification context. 1324 * All fields for the context structure are internal. Firmware never reads or 1325 * writes these values. Firmware allocates the structure and provides the 1326 * address of the structure to the driver in the function calls. Firmware must 1327 * ensure that the defined instance of this structure remains in scope 1328 * while the drive is in use. 1329 */ 1330 typedef struct 1331 { 1332 /** \cond INTERNAL */ 1333 /** Pointer to verification result /ref cy_en_crypto_rsa_ver_result_t */ 1334 cy_en_crypto_rsa_ver_result_t *verResult; 1335 /** SHA digest type, used with SHA calculation of the message */ 1336 cy_en_crypto_sha_mode_t digestType; 1337 /** SHA digest of the message, calculated with digestType */ 1338 uint32_t const *hash; 1339 /** Previously decrypted RSA signature */ 1340 uint32_t const *decryptedSignature; 1341 /** Length of the decrypted RSA signature */ 1342 uint32_t decryptedSignatureLength; 1343 /** \endcond */ 1344 } cy_stc_crypto_context_rsa_ver_t; 1345 #endif /* defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) && (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 1346 #endif /* defined(CY_CRYPTO_CFG_RSA_C) */ 1347 1348 #if defined(CY_CRYPTO_CFG_ECDSA_C) 1349 /** The structure for storing the ECC operations context. 1350 * All fields for the context structure are internal. Firmware never reads or 1351 * writes these values. Firmware allocates the structure and provides the 1352 * address of the structure to the driver in function calls. Firmware must 1353 * ensure that the defined instance of this structure remains in scope 1354 * while the drive is in use. 1355 */ 1356 typedef struct 1357 { 1358 /** \cond INTERNAL */ 1359 /** Elliptic curve ID */ 1360 cy_en_crypto_ecc_curve_id_t curveID; 1361 /** Pointer to key data */ 1362 const cy_stc_crypto_ecc_key *key; 1363 /** Operation data length */ 1364 uint32_t datalen; 1365 /** Pointer to the first source data block */ 1366 const uint8_t *src0; 1367 /** Pointer to the second source data block */ 1368 const uint8_t *src1; 1369 /** Pointer to the third source data block */ 1370 const uint8_t *src2; 1371 /** Pointer to the first destination data block */ 1372 uint8_t *dst0; 1373 /** Pointer to the second destination data block */ 1374 uint8_t *dst1; 1375 /** \endcond */ 1376 } cy_stc_crypto_context_ecc_t; 1377 #endif /* defined(CY_CRYPTO_CFG_ECDSA_C) */ 1378 #endif /* #if (CPUSS_CRYPTO_VU == 1) */ 1379 1380 1381 #if defined(CY_CRYPTO_CFG_CHACHA_ENABLED) && (CPUSS_CRYPTO_CHACHA == 1) 1382 1383 /** Defines the chacha state size (in bytes) */ 1384 #define CHACHA_STATE_SIZE 64u 1385 1386 /** Defines the chacha key stream size (in bytes) */ 1387 #define CHACHA_KEYSTREAM_SIZE 64u 1388 1389 /** Defines the chacha state block size (in bytes) */ 1390 #define CHACHA_BLOCK_SIZE 64u 1391 1392 /** \cond INTERNAL */ 1393 1394 /** Defines the chacha key size (in bytes) */ 1395 #define CHACHA_KEY_SIZE 32u 1396 1397 /** Defines the chacha nonce size (in bytes) */ 1398 #define CHACHA_NONCE_SIZE 12u 1399 1400 /** Defines the chacha counter size (in bytes) */ 1401 #define CHACHA_COUNTER_SIZE 4u 1402 1403 /** Defines the chacha const size (in bytes) */ 1404 #define CHACHA_CONST_SIZE 16u 1405 /** \endcond */ 1406 1407 typedef struct 1408 { 1409 /** \cond INTERNAL */ 1410 1411 /** buffer to store the constant*/ 1412 uint32_t constant[CHACHA_CONST_SIZE/4u]; 1413 1414 /** buffer to store the chacha key*/ 1415 uint8_t key[CHACHA_KEY_SIZE]; 1416 1417 /** To store the counter*/ 1418 uint32_t counter; 1419 1420 /** buffer to store the nonce*/ 1421 uint8_t nonce[CHACHA_NONCE_SIZE]; 1422 /** \endcond */ 1423 }cy_stc_crypto_v2_chacha_input_buffer; 1424 1425 typedef struct 1426 { 1427 /** \cond INTERNAL */ 1428 /** The pointer to store chacha state */ 1429 cy_stc_crypto_v2_chacha_input_buffer *state; 1430 /** The pointer to chacha key stream */ 1431 uint8_t *key; 1432 /** To store the chacha key bytes used */ 1433 uint8_t keyIndexUsed; 1434 /** To store the rounds for the chacha operation*/ 1435 uint8_t round; 1436 /** \endcond */ 1437 } cy_stc_crypto_chacha_state_t; 1438 1439 #endif 1440 1441 #if (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_POLY1305_ENABLED) 1442 1443 /** Defines the poly1305 block size (in bytes) */ 1444 #define CY_CRYPTO_POLY1305_BLOCK_SIZE (16u) 1445 1446 #endif 1447 1448 /** \} group_crypto_cli_data_structures */ 1449 1450 #if defined(__cplusplus) 1451 } 1452 #endif 1453 1454 #endif /* defined(CY_IP_MXCRYPTO) */ 1455 1456 #endif /* #if !defined (CY_CRYPTO_COMMON_H) */ 1457 1458 1459 /* [] END OF FILE */ 1460
