Searched refs:pll (Results 1 – 11 of 11) sorted by relevance
| /hal_infineon-3.4.0/mtb-pdl-cat1/udd/devices/MXS40/PSoC6A2M/studio_3.0/ |
| D | clocksResourceMap.txt | 13 PLL 0 srss[0].clock[0].pll[0]
14 PLL 1 srss[0].clock[0].pll[1]
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| /hal_infineon-3.4.0/mtb-pdl-cat1/udd/devices/MXS40/PSoC6A2M/studio_4.0/ |
| D | clocksResourceMap.txt | 13 PLL 0 srss[0].clock[0].pll[0]
14 PLL 1 srss[0].clock[0].pll[1]
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| /hal_infineon-3.4.0/mtb-hal-cat1/COMPONENT_PSOC6HAL/source/ |
| D | cyhal_usb_dev.c | 113 static cy_rslt_t _cyhal_usb_dev_init_pll(uint32_t clock, uint32_t pll, uint32_t target_freq);
239 static cy_rslt_t _cyhal_usb_dev_init_pll(uint32_t clock, uint32_t pll, uint32_t target_freq) in _cyhal_usb_dev_init_pll() argument
243 Cy_SysClk_PllDisable(pll); in _cyhal_usb_dev_init_pll()
244 Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t)(pll)); in _cyhal_usb_dev_init_pll()
251 Cy_SysClk_ClkPathSetSource(pll, CY_SYSCLK_CLKPATH_IN_IMO); in _cyhal_usb_dev_init_pll()
252 cy_rslt_t result = Cy_SysClk_PllConfigure(pll, &cfg); in _cyhal_usb_dev_init_pll()
256 result = Cy_SysClk_PllEnable(pll, 1000000); in _cyhal_usb_dev_init_pll()
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| /hal_infineon-3.4.0/mtb-pdl-cat1/drivers/source/ |
| D | cy_pra_cfg.c | 77 …ic cy_en_pra_status_t Cy_PRA_ValidatePLL(const cy_stc_pra_system_config_t *devConfig, uint8_t pll);
1331 …tic cy_en_pra_status_t Cy_PRA_ValidatePLL(const cy_stc_pra_system_config_t *devConfig, uint8_t pll) in Cy_PRA_ValidatePLL() argument
1337 if ((pll == CY_PRA_DEFAULT_ZERO) || (pll > CY_SRSS_NUM_PLL)) in Cy_PRA_ValidatePLL()
1342 if (pll == CY_PRA_CLKPLL_1) in Cy_PRA_ValidatePLL()
1350 else if (pll == CY_PRA_CLKPLL_2) in Cy_PRA_ValidatePLL()
1396 if (outFreq != Cy_PRA_CalculatePLLOutFreq(pll, devConfig)) in Cy_PRA_ValidatePLL()
2466 uint32_t Cy_PRA_CalculatePLLOutFreq(uint8_t pll, const cy_stc_pra_system_config_t *devConfig) in Cy_PRA_CalculatePLLOutFreq() argument
2474 if ((pll > CY_PRA_DEFAULT_ZERO) && (pll <= CY_SRSS_NUM_PLL)) /* 0 is invalid pll number */ in Cy_PRA_CalculatePLLOutFreq()
2476 if (pll == CY_PRA_CLKPLL_1) in Cy_PRA_CalculatePLLOutFreq()
2484 else if (pll == CY_PRA_CLKPLL_2) in Cy_PRA_CalculatePLLOutFreq()
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| /hal_infineon-3.4.0/mtb-pdl-cat1/udd/devices/MXS40/PSoC6A512K/studio_3.0/ |
| D | clocksResourceMap.txt | 12 PLL 0 srss[0].clock[0].pll[0]
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| /hal_infineon-3.4.0/mtb-pdl-cat1/udd/devices/MXS40/PSoC6A512K/studio_4.0/ |
| D | clocksResourceMap.txt | 12 PLL 0 srss[0].clock[0].pll[0]
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| /hal_infineon-3.4.0/mtb-pdl-cat1/udd/devices/MXS40/PSoC6A256K/studio_3.0/ |
| D | clocksResourceMap.txt | 12 PLL 0 srss[0].clock[0].pll[0]
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| /hal_infineon-3.4.0/mtb-pdl-cat1/udd/devices/MXS40/PSoC6A256K/studio_4.0/ |
| D | clocksResourceMap.txt | 12 PLL 0 srss[0].clock[0].pll[0]
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| /hal_infineon-3.4.0/mtb-pdl-cat1/udd/devices/MXS40/PSoC6ABLE2/studio_3.0/ |
| D | clocksResourceMap.txt | 14 PLL 0 srss[0].clock[0].pll[0]
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| /hal_infineon-3.4.0/mtb-pdl-cat1/udd/devices/MXS40/PSoC6ABLE2/studio_4.0/ |
| D | clocksResourceMap.txt | 14 PLL 0 srss[0].clock[0].pll[0]
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| /hal_infineon-3.4.0/mtb-pdl-cat1/drivers/include/ |
| D | cy_pra_cfg.h | 357 uint32_t Cy_PRA_CalculatePLLOutFreq(uint8_t pll, const cy_stc_pra_system_config_t *devConfig);
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