Searched refs:memory (Results 1 – 25 of 146) sorted by relevance
123456
| /hal_infineon-3.4.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| D | cyb06xx7_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
70 ; You can assign sections to this memory region for only one of the cores.
71 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
72 ; Therefore, repurposing this memory region will prevent such middleware from operation.
76 ; The following defines describe device specific memory regions and must not be changed.
77 ; External memory
|
| D | cyb06xxa_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
70 ; You can assign sections to this memory region for only one of the cores.
71 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
72 ; Therefore, repurposing this memory region will prevent such middleware from operation.
76 ; The following defines describe device specific memory regions and must not be changed.
77 ; External memory
|
| D | cyb06xx7_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
64 ; You can assign sections to this memory region for only one of the cores.
65 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
66 ; Therefore, repurposing this memory region will prevent such middleware from operation.
70 ; The following defines describe device specific memory regions and must not be changed.
71 ; External memory
|
| D | cyb06xxa_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
64 ; You can assign sections to this memory region for only one of the cores.
65 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
66 ; Therefore, repurposing this memory region will prevent such middleware from operation.
70 ; The following defines describe device specific memory regions and must not be changed.
71 ; External memory
|
| D | cys06xxa_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
64 ; You can assign sections to this memory region for only one of the cores.
65 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
66 ; Therefore, repurposing this memory region will prevent such middleware from operation.
70 ; The following defines describe device specific memory regions and must not be changed.
71 ; External memory
|
| D | cy8c6xx5_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx6_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx7_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx8_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xxa_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx5_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cy8c6xx6_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cy8c6xx7_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cy8c6xx8_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| D | cy8c6xxa_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
50 ; Using this memory region for other purposes will lead to unexpected behavior.
63 ; You can assign sections to this memory region for only one of the cores.
64 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 ; Therefore, repurposing this memory region will prevent such middleware from operation.
69 ; The following defines describe device specific memory regions and must not be changed.
90 ; External memory
|
| /hal_infineon-3.4.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| D | cy8c6xx5_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
92 ; The defines below describe the location and size of blocks of memory in the target.
93 ; Use these defines to specify the memory regions available for allocation.
95 ; The following defines control RAM and flash memory allocation for the CM0+ core.
96 ; You can change the memory allocation by editing the RAM and Flash defines.
98 ; Using this memory region for other purposes will lead to unexpected behavior.
113 ; You can assign sections to this memory region for only one of the cores.
114 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
115 ; Therefore, repurposing this memory region will prevent such middleware from operation.
119 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx6_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
92 ; The defines below describe the location and size of blocks of memory in the target.
93 ; Use these defines to specify the memory regions available for allocation.
95 ; The following defines control RAM and flash memory allocation for the CM0+ core.
96 ; You can change the memory allocation by editing the RAM and Flash defines.
98 ; Using this memory region for other purposes will lead to unexpected behavior.
113 ; You can assign sections to this memory region for only one of the cores.
114 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
115 ; Therefore, repurposing this memory region will prevent such middleware from operation.
119 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx7_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
92 ; The defines below describe the location and size of blocks of memory in the target.
93 ; Use these defines to specify the memory regions available for allocation.
95 ; The following defines control RAM and flash memory allocation for the CM0+ core.
96 ; You can change the memory allocation by editing the RAM and Flash defines.
98 ; Using this memory region for other purposes will lead to unexpected behavior.
113 ; You can assign sections to this memory region for only one of the cores.
114 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
115 ; Therefore, repurposing this memory region will prevent such middleware from operation.
119 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx8_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
92 ; The defines below describe the location and size of blocks of memory in the target.
93 ; Use these defines to specify the memory regions available for allocation.
95 ; The following defines control RAM and flash memory allocation for the CM0+ core.
96 ; You can change the memory allocation by editing the RAM and Flash defines.
98 ; Using this memory region for other purposes will lead to unexpected behavior.
113 ; You can assign sections to this memory region for only one of the cores.
114 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
115 ; Therefore, repurposing this memory region will prevent such middleware from operation.
119 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xxa_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
92 ; The defines below describe the location and size of blocks of memory in the target.
93 ; Use these defines to specify the memory regions available for allocation.
95 ; The following defines control RAM and flash memory allocation for the CM0+ core.
96 ; You can change the memory allocation by editing the RAM and Flash defines.
98 ; Using this memory region for other purposes will lead to unexpected behavior.
113 ; You can assign sections to this memory region for only one of the cores.
114 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
115 ; Therefore, repurposing this memory region will prevent such middleware from operation.
119 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| /hal_infineon-3.4.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| D | cy8c6xx5_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx6_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx7_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xx8_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
| D | cy8c6xxa_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
|
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