Searched refs:clkSel (Results 1 – 4 of 4) sorted by relevance
572 void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel);574 void Cy_RTC_SelectClockSource(cy_rtc_clk_select_sources_t clkSel);829 #define CY_RTC_IS_CLK_VALID(clkSel) (((clkSel) == CY_RTC_FREQ_WCO_32768_HZ) || \ argument830 ((clkSel) == CY_RTC_FREQ_60_HZ) || \831 ((clkSel) == CY_RTC_FREQ_50_HZ))834 #define CY_RTC_IS_SRC_CLK_SELECT_VALID(clkSel) (((clkSel) == CY_RTC_CLK_SELECT_WCO) |… argument835 ((clkSel) == CY_RTC_CLK_SELECT_ALTBAK) || \836 ((clkSel) == CY_RTC_CLK_SELECT_ILO) || \837 … ((clkSel) == CY_RTC_CLK_SELECT_LPECO_PRESCALER) || \838 ((clkSel) == CY_RTC_CLK_SELECT_PILO))
593 #define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_OUTPUT_CLK == (cy_en_smif_clk_select_t)(c… argument594 … (CY_SMIF_SEL_INVERTED_OUTPUT_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \595 … (CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \596 … (CY_SMIF_SEL_INVERTED_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \597 … (CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \598 … (CY_SMIF_SEL_INVERTED_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)))600 #define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)…601 … (CY_SMIF_SEL_INVERTED_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \602 … (CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \603 … (CY_SMIF_SEL_INVERTED_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)))
854 void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel) in Cy_RTC_SelectFrequencyPrescaler() argument856 CY_ASSERT_L3(CY_RTC_IS_CLK_VALID(clkSel)); in Cy_RTC_SelectFrequencyPrescaler()858 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, BACKUP_CTL_PRESCALER, (uint32_t) clkSel)); in Cy_RTC_SelectFrequencyPrescaler()872 void Cy_RTC_SelectClockSource(cy_rtc_clk_select_sources_t clkSel) in Cy_RTC_SelectClockSource() argument874 CY_ASSERT_L3(CY_RTC_IS_SRC_CLK_SELECT_VALID(clkSel)); in Cy_RTC_SelectClockSource()876 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, BACKUP_CTL_CLK_SEL, (uint32_t) clkSel)); in Cy_RTC_SelectClockSource()
888 …false == cfg->config->rx_config->enable) || (CY_TDM_SEL_MCLK_IN == cfg->config->rx_config->clkSel)) in _cyhal_audioss_init_cfg()889 …alse == cfg->config->tx_config->enable) || (CY_TDM_SEL_MCLK_IN == cfg->config->tx_config->clkSel)); in _cyhal_audioss_init_cfg()1541 …pdl_config->tx_config->clkSel = (cy_en_tdm_clock_sel_t)_FLD2VAL(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF… in _cyhal_audioss_reconstruct_pdl_config()1562 …pdl_config->rx_config->clkSel = (cy_en_tdm_clock_sel_t)_FLD2VAL(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF… in _cyhal_audioss_reconstruct_pdl_config()1683 pdl_config->tx_config->clkSel = mclk_tx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()1702 pdl_config->rx_config->clkSel = mclk_rx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()
