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Searched refs:TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW2 (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.4.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_03_config.h825 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW2 = 0x00000909u, /* tcpwm[0].tr_underflow[2] */ enumerator
Dpsoc6_02_config.h1216 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW2 = 0x00000909u, /* tcpwm[0].tr_underflow[2] */ enumerator