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Searched refs:TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW0 (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.4.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_03_config.h208 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW0 = 0x00000221u, /* tcpwm[1].tr_overflow[0] */ enumerator
Dpsoc6_02_config.h311 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW0 = 0x00000221u, /* tcpwm[1].tr_overflow[0] */ enumerator