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Searched refs:MIRRSTS (Results 1 – 8 of 8) sorted by relevance

/hal_infineon-3.4.0/XMCLib/drivers/src/
Dxmc4_scu.c475 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) in XMC_SCU_WriteToRetentionMemory()
495 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) in XMC_SCU_ReadFromRetentionMemory()
948 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) in XMC_SCU_HIB_SetRtcClockSource()
959 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) in XMC_SCU_HIB_SetStandbyClockSource()
1251 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) in XMC_SCU_HIB_EnableInternalSlowClock()
1261 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) in XMC_SCU_HIB_DisableInternalSlowClock()
1270 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCLR_Msk) in XMC_SCU_HIB_ClearEventStatus()
1279 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDSET_Msk) in XMC_SCU_HIB_TriggerEvent()
1299 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) in XMC_SCU_HIB_EnableEvent()
1319 while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) in XMC_SCU_HIB_DisableEvent()
[all …]
/hal_infineon-3.4.0/XMCLib/devices/XMC4500/Source/
Dsystem_XMC4500.c396 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) in SystemCoreClockSetup()
403 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) in SystemCoreClockSetup()
412 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk) in SystemCoreClockSetup()
426 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) in SystemCoreClockSetup()
/hal_infineon-3.4.0/XMCLib/devices/XMC4700/Source/
Dsystem_XMC4700.c459 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) in SystemCoreClockSetup()
466 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) in SystemCoreClockSetup()
475 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk) in SystemCoreClockSetup()
489 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) in SystemCoreClockSetup()
/hal_infineon-3.4.0/XMCLib/devices/XMC4800/Source/
Dsystem_XMC4800.c512 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) in SystemCoreClockSetup()
519 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) in SystemCoreClockSetup()
528 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk) in SystemCoreClockSetup()
542 while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) in SystemCoreClockSetup()
/hal_infineon-3.4.0/XMCLib/drivers/inc/
Dxmc_scu.h545 return(SCU_GENERAL->MIRRSTS); in XMC_SCU_GetMirrorStatus()
/hal_infineon-3.4.0/XMCLib/devices/XMC4500/Include/
DXMC4500.h989 …__I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register… member
/hal_infineon-3.4.0/XMCLib/devices/XMC4700/Include/
DXMC4700.h1017 …__I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register… member
/hal_infineon-3.4.0/XMCLib/devices/XMC4800/Include/
DXMC4800.h1025 …__I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register… member