1 /***************************************************************************//**
2 * \file cy_dma.h
3 * \version 2.40
4 *
5 * \brief
6 * The header file of the DMA driver.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2016-2020 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_dma
28 * \{
29 * Configures a DMA channel and its descriptor(s).
30 *
31 * The functions and other declarations used in this driver are in cy_dma.h.
32 * You can include cy_pdl.h to get access to all functions
33 * and declarations in the PDL.
34 *
35 * The DMA channel can be used in any project to transfer data
36 * without CPU intervention basing on a hardware trigger signal from another component.
37 *
38 * A device may support more than one DMA hardware block. Each block has a set of
39 * registers, a base hardware address, and supports multiple channels.
40 * Many API functions for the DMA driver require a base hardware address and
41 * channel number. Ensure that you use the correct hardware address for the DMA block in use.
42 *
43 * Features:
44 * * Multiple DW blocks (device specific)
45 * * Multiple channels per each DW block (device specific)
46 * * Four priority levels for each channel
47 * * Byte, half-word (2-byte), and word (4-byte) transfers
48 * * Configurable source and destination addresses
49 * * CRC calculation support (only for CPUSS_ver2)
50 *
51 * \section group_dma_configuration Configuration Considerations
52 *
53 * To set up a DMA driver, initialize a descriptor,
54 * initialize and enable a channel, and enable the DMA block.
55 *
56 * To set up a descriptor, provide the configuration parameters for the
57 * descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the
58 * \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can
59 * modify the source and destination addresses dynamically by calling
60 * \ref Cy_DMA_Descriptor_SetSrcAddress and \ref Cy_DMA_Descriptor_SetDstAddress.
61 *
62 * To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t
63 * structure. Call the \ref Cy_DMA_Channel_Init function, specifying the channel
64 * number. Use \ref Cy_DMA_Channel_Enable to enable the configured DMA channel.
65 *
66 * Call \ref Cy_DMA_Channel_Enable for each DMA channel in use.
67 *
68 * When configured, another peripheral typically triggers the DMA. The trigger is
69 * connected to the DMA using the trigger multiplexer. The trigger multiplexer
70 * driver has a software trigger you can use in firmware to trigger the DMA. See the
71 * <a href="group__group__trigmux.html">Trigger Multiplexer</a> documentation.
72 *
73 * The following is a simplified structure of the DMA driver API interdependencies
74 * in a typical user application:
75 * \image html dma.png
76 *
77 * <B>NOTE:</B> Even if a DMA channel is enabled, it is not operational until
78 * the DMA block is enabled using function \ref Cy_DMA_Enable.\n
79 * <B>NOTE:</B> If the DMA descriptor is configured to generate an interrupt,
80 * the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask
81 * function for each DMA channel.
82 *
83 * For example:
84 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
85 *
86 * \section group_dma_more_information More Information.
87 * See: the DMA chapter of the device technical reference manual (TRM);
88 * the DMA Component datasheet;
89 * CE219940 - PSoC 6 MCU Multiple DMA Concatenation.
90 *
91 * \section group_dma_changelog Changelog
92 *
93 * <table class="doxtable">
94 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
95 * <tr>
96 * <td>2.40</td>
97 * <td>Minor Bug fixes.</td>
98 * <td>Check for valid parameters.</td>
99 * </tr>
100 * <tr>
101 * <td>2.30</td>
102 * <td>Fixed MISRA 2012 violations.</td>
103 * <td>MISRA 2012 compliance.</td>
104 * </tr>
105 * <tr>
106 * <td>2.20.1</td>
107 * <td>Minor documentation updates.</td>
108 * <td>Documentation enhancement.</td>
109 * </tr>
110 * <tr>
111 * <td>2.20</td>
112 * <td>The channel number validation method is updated.</td>
113 * <td>New devices support.</td>
114 * </tr>
115 * <tr>
116 * <td rowspan="3">2.10</td>
117 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
118 * <td>Driver library directory-structure simplification.</td>
119 * </tr>
120 * <tr>
121 * <td>Added CRC mode and the CRC descriptor support. \n Added the \ref Cy_DMA_Crc_Init function.</td>
122 * <td>New devices support.</td>
123 * </tr>
124 * <tr>
125 * <td>Added register access layer. Use register access macros instead
126 * of direct register access using dereferenced pointers.</td>
127 * <td>Makes register access device-independent, so that the PDL does
128 * not need to be recompiled for each supported part number.</td>
129 * </tr>
130 * <tr>
131 * <td>2.0.1</td>
132 * <td>Changed CY_DMA_BWC macro values from Boolean to numeric</td>
133 * <td>Improvements made based on usability feedback</td>
134 * </tr>
135 * <tr>
136 * <td>2.0</td>
137 * <td> * All the API is refactored to be consistent within itself and with the
138 * rest of the PDL content.
139 * * The descriptor API is updated as follows:
140 * The \ref Cy_DMA_Descriptor_Init function sets a full bunch of descriptor
141 * settings, and the rest of the descriptor API is a get/set interface
142 * to each of the descriptor settings.
143 * * There is a group of macros to support the backward compatibility with most
144 * of the driver version 1.0 API. But, you should use
145 * the new v2.0 interface in new designs (do not just copy-paste from old
146 * projects). To enable the backward compatibility support, the CY_DMA_BWC
147 * definition should be changed to "1".</td>
148 * <td></td>
149 * </tr>
150 * <tr>
151 * <td>1.0</td>
152 * <td>Initial version</td>
153 * <td></td>
154 * </tr>
155 * </table>
156 *
157
158 * \defgroup group_dma_macros Macros
159 * \defgroup group_dma_functions Functions
160 * \{
161 * \defgroup group_dma_block_functions Block Functions
162 * \defgroup group_dma_channel_functions Channel Functions
163 * \defgroup group_dma_descriptor_functions Descriptor Functions
164 * \}
165 * \defgroup group_dma_data_structures Data Structures
166 * \defgroup group_dma_enums Enumerated Types
167 */
168
169 #if !defined (CY_DMA_H)
170 #define CY_DMA_H
171
172 #include "cy_device.h"
173
174 #if defined (CY_IP_M4CPUSS_DMA) || defined (CY_IP_MXDW)
175
176 #include "cy_syslib.h"
177 #include <stdint.h>
178 #include <stdbool.h>
179 #include <stddef.h>
180
181 #if defined(__cplusplus)
182 extern "C" {
183 #endif
184
185 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.8', 15, \
186 'Value extracted from _VAL2FLD macro will not exceed enum range.');
187
188 /******************************************************************************
189 * Macro definitions *
190 ******************************************************************************/
191
192 /**
193 * \addtogroup group_dma_macros
194 * \{
195 */
196
197 /** The driver major version */
198 #define CY_DMA_DRV_VERSION_MAJOR 2
199
200 /** The driver minor version */
201 #define CY_DMA_DRV_VERSION_MINOR 40
202
203 /** The DMA driver identifier */
204 #define CY_DMA_ID (CY_PDL_DRV_ID(0x13U))
205
206 /** The DMA channel interrupt mask */
207 #define CY_DMA_INTR_MASK (0x01UL)
208
209 /** The minimum X/Y Count API parameters */
210 #define CY_DMA_LOOP_COUNT_MIN (1UL)
211 /** The maximum X/Y Count API parameters */
212 #define CY_DMA_LOOP_COUNT_MAX (256UL)
213
214 /** The minimum X/Y Increment API parameters */
215 #define CY_DMA_LOOP_INCREMENT_MIN (-2048L)
216 /** The maximum X/Y Increment API parameters */
217 #define CY_DMA_LOOP_INCREMENT_MAX (2047L)
218
219 /** The backward compatibility flag. Enables a group of macros which provide
220 * the backward compatibility with most of the DMA driver version 1.0 interface. */
221 #ifndef CY_DMA_BWC
222 #define CY_DMA_BWC (0U) /* Disabled by default */
223 #endif
224
225 /** \} group_dma_macros */
226
227 /**
228 * \addtogroup group_dma_enums
229 * \{
230 */
231
232 /** Contains the possible interrupt cause values */
233 typedef enum
234 {
235 CY_DMA_INTR_CAUSE_NO_INTR = 0U, /**< No interrupt. */
236 CY_DMA_INTR_CAUSE_COMPLETION = 1U, /**< Completion. */
237 CY_DMA_INTR_CAUSE_SRC_BUS_ERROR = 2U, /**< Source bus error. */
238 CY_DMA_INTR_CAUSE_DST_BUS_ERROR = 3U, /**< Destination bus error. */
239 CY_DMA_INTR_CAUSE_SRC_MISAL = 4U, /**< Source address is not aligned. */
240 CY_DMA_INTR_CAUSE_DST_MISAL = 5U, /**< Destination address is not aligned. */
241 CY_DMA_INTR_CAUSE_CURR_PTR_NULL = 6U, /**< Current descriptor pointer is NULL. */
242 CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED = 7U, /**< Active channel is disabled. */
243 CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR = 8U /**< Descriptor bus error. */
244 } cy_en_dma_intr_cause_t;
245
246 /** Contains the options for the descriptor type */
247 typedef enum
248 {
249 CY_DMA_SINGLE_TRANSFER = 0UL, /**< Single transfer. */
250 CY_DMA_1D_TRANSFER = 1UL, /**< 1D transfer. */
251 CY_DMA_2D_TRANSFER = 2UL, /**< 2D transfer. */
252 CY_DMA_CRC_TRANSFER = 3UL, /**< CRC transfer. Supported by the CPUSS_ver2 only. */
253 } cy_en_dma_descriptor_type_t;
254
255 /** Contains the options for the interrupt, trig-in and trig-out type parameters of the descriptor */
256 typedef enum
257 {
258 CY_DMA_1ELEMENT = 0UL, /**< One element transfer. */
259 CY_DMA_X_LOOP = 1UL, /**< One X loop transfer. */
260 CY_DMA_DESCR = 2UL, /**< One descriptor transfer. */
261 CY_DMA_DESCR_CHAIN = 3UL /**< Entire descriptor chain transfer. */
262 } cy_en_dma_trigger_type_t;
263
264 /** Contains the options for the data size */
265 typedef enum
266 {
267 CY_DMA_BYTE = 0UL, /**< One byte. */
268 CY_DMA_HALFWORD = 1UL, /**< Half word (two bytes). */
269 CY_DMA_WORD = 2UL /**< Full word (four bytes). */
270 } cy_en_dma_data_size_t;
271
272 /** Contains the options for descriptor retriggering */
273 typedef enum
274 {
275 CY_DMA_RETRIG_IM = 0UL, /**< Retrigger immediately. */
276 CY_DMA_RETRIG_4CYC = 1UL, /**< Retrigger after 4 Clk_Slow cycles. */
277 CY_DMA_RETRIG_16CYC = 2UL, /**< Retrigger after 16 Clk_Slow cycles. */
278 CY_DMA_WAIT_FOR_REACT = 3UL /**< Wait for trigger reactivation. */
279 } cy_en_dma_retrigger_t;
280
281 /** Contains the options for the transfer size */
282 typedef enum
283 {
284 CY_DMA_TRANSFER_SIZE_DATA = 0UL, /**< As specified by dataSize. */
285 CY_DMA_TRANSFER_SIZE_WORD = 1UL, /**< A full word (four bytes). */
286 } cy_en_dma_transfer_size_t;
287
288 /** Contains the options for the state of the channel when the descriptor is completed */
289 typedef enum
290 {
291 CY_DMA_CHANNEL_ENABLED = 0UL, /**< Channel stays enabled. */
292 CY_DMA_CHANNEL_DISABLED = 1UL /**< Channel is disabled. */
293 } cy_en_dma_channel_state_t;
294
295 /** Contains the return values of the DMA driver */
296 typedef enum
297 {
298 CY_DMA_SUCCESS = 0x00UL, /**< Success. */
299 CY_DMA_BAD_PARAM = CY_DMA_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< The input parameters passed to the DMA API are not valid. */
300 } cy_en_dma_status_t;
301
302 /** \} group_dma_enums */
303
304
305 /** \cond Internal */
306
307 /* Macros for the conditions used by CY_ASSERT calls */
308 #define CY_DMA_IS_LOOP_COUNT_VALID(count) (((count) >= CY_DMA_LOOP_COUNT_MIN) && ((count) <= CY_DMA_LOOP_COUNT_MAX))
309 #define CY_DMA_IS_LOOP_INCR_VALID(incr) (((incr) >= CY_DMA_LOOP_INCREMENT_MIN) && ((incr) <= CY_DMA_LOOP_INCREMENT_MAX))
310 #define CY_DMA_IS_PRIORITY_VALID(prio) ((prio) <= 3UL)
311 #define CY_DMA_IS_INTR_MASK_VALID(intr) (0UL == ((intr) & ((uint32_t) ~CY_DMA_INTR_MASK)))
312
313 #define CY_DMA_IS_RETRIG_VALID(retrig) ((CY_DMA_RETRIG_IM == (retrig)) || \
314 (CY_DMA_RETRIG_4CYC == (retrig)) || \
315 (CY_DMA_RETRIG_16CYC == (retrig)) || \
316 (CY_DMA_WAIT_FOR_REACT == (retrig)))
317
318 #define CY_DMA_IS_TRIG_TYPE_VALID(trigType) ((CY_DMA_1ELEMENT == (trigType)) || \
319 (CY_DMA_X_LOOP == (trigType)) || \
320 (CY_DMA_DESCR == (trigType)) || \
321 (CY_DMA_DESCR_CHAIN == (trigType)))
322
323 #define CY_DMA_IS_XFER_SIZE_VALID(xferSize) ((CY_DMA_TRANSFER_SIZE_DATA == (xferSize)) || \
324 (CY_DMA_TRANSFER_SIZE_WORD == (xferSize)))
325
326 #define CY_DMA_IS_CHANNEL_STATE_VALID(state) ((CY_DMA_CHANNEL_ENABLED == (state)) || \
327 (CY_DMA_CHANNEL_DISABLED == (state)))
328
329 #define CY_DMA_IS_DATA_SIZE_VALID(dataSize) ((CY_DMA_BYTE == (dataSize)) || \
330 (CY_DMA_HALFWORD == (dataSize)) || \
331 (CY_DMA_WORD == (dataSize)))
332
333 #define CY_DMA_IS_TYPE_VALID(descrType) ((CY_DMA_SINGLE_TRANSFER == (descrType)) || \
334 (CY_DMA_1D_TRANSFER == (descrType)) || \
335 (CY_DMA_2D_TRANSFER == (descrType)) || \
336 (CY_DMA_CRC_TRANSFER == (descrType)))
337
338 #define CY_DMA_IS_CH_NR_VALID(base, chNr) ((CY_DW0_BASE == (base)) ? ((chNr) < CY_DW0_CH_NR) : \
339 ((chNr) < CY_DW1_CH_NR))
340
341 /* The descriptor structure bit field definitions */
342 #define CY_DMA_CTL_RETRIG_Pos (0UL)
343 #define CY_DMA_CTL_RETRIG_Msk ((uint32_t)0x3UL << CY_DMA_CTL_RETRIG_Pos)
344 #define CY_DMA_CTL_INTR_TYPE_Pos (2UL)
345 #define CY_DMA_CTL_INTR_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_INTR_TYPE_Pos)
346 #define CY_DMA_CTL_TR_OUT_TYPE_Pos (4UL)
347 #define CY_DMA_CTL_TR_OUT_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TR_OUT_TYPE_Pos)
348 #define CY_DMA_CTL_TR_IN_TYPE_Pos (6UL)
349 #define CY_DMA_CTL_TR_IN_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TR_IN_TYPE_Pos)
350 #define CY_DMA_CTL_CH_DISABLE_Pos (24UL)
351 #define CY_DMA_CTL_CH_DISABLE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_CH_DISABLE_Pos)
352 #define CY_DMA_CTL_SRC_SIZE_Pos (26UL)
353 #define CY_DMA_CTL_SRC_SIZE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_SRC_SIZE_Pos)
354 #define CY_DMA_CTL_DST_SIZE_Pos (27UL)
355 #define CY_DMA_CTL_DST_SIZE_Msk ((uint32_t)0x1UL << CY_DMA_CTL_DST_SIZE_Pos)
356 #define CY_DMA_CTL_DATA_SIZE_Pos (28UL)
357 #define CY_DMA_CTL_DATA_SIZE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_DATA_SIZE_Pos)
358 #define CY_DMA_CTL_TYPE_Pos (30UL)
359 #define CY_DMA_CTL_TYPE_Msk ((uint32_t)0x3UL << CY_DMA_CTL_TYPE_Pos)
360
361 #define CY_DMA_CTL_SRC_INCR_Pos (0UL)
362 #define CY_DMA_CTL_SRC_INCR_Msk ((uint32_t)0xFFFUL << CY_DMA_CTL_SRC_INCR_Pos)
363 #define CY_DMA_CTL_DST_INCR_Pos (12UL)
364 #define CY_DMA_CTL_DST_INCR_Msk ((uint32_t)0xFFFUL << CY_DMA_CTL_DST_INCR_Pos)
365 #define CY_DMA_CTL_COUNT_Pos (24UL)
366 #define CY_DMA_CTL_COUNT_Msk ((uint32_t)0xFFUL << CY_DMA_CTL_COUNT_Pos)
367
368 /** \endcond */
369
370
371 /**
372 * \addtogroup group_dma_data_structures
373 * \{
374 */
375
376 /**
377 * DMA descriptor structure type. It is a user/component-declared structure
378 * allocated in RAM. The DMA HW requires a pointer to this structure to work with it.
379 *
380 * For advanced users: the descriptor can be allocated even in flash, then the user
381 * manually predefines all the structure items with constants. This is
382 * because most of the driver's API (especially functions modifying
383 * descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with
384 * read-only descriptors.
385 */
386 typedef struct
387 {
388 uint32_t ctl; /*!< 0x00000000 Descriptor control */
389 uint32_t src; /*!< 0x00000004 Descriptor source */
390 uint32_t dst; /*!< 0x00000008 Descriptor destination */
391 uint32_t xCtl; /*!< 0x0000000C Descriptor X loop control */
392 uint32_t yCtl; /*!< 0x00000010 Descriptor Y loop control */
393 uint32_t nextPtr; /*!< 0x00000014 Descriptor next pointer */
394 } cy_stc_dma_descriptor_t;
395
396 /**
397 * This structure is a configuration structure pre-initialized by the user and
398 * passed as a parameter to the \ref Cy_DMA_Descriptor_Init().
399 * It can be allocated in RAM/flash (the user's choice).
400 * In case of flash allocation, there is a possibility to reinitialize the descriptor in runtime.
401 * This structure has all the parameters of the descriptor as separate parameters.
402 * Most of these parameters are represented in the \ref cy_stc_dma_descriptor_t structure as bitfields.
403 */
404 typedef struct
405 {
406 cy_en_dma_retrigger_t retrigger; /**< Specifies whether the DW controller should wait for the input trigger to be deactivated. */
407 cy_en_dma_trigger_type_t interruptType; /**< Sets the event that triggers an interrupt. See \ref cy_en_dma_trigger_type_t. */
408 cy_en_dma_trigger_type_t triggerOutType; /**< Sets the event that triggers an output. See \ref cy_en_dma_trigger_type_t. */
409 cy_en_dma_channel_state_t channelState; /**< Specifies whether the channel is enabled or disabled on completion of descriptor. See \ref cy_en_dma_channel_state_t. */
410 cy_en_dma_trigger_type_t triggerInType; /**< Sets what type of transfer is triggered. See \ref cy_en_dma_trigger_type_t. */
411 cy_en_dma_data_size_t dataSize; /**< The size of the data bus for transfer. See \ref cy_en_dma_data_size_t. */
412 cy_en_dma_transfer_size_t srcTransferSize; /**< The source transfer size. */
413 cy_en_dma_transfer_size_t dstTransferSize; /**< The destination transfer size. */
414 cy_en_dma_descriptor_type_t descriptorType; /**< The type of the descriptor. See \ref cy_en_dma_descriptor_type_t. */
415 void * srcAddress; /**< The source address of the transfer. */
416 void * dstAddress; /**< The destination address of the transfer.
417 * For CPUSS_ver2 only: for CRC transfer, the CRC result without post-processing
418 * (reversing and/or XORing, if used) is placed into the dstAddress.
419 */
420 int32_t srcXincrement; /**< The address increment of the source after each X-loop transfer. Valid range is -2048 ... 2047. */
421 int32_t dstXincrement; /**< The address increment of the destination after each X-loop transfer. Valid range is -2048 ... 2047. */
422 uint32_t xCount; /**< The number of transfers in an X-loop. Valid range is 1 ... 256. */
423 int32_t srcYincrement; /**< The address increment of the source after each Y-loop transfer. Valid range is -2048 ... 2047. */
424 int32_t dstYincrement; /**< The address increment of the destination after each Y-loop transfer. Valid range is -2048 ... 2047. */
425 uint32_t yCount; /**< The number of X-loops in the Y-loop. Valid range is 1 ... 256. */
426 cy_stc_dma_descriptor_t * nextDescriptor; /**< The next descriptor to chain after completion. A NULL value will signify no chaining. */
427 } cy_stc_dma_descriptor_config_t;
428
429 /** This structure holds the initialization values for the DMA channel */
430 typedef struct
431 {
432 cy_stc_dma_descriptor_t * descriptor; /**< The DMA descriptor associated with the channel being initialized. */
433 bool preemptable; /**< Specifies whether the channel is preemptable by another higher-priority channel. */
434 uint32_t priority; /**< This parameter specifies the channel's priority. */
435 bool enable; /**< This parameter specifies whether the channel is enabled after initializing. */
436 bool bufferable; /**< This parameter specifies whether a write transaction can complete.
437 without waiting for the destination to accept the write transaction data. */
438 } cy_stc_dma_channel_config_t;
439
440
441 /** This structure holds the initialization values for the CRC feature, only for CPUSS_ver2 */
442 typedef struct
443 {
444 bool dataReverse; /**< Specifies the bit order in which a data byte is processed (reversal is performed after XORing):
445 * 'false': Most significant bit (bit 1) first.
446 * 'true': Least significant bit (bit 0) first.
447 */
448 uint32_t dataXor; /**< Specifies a byte mask with which each data byte is XORed. The XOR is performed before data reversal. */
449 bool reminderReverse; /**< Specifies whether the remainder is bit reversed (reversal is performed after XORing).
450 * Note: this parameter doesn't affect the CRC value stored into the dstAddress.
451 * The reversed value remains in the CRC_REM_RESULT register.
452 */
453 uint32_t reminderXor; /**< Specifies a mask with which the remainder is XORed. The XOR is performed before remainder reversal.
454 * Note: this parameter doesn't affect the CRC value stored into the dstAddress.
455 * The XORed value remains in the CRC_REM_RESULT register.
456 */
457 uint32_t polynomial; /**< CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1').
458 * The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial
459 * and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
460 * - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
461 * - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
462 * - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).
463 */
464 uint32_t lfsrInitVal; /**< The initial value of the Linear Feedback Shift Register */
465 } cy_stc_dma_crc_config_t;
466
467 /** \} group_dma_data_structures */
468
469
470 /**
471 * \addtogroup group_dma_functions
472 * \{
473 */
474
475
476 /**
477 * \addtogroup group_dma_block_functions
478 * \{
479 */
480
481
482 __STATIC_INLINE void Cy_DMA_Enable (DW_Type * base);
483 __STATIC_INLINE void Cy_DMA_Disable (DW_Type * base);
484 __STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel (DW_Type const * base);
485 __STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base);
486 __STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base);
487 cy_en_dma_status_t Cy_DMA_Crc_Init (DW_Type * base, cy_stc_dma_crc_config_t const * crcConfig);
488
489 /** \} group_dma_block_functions */
490
491
492 /**
493 * \addtogroup group_dma_channel_functions
494 * \{
495 */
496 cy_en_dma_status_t Cy_DMA_Channel_Init (DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig);
497 void Cy_DMA_Channel_DeInit (DW_Type * base, uint32_t channel);
498 __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor (DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor);
499 __STATIC_INLINE void Cy_DMA_Channel_Enable (DW_Type * base, uint32_t channel);
500 __STATIC_INLINE void Cy_DMA_Channel_Disable (DW_Type * base, uint32_t channel);
501 __STATIC_INLINE void Cy_DMA_Channel_SetPriority (DW_Type * base, uint32_t channel, uint32_t priority);
502 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority (DW_Type const * base, uint32_t channel);
503 __STATIC_INLINE
504 cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus (DW_Type const * base, uint32_t channel);
505 __STATIC_INLINE
506 cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor (DW_Type const * base, uint32_t channel);
507
508 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus (DW_Type const * base, uint32_t channel);
509 __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt (DW_Type * base, uint32_t channel);
510 __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt (DW_Type * base, uint32_t channel);
511 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask (DW_Type const * base, uint32_t channel);
512 __STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask (DW_Type * base, uint32_t channel, uint32_t interrupt);
513 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel);
514
515 /** \} group_dma_channel_functions */
516
517
518 /**
519 * \addtogroup group_dma_descriptor_functions
520 * \{
521 */
522
523 cy_en_dma_status_t Cy_DMA_Descriptor_Init (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_config_t const * config);
524 void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor);
525
526 void Cy_DMA_Descriptor_SetNextDescriptor (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor);
527 void Cy_DMA_Descriptor_SetDescriptorType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType);
528 __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress (cy_stc_dma_descriptor_t * descriptor, void const * srcAddress);
529 __STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress (cy_stc_dma_descriptor_t * descriptor, void const * dstAddress);
530 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t xCount);
531 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t yCount);
532 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement);
533 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement);
534 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement);
535 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement);
536 __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType);
537 __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType);
538 __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType);
539 __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize);
540 __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize);
541 __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize);
542 __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger);
543 __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState);
544
545 cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor (cy_stc_dma_descriptor_t const * descriptor);
546 __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType (cy_stc_dma_descriptor_t const * descriptor);
547 __STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress (cy_stc_dma_descriptor_t const * descriptor);
548 __STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress (cy_stc_dma_descriptor_t const * descriptor);
549 __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount (cy_stc_dma_descriptor_t const * descriptor);
550 __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount (cy_stc_dma_descriptor_t const * descriptor);
551 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor);
552 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor);
553 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor);
554 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor);
555 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType (cy_stc_dma_descriptor_t const * descriptor);
556 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType (cy_stc_dma_descriptor_t const * descriptor);
557 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType (cy_stc_dma_descriptor_t const * descriptor);
558 __STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize (cy_stc_dma_descriptor_t const * descriptor);
559 __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize (cy_stc_dma_descriptor_t const * descriptor);
560 __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize (cy_stc_dma_descriptor_t const * descriptor);
561 __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger (cy_stc_dma_descriptor_t const * descriptor);
562 __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState (cy_stc_dma_descriptor_t const * descriptor);
563
564 /** \} group_dma_descriptor_functions */
565
566
567
568 /***************************************
569 * In-line Function Implementation
570 ***************************************/
571
572
573 /**
574 * \addtogroup group_dma_block_functions
575 * \{
576 */
577
578
579 /*******************************************************************************
580 * Function Name: Cy_DMA_Enable
581 ****************************************************************************//**
582 *
583 * Enables the DMA block.
584 *
585 * \param base
586 * The pointer to the hardware DMA block.
587 *
588 * \funcusage
589 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
590 *
591 *******************************************************************************/
Cy_DMA_Enable(DW_Type * base)592 __STATIC_INLINE void Cy_DMA_Enable(DW_Type * base)
593 {
594 DW_CTL(base) |= DW_CTL_ENABLED_Msk;
595 }
596
597
598 /*******************************************************************************
599 * Function Name: Cy_DMA_Disable
600 ****************************************************************************//**
601 *
602 * Disables the DMA block.
603 *
604 * \param base
605 * The pointer to the hardware DMA block.
606 *
607 * \funcusage
608 * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
609 *
610 *******************************************************************************/
Cy_DMA_Disable(DW_Type * base)611 __STATIC_INLINE void Cy_DMA_Disable(DW_Type * base)
612 {
613 DW_CTL(base) &= (uint32_t) ~DW_CTL_ENABLED_Msk;
614 }
615
616
617 /*******************************************************************************
618 * Function Name: Cy_DMA_GetActiveChannel
619 ****************************************************************************//**
620 *
621 * Returns the status of the active/pending channels.
622 * the DMA block.
623 *
624 * \param base
625 * The pointer to the hardware DMA block.
626 *
627 * \return
628 * Returns a bit-field with all of the currently active/pending channels in the
629 * DMA block.
630 *
631 * \funcusage
632 * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
633 *
634 *******************************************************************************/
Cy_DMA_GetActiveChannel(DW_Type const * base)635 __STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base)
636 {
637 return(_FLD2VAL(CY_DW_STATUS_CH_IDX, DW_STATUS(base)));
638 }
639
640
641 /*******************************************************************************
642 * Function Name: Cy_DMA_GetActiveSrcAddress
643 ****************************************************************************//**
644 *
645 * Returns the source address being used for the current transfer.
646 *
647 * \param base
648 * The pointer to the hardware DMA block.
649 *
650 * \return
651 * Returns the pointer to the source of transfer.
652 *
653 * \funcusage
654 * \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress
655 *
656 *******************************************************************************/
Cy_DMA_GetActiveSrcAddress(DW_Type const * base)657 __STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base)
658 {
659 return ((void *) DW_DESCR_SRC(base));
660 }
661
662
663 /*******************************************************************************
664 * Function Name: Cy_DMA_GetActiveDstAddress
665 ****************************************************************************//**
666 *
667 * Returns the destination address being used for the current transfer.
668 *
669 * \param base
670 * The pointer to the hardware DMA block.
671 *
672 * \return
673 * Returns the pointer to the destination of transfer.
674 *
675 * \funcusage
676 * \snippet dma/snippet/main.c snippet_Cy_DMA_GetActiveSrcAddress
677 *
678 *******************************************************************************/
Cy_DMA_GetActiveDstAddress(DW_Type const * base)679 __STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base)
680 {
681 return ((void *) DW_DESCR_DST(base));
682 }
683
684 /** \} group_dma_block_functions */
685
686 /**
687 * \addtogroup group_dma_descriptor_functions
688 * \{
689 */
690
691
692 /*******************************************************************************
693 * Function Name: Cy_DMA_Descriptor_SetSrcAddress
694 ****************************************************************************//**
695 *
696 * Sets the source address for the specified descriptor.
697 *
698 * \param descriptor
699 * The descriptor structure instance declared by the user/component.
700 *
701 * \param srcAddress
702 * The source address value for the descriptor.
703 *
704 * \funcusage
705 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
706 *
707 *******************************************************************************/
Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor,void const * srcAddress)708 __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor, void const * srcAddress)
709 {
710 descriptor->src = (uint32_t) srcAddress;
711 }
712
713
714 /*******************************************************************************
715 * Function Name: Cy_DMA_Descriptor_GetSrcAddress
716 ****************************************************************************//**
717 *
718 * Returns the source address parameter of the specified descriptor.
719 *
720 * \param descriptor
721 * The descriptor structure instance declared by the user/component.
722 *
723 * \return
724 * The source address value of the descriptor.
725 *
726 * \funcusage
727 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
728 *
729 *******************************************************************************/
Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor)730 __STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor)
731 {
732 return ((void *) descriptor->src);
733 }
734
735
736 /*******************************************************************************
737 * Function Name: Cy_DMA_Descriptor_SetDstAddress
738 ****************************************************************************//**
739 *
740 * Sets the destination address for the specified descriptor.
741 *
742 * \param descriptor
743 * The descriptor structure instance declared by the user/component.
744 *
745 * \param dstAddress
746 * The destination address value for the descriptor.
747 *
748 * \funcusage
749 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
750 *
751 *******************************************************************************/
Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor,void const * dstAddress)752 __STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor, void const * dstAddress)
753 {
754 descriptor->dst = (uint32_t) dstAddress;
755 }
756
757
758 /*******************************************************************************
759 * Function Name: Cy_DMA_Descriptor_GetDstAddress
760 ****************************************************************************//**
761 *
762 * Returns the destination address parameter of the specified descriptor.
763 *
764 * \param descriptor
765 * The descriptor structure instance declared by the user/component.
766 *
767 * \return
768 * The destination address value of the descriptor.
769 *
770 * \funcusage
771 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
772 *
773 *******************************************************************************/
Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor)774 __STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor)
775 {
776 return ((void *) descriptor->dst);
777 }
778
779
780 /*******************************************************************************
781 * Function Name: Cy_DMA_Descriptor_SetInterruptType
782 ****************************************************************************//**
783 *
784 * Sets the interrupt type for the specified descriptor.
785 *
786 * \param descriptor
787 * The descriptor structure instance declared by the user/component.
788 *
789 * \param interruptType
790 * The interrupt type set for the descriptor. \ref cy_en_dma_trigger_type_t
791 *
792 * \funcusage
793 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
794 *
795 *******************************************************************************/
Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_trigger_type_t interruptType)796 __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType)
797 {
798 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(interruptType));
799
800 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType);
801 }
802
803
804 /*******************************************************************************
805 * Function Name: Cy_DMA_Descriptor_GetInterruptType
806 ****************************************************************************//**
807 *
808 * Returns the Interrupt-Type of the specified descriptor.
809 *
810 * \param descriptor
811 * The descriptor structure instance declared by the user/component.
812 *
813 * \return
814 * The Interrupt-Type \ref cy_en_dma_trigger_type_t.
815 *
816 * \funcusage
817 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
818 *
819 *******************************************************************************/
Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor)820 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor)
821 {
822 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_INTR_TYPE, descriptor->ctl));
823 }
824
825
826 /*******************************************************************************
827 * Function Name: Cy_DMA_Descriptor_SetTriggerInType
828 ****************************************************************************//**
829 *
830 * Sets the Trigger-In-Type for the specified descriptor.
831 *
832 * \param descriptor
833 * The descriptor structure instance declared by the user/component.
834 *
835 * \param triggerInType
836 * The Trigger In Type parameter \ref cy_en_dma_trigger_type_t
837 *
838 * \funcusage
839 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
840 *
841 *******************************************************************************/
Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_trigger_type_t triggerInType)842 __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType)
843 {
844 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerInType));
845
846 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType);
847 }
848
849
850 /*******************************************************************************
851 * Function Name: Cy_DMA_Descriptor_GetTriggerInType
852 ****************************************************************************//**
853 *
854 * Returns the Trigger-In-Type parameter of the specified descriptor.
855 *
856 * \param descriptor
857 * The descriptor structure instance declared by the user/component.
858 *
859 * \return
860 * The Trigger-In-Type \ref cy_en_dma_trigger_type_t
861 *
862 * \funcusage
863 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
864 *
865 *******************************************************************************/
Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor)866 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor)
867 {
868 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_IN_TYPE, descriptor->ctl));
869 }
870
871
872 /*******************************************************************************
873 * Function Name: Cy_DMA_Descriptor_SetTriggerOutType
874 ****************************************************************************//**
875 *
876 * Sets the Trigger-Out-Type for the specified descriptor.
877 *
878 * \param descriptor
879 * The descriptor structure instance declared by the user/component.
880 *
881 * \param triggerOutType
882 * The Trigger-Out-Type set for the descriptor. \ref cy_en_dma_trigger_type_t
883 *
884 * \funcusage
885 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
886 *
887 *******************************************************************************/
Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_trigger_type_t triggerOutType)888 __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType)
889 {
890 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerOutType));
891
892 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType);
893 }
894
895
896 /*******************************************************************************
897 * Function Name: Cy_DMA_Descriptor_GetTriggerOutType
898 ****************************************************************************//**
899 *
900 * Returns the Trigger-Out-Type parameter of the specified descriptor.
901 *
902 * \param descriptor
903 * The descriptor structure instance declared by the user/component.
904 *
905 * \return
906 * The Trigger-Out-Type parameter \ref cy_en_dma_trigger_type_t.
907 *
908 * \funcusage
909 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
910 *
911 *******************************************************************************/
Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor)912 __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor)
913 {
914 return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_OUT_TYPE, descriptor->ctl));
915 }
916
917
918 /*******************************************************************************
919 * Function Name: Cy_DMA_Descriptor_SetDataSize
920 ****************************************************************************//**
921 *
922 * Sets the Data Element Size for the specified descriptor.
923 *
924 * \param descriptor
925 * The descriptor structure instance declared by the user/component.
926 *
927 * \param dataSize
928 * The Data Element Size \ref cy_en_dma_data_size_t
929 *
930 * \funcusage
931 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
932 *
933 *******************************************************************************/
Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_data_size_t dataSize)934 __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize)
935 {
936 CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(dataSize));
937
938 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize);
939 }
940
941
942 /*******************************************************************************
943 * Function Name: Cy_DMA_Descriptor_GetDataSize
944 ****************************************************************************//**
945 *
946 * Returns the Data Element Size parameter of the specified descriptor.
947 *
948 * \param descriptor
949 * The descriptor structure instance declared by the user/component.
950 *
951 * \return
952 * The Data Element Size \ref cy_en_dma_data_size_t.
953 *
954 * \funcusage
955 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
956 *
957 *******************************************************************************/
Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor)958 __STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor)
959 {
960 return((cy_en_dma_data_size_t) _FLD2VAL(CY_DMA_CTL_DATA_SIZE, descriptor->ctl));
961 }
962
963
964 /*******************************************************************************
965 * Function Name: Cy_DMA_Descriptor_SetSrcTransferSize
966 ****************************************************************************//**
967 *
968 * Sets the Source Transfer Size for the specified descriptor.
969 *
970 * \param descriptor
971 * The descriptor structure instance declared by the user/component.
972 *
973 * \param srcTransferSize
974 * The Source Transfer Size \ref cy_en_dma_transfer_size_t.
975 *
976 * \funcusage
977 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
978 *
979 *******************************************************************************/
Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_transfer_size_t srcTransferSize)980 __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize)
981 {
982 CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(srcTransferSize));
983
984 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_SRC_SIZE, srcTransferSize);
985 }
986
987
988 /*******************************************************************************
989 * Function Name: Cy_DMA_Descriptor_GetSrcTransferSize
990 ****************************************************************************//**
991 *
992 * Returns the Source Transfer Size parameter of the specified descriptor.
993 *
994 * \param descriptor
995 * The descriptor structure instance declared by the user/component.
996 *
997 * \return
998 * The Source Transfer Size \ref cy_en_dma_transfer_size_t.
999 *
1000 * \funcusage
1001 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1002 *
1003 *******************************************************************************/
Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor)1004 __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor)
1005 {
1006 return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_SRC_SIZE, descriptor->ctl));
1007 }
1008
1009
1010 /*******************************************************************************
1011 * Function Name: Cy_DMA_Descriptor_SetDstTransferSize
1012 ****************************************************************************//**
1013 *
1014 * Sets the Destination Transfer Size for the specified descriptor.
1015 *
1016 * \param descriptor
1017 * The descriptor structure instance declared by the user/component.
1018 *
1019 * \param dstTransferSize
1020 * The Destination Transfer Size \ref cy_en_dma_transfer_size_t.
1021 *
1022 * \funcusage
1023 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1024 *
1025 *******************************************************************************/
Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_transfer_size_t dstTransferSize)1026 __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize)
1027 {
1028 CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(dstTransferSize));
1029
1030 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize);
1031 }
1032
1033
1034 /*******************************************************************************
1035 * Function Name: Cy_DMA_Descriptor_GetDstTransferSize
1036 ****************************************************************************//**
1037 *
1038 * Returns the Destination Transfer Size parameter of the specified descriptor.
1039 *
1040 * \param descriptor
1041 * The descriptor structure instance declared by the user/component.
1042 *
1043 * \return
1044 * The Destination Transfer Size \ref cy_en_dma_transfer_size_t.
1045 *
1046 * \funcusage
1047 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1048 *
1049 *******************************************************************************/
Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor)1050 __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor)
1051 {
1052 return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_DST_SIZE, descriptor->ctl));
1053 }
1054
1055
1056 /*******************************************************************************
1057 * Function Name: Cy_DMA_Descriptor_SetRetrigger
1058 ****************************************************************************//**
1059 *
1060 * Sets the retrigger value that specifies whether the controller should
1061 * wait for the input trigger to be deactivated.
1062 *
1063 * \param descriptor
1064 * The descriptor structure instance declared by the user/component.
1065 *
1066 * \param retrigger
1067 * The \ref cy_en_dma_retrigger_t parameter specifies whether the controller
1068 * should wait for the input trigger to be deactivated.
1069 *
1070 * \funcusage
1071 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1072 *
1073 *******************************************************************************/
Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_retrigger_t retrigger)1074 __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger)
1075 {
1076 CY_ASSERT_L3(CY_DMA_IS_RETRIG_VALID(retrigger));
1077
1078 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger);
1079 }
1080
1081
1082 /*******************************************************************************
1083 * Function Name: Cy_DMA_Descriptor_GetRetrigger
1084 ****************************************************************************//**
1085 *
1086 * Returns a value that specifies whether the controller should
1087 * wait for the input trigger to be deactivated.
1088 *
1089 * \param descriptor
1090 * The descriptor structure instance declared by the user/component.
1091 *
1092 * \return
1093 * The Retrigger setting \ref cy_en_dma_retrigger_t.
1094 *
1095 * \funcusage
1096 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1097 *
1098 *******************************************************************************/
Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor)1099 __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor)
1100 {
1101 return((cy_en_dma_retrigger_t) _FLD2VAL(CY_DMA_CTL_RETRIG, descriptor->ctl));
1102 }
1103
1104
1105 /*******************************************************************************
1106 * Function Name: Cy_DMA_Descriptor_GetDescriptorType
1107 ****************************************************************************//**
1108 *
1109 * Returns the descriptor's type of the specified descriptor.
1110 *
1111 * \param descriptor
1112 * The descriptor structure instance declared by the user/component.
1113 *
1114 * \return
1115 * The descriptor type \ref cy_en_dma_descriptor_type_t.
1116 *
1117 * \funcusage
1118 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1119 *
1120 *******************************************************************************/
Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor)1121 __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor)
1122 {
1123 return((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl));
1124 }
1125
1126
1127 /*******************************************************************************
1128 * Function Name: Cy_DMA_Descriptor_SetChannelState
1129 ****************************************************************************//**
1130 *
1131 * Sets the channel state on completion of the specified descriptor.
1132 *
1133 * \param descriptor
1134 * The descriptor structure instance declared by the user/component.
1135 *
1136 * \param channelState
1137 * The channel state \ref cy_en_dma_channel_state_t.
1138 *
1139 * \funcusage
1140 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1141 *
1142 *******************************************************************************/
Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor,cy_en_dma_channel_state_t channelState)1143 __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState)
1144 {
1145 CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(channelState));
1146
1147 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState);
1148 }
1149
1150
1151 /*******************************************************************************
1152 * Function Name: Cy_DMA_Descriptor_GetChannelState
1153 ****************************************************************************//**
1154 *
1155 * Returns the channel state on completion of the specified descriptor.
1156 *
1157 * \param descriptor
1158 * The descriptor structure instance declared by the user/component.
1159 *
1160 * \return
1161 * The Channel State setting \ref cy_en_dma_channel_state_t.
1162 *
1163 * \funcusage
1164 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1165 *
1166 *******************************************************************************/
Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor)1167 __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor)
1168 {
1169 return((cy_en_dma_channel_state_t) _FLD2VAL(CY_DMA_CTL_CH_DISABLE, descriptor->ctl));
1170 }
1171
1172
1173 /*******************************************************************************
1174 * Function Name: Cy_DMA_Descriptor_SetXloopDataCount
1175 ****************************************************************************//**
1176 *
1177 * Sets the number of data elements to transfer in the X loop
1178 * for the specified descriptor (for 1D or 2D descriptors only).
1179 *
1180 * \param descriptor
1181 * The descriptor structure instance declared by the user/component.
1182 *
1183 * \param xCount
1184 * The number of data elements to transfer in the X loop. Valid range is 1 ... 256.
1185 *
1186 * \funcusage
1187 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1188 *
1189 *******************************************************************************/
Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor,uint32_t xCount)1190 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount)
1191 {
1192 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1193 CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(xCount));
1194 /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
1195 CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_COUNT, xCount - 1UL);
1196 }
1197
1198
1199 /*******************************************************************************
1200 * Function Name: Cy_DMA_Descriptor_GetXloopDataCount
1201 ****************************************************************************//**
1202 *
1203 * Returns the number of data elements for the X loop of the specified
1204 * descriptor (for 1D or 2D descriptors only).
1205 *
1206 * \param descriptor
1207 * The descriptor structure instance declared by the user/component.
1208 *
1209 * \return
1210 * The number of data elements to transfer in the X loop. The range is 1 ... 256.
1211 *
1212 * \funcusage
1213 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1214 *
1215 *******************************************************************************/
Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor)1216 __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
1217 {
1218 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1219 /* Convert the data count from the machine range (0-255) into the user's range (1-256). */
1220 return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->xCtl) + 1UL);
1221 }
1222
1223
1224 /*******************************************************************************
1225 * Function Name: Cy_DMA_Descriptor_SetXloopSrcIncrement
1226 ****************************************************************************//**
1227 *
1228 * Sets the source increment parameter for the X loop of the specified
1229 * descriptor (for 1D or 2D descriptors only).
1230 *
1231 * \param descriptor
1232 * The descriptor structure instance declared by the user/component.
1233 *
1234 * \param srcXincrement
1235 * The value of the source increment. The valid range is -2048 ... 2047.
1236 *
1237 * \funcusage
1238 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1239 *
1240 *******************************************************************************/
Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor,int32_t srcXincrement)1241 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement)
1242 {
1243 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1244 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(srcXincrement));
1245
1246 CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement);
1247 }
1248
1249
1250 /*******************************************************************************
1251 * Function Name: Cy_DMA_Descriptor_GetXloopSrcIncrement
1252 ****************************************************************************//**
1253 *
1254 * Returns the source increment parameter for the X loop of the specified
1255 * descriptor (for 1D or 2D descriptors only).
1256 *
1257 * \param descriptor
1258 * The descriptor structure instance declared by the user/component.
1259 *
1260 * \return
1261 * The value of the source increment. The range is -2048 ... 2047.
1262 *
1263 * \funcusage
1264 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1265 *
1266 *******************************************************************************/
Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)1267 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
1268 {
1269 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1270
1271 return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->xCtl));
1272 }
1273
1274
1275 /*******************************************************************************
1276 * Function Name: Cy_DMA_Descriptor_SetXloopDstIncrement
1277 ****************************************************************************//**
1278 *
1279 * Sets the destination increment parameter for the X loop for the specified
1280 * descriptor (for 1D or 2D descriptors only).
1281 *
1282 * \param descriptor
1283 * The descriptor structure instance declared by the user/component.
1284 *
1285 * \param dstXincrement
1286 * The value of the destination increment. The valid range is -2048 ... 2047.
1287 *
1288 * \funcusage
1289 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1290 *
1291 *******************************************************************************/
Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor,int32_t dstXincrement)1292 __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement)
1293 {
1294 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1295 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(dstXincrement));
1296
1297 CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_DST_INCR, dstXincrement);
1298 }
1299
1300
1301 /*******************************************************************************
1302 * Function Name: Cy_DMA_Descriptor_GetXloopDstIncrement
1303 ****************************************************************************//**
1304 *
1305 * Returns the destination increment parameter for the X loop of the specified
1306 * descriptor (for 1D or 2D descriptors only).
1307 *
1308 * \param descriptor
1309 * The descriptor structure instance declared by the user/component.
1310 *
1311 * \return
1312 * The value of the destination increment. The range is -2048 ... 2047.
1313 *
1314 * \funcusage
1315 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1316 *
1317 *******************************************************************************/
Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)1318 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
1319 {
1320 CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1321
1322 return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->xCtl));
1323 }
1324
1325
1326 /*******************************************************************************
1327 * Function Name: Cy_DMA_Descriptor_SetYloopDataCount
1328 ****************************************************************************//**
1329 *
1330 * Sets the number of data elements for the Y loop of the specified descriptor
1331 * (for 2D descriptors only).
1332 *
1333 * \param descriptor
1334 * The descriptor structure instance declared by the user/component.
1335 *
1336 * \param yCount
1337 * The number of X loops to execute in the Y loop. The valid range is 1 ... 256.
1338 *
1339 * \funcusage
1340 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1341 *
1342 *******************************************************************************/
Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor,uint32_t yCount)1343 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount)
1344 {
1345 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1346 CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(yCount));
1347 /* Convert the data count from the user's range (1-256) into the machine range (0-255). */
1348 CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_COUNT, yCount - 1UL);
1349 }
1350
1351
1352 /*******************************************************************************
1353 * Function Name: Cy_DMA_Descriptor_GetYloopDataCount
1354 ****************************************************************************//**
1355 *
1356 * Returns the number of X loops to execute in the Y loop of the specified
1357 * descriptor (for 2D descriptors only).
1358 *
1359 * \param descriptor
1360 * The descriptor structure instance declared by the user/component.
1361 *
1362 * \return
1363 * The number of X loops to execute in the Y loop. The range is 1 ... 256.
1364 *
1365 * \funcusage
1366 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1367 *
1368 *******************************************************************************/
Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor)1369 __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
1370 {
1371 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1372 /* Convert the data count from the machine range (0-255) into the user's range (1-256). */
1373 return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->yCtl) + 1UL);
1374 }
1375
1376
1377 /*******************************************************************************
1378 * Function Name: Cy_DMA_Descriptor_SetYloopSrcIncrement
1379 ****************************************************************************//**
1380 *
1381 * Sets the source increment parameter for the Y loop for the specified
1382 * descriptor (for 2D descriptors only).
1383 *
1384 * \param descriptor
1385 * The descriptor structure instance declared by the user/component.
1386 *
1387 * \param srcYincrement
1388 * The value of the source increment. The valid range is -2048 ... 2047.
1389 *
1390 * \funcusage
1391 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1392 *
1393 *******************************************************************************/
Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor,int32_t srcYincrement)1394 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement)
1395 {
1396 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1397 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(srcYincrement));
1398
1399 CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_SRC_INCR, srcYincrement);
1400 }
1401
1402
1403 /*******************************************************************************
1404 * Function Name: Cy_DMA_Descriptor_GetYloopSrcIncrement
1405 ****************************************************************************//**
1406 *
1407 * Returns the source increment parameter for the outer Y of the specified
1408 * descriptor (for 2D descriptors only).
1409 *
1410 * \param descriptor
1411 * The descriptor structure instance declared by the user/component.
1412 *
1413 * \return
1414 * The value of the source increment. The range is -2048 ... 2047.
1415 *
1416 * \funcusage
1417 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1418 *
1419 *******************************************************************************/
Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)1420 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
1421 {
1422 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1423
1424 return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->yCtl));
1425 }
1426
1427
1428 /*******************************************************************************
1429 * Function Name: Cy_DMA_Descriptor_SetYloopDstIncrement
1430 ****************************************************************************//**
1431 *
1432 * Sets the destination increment parameter for the Y loop of the specified
1433 * descriptor (for 2D descriptors only).
1434 *
1435 * \param descriptor
1436 * The descriptor structure instance declared by the user/component.
1437 *
1438 * \param dstYincrement
1439 * The value of the destination increment. The valid range is -2048 ... 2047.
1440 *
1441 * \funcusage
1442 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_SetterFunctions
1443 *
1444 *******************************************************************************/
Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor,int32_t dstYincrement)1445 __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement)
1446 {
1447 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1448 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(dstYincrement));
1449
1450 CY_REG32_CLR_SET(descriptor->yCtl, CY_DMA_CTL_DST_INCR, dstYincrement);
1451 }
1452
1453
1454 /*******************************************************************************
1455 * Function Name: Cy_DMA_Descriptor_GetYloopDstIncrement
1456 ****************************************************************************//**
1457 *
1458 * Returns the destination increment parameter for the Y loop of the specified
1459 * descriptor (for 2D descriptors only).
1460 *
1461 * \param descriptor
1462 * The descriptor structure instance declared by the user/component.
1463 *
1464 * \return
1465 * The value of the destination increment. The range is -2048 ... 2047.
1466 *
1467 * \funcusage
1468 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_GetterFunctions
1469 *
1470 *******************************************************************************/
Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)1471 __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
1472 {
1473 CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
1474
1475 return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->yCtl));
1476 }
1477
1478
1479 /** \} group_dma_descriptor_functions */
1480
1481
1482 /**
1483 * \addtogroup group_dma_channel_functions
1484 * \{
1485 */
1486
1487
1488 /*******************************************************************************
1489 * Function Name: Cy_DMA_Channel_SetDescriptor
1490 ****************************************************************************//**
1491 *
1492 * Sets a descriptor as current for the specified DMA channel.
1493 *
1494 * \param base
1495 * The pointer to the hardware DMA block.
1496 *
1497 * \param channel
1498 * The channel number.
1499 *
1500 * \param descriptor
1501 * This is the descriptor to be associated with the channel.
1502 *
1503 * \funcusage
1504 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
1505 *
1506 *******************************************************************************/
Cy_DMA_Channel_SetDescriptor(DW_Type * base,uint32_t channel,cy_stc_dma_descriptor_t const * descriptor)1507 __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor)
1508 {
1509 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1510
1511 DW_CH_CURR_PTR(base, channel) = (uint32_t)descriptor;
1512 DW_CH_IDX(base, channel) &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk);
1513 }
1514
1515
1516 /*******************************************************************************
1517 * Function Name: Cy_DMA_Channel_Enable
1518 ****************************************************************************//**
1519 *
1520 * The function is used to enable a DMA channel.
1521 *
1522 * \param base
1523 * The pointer to the hardware DMA block.
1524 *
1525 * \param channel
1526 * The channel number.
1527 *
1528 * \funcusage
1529 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
1530 *
1531 *******************************************************************************/
Cy_DMA_Channel_Enable(DW_Type * base,uint32_t channel)1532 __STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel)
1533 {
1534 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1535
1536 DW_CH_CTL(base, channel) |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
1537 }
1538
1539
1540 /*******************************************************************************
1541 * Function Name: Cy_DMA_Channel_Disable
1542 ****************************************************************************//**
1543 *
1544 * The function is used to disable a DMA channel.
1545 *
1546 * \param base
1547 * The pointer to the hardware DMA block.
1548 *
1549 * \param channel
1550 * The channel number.
1551 *
1552 * \funcusage
1553 * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
1554 *
1555 *******************************************************************************/
Cy_DMA_Channel_Disable(DW_Type * base,uint32_t channel)1556 __STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel)
1557 {
1558 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1559
1560 DW_CH_CTL(base, channel) &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
1561 }
1562
1563
1564 /*******************************************************************************
1565 * Function Name: Cy_DMA_Channel_SetPriority
1566 ****************************************************************************//**
1567 *
1568 * The function is used to set a priority for the DMA channel.
1569 *
1570 * \param base
1571 * The pointer to the hardware DMA block.
1572 *
1573 * \param channel
1574 * The channel number.
1575 *
1576 * \param priority
1577 * The priority to be set for the DMA channel. The allowed values are 0,1,2,3.
1578 *
1579 * \funcusage
1580 * \snippet dma/snippet/main.c snippet_Cy_DMA_Enable
1581 *
1582 *******************************************************************************/
Cy_DMA_Channel_SetPriority(DW_Type * base,uint32_t channel,uint32_t priority)1583 __STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel, uint32_t priority)
1584 {
1585 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1586 CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority));
1587
1588 CY_REG32_CLR_SET(DW_CH_CTL(base, channel), CY_DW_CH_CTL_PRIO, priority);
1589 }
1590
1591
1592 /*******************************************************************************
1593 * Function Name: Cy_DMA_Channel_GetPriority
1594 ****************************************************************************//**
1595 *
1596 * Returns the priority of the DMA channel.
1597 *
1598 * \param base
1599 * The pointer to the hardware DMA block.
1600 *
1601 * \param channel
1602 * The channel number.
1603 *
1604 * \return
1605 * The priority of the channel.
1606 *
1607 * \funcusage
1608 * \snippet dma/snippet/main.c snippet_Cy_DMA_Disable
1609 *
1610 *******************************************************************************/
Cy_DMA_Channel_GetPriority(DW_Type const * base,uint32_t channel)1611 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel)
1612 {
1613 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1614
1615 return ((uint32_t) _FLD2VAL(CY_DW_CH_CTL_PRIO, DW_CH_CTL(base, channel)));
1616 }
1617
1618
1619 /*******************************************************************************
1620 * Function Name: Cy_DMA_Channel_GetCurrentDescriptor
1621 ****************************************************************************//**
1622 *
1623 * Returns the descriptor that is active in the channel.
1624 *
1625 * \param base
1626 * The pointer to the hardware DMA block.
1627 *
1628 * \param channel
1629 * The channel number.
1630 *
1631 * \return
1632 * The pointer to the descriptor associated with the channel.
1633 *
1634 * \funcusage
1635 * \snippet dma/snippet/main.c snippet_Cy_DMA_Descriptor_Deinit
1636 *
1637 *******************************************************************************/
Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base,uint32_t channel)1638 __STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel)
1639 {
1640 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1641
1642 return ((cy_stc_dma_descriptor_t*)(DW_CH_CURR_PTR(base, channel)));
1643 }
1644
1645
1646
1647 /*******************************************************************************
1648 * Function Name: Cy_DMA_Channel_GetInterruptStatus
1649 ****************************************************************************//**
1650 *
1651 * Returns the interrupt status of the specified channel.
1652 *
1653 * \param base
1654 * The pointer to the hardware DMA block.
1655 *
1656 * \param channel
1657 * The channel number.
1658 *
1659 * \return
1660 * The status of an interrupt for the specified channel.
1661 *
1662 * \funcusage
1663 * \snippet dma/snippet/main.c snippet_Cy_DMA_GetInterruptStatus
1664 *
1665 *******************************************************************************/
Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base,uint32_t channel)1666 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel)
1667 {
1668 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1669
1670 return (DW_CH_INTR(base, channel));
1671 }
1672
1673
1674 /*******************************************************************************
1675 * Function Name: Cy_DMA_Channel_GetStatus
1676 ****************************************************************************//**
1677 *
1678 * Returns the interrupt reason of the specified channel.
1679 *
1680 * \param base
1681 * The pointer to the hardware DMA block.
1682 *
1683 * \param channel
1684 * The channel number.
1685 *
1686 * \return
1687 * The cause \ref cy_en_dma_intr_cause_t of the interrupt.
1688 *
1689 * \funcusage
1690 * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
1691 *
1692 *******************************************************************************/
Cy_DMA_Channel_GetStatus(DW_Type const * base,uint32_t channel)1693 __STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel)
1694 {
1695 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1696
1697 return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, DW_CH_STATUS(base, channel)));
1698 }
1699
1700
1701 /*******************************************************************************
1702 * Function Name: Cy_DMA_Channel_ClearInterrupt
1703 ****************************************************************************//**
1704 *
1705 * Clears the interrupt status of the specified channel.
1706 *
1707 * \param base
1708 * The pointer to the hardware DMA block.
1709 *
1710 * \param channel
1711 * The channel number.
1712 *
1713 * \funcusage
1714 * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
1715 *
1716 *******************************************************************************/
Cy_DMA_Channel_ClearInterrupt(DW_Type * base,uint32_t channel)1717 __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel)
1718 {
1719 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1720
1721 DW_CH_INTR(base, channel) = CY_DMA_INTR_MASK;
1722 (void) DW_CH_INTR(base, channel);
1723 }
1724
1725
1726 /*******************************************************************************
1727 * Function Name: Cy_DMA_Channel_SetInterrupt
1728 ****************************************************************************//**
1729 *
1730 * Sets the interrupt for the specified channel.
1731 *
1732 * \param base
1733 * The pointer to the hardware DMA block.
1734 *
1735 * \param channel
1736 * The channel number.
1737 *
1738 * \funcusage
1739 * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
1740 *
1741 *******************************************************************************/
Cy_DMA_Channel_SetInterrupt(DW_Type * base,uint32_t channel)1742 __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel)
1743 {
1744 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1745
1746 DW_CH_INTR_SET(base, channel) = CY_DMA_INTR_MASK;
1747 }
1748
1749
1750 /*******************************************************************************
1751 * Function Name: Cy_DMA_Channel_GetInterruptMask
1752 ****************************************************************************//**
1753 *
1754 * Returns the interrupt mask value of the specified channel.
1755 *
1756 * \param base
1757 * The pointer to the hardware DMA block.
1758 *
1759 * \param channel
1760 * The channel number.
1761 *
1762 * \return
1763 * The interrupt mask value.
1764 *
1765 * \funcusage
1766 * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
1767 *
1768 *******************************************************************************/
Cy_DMA_Channel_GetInterruptMask(DW_Type const * base,uint32_t channel)1769 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel)
1770 {
1771 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1772
1773 return (DW_CH_INTR_MASK(base, channel));
1774 }
1775
1776
1777 /*******************************************************************************
1778 * Function Name: Cy_DMA_Channel_SetInterruptMask
1779 ****************************************************************************//**
1780 *
1781 * Sets an interrupt mask value for the specified channel.
1782 *
1783 * \param base
1784 * The pointer to the hardware DMA block.
1785 *
1786 * \param channel
1787 * The channel number.
1788 *
1789 * \param interrupt
1790 * The interrupt mask:
1791 * CY_DMA_INTR_MASK to enable the interrupt or 0UL to disable the interrupt.
1792 *
1793 * \funcusage
1794 * \snippet dma/snippet/main.c snippet_Cy_DMA_SetInterruptMask
1795 *
1796 *******************************************************************************/
Cy_DMA_Channel_SetInterruptMask(DW_Type * base,uint32_t channel,uint32_t interrupt)1797 __STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t channel, uint32_t interrupt)
1798 {
1799 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1800 CY_ASSERT_L2(CY_DMA_IS_INTR_MASK_VALID(interrupt));
1801 DW_CH_INTR_MASK(base, channel) = interrupt;
1802 }
1803
1804
1805 /*******************************************************************************
1806 * Function Name: Cy_DMA_Channel_GetInterruptStatusMasked
1807 ****************************************************************************//**
1808 *
1809 * Returns the logical AND of the corresponding INTR and INTR_MASK fields
1810 * in a single-load operation.
1811 *
1812 * \param base
1813 * The pointer to the hardware DMA block.
1814 *
1815 * \param channel
1816 * The channel number.
1817 *
1818 * \funcusage
1819 * \snippet dma/snippet/main.c snippet_Cy_DMA_ClearInterrupt
1820 *
1821 *******************************************************************************/
Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base,uint32_t channel)1822 __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel)
1823 {
1824 CY_ASSERT_L1(CY_DMA_IS_CH_NR_VALID(base, channel));
1825
1826 return (DW_CH_INTR_MASKED(base, channel));
1827 }
1828
1829
1830 /** \} group_dma_channel_functions */
1831
1832 /** \} group_dma_functions */
1833
1834
1835 /** \cond The definitions to support the backward compatibility, do not use them in new designs */
1836
1837 #if(0U != CY_DMA_BWC)
1838
1839 /* Type definitions */
1840 #define cy_stc_dma_chnl_config_t cy_stc_dma_channel_config_t
1841 #define cy_stc_dma_descr_t cy_stc_dma_descriptor_t
1842 #define cy_stc_dma_descr_config_t cy_stc_dma_descriptor_config_t
1843 #define cy_en_dma_trig_type_t cy_en_dma_trigger_type_t
1844
1845 /* Structure items */
1846 #define DMA_Descriptor descriptor
1847 #define deact retrigger
1848 #define intrType interruptType
1849 #define chStateAtCmplt channelState
1850 #define srcTxfrSize srcTransferSize
1851 #define destTxfrSize dstTransferSize
1852 #define trigoutType triggerOutType
1853 #define triginType triggerInType
1854 #define descrType descriptorType
1855 #define srcAddr srcAddress
1856 #define destAddr dstAddress
1857 #define srcXincr srcXincrement
1858 #define srcYincr srcYincrement
1859 #define destXincr dstXincrement
1860 #define destYincr dstYincrement
1861 #define descrNext nextDescriptor
1862
1863 /* Constants */
1864 #define CY_DMA_CH_DISABLED (CY_DMA_CHANNEL_DISABLED)
1865 #define CY_DMA_CH_ENABLED (CY_DMA_CHANNEL_ENABLED)
1866
1867 #define CY_DMA_TXFR_SIZE_DATA_SIZE (CY_DMA_TRANSFER_SIZE_DATA)
1868 #define CY_DMA_TXFR_SIZE_WORD (CY_DMA_TRANSFER_SIZE_WORD)
1869
1870 #define CY_DMA_INTR_1ELEMENT_CMPLT (CY_DMA_1ELEMENT)
1871 #define CY_DMA_INTR_X_LOOP_CMPLT (CY_DMA_X_LOOP)
1872 #define CY_DMA_INTR_DESCR_CMPLT (CY_DMA_DESCR)
1873 #define CY_DMA_INTR_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
1874
1875 #define CY_DMA_TRIGOUT_1ELEMENT_CMPLT (CY_DMA_1ELEMENT)
1876 #define CY_DMA_TRIGOUT_X_LOOP_CMPLT (CY_DMA_X_LOOP)
1877 #define CY_DMA_TRIGOUT_DESCR_CMPLT (CY_DMA_DESCR)
1878 #define CY_DMA_TRIGOUT_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
1879
1880 #define CY_DMA_TRIGIN_1ELEMENT (CY_DMA_1ELEMENT)
1881 #define CY_DMA_TRIGIN_XLOOP (CY_DMA_X_LOOP)
1882 #define CY_DMA_TRIGIN_DESCR (CY_DMA_DESCR)
1883 #define CY_DMA_TRIGIN_DESCRCHAIN (CY_DMA_DESCR_CHAIN)
1884
1885 #define CY_DMA_INVALID_INPUT_PARAMETERS (CY_DMA_BAD_PARAM)
1886
1887 #define CY_DMA_RETDIG_IM (CY_DMA_RETRIG_IM)
1888 #define CY_DMA_RETDIG_4CYC (CY_DMA_RETRIG_4CYC)
1889 #define CY_DMA_RETDIG_16CYC (CY_DMA_RETRIG_16CYC)
1890
1891 /* Descriptor structure items */
1892 #define DESCR_CTL ctl
1893 #define DESCR_SRC src
1894 #define DESCR_DST dst
1895 #define DESCR_X_CTL xCtl
1896 #define DESCR_Y_CTL yCtl
1897 #define DESCR_NEXT_PTR nextPtr
1898
1899 /* Descriptor structure bitfields */
1900 #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL
1901 #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL
1902 #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Pos 2UL
1903 #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Msk 0xCUL
1904 #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Pos 4UL
1905 #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL
1906 #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Pos 6UL
1907 #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL
1908 #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Pos 24UL
1909 #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL
1910 #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL
1911 #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL
1912 #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL
1913 #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL
1914 #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Pos 28UL
1915 #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk 0x30000000UL
1916 #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Pos 30UL
1917 #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Msk 0xC0000000UL
1918 #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Pos 0UL
1919 #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
1920 #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Pos 0UL
1921 #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Msk 0xFFFFFFFFUL
1922 #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Pos 0UL
1923 #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Msk 0xFFFUL
1924 #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Pos 12UL
1925 #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Msk 0xFFF000UL
1926 #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Pos 24UL
1927 #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Msk 0xFF000000UL
1928 #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Pos 0UL
1929 #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Msk 0xFFFUL
1930 #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Pos 12UL
1931 #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Msk 0xFFF000UL
1932 #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Pos 24UL
1933 #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Msk 0xFF000000UL
1934 #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Pos 2UL
1935 #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
1936
1937 /* Functions */
1938 #define Cy_DMA_GetActiveChnl Cy_DMA_GetActiveChannel
1939 #define Cy_DMA_GetActiveSrcAddr Cy_DMA_GetActiveSrcAddress
1940 #define Cy_DMA_GetActiveDstAddr Cy_DMA_GetActiveDstAddress
1941 #define Cy_DMA_Descr_Init Cy_DMA_Descriptor_Init
1942 #define Cy_DMA_Descr_DeInit Cy_DMA_Descriptor_DeInit
1943 #define Cy_DMA_Descr_SetSrcAddr Cy_DMA_Descriptor_SetSrcAddress
1944 #define Cy_DMA_Descr_SetDestAddr Cy_DMA_Descriptor_SetDstAddress
1945 #define Cy_DMA_Descr_SetNxtDescr Cy_DMA_Descriptor_SetNextDescriptor
1946 #define Cy_DMA_Descr_SetIntrType Cy_DMA_Descriptor_SetInterruptType
1947 #define Cy_DMA_Descr_SetTrigInType Cy_DMA_Descriptor_SetTriggerInType
1948 #define Cy_DMA_Descr_SetTrigOutType Cy_DMA_Descriptor_SetTriggerOutType
1949 #define Cy_DMA_Chnl_Init Cy_DMA_Channel_Init
1950 #define Cy_DMA_Chnl_DeInit Cy_DMA_Channel_DeInit
1951 #define Cy_DMA_Chnl_SetDescr Cy_DMA_Channel_SetDescriptor
1952 #define Cy_DMA_Chnl_Enable Cy_DMA_Channel_Enable
1953 #define Cy_DMA_Chnl_Disable Cy_DMA_Channel_Disable
1954 #define Cy_DMA_Chnl_GetCurrentDescr Cy_DMA_Channel_GetCurrentDescriptor
1955 #define Cy_DMA_Chnl_SetPriority Cy_DMA_Channel_SetPriority
1956 #define Cy_DMA_Chnl_GetPriority Cy_DMA_Channel_GetPriority
1957 #define Cy_DMA_Chnl_GetInterruptStatus Cy_DMA_Channel_GetInterruptStatus
1958 #define Cy_DMA_Chnl_GetInterruptCause Cy_DMA_Channel_GetStatus
1959 #define Cy_DMA_Chnl_ClearInterrupt Cy_DMA_Channel_ClearInterrupt
1960 #define Cy_DMA_Chnl_SetInterrupt Cy_DMA_Channel_SetInterrupt
1961 #define Cy_DMA_Chnl_GetInterruptMask Cy_DMA_Channel_GetInterruptMask
1962 #define Cy_DMA_Chnl_GetInterruptStatusMasked Cy_DMA_Channel_GetInterruptStatusMasked
1963 #define Cy_DMA_Chnl_SetInterruptMask(base, channel) (Cy_DMA_Channel_SetInterruptMask(base, channel, CY_DMA_INTR_MASK))
1964
1965
1966 /*******************************************************************************
1967 * Function Name: Cy_DMA_Descr_SetTxfrWidth
1968 ****************************************************************************//**
1969 * This is a legacy API function. It is left here just for backward compatibility.
1970 * Do not use it in new designs.
1971 *******************************************************************************/
Cy_DMA_Descr_SetTxfrWidth(cy_stc_dma_descr_t * descriptor,uint32_t dataElementSize,uint32_t srcTxfrWidth,uint32_t dstTxfrWidth)1972 __STATIC_INLINE void Cy_DMA_Descr_SetTxfrWidth(cy_stc_dma_descr_t * descriptor,
1973 uint32_t dataElementSize,
1974 uint32_t srcTxfrWidth,
1975 uint32_t dstTxfrWidth)
1976 {
1977 uint32_t regValue;
1978 regValue = descriptor->ctl & ((uint32_t)(~(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk |
1979 DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk |
1980 DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk)));
1981
1982 descriptor->ctl = regValue |
1983 _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE, dataElementSize) |
1984 _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE, srcTxfrWidth) |
1985 _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE, dstTxfrWidth);
1986 }
1987
1988 #endif /* CY_DMA_BWC */
1989
1990 /** \endcond */
1991
1992 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.8');
1993
1994 #if defined(__cplusplus)
1995 }
1996 #endif
1997
1998 #endif /* CY_IP_M4CPUSS_DMA, CY_IP_MXDW */
1999
2000 #endif /* (CY_DMA_H) */
2001
2002 /** \} group_dma */
2003
2004
2005 /* [] END OF FILE */
2006
