1 /***************************************************************************//**
2 * \file cy_syslib.h
3 * \version 2.90
4 *
5 * Provides an API declaration of the SysLib driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_syslib
27 * \{
28 * The system libraries provide APIs that can be called in the user application
29 * to handle the timing, logical checking or register.
30 *
31 * The functions and other declarations used in this driver are in cy_syslib.h.
32 * You can include cy_pdl.h to get access to all functions
33 * and declarations in the PDL.
34 *
35 * The SysLib driver contains a set of different system functions. These functions
36 * can be called in the application routine. Major features of the system library:
37 * * Delay functions
38 * * The register Read/Write macro
39 * * Assert and Halt
40 * * Assert Classes and Levels
41 * * A software reset
42 * * Reading the reset cause
43 * * An API to invalidate the flash cache and buffer
44 * * Data manipulation macro
45 * * A variable type definition from MISRA-C which specifies signedness
46 * * Cross compiler compatible attributes
47 * * Getting a silicon-unique ID API
48 * * Setting wait states API
49 * * Resetting the backup domain API
50 * * APIs to serve Fault handler
51 *
52 * \section group_syslib_configuration Configuration Considerations
53 * <b> Assertion Usage </b> <br />
54 * Use the CY_ASSERT() macro to check expressions that must be true if the
55 * program is running correctly. It is a convenient way to insert sanity checks.
56 * The CY_ASSERT() macro is defined in the cy_utils.h file, which is part of the
57 * <a href="https://github.com/cypresssemiconductorco/core-lib">Cypress Core Library (core-lib)</a>.
58 * The macro behavior is as follows: if the expression passed
59 * to the macro is false, the CPU is halted. \n
60 *
61 * Starting from the driver version 2.50, the CY_ASSERT macro was moved
62 * to the Cypress Core Library (core-lib). Also, the CY_ASSERT implementation
63 * was changed not to call Cy_SysLib_AssertFailed() function, so user application
64 * that relied on that should take this change into account. \n
65 *
66 *
67 * The PDL source code uses this assert mechanism extensively. It is recommended
68 * that you enable asserts when debugging firmware. \n
69 * <b> Assertion Classes and Levels </b> <br />
70 * The <a href="https://github.com/cypresssemiconductorco/core-lib">Cypress Core Library</a>
71 * defines three assert classes, which correspond to different
72 * kinds of parameters. There is a corresponding assert "level" for each class.
73 * <table class="doxtable">
74 * <tr><th>Class Macro</th><th>Level Macro</th><th>Type of check</th></tr>
75 * <tr>
76 * <td>CY_ASSERT_CLASS_1</td>
77 * <td>CY_ASSERT_L1</td>
78 * <td>A parameter that could change between different PSoC devices
79 * (e.g. the number of clock paths)</td>
80 * </tr>
81 * <tr>
82 * <td>CY_ASSERT_CLASS_2</td>
83 * <td>CY_ASSERT_L2</td>
84 * <td>A parameter that has fixed limits such as a counter period</td>
85 * </tr>
86 * <tr>
87 * <td>CY_ASSERT_CLASS_3</td>
88 * <td>CY_ASSERT_L3</td>
89 * <td>A parameter that is an enum constant</td>
90 * </tr>
91 * </table>
92 * Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL.
93 * This is a compiler command line argument, similar to how the DEBUG / NDEBUG
94 * macro is passed. \n
95 * Enabling any class also enables any lower-numbered class.
96 * CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three
97 * classes. The following example shows the command-line option to enable all
98 * the assert levels:
99 * \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode
100 * \note The use of special characters, such as spaces, parenthesis, etc. must
101 * be protected with quotes.
102 *
103 * After CY_ASSERT_LEVEL is defined, firmware can use
104 * one of the three level macros to make an assertion. For example, if the
105 * parameter can vary between devices, firmware uses the L1 macro.
106 * \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode
107 * If the parameter has bounds, firmware uses L2.
108 * \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode
109 * If the parameter is an enum, firmware uses L3.
110 * \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode
111 * Each check uses the appropriate level macro for the kind of parameter being checked.
112 * If a particular assert class/level is not enabled, then the assert does nothing.
113 *
114 * \section group_syslib_more_information More Information
115 * Refer to the technical reference manual (TRM).
116 *
117 * \section group_syslib_changelog Changelog
118 * <table class="doxtable">
119 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
120 * <tr>
121 * <td rowspan="2">2.90</td>
122 * <td>Added new functions \ref Cy_SysLib_Rtos_Delay, \ref Cy_SysLib_Rtos_DelayUs.</td>
123 * <td>Provide user an option to overwrite delay function implementation based on target RTOS environment.</td>
124 * </tr>
125 * <tr>
126 * <td>Added new functions \ref Cy_SysLib_GetResetStatus, \ref Cy_SysLib_GetWcoTrim and \ref Cy_SysLib_SetWcoTrim.</td>
127 * <td>Add a possibility to manage the backup domain reset better and to store/restore the WCO trimming value.</td>
128 * </tr>
129 * <tr>
130 * <td rowspan="2">2.80</td>
131 * <td>Support for CM33.</td>
132 * <td>New devices support.</td>
133 * </tr>
134 * <tr>
135 * <td>Update \ref Cy_SysLib_GetResetReason API to read RES_CAUSE2 register as well.</td>
136 * <td>Code Enhancement/Bug Fix.</td>
137 * </tr>
138 * <tr>
139 * <td rowspan="4">2.70</td>
140 * <td>Added new macros CY_SECTION_RAMFUNC_BEGIN, CY_SECTION_RAMFUNC_END,
141 * CY_SECTION_SHAREDMEM to enable overriding of the linker section placement.</td>
142 * <td>Enhancement based on usability feedback.</td>
143 * </tr>
144 * <tr>
145 * <td>Noted that implementation of CY_ASSERT() was changed back in version 2.50,
146 * so that Cy_SysLib_AssertFailed() function is not called and user application
147 * may need to be updated.</td>
148 * <td>Documentation update.</td>
149 * </tr>
150 * <tr>
151 * <td>Removed the issue related to the malloc() failure to report error for the case when
152 * requested allocation size is bigger than the heap size.
153 * Refer to the \ref group_system_config_heap_stack_config_gcc section for the more details.
154 * Removed empty Known Issues section.
155 * <td>Documentation update and clarification.</td>
156 * </tr>
157 * <tr>
158 * <td>Fixed/Documented MISRA 2012 violations.</td>
159 * <td>MISRA 2012 compliance.</td>
160 * </tr>
161 * <tr>
162 * <td>2.60.1</td>
163 * <td>Updated the Configuration Considerations section with the information that
164 * CY_ASSERT() macro is defined in the cy_utils.h file, which is part of the
165 * <a href="https://github.com/cypresssemiconductorco/core-lib">Cypress Core Library (core-lib)</a>
166 * <td>Documentation update and clarification.</td>
167 * </tr>
168 * <tr>
169 * <td rowspan="2">2.60</td>
170 * <td>Updated the following functions for the PSoC 64 devices:
171 * \ref Cy_SysLib_ClearFlashCacheAndBuffer, \ref Cy_SysLib_ClearResetReason,
172 * \ref Cy_SysLib_SetWaitStates.
173 * <td>Added PSoC 64 device support.</td>
174 * </tr>
175 * <tr>
176 * <td>Minor documentation updates.</td>
177 * <td>Documentation enhancement.</td>
178 * </tr>
179 * <tr>
180 * <td>2.50.3</td>
181 * <td>Add section Known Issues
182 * <td>Documentation update and clarification.</td>
183 * </tr>
184 * <tr>
185 * <td>2.50.1</td>
186 * <td>Used the core library defines for the message codes forming.
187 * <td>Improve PDL code base.</td>
188 * </tr>
189 * <tr>
190 * <td>2.50</td>
191 * <td>Moved following macros to the core library:
192 * CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32,
193 * CY_SWAP_ENDIAN64,CY_GET_REG8,CY_SET_REG8,CY_GET_REG16,CY_SET_REG16,
194 * CY_GET_REG24,CY_SET_REG24,CY_GET_REG32,CY_SET_REG32,_CLR_SET_FLD32U,
195 * CY_REG32_CLR_SET,_CLR_SET_FLD16U,CY_REG16_CLR_SET,_CLR_SET_FLD8U,
196 * CY_REG8_CLR_SET,_BOOL2FLD,_FLD2BOOL,CY_SYSLIB_DIV_ROUND,
197 * CY_SYSLIB_DIV_ROUNDUP,CY_NOINIT,CY_SECTION,CY_UNUSED,CY_NOINLINE,
198 * CY_ALIGN,CY_RAMFUNC_BEGIN,CY_RAMFUNC_END.
199 * Use at least version 1.1 of the core library: https://github.com/cypresssemiconductorco/core-lib.
200 * <td>Improve PDL code base.</td>
201 * </tr>
202 * <tr>
203 * <td>2.40.1</td>
204 * <td>Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.</td>
205 * <td>Removed the IAR compiler warning.</td>
206 * </tr>
207 * <tr>
208 * <td>2.40</td>
209 * <td>Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.</td>
210 * <td>Improve PDL code base.</td>
211 * </tr>
212 * <tr>
213 * <td rowspan="3">2.30</td>
214 * <td>Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.</td>
215 * <td>Provided support for the ARM Compiler 6.</td>
216 * </tr>
217 * <tr>
218 * <td>Minor documentation edits.</td>
219 * <td>Documentation update and clarification.</td>
220 * </tr>
221 * <tr>
222 * <td>Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.</td>
223 * <td>Improve user experience.</td>
224 * </tr>
225 * <tr>
226 * <td rowspan="2">2.20</td>
227 * <td>Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.</td>
228 * <td>Provided support for the PDL static library in Release mode.</td>
229 * </tr>
230 * <tr>
231 * <td>Minor documentation edits.</td>
232 * <td>Documentation update and clarification.</td>
233 * </tr>
234 * <tr>
235 * <td rowspan="4">2.10</td>
236 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
237 * <td>Driver library directory-structure simplification.</td>
238 * </tr>
239 * <tr>
240 * <td>Added the following macros: CY_REG32_CLR_SET, _CLR_SET_FLD16U, CY_REG16_CLR_SET, _CLR_SET_FLD8U, CY_REG8_CLR_SET</td>
241 * <td>Register access simplification.</td>
242 * </tr>
243 * <tr>
244 * <td>Removed the Cy_SysLib_GetNumHfclkResetCause API function.</td>
245 * <td>This feature is not supported by SRSS_ver1.</td>
246 * </tr>
247 * <tr>
248 * <td>Added register access layer. Use register access macros instead
249 * of direct register access using dereferenced pointers.</td>
250 * <td>Makes register access device-independent, so that the PDL does
251 * not need to be recompiled for each supported part number.</td>
252 * </tr>
253 * <tr>
254 * <td>2.0.1</td>
255 * <td>Minor documentation edits</td>
256 * <td>Documentation update and clarification</td>
257 * </tr>
258 * <tr>
259 * <td rowspan="4"> 2.0</td>
260 * <td>
261 * Added Cy_SysLib_ResetBackupDomain() API implementation. \n
262 * Added CY_NOINLINE attribute implementation. \n
263 * Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n
264 * Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n
265 * Optimized Cy_SysLib_SetWaitStates() API implementation.
266 * </td>
267 * <td>Improvements made based on usability feedback.</td>
268 * </tr>
269 * <tr>
270 * <td>Added Assertion Classes and Levels.</td>
271 * <td>For error checking, parameter validation and status returns in the PDL API.</td>
272 * </tr>
273 * <tr>
274 * <td>Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.</td>
275 * <td>To store debug information into a non-zero init area for future analysis.</td>
276 * </tr>
277 * <tr>
278 * <td>Removed CY_WEAK attribute implementation.</td>
279 * <td>CMSIS __WEAK attribute should be used instead.</td>
280 * </tr>
281 * <tr>
282 * <td>1.0</td>
283 * <td>Initial version</td>
284 * <td></td>
285 * </tr>
286 * </table>
287 *
288 * \defgroup group_syslib_macros Macros
289 * \defgroup group_syslib_functions Functions
290 * \defgroup group_syslib_data_structures Data Structures
291 * \defgroup group_syslib_enumerated_types Enumerated Types
292 *
293 */
294
295 #if !defined (CY_SYSLIB_H)
296 #define CY_SYSLIB_H
297
298 #include "cy_device.h"
299
300 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS)
301
302 #include <stdint.h>
303 #include <stdbool.h>
304 #include "cy_utils.h"
305 #include "cy_result.h"
306
307 #if defined(__cplusplus)
308 extern "C" {
309 #endif /* defined(__cplusplus) */
310
311 #if defined( __ICCARM__ )
312 /* Suppress the warning for multiple volatile variables in an expression. */
313 /* This is common for driver's code and the usage is not order-dependent. */
314 #pragma diag_suppress=Pa082
315 #endif /* defined( __ICCARM__ ) */
316
317 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 8.6', 3, \
318 'Coverity does not check the .S assembly files, the definition is a part of syslib assembly source file.');
319
320 /**
321 * \addtogroup group_syslib_macros
322 * \{
323 */
324
325 /******************************************************************************
326 * Macros
327 *****************************************************************************/
328
329 #ifdef CY_IP_M4CPUSS
330
331 /**
332 * \note
333 * This macro is available for devices having M4CPUSS IP.
334 **/
335 #define CY_CPU_CORTEX_M0P (__CORTEX_M == 0) /**< CM0+ core CPU Code */
336 /**
337 * \note
338 * This macro is available for devices having M4CPUSS IP.
339 **/
340 #define CY_CPU_CORTEX_M4 (__CORTEX_M == 4) /**< CM4 core CPU Code */
341 /**
342 * \note
343 * This macro is available for devices having M4CPUSS IP.
344 **/
345 /** The macro to disable the Fault Handler */
346 #define CY_ARM_FAULT_DEBUG_DISABLED (0U)
347 /**
348 * \note
349 * This macro is available for devices having M4CPUSS IP.
350 **/
351 /** The macro to enable the Fault Handler */
352 #define CY_ARM_FAULT_DEBUG_ENABLED (1U)
353
354 #if !defined (CY_ARM_FAULT_DEBUG)
355 /**
356 * \note
357 * This macro is available for devices having M4CPUSS IP.
358 **/
359 /** The macro defines if the Fault Handler is enabled. Enabled by default. */
360 #define CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED)
361 #endif /* CY_ARM_FAULT_DEBUG */
362
363 #endif /* CY_IP_M4CPUSS */
364
365 /**
366 * \defgroup group_syslib_macros_status_codes Status codes
367 * \{
368 * Function status type codes
369 */
370 /** \cond INTERNAL */
371
372 #ifdef CY_IP_M4CPUSS
373 /**
374 * \note
375 * This macro is available for devices having M4CPUSS IP.
376 **/
377 #define CY_PDL_STATUS_CODE_Pos (CY_RSLT_CODE_POSITION) /**< The module status code position in the status code */
378 /**
379 * \note
380 * This macro is available for devices having M4CPUSS IP.
381 **/
382 #define CY_PDL_STATUS_TYPE_Pos (CY_RSLT_TYPE_POSITION) /**< The status type position in the status code */
383 /**
384 * \note
385 * This macro is available for devices having M4CPUSS IP.
386 **/
387 #define CY_PDL_MODULE_ID_Pos (CY_RSLT_MODULE_POSITION) /**< The software module ID position in the status code */
388 /**
389 * \note
390 * This macro is available for devices having M4CPUSS IP.
391 **/
392 #define CY_PDL_STATUS_INFO ((uint32_t)CY_RSLT_TYPE_INFO << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */
393 /**
394 * \note
395 * This macro is available for devices having M4CPUSS IP.
396 **/
397 #define CY_PDL_STATUS_WARNING ((uint32_t)CY_RSLT_TYPE_WARNING << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */
398 /**
399 * \note
400 * This macro is available for devices having M4CPUSS IP.
401 **/
402 #define CY_PDL_STATUS_ERROR ((uint32_t)CY_RSLT_TYPE_ERROR << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */
403 /**
404 * \note
405 * This macro is available for devices having M4CPUSS IP.
406 **/
407 #define CY_PDL_MODULE_ID_Msk (CY_RSLT_MODULE_MASK) /**< The software module ID mask */
408 #endif /* CY_IP_M4CPUSS */
409
410 /** \endcond */
411
412 #if defined (CY_IP_M33SYSCPUSS)
413
414 #define CY_PDL_STATUS_CODE_Pos (0U) /**< The module status code position in the status code */
415 #define CY_PDL_STATUS_TYPE_Pos (16U) /**< The status type position in the status code */
416 #define CY_PDL_MODULE_ID_Pos (18U) /**< The software module ID position in the status code */
417 #define CY_PDL_STATUS_INFO (0UL << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */
418 #define CY_PDL_STATUS_WARNING (1UL << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */
419 #define CY_PDL_STATUS_ERROR (2UL << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */
420 #define CY_PDL_MODULE_ID_Msk (0x3FFFU) /**< The software module ID mask */
421
422 #endif
423
424 /** Get the software PDL module ID */
425 #define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos))
426 #define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11U) /**< SYSLIB PDL ID */
427 /** \} group_syslib_macros_status_codes */
428
429 /** \} group_syslib_macros */
430
431 /**
432 * \addtogroup group_syslib_enumerated_types
433 * \{
434 */
435
436 /** The SysLib status code structure. */
437 typedef enum
438 {
439 CY_SYSLIB_SUCCESS = 0x00UL, /**< The success status code */
440 CY_SYSLIB_BAD_PARAM = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< The bad parameter status code */
441 CY_SYSLIB_TIMEOUT = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< The time out status code */
442 CY_SYSLIB_INVALID_STATE = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< The invalid state status code */
443 CY_SYSLIB_UNKNOWN = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown status code */
444 } cy_en_syslib_status_t;
445
446 /** \} group_syslib_enumerated_types */
447 /**
448 * \addtogroup group_syslib_data_structures
449 * \{
450 */
451
452 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
453 #if (CY_CPU_CORTEX_M4)
454 /** Configurable Fault Status Register - CFSR */
455 typedef struct
456 {
457 /** MemManage Fault Status Sub-register - MMFSR */
458 uint32_t iaccViol : 1; /**< MemManage Fault - The instruction access violation flag */
459 uint32_t daccViol : 1; /**< MemManage Fault - The data access violation flag */
460 uint32_t reserved1 : 1; /**< Reserved */
461 uint32_t mUnstkErr : 1; /**< MemManage Fault - Unstacking for a return from exception */
462 uint32_t mStkErr : 1; /**< MemManage Fault - MemManage fault on stacking for exception entry */
463 uint32_t mlspErr : 1; /**< MemManage Fault - MemManage fault occurred during floating-point lazy state preservation */
464 uint32_t reserved2 : 1; /**< Reserved */
465 uint32_t mmarValid : 1; /**< MemManage Fault - The MemManage Address register valid flag */
466 /** Bus Fault Status Sub-register - UFSR */
467 uint32_t iBusErr : 1; /**< Bus Fault - The instruction bus error */
468 uint32_t precisErr : 1; /**< Bus Fault - The precise Data bus error */
469 uint32_t imprecisErr : 1; /**< Bus Fault - The imprecise data bus error */
470 uint32_t unstkErr : 1; /**< Bus Fault - Unstacking for an exception return has caused one or more bus faults */
471 uint32_t stkErr : 1; /**< Bus Fault - Stacking for an exception entry has caused one or more bus faults */
472 uint32_t lspErr : 1; /**< Bus Fault - A bus fault occurred during the floating-point lazy state */
473 uint32_t reserved3 : 1; /**< Reserved */
474 uint32_t bfarValid : 1; /**< Bus Fault - The bus fault address register valid flag */
475 /** Usage Fault Status Sub-register - UFSR */
476 uint32_t undefInstr : 1; /**< Usage Fault - An undefined instruction */
477 uint32_t invState : 1; /**< Usage Fault - The invalid state */
478 uint32_t invPC : 1; /**< Usage Fault - An invalid PC */
479 uint32_t noCP : 1; /**< Usage Fault - No coprocessor */
480 uint32_t reserved4 : 4; /**< Reserved */
481 uint32_t unaligned : 1; /**< Usage Fault - Unaligned access */
482 uint32_t divByZero : 1; /**< Usage Fault - Divide by zero */
483 uint32_t reserved5 : 6; /**< Reserved */
484 } cy_stc_fault_cfsr_t;
485
486 /** Hard Fault Status Register - HFSR */
487 typedef struct
488 {
489 uint32_t reserved1 : 1; /**< Reserved. */
490 uint32_t vectTbl : 1; /**< HFSR - Indicates a bus fault on a vector table read during exception processing */
491 uint32_t reserved2 : 28; /**< Reserved. */
492 uint32_t forced : 1; /**< HFSR - Indicates a forced hard fault */
493 uint32_t debugEvt : 1; /**< HFSR - Reserved for the debug use. */
494 } cy_stc_fault_hfsr_t;
495
496 /** System Handler Control and State Register - SHCSR */
497 typedef struct
498 {
499 uint32_t memFaultAct : 1; /**< SHCSR - The MemManage exception active bit, reads as 1 if the exception is active */
500 uint32_t busFaultAct : 1; /**< SHCSR - The BusFault exception active bit, reads as 1 if the exception is active */
501 uint32_t reserved1 : 1; /**< Reserved. */
502 uint32_t usgFaultAct : 1; /**< SHCSR - The UsageFault exception active bit, reads as 1 if the exception is active */
503 uint32_t reserved2 : 3; /**< Reserved. */
504 uint32_t svCallAct : 1; /**< SHCSR - The SVCall active bit, reads as 1 if the SVC call is active */
505 uint32_t monitorAct : 1; /**< SHCSR - The debug monitor active bit, reads as 1 if the debug monitor is active */
506 uint32_t reserved3 : 1; /**< Reserved. */
507 uint32_t pendSVAct : 1; /**< SHCSR - The PendSV exception active bit, reads as 1 if the exception is active */
508 uint32_t sysTickAct : 1; /**< SHCSR - The SysTick exception active bit, reads as 1 if the exception is active */
509 uint32_t usgFaultPended : 1; /**< SHCSR - The UsageFault exception pending bit, reads as 1 if the exception is pending */
510 uint32_t memFaultPended : 1; /**< SHCSR - The MemManage exception pending bit, reads as 1 if the exception is pending */
511 uint32_t busFaultPended : 1; /**< SHCSR - The BusFault exception pending bit, reads as 1 if the exception is pending */
512 uint32_t svCallPended : 1; /**< SHCSR - The SVCall pending bit, reads as 1 if the exception is pending */
513 uint32_t memFaultEna : 1; /**< SHCSR - The MemManage enable bit, set to 1 to enable */
514 uint32_t busFaultEna : 1; /**< SHCSR - The BusFault enable bit, set to 1 to enable */
515 uint32_t usgFaultEna : 1; /**< SHCSR - The UsageFault enable bit, set to 1 to enable */
516 uint32_t reserved4 : 13; /**< Reserved */
517 } cy_stc_fault_shcsr_t;
518 #endif /* CY_CPU_CORTEX_M4 */
519
520 /** The fault configuration structure. */
521 typedef struct
522 {
523 uint32_t r0; /**< R0 register content */
524 uint32_t r1; /**< R1 register content */
525 uint32_t r2; /**< R2 register content */
526 uint32_t r3; /**< R3 register content */
527 uint32_t r12; /**< R12 register content */
528 uint32_t lr; /**< LR register content */
529 uint32_t pc; /**< PC register content */
530 uint32_t psr; /**< PSR register content */
531 #if (CY_CPU_CORTEX_M4)
532 union
533 {
534 uint32_t cfsrReg; /**< CFSR register content as a word */
535 cy_stc_fault_cfsr_t cfsrBits; /**< CFSR register content as a structure */
536 } cfsr;
537 union
538 {
539 uint32_t hfsrReg; /**< HFSR register content as a word */
540 cy_stc_fault_hfsr_t hfsrBits; /**< HFSR register content as a structure */
541 } hfsr;
542 union
543 {
544 uint32_t shcsrReg; /**< SHCSR register content as a word */
545 cy_stc_fault_shcsr_t shcsrBits; /**< SHCSR register content as a structure */
546 } shcsr;
547 uint32_t mmfar; /**< MMFAR register content */
548 uint32_t bfar; /**< BFAR register content */
549 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
550 (defined (__FPU_USED ) && (__FPU_USED == 1U)))
551 uint32_t s0; /**< FPU S0 register content */
552 uint32_t s1; /**< FPU S1 register content */
553 uint32_t s2; /**< FPU S2 register content */
554 uint32_t s3; /**< FPU S3 register content */
555 uint32_t s4; /**< FPU S4 register content */
556 uint32_t s5; /**< FPU S5 register content */
557 uint32_t s6; /**< FPU S6 register content */
558 uint32_t s7; /**< FPU S7 register content */
559 uint32_t s8; /**< FPU S8 register content */
560 uint32_t s9; /**< FPU S9 register content */
561 uint32_t s10; /**< FPU S10 register content */
562 uint32_t s11; /**< FPU S11 register content */
563 uint32_t s12; /**< FPU S12 register content */
564 uint32_t s13; /**< FPU S13 register content */
565 uint32_t s14; /**< FPU S14 register content */
566 uint32_t s15; /**< FPU S15 register content */
567 uint32_t fpscr; /**< FPU FPSCR register content */
568 #endif /* __FPU_PRESENT */
569 #endif /* CY_CPU_CORTEX_M4 */
570 } cy_stc_fault_frame_t;
571 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
572
573 /** \} group_syslib_data_structures */
574
575 /**
576 * \addtogroup group_syslib_macros
577 * \{
578 */
579
580 /** The driver major version */
581 #define CY_SYSLIB_DRV_VERSION_MAJOR 2
582
583 /** The driver minor version */
584 #define CY_SYSLIB_DRV_VERSION_MINOR 90
585
586 /** Define start of the function placed to the SRAM area by the linker */
587 #ifndef CY_SECTION_RAMFUNC_BEGIN
588 #if defined (__ICCARM__)
589 #define CY_SECTION_RAMFUNC_BEGIN CY_PRAGMA(diag_suppress = Ta023) __ramfunc
590 #else
591 #define CY_SECTION_RAMFUNC_BEGIN CY_SECTION(".cy_ramfunc")
592 #endif
593 #endif
594
595 /** Define end of the function placed to the SRAM area by the linker */
596 #ifndef CY_SECTION_RAMFUNC_END
597 #if defined (__ICCARM__)
598 #define CY_SECTION_RAMFUNC_END CY_PRAGMA(diag_default = Ta023)
599 #else
600 #define CY_SECTION_RAMFUNC_END
601 #endif
602 #endif
603
604 /** Define variable to be placed to the shared SRAM area by the linker */
605 #ifndef CY_SECTION_SHAREDMEM
606 #define CY_SECTION_SHAREDMEM CY_SECTION(".cy_sharedmem")
607 #endif
608
609 typedef void (* cy_israddress)(void); /**< Type of ISR callbacks */
610 #if defined (__ICCARM__)
611 typedef union { cy_israddress __fun; void * __ptr; } cy_intvec_elem;
612 #endif /* defined (__ICCARM__) */
613
614 /* MISRA rule 6.3 recommends using specific-length typedef for the basic
615 * numerical types of signed and unsigned variants of char, float, and double.
616 */
617 typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */
618 typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */
619 typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */
620
621 #if !defined(NDEBUG)
622 /** The max size of the file name which stores the ASSERT location */
623 #define CY_MAX_FILE_NAME_SIZE (24U)
624 extern CY_NOINIT char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE]; /**< The assert buffer */
625 extern CY_NOINIT uint32_t cy_assertLine; /**< The assert line value */
626 #endif /* NDEBUG */
627
628 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
629 #define CY_R0_Pos (0U) /**< The position of the R0 content in a fault structure */
630 #define CY_R1_Pos (1U) /**< The position of the R1 content in a fault structure */
631 #define CY_R2_Pos (2U) /**< The position of the R2 content in a fault structure */
632 #define CY_R3_Pos (3U) /**< The position of the R3 content in a fault structure */
633 #define CY_R12_Pos (4U) /**< The position of the R12 content in a fault structure */
634 #define CY_LR_Pos (5U) /**< The position of the LR content in a fault structure */
635 #define CY_PC_Pos (6U) /**< The position of the PC content in a fault structure */
636 #define CY_PSR_Pos (7U) /**< The position of the PSR content in a fault structure */
637 #if (CY_CPU_CORTEX_M4) && ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
638 (defined (__FPU_USED ) && (__FPU_USED == 1U)))
639 #define CY_FPSCR_IXC_Msk (0x00000010U) /**< The cumulative exception bit for floating-point exceptions */
640 #define CY_FPSCR_IDC_Msk (0x00000080U) /**< The cumulative exception bit for floating-point exceptions */
641 #define CY_S0_Pos (8U) /**< The position of the FPU S0 content in a fault structure */
642 #define CY_S1_Pos (9U) /**< The position of the FPU S1 content in a fault structure */
643 #define CY_S2_Pos (10U) /**< The position of the FPU S2 content in a fault structure */
644 #define CY_S3_Pos (11U) /**< The position of the FPU S3 content in a fault structure */
645 #define CY_S4_Pos (12U) /**< The position of the FPU S4 content in a fault structure */
646 #define CY_S5_Pos (13U) /**< The position of the FPU S5 content in a fault structure */
647 #define CY_S6_Pos (14U) /**< The position of the FPU S6 content in a fault structure */
648 #define CY_S7_Pos (15U) /**< The position of the FPU S7 content in a fault structure */
649 #define CY_S8_Pos (16U) /**< The position of the FPU S8 content in a fault structure */
650 #define CY_S9_Pos (17U) /**< The position of the FPU S9 content in a fault structure */
651 #define CY_S10_Pos (18U) /**< The position of the FPU S10 content in a fault structure */
652 #define CY_S11_Pos (19U) /**< The position of the FPU S11 content in a fault structure */
653 #define CY_S12_Pos (20U) /**< The position of the FPU S12 content in a fault structure */
654 #define CY_S13_Pos (21U) /**< The position of the FPU S13 content in a fault structure */
655 #define CY_S14_Pos (22U) /**< The position of the FPU S14 content in a fault structure */
656 #define CY_S15_Pos (23U) /**< The position of the FPU S15 content in a fault structure */
657 #define CY_FPSCR_Pos (24U) /**< The position of the FPU FPSCR content in a fault structure */
658 #endif /* CY_CPU_CORTEX_M4 && __FPU_PRESENT */
659
660 extern CY_NOINIT cy_stc_fault_frame_t cy_faultFrame; /**< Fault frame structure */
661 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
662
663
664 /**
665 * \defgroup group_syslib_macros_assert Assert Classes and Levels
666 * \{
667 * Defines for the Assert Classes and Levels
668 */
669
670 /**
671 * Class 1 - The highest class, safety-critical functions which rely on parameters that could be
672 * changed between different PSoC devices
673 */
674 #define CY_ASSERT_CLASS_1 (1U)
675
676 /** Class 2 - Functions that have fixed limits such as counter periods (16-bits/32-bits etc.) */
677 #define CY_ASSERT_CLASS_2 (2U)
678
679 /** Class 3 - Functions that accept enums as constant parameters */
680 #define CY_ASSERT_CLASS_3 (3U)
681
682 #ifndef CY_ASSERT_LEVEL
683 /** The user-definable assert level from compiler command-line argument (similarly to DEBUG / NDEBUG) */
684 #define CY_ASSERT_LEVEL CY_ASSERT_CLASS_3
685 #endif /* CY_ASSERT_LEVEL */
686
687 #if (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1)
688 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
689 #define CY_ASSERT_L2(x) do{}while(false) /**< Assert Level 2 */
690 #define CY_ASSERT_L3(x) do{}while(false) /**< Assert Level 3 */
691 #elif (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_2)
692 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
693 #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
694 #define CY_ASSERT_L3(x) do{}while(false) /**< Assert Level 3 */
695 #else /* Default is Level 3 */
696 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
697 #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
698 #define CY_ASSERT_L3(x) CY_ASSERT(x) /**< Assert Level 3 */
699 #endif /* CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1 */
700
701 /** \} group_syslib_macros_assert */
702
703 #ifdef CY_IP_M33SYSCPUSS
704 /*******************************************************************************
705 * Macro Name: CY_UNUSED_PARAM
706 ****************************************************************************//**
707 *
708 * Suppresses the unused parameter warning
709 *
710 * \note
711 * This macro is available for devices having M33SYSCPUSS IP.
712 *
713 *******************************************************************************/
714 #define CY_UNUSED_PARAM(a) (void)(a)
715
716 /*******************************************************************************
717 * Macro Name: CY_ARRAY_SIZE(x)
718 ****************************************************************************//**
719 *
720 * Returns the size of Array
721 *
722 * \param x Array Name
723 *
724 * \note
725 * This macro is available for devices having M33SYSCPUSS IP.
726 *
727 *******************************************************************************/
728 #define CY_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
729 #endif /* CY_IP_M33SYSCPUSS */
730
731
732 /******************************************************************************
733 * Constants
734 *****************************************************************************/
735 /** Defines a 32-kHz clock delay */
736 #define CY_DELAY_MS_OVERFLOW (0x8000U)
737
738 /**
739 * \defgroup group_syslib_macros_reset_cause Reset cause
740 * \{
741 * Define RESET_CAUSE mask values
742 */
743 /** A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. */
744 #define CY_SYSLIB_RESET_HWWDT (0x0001U)
745 /** The fault logging system requested a reset from its Active logic. */
746 #define CY_SYSLIB_RESET_ACT_FAULT (0x0002U)
747 /** The fault logging system requested a reset from its Deep-Sleep logic. */
748 #define CY_SYSLIB_RESET_DPSLP_FAULT (0x0004U)
749
750 #ifdef CY_IP_M33SYSCPUSS
751 /** The fault logging system requested a reset from its Test Controller or debugger asserted test. */
752 /**
753 * \note
754 * This macro is available for devices having M33SYSCPUSS IP.
755 **/
756 #define CY_SYSLIB_RESET_TC_DBGRESET (0x0008U)
757 #endif
758
759 /** The CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. */
760 #define CY_SYSLIB_RESET_SOFT (0x0010U)
761 /** The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle. */
762 #define CY_SYSLIB_RESET_SWWDT0 (0x0020U)
763 /** The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle. */
764 #define CY_SYSLIB_RESET_SWWDT1 (0x0040U)
765 /** The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle. */
766 #define CY_SYSLIB_RESET_SWWDT2 (0x0080U)
767 /** The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle. */
768 #define CY_SYSLIB_RESET_SWWDT3 (0x0100U)
769 /** The reset has occured on a loss of high-frequency clock. */
770 #define CY_SYSLIB_RESET_CSV_LOSS_WAKEUP (0x10000UL)
771 /** The reset has occured due to frequency error of high-frequency clock. */
772 #define CY_SYSLIB_RESET_CSV_ERROR_WAKEUP (0x20000UL)
773 /** The reset has occurred on a wakeup from Hibernate power mode. */
774 #define CY_SYSLIB_RESET_HIB_WAKEUP (0x40000UL)
775
776 /** \} group_syslib_macros_reset_cause */
777
778 #ifdef CY_IP_M4CPUSS
779 /** Bit[31:24] Opcode = 0x1B (SoftReset)
780 * Bit[7:1] Type = 1 (Only CM4 reset)
781 */
782 /**
783 * \note
784 * This macro is available for devices having M4CPUSS IP.
785 **/
786 #define CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL)
787
788 /**
789 * \defgroup group_syslib_macros_unique_id Unique ID
790 * \{
791 * Unique ID fields positions
792 */
793 /**
794 * \note
795 * This macro is available for devices having M4CPUSS IP.
796 **/
797 #define CY_UNIQUE_ID_DIE_YEAR_Pos (57U) /**< The position of the DIE_YEAR field in the silicon Unique ID */
798 /**
799 * \note
800 * This macro is available for devices having M4CPUSS IP.
801 **/
802 #define CY_UNIQUE_ID_DIE_MINOR_Pos (56U) /**< The position of the DIE_MINOR field in the silicon Unique ID */
803 /**
804 * \note
805 * This macro is available for devices having M4CPUSS IP.
806 **/
807 #define CY_UNIQUE_ID_DIE_SORT_Pos (48U) /**< The position of the DIE_SORT field in the silicon Unique ID */
808 /**
809 * \note
810 * This macro is available for devices having M4CPUSS IP.
811 **/
812 #define CY_UNIQUE_ID_DIE_Y_Pos (40U) /**< The position of the DIE_Y field in the silicon Unique ID */
813 /**
814 * \note
815 * This macro is available for devices having M4CPUSS IP.
816 **/
817 #define CY_UNIQUE_ID_DIE_X_Pos (32U) /**< The position of the DIE_X field in the silicon Unique ID */
818 /**
819 * \note
820 * This macro is available for devices having M4CPUSS IP.
821 **/
822 #define CY_UNIQUE_ID_DIE_WAFER_Pos (24U) /**< The position of the DIE_WAFER field in the silicon Unique ID */
823 /**
824 * \note
825 * This macro is available for devices having M4CPUSS IP.
826 **/
827 #define CY_UNIQUE_ID_DIE_LOT_2_Pos (16U) /**< The position of the DIE_LOT_2 field in the silicon Unique ID */
828 /**
829 * \note
830 * This macro is available for devices having M4CPUSS IP.
831 **/
832 #define CY_UNIQUE_ID_DIE_LOT_1_Pos (8U) /**< The position of the DIE_LOT_1 field in the silicon Unique ID */
833 /**
834 * \note
835 * This macro is available for devices having M4CPUSS IP.
836 **/
837 #define CY_UNIQUE_ID_DIE_LOT_0_Pos (0U) /**< The position of the DIE_LOT_0 field in the silicon Unique ID */
838
839 /** \} group_syslib_macros_unique_id */
840 #endif
841
842 /** \} group_syslib_macros */
843
844 /******************************************************************************
845 * Function prototypes
846 ******************************************************************************/
847
848 /**
849 * \addtogroup group_syslib_functions
850 * \{
851 */
852
853 /*******************************************************************************
854 * Function Name: Cy_SysLib_Delay
855 ****************************************************************************//**
856 *
857 * The function delays by the specified number of milliseconds.
858 * By default, the number of cycles to delay is calculated based on the
859 * \ref SystemCoreClock.
860 *
861 * \param milliseconds The number of milliseconds to delay.
862 *
863 * \note The function calls \ref Cy_SysLib_DelayCycles() API to generate a delay.
864 * If the function parameter (milliseconds) is bigger than
865 * CY_DELAY_MS_OVERFLOW constant, then an additional loop runs to prevent
866 * an overflow in parameter passed to \ref Cy_SysLib_DelayCycles() API.
867 *
868 *******************************************************************************/
869 void Cy_SysLib_Delay(uint32_t milliseconds);
870
871
872 /*******************************************************************************
873 * Function Name: Cy_SysLib_DelayUs
874 ****************************************************************************//**
875 *
876 * The function delays by the specified number of microseconds.
877 * By default, the number of cycles to delay is calculated based on the
878 * \ref SystemCoreClock.
879 *
880 * \param microseconds The number of microseconds to delay.
881 *
882 * \note If the CPU frequency is a small non-integer number, the actual delay
883 * can be up to twice as long as the nominal value. The actual delay
884 * cannot be shorter than the nominal one.
885 *
886 *******************************************************************************/
887 void Cy_SysLib_DelayUs(uint16_t microseconds);
888
889 /*******************************************************************************
890 * Function Name: Cy_SysLib_Rtos_Delay
891 ****************************************************************************//**
892 *
893 * The function is same as \ref Cy_SysLib_Delay. However, this API is declared WEAK
894 * providing option for user to overwrite the implementation based on target RTOS.
895 *
896 * \param milliseconds The number of milliseconds to delay.
897 *
898 *******************************************************************************/
899 void Cy_SysLib_Rtos_Delay(uint32_t milliseconds);
900
901
902 /*******************************************************************************
903 * Function Name: Cy_SysLib_Rtos_DelayUs
904 ****************************************************************************//**
905 *
906 * The function is same as \ref Cy_SysLib_DelayUs. However, this API is declared WEAK
907 * providing option for user to overwrite the imlementation based on target RTOS.
908 *
909 * \param microseconds The number of microseconds to delay.
910 *
911 *******************************************************************************/
912 void Cy_SysLib_Rtos_DelayUs(uint16_t microseconds);
913
914
915 /** Delays for the specified number of cycles.
916 * The function is implemented in the assembler for each supported compiler.
917 * \param cycles The number of cycles to delay.
918 */
919 void Cy_SysLib_DelayCycles(uint32_t cycles);
920
921
922 /*******************************************************************************
923 * Function Name: Cy_SysLib_Halt
924 ****************************************************************************//**
925 *
926 * This function halts the CPU but only the CPU which calls the function.
927 * It doesn't affect other CPUs.
928 *
929 * \param reason The value to be used during debugging.
930 *
931 * \note The function executes the BKPT instruction for halting CPU and is
932 * intended to be used for the debug purpose. A regular use case requires
933 * Debugger attachment before the function call.
934 * The BKPT instruction causes the CPU to enter the Debug state. Debug
935 * tools can use this to investigate the system state, when the
936 * instruction at a particular address is reached.
937 *
938 * \note Execution of a BKPT instruction without a debugger attached produces
939 * a fault. The fault results in the HardFault exception being taken
940 * or causes a Lockup state if it occurs in the NMI or HardFault handler.
941 * The default HardFault handler make a software reset if the build option
942 * is the release mode (NDEBUG). If the build option is the debug mode,
943 * the system will stay in the infinite loop of the
944 * \ref Cy_SysLib_ProcessingFault() function.
945 *
946 *******************************************************************************/
947 #ifdef CY_IP_M4CPUSS
948 /** \cond INTERNAL */
949 __NO_RETURN void Cy_SysLib_Halt(uint32_t reason);
950 /** \endcond */
951 #endif
952 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_DOXYGEN)
953 void Cy_SysLib_Halt(uint32_t reason);
954 #endif
955
956
957 /*******************************************************************************
958 * Macro Name: Cy_SysLib_AssertFailed
959 ****************************************************************************//**
960 *
961 * This function stores the ASSERT location of the file name (including path
962 * to file) and line number in a non-zero init area for debugging. Also it calls
963 * the \ref Cy_SysLib_Halt() function to halt the processor.
964 *
965 * \param file The file name of the ASSERT location.
966 * \param line The line number of the ASSERT location.
967 *
968 * \note A stored file name and line number could be accessed by
969 * cy_assertFileName and cy_assertLine global variables.
970 * \note This function has the WEAK option, so the user can redefine
971 * the function for a custom processing.
972 *
973 *******************************************************************************/
974 void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line);
975
976 #ifdef CY_IP_M4CPUSS
977
978
979 /*******************************************************************************
980 * Function Name: Cy_SysLib_ClearFlashCacheAndBuffer
981 ****************************************************************************//**
982 *
983 * This function invalidates the flash cache and buffer. It ensures the valid
984 * data is read from flash instead of using outdated data from the cache.
985 * The caches' LRU structure is also reset to their default state.
986 *
987 * \note The operation takes a maximum of three clock cycles on the slowest of
988 * the clk_slow and clk_fast clocks.
989 *
990 * \note
991 * This API is available for devices having M4CPUSS IP.
992 *
993 *******************************************************************************/
994 void Cy_SysLib_ClearFlashCacheAndBuffer(void);
995
996
997 /*******************************************************************************
998 * Function Name: Cy_SysLib_GetUniqueId
999 ****************************************************************************//**
1000 *
1001 * This function returns the silicon unique ID.
1002 * The ID includes Die lot[3]#, Die Wafer#, Die X, Die Y, Die Sort#, Die Minor
1003 * and Die Year.
1004 *
1005 * \return A combined 64-bit unique ID.
1006 * [63:57] - DIE_YEAR
1007 * [56:56] - DIE_MINOR
1008 * [55:48] - DIE_SORT
1009 * [47:40] - DIE_Y
1010 * [39:32] - DIE_X
1011 * [31:24] - DIE_WAFER
1012 * [23:16] - DIE_LOT[2]
1013 * [15: 8] - DIE_LOT[1]
1014 * [ 7: 0] - DIE_LOT[0]
1015 *
1016 * \note
1017 * This API is available for devices having M4CPUSS IP.
1018 *
1019 *******************************************************************************/
1020 uint64_t Cy_SysLib_GetUniqueId(void);
1021
1022
1023 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
1024 /*******************************************************************************
1025 * Function Name: Cy_SysLib_SoftResetCM4
1026 ****************************************************************************//**
1027 *
1028 * This function performs a CM4 Core software reset using the CM4_PWR_CTL
1029 * register. The register is accessed by CM0 Core by using a command transferred
1030 * to SROM API through the IPC channel. When the command is sent, the API waits
1031 * for the IPC channel release.
1032 *
1033 * \note This function should be called only when the CM4 core is in Deep
1034 * Sleep mode.
1035 * \note This function will not reset CM0+ Core.
1036 * \note This function waits for an IPC channel release state.
1037 *
1038 * \note
1039 * This API is available for devices having M4CPUSS IP.
1040 *
1041 *******************************************************************************/
1042 void Cy_SysLib_SoftResetCM4(void);
1043 #endif /* CY_CPU_CORTEX_M0P */
1044 #endif
1045
1046
1047 /*******************************************************************************
1048 * Function Name: Cy_SysLib_ResetBackupDomain
1049 ****************************************************************************//**
1050 *
1051 * This function resets the backup domain power to avoid the ILO glitch. The
1052 * glitch can occur when the device is reset due to POR/BOD/XRES while
1053 * the backup voltage is supplied into the system.
1054 *
1055 * \note Writing 1 to BACKUP->RESET resets the backup logic. Hardware clears it
1056 * when the reset is complete. After setting the register, this function
1057 * reads the register immediately for returning the result of the backup
1058 * domain reset state. The reading register is important because the Read
1059 * itself takes multiple AHB clock cycles, and the reset is actually
1060 * finishing during that time. Use \ref Cy_SysLib_GetResetStatus to check
1061 * the BACKUP->RESET before any other BACKUP register write.
1062 *
1063 * \note This function also resets the WCO trimming value - use the
1064 * \ref Cy_SysLib_GetWcoTrim and \ref Cy_SysLib_SetWcoTrim to store/restore
1065 * the WCO trimming value.
1066 *
1067 * \return CY_SYSLIB_SUCCESS, if BACKUP->RESET read-back is 0.
1068 * Otherwise returns CY_SYSLIB_INVALID_STATE.
1069 *
1070 * \funcusage
1071 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1072 *
1073 *******************************************************************************/
1074 cy_en_syslib_status_t Cy_SysLib_ResetBackupDomain(void);
1075
1076
1077 /*******************************************************************************
1078 * Function Name: Cy_SysLib_GetResetReason
1079 ****************************************************************************//**
1080 *
1081 * The function returns the cause for the latest reset(s) that occurred in
1082 * the system. The reset causes include system faults and
1083 * device reset on a wakeup from Hibernate mode. For M33SYSCPUSS IP,
1084 * the reset causes also include an HFCLK error.
1085 * The return results are consolidated reset causes from reading RES_CAUSE,
1086 * RES_CAUSE2 and PWR_HIBERNATE token registers.
1087 *
1088 * \return The cause of a system reset.
1089 * Return values to be checked as per the CPUSS IP of the device.
1090 *
1091 * | Name in M4CPUSS IP | Name in M33SYSCPUSS IP | Value
1092 * |-------------------------------|------------------------------|-------------------
1093 * | CY_SYSLIB_RESET_HWWDT | CY_SYSLIB_RESET_HWWDT | 0x00001 (bit0)
1094 * | CY_SYSLIB_RESET_ACT_FAULT | CY_SYSLIB_RESET_ACT_FAULT | 0x00002 (bit1)
1095 * | CY_SYSLIB_RESET_DPSLP_FAULT | CY_SYSLIB_RESET_DPSLP_FAULT | 0x00004 (bit2)
1096 * | CY_SYSLIB_RESET_TC_DBGRESET | CY_SYSLIB_RESET_CSV_WCO_LOSS | 0x00008 (bit3)
1097 * | CY_SYSLIB_RESET_SOFT | CY_SYSLIB_RESET_SOFT | 0x00010 (bit4)
1098 * | CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT0 | 0x00020 (bit5)
1099 * | CY_SYSLIB_RESET_SWWDT1 | CY_SYSLIB_RESET_SWWDT1 | 0x00040 (bit6)
1100 * | CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT2 | 0x00080 (bit7)
1101 * | CY_SYSLIB_RESET_SWWDT3 | CY_SYSLIB_RESET_SWWDT3 | 0x00100 (bit8)
1102 * | | CY_SYSLIB_RESET_HFCLK_LOSS | 0x10000 (bit16)
1103 * | | CY_SYSLIB_RESET_HFCLK_ERR | 0x20000 (bit17)
1104 * | CY_SYSLIB_RESET_HIB_WAKEUP | CY_SYSLIB_RESET_HIB_WAKEUP | 0x40000 (bit18)
1105 *
1106 * \note This not is available for devices having M33SYSCPUSS IP
1107 * CY_SYSLIB_RESET_CSV_WCO_LOSS, CY_SYSLIB_RESET_HFCLK_LOSS and
1108 * CY_SYSLIB_RESET_HFCLK_ERR causes of a system reset available only if
1109 * WCO CSV present in the device.
1110 *
1111 *******************************************************************************/
1112 uint32_t Cy_SysLib_GetResetReason(void);
1113
1114
1115 /*******************************************************************************
1116 * Function Name: Cy_SysLib_ClearResetReason
1117 ****************************************************************************//**
1118 *
1119 * This function clears the values of RES_CAUSE and RES_CAUSE2. Also it clears
1120 * PWR_HIBERNATE token, which indicates reset event on waking up from HIBERNATE.
1121 *
1122 *******************************************************************************/
1123 void Cy_SysLib_ClearResetReason(void);
1124
1125
1126 /*******************************************************************************
1127 * Function Name: Cy_SysLib_GetResetStatus
1128 ****************************************************************************//**
1129 *
1130 * This function returns the BACKUP->RESET bit value.
1131 * It is reused by the \ref Cy_SysLib_ResetBackupDomain itself and also intended to
1132 * check for CY_SYSLIB_SUCCESS in loop after the \ref Cy_SysLib_ResetBackupDomain call.
1133 *
1134 * \note Writing 1 to BACKUP->RESET resets the backup logic. Hardware clears it
1135 * when the reset is complete. After setting the register, this function
1136 * reads the register immediately for returning the result of the backup
1137 * domain reset state. The reading register is important because the Read
1138 * itself takes multiple AHB clock cycles, and the reset is actually
1139 * finishing during that time.
1140 *
1141 * \return CY_SYSLIB_SUCCESS, if BACKUP->RESET read-back is 0.
1142 * Otherwise returns CY_SYSLIB_INVALID_STATE.
1143 *
1144 * \funcusage
1145 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_ResetBackup
1146 *
1147 *******************************************************************************/
Cy_SysLib_GetResetStatus(void)1148 __STATIC_INLINE cy_en_syslib_status_t Cy_SysLib_GetResetStatus (void)
1149 {
1150 return ((0UL == (BACKUP_RESET & BACKUP_RESET_RESET_Msk)) ? CY_SYSLIB_SUCCESS : CY_SYSLIB_INVALID_STATE);
1151 }
1152
1153
1154 #if defined (CY_IP_MXS40SRSS)
1155 /*******************************************************************************
1156 * Function Name: Cy_SysLib_GetWcoTrim
1157 ****************************************************************************//**
1158 *
1159 * This function returns the BACKUP->TRIM bitfield value.
1160 * It is intended to store the WCO trimming value before
1161 * the \ref Cy_SysLib_ResetBackupDomain usage.
1162 *
1163 * \return The WCO trimming value.
1164 *
1165 * \funcusage
1166 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1167 *
1168 *******************************************************************************/
Cy_SysLib_GetWcoTrim(void)1169 __STATIC_INLINE uint32_t Cy_SysLib_GetWcoTrim (void)
1170 {
1171 return (BACKUP_TRIM & BACKUP_TRIM_TRIM_Msk);
1172 }
1173
1174
1175 /*******************************************************************************
1176 * Function Name: Cy_SysLib_SetWcoTrim
1177 ****************************************************************************//**
1178 *
1179 * This function writes the value into the BACKUP->TRIM bitfield.
1180 * It is intended to restore the WCO trimming value after
1181 * the \ref Cy_SysLib_ResetBackupDomain usage.
1182 *
1183 * \param wcoTrim The WCO trimming value.
1184 *
1185 * \funcusage
1186 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1187 *
1188 *******************************************************************************/
Cy_SysLib_SetWcoTrim(uint32_t wcoTrim)1189 __STATIC_INLINE void Cy_SysLib_SetWcoTrim (uint32_t wcoTrim)
1190 {
1191 BACKUP_TRIM = wcoTrim & BACKUP_TRIM_TRIM_Msk;
1192 }
1193 #endif /* CY_IP_MXS40SRSS */
1194
1195
1196 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN)
1197
1198
1199 /*******************************************************************************
1200 * Function Name: Cy_SysLib_FaultHandler
1201 ****************************************************************************//**
1202 *
1203 * This function stores the ARM Cortex registers into a non-zero init area for
1204 * debugging. This function calls Cy_SysLib_ProcessingFault() after storing all
1205 * information.
1206 *
1207 * \param faultStackAddr The address of the stack pointer, indicates the lowest
1208 * address in the fault stack frame to be stored.
1209 * \note This function stores the fault stack frame only for the first occurred
1210 * fault.
1211 * \note The PDL doesn't provide an API to analyze the stored register
1212 * values. The user has to add additional functions for the analysis,
1213 * if necessary.
1214 * \note The CY_ARM_FAULT_DEBUG macro defines if the Fault Handler is enabled.
1215 * By default it is set to CY_ARM_FAULT_DEBUG_ENABLED and enables the
1216 * Fault Handler.
1217 * If there is a necessity to save memory or have some specific custom
1218 * handler, etc. then CY_ARM_FAULT_DEBUG should be redefined as
1219 * CY_ARM_FAULT_DEBUG_DISABLED. To do this, the following definition should
1220 * be added to the compiler Command Line (through the project Build
1221 * Settings): "-D CY_ARM_FAULT_DEBUG=0".
1222 *
1223 *******************************************************************************/
1224 void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr);
1225
1226
1227 /*******************************************************************************
1228 * Function Name: Cy_SysLib_ProcessingFault
1229 ****************************************************************************//**
1230 *
1231 * This function determines how to process the current fault state. By default
1232 * in case of exception the system will stay in the infinite loop of this
1233 * function.
1234 *
1235 * \note This function has the WEAK option, so the user can redefine the function
1236 * behavior for a custom processing.
1237 * For example, the function redefinition could be constructed from fault
1238 * stack processing and NVIC_SystemReset() function call.
1239 *
1240 *******************************************************************************/
1241 void Cy_SysLib_ProcessingFault(void);
1242 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
1243
1244
1245 /*******************************************************************************
1246 * Function Name: Cy_SysLib_SetWaitStates
1247 ****************************************************************************//**
1248 *
1249 * Sets the number of clock cycles the cache will wait for, before it samples
1250 * data coming back from ROM, SRAM, and Flash.
1251 *
1252 * Call this function before increasing the HFClk0 High Frequency clock.
1253 * Call this function optionally after lowering the HFClk0 High Frequency clock
1254 * in order to improve the CPU performance.
1255 *
1256 * Also, call this function before switching the core supply regulator voltage
1257 * (LDO or SIMO Buck) from 1.1V to 0.9V.
1258 * Call this function optionally after switching the core supply regulator
1259 * voltage from 0.9V to 1.1V in order to improve the CPU performance.
1260 *
1261 * \param ulpMode The device power mode.
1262 * true if the device should be switched to the ULP mode (nominal
1263 * voltage of the core supply regulator should be switched to 0.9V);
1264 * false if the device should be switched to the LP mode (nominal
1265 * voltage of the core supply regulator should be switched to 1.1V).
1266 *
1267 * \note Refer to the device TRM for the low power modes description.
1268 *
1269 * \param clkHfMHz The HFClk0 clock frequency in MHz. Specifying a frequency
1270 * above the supported maximum will set the wait states as for
1271 * the maximum frequency.
1272 *
1273 *******************************************************************************/
1274 void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz);
1275
1276
1277 /*******************************************************************************
1278 * Function Name: Cy_SysLib_EnterCriticalSection
1279 ****************************************************************************//**
1280 *
1281 * Cy_SysLib_EnterCriticalSection disables interrupts and returns a value
1282 * indicating whether the interrupts were previously enabled.
1283 *
1284 * \return Returns the current interrupt status. Returns 0 if the interrupts
1285 * were previously enabled or 1 if the interrupts were previously
1286 * disabled.
1287 *
1288 * \note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ
1289 * enable bit with interrupts still enabled.
1290 *
1291 *******************************************************************************/
1292 uint32_t Cy_SysLib_EnterCriticalSection(void);
1293
1294
1295 /*******************************************************************************
1296 * Function Name: Cy_SysLib_ExitCriticalSection
1297 ****************************************************************************//**
1298 *
1299 * Re-enables the interrupts if they were enabled before
1300 * Cy_SysLib_EnterCriticalSection() was called. The argument should be the value
1301 * returned from \ref Cy_SysLib_EnterCriticalSection().
1302 *
1303 * \param savedIntrStatus Puts the saved interrupts status returned by
1304 * the \ref Cy_SysLib_EnterCriticalSection().
1305 *
1306 *******************************************************************************/
1307 void Cy_SysLib_ExitCriticalSection(uint32_t savedIntrStatus);
1308
1309
1310 /** \cond INTERNAL */
1311 #define CY_SYSLIB_DEVICE_REV_0A (0x21U) /**< The device TO *A Revision ID */
1312 #define CY_SYSLIB_DEVICE_PSOC6ABLE2 (0x100U) /**< The PSoC6 BLE2 device Family ID */
1313
1314
1315 /*******************************************************************************
1316 * Function Name: Cy_SysLib_GetDeviceRevision
1317 ****************************************************************************//**
1318 *
1319 * This function returns a device Revision ID.
1320 *
1321 * \return A device Revision ID.
1322 *
1323 *******************************************************************************/
1324 uint8_t Cy_SysLib_GetDeviceRevision(void);
1325
1326 /*******************************************************************************
1327 * Function Name: Cy_SysLib_GetDevice
1328 ****************************************************************************//**
1329 *
1330 * This function returns a device Family ID.
1331 *
1332 * \return A device Family ID.
1333 *
1334 *******************************************************************************/
1335 uint16_t Cy_SysLib_GetDevice(void);
1336
1337 typedef uint32_t cy_status;
1338 /** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */
1339 typedef uint32_t cystatus;
1340 typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */
1341 typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */
1342 typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */
1343 typedef int8_t int8; /**< Alias to int8_t for backward compatibility */
1344 typedef int16_t int16; /**< Alias to int16_t for backward compatibility */
1345 typedef int32_t int32; /**< Alias to int32_t for backward compatibility */
1346 typedef float float32; /**< Alias to float for backward compatibility */
1347 typedef double float64; /**< Alias to double for backward compatibility */
1348 typedef int64_t int64; /**< Alias to int64_t for backward compatibility */
1349 typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */
1350 /* Signed or unsigned depending on the compiler selection */
1351 typedef char char8; /**< Alias to char for backward compatibility */
1352 typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */
1353 typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */
1354 typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */
1355
1356 /** The ARM 32-bit Return error / status code for backward compatibility.
1357 * Do not use them in your code.
1358 */
1359 #define CY_RET_SUCCESS (0x00U) /* Successful */
1360 #define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */
1361 #define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */
1362 #define CY_RET_MEMORY (0x03U) /* A memory-related failure */
1363 #define CY_RET_LOCKED (0x04U) /* A resource lock failure */
1364 #define CY_RET_EMPTY (0x05U) /* No more objects available */
1365 #define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
1366 #define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
1367 #define CY_RET_FINISHED (0x08U) /* Operation is completed */
1368 #define CY_RET_CANCELED (0x09U) /* Operation is canceled */
1369 #define CY_RET_TIMEOUT (0x10U) /* Operation timed out */
1370 #define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
1371 #define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */
1372
1373 /** ARM 32-bit Return error / status codes for backward compatibility with the UDB components.
1374 * Do not use them in your code.
1375 */
1376 #define CYRET_SUCCESS (0x00U) /* Successful */
1377 #define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */
1378 #define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */
1379 #define CYRET_MEMORY (0x03U) /* A memory-related failure */
1380 #define CYRET_LOCKED (0x04U) /* A resource lock failure */
1381 #define CYRET_EMPTY (0x05U) /* No more objects available */
1382 #define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
1383 #define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
1384 #define CYRET_FINISHED (0x08U) /* Operation is completed */
1385 #define CYRET_CANCELED (0x09U) /* Operation is canceled */
1386 #define CYRET_TIMEOUT (0x10U) /* Operation timed out */
1387 #define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
1388 #define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */
1389
1390 /** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
1391 typedef void (* cyisraddress)(void);
1392 #if defined (__ICCARM__)
1393 /** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
1394 typedef union { cyisraddress __fun; void * __ptr; } intvec_elem;
1395 #endif /* defined (__ICCARM__) */
1396
1397 /** The backward compatibility define for the CyDelay() API for the UDB components.
1398 * Do not use it in your code.
1399 */
1400 #define CyDelay Cy_SysLib_Delay
1401 /** The backward compatibility define for the CyDelayUs() API for the UDB components.
1402 * Do not use it in your code.
1403 */
1404 #define CyDelayUs Cy_SysLib_DelayUs
1405 /** The backward compatibility define for the CyDelayCycles() API for the UDB components.
1406 * Do not use it in your code.
1407 */
1408 #define CyDelayCycles Cy_SysLib_DelayCycles
1409 /** The backward compatibility define for the CyEnterCriticalSection() API for the UDB components.
1410 * Do not use it in your code.
1411 */
1412 #define CyEnterCriticalSection() ((uint8_t) Cy_SysLib_EnterCriticalSection())
1413 /** The backward compatibility define for the CyExitCriticalSection() API for the UDB components.
1414 * Do not use it in your code.
1415 */
1416 #define CyExitCriticalSection(x) (Cy_SysLib_ExitCriticalSection((uint32_t) (x)))
1417 /** \endcond */
1418
1419 /** \} group_syslib_functions */
1420 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6');
1421 /** \cond INTERNAL */
1422
1423 /** \endcond */
1424
1425
1426 #if defined(__cplusplus)
1427 }
1428 #endif /* defined(__cplusplus) */
1429
1430 #endif /* CY_IP_M33SYSCPUSS, CY_IP_M4CPUSS */
1431
1432 #endif /* CY_SYSLIB_H */
1433
1434 /** \} group_syslib */
1435
1436 /* [] END OF FILE */
1437
