1 /***************************************************************************//** 2 * \file cy_sysint.h 3 * \version 1.60 4 * 5 * \brief 6 * Provides an API declaration of the SysInt driver 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright 2016-2020 Cypress Semiconductor Corporation 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 *******************************************************************************/ 25 26 /** 27 * \addtogroup group_sysint 28 * \{ 29 * The SysInt driver provides an API to configure the device peripheral interrupts. 30 * It provides a lightweight interface to complement 31 * the <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html">CMSIS core NVIC API</a>. 32 * The provided functions are applicable for all cores in a device and they can 33 * be used to configure and connect device peripheral interrupts to one or more 34 * cores. 35 * 36 * The functions and other declarations used in this driver are in cy_sysint.h. 37 * You can include cy_pdl.h to get access to all functions 38 * and declarations in the PDL. 39 * 40 * \section group_sysint_vector_table Vector Table 41 * \subsection group_sysint_CM0_CM4 CM0+/CM4 42 * The vector table defines the entry addresses of the processor exceptions and 43 * the device specific interrupts. It is located at the start address of the flash 44 * and is copied by the startup code to RAM. The symbol code __Vectors is the 45 * address of the vector table in the startup code and the register SCB->VTOR 46 * holds the start address of the vector table. See \ref group_system_config_device_vector_table 47 * section for the implementation details. 48 * The default interrupt handler functions are defined as weak functions to a dummy handler 49 * in the startup file. The naming convention is \<interrupt_name\>_IRQHandler. 50 * 51 * Defining these in the user application allows the linker to place them in 52 * the vector table in flash/ROM. For example: 53 * \code 54 * void ioss_interrupts_gpio_0_IRQHandler(void) 55 * { 56 * ... 57 * } 58 * \endcode 59 * And can be used like this: 60 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_flashVT 61 * Using this method avoids the need for a RAM vector table. However in this scenario, 62 * interrupt handler re-location at run-time is not possible, unless the vector table is 63 * relocated to RAM. 64 * 65 * \subsection group_sysint_CM33 CM33 66 * CM33 with Security extension supports two vector tables, one for secure world and another 67 * for non-secure world. Secure interrupt vector table is placed in the secure ROM/FLASH, where as 68 * non-secure interrupt vector table is placed in the non-secure ROM/FLASH. In both scenarios, 69 * vector tables are copied by the startup code to secure and non-secure RAM respectively. 70 * The symbol code __s_vector_table is the address of the secure vector table and 71 * __ns_vector_table is for the non-secure world in the startup code. The register SCB->VTOR 72 * holds the start address of the vector table. See \ref group_system_config_device_vector_table 73 * section for the implementation details. 74 * 75 * CM33 without Security extension will support only non-secure interrupts. 76 * 77 * The default interrupt handler functions are defined to a dummy handler in the startup file. 78 * The naming convention is \<interrupt_name\>_IRQHandler. 79 * 80 * 81 * \section group_sysint_driver_usage Driver Usage 82 * 83 * \subsection group_sysint_initialization Initialization 84 * 85 * Interrupt numbers are defined in a device-specific header file, such as 86 * cy8c68237bz_ble.h, and are consistent with interrupt handlers defined in the 87 * vector table. 88 * 89 * To configure an interrupt, call Cy_SysInt_Init(). Populate 90 * the configuration structure (cy_stc_sysint_t) and pass it as a parameter 91 * along with the ISR address. This initializes the interrupt and 92 * instructs the CPU to jump to the specified ISR vector upon a valid trigger. 93 * For CM0+ core, the configuration structure (cy_stc_sysint_t) 94 * must specify the device interrupt source (cm0pSrc) that feeds into the CM0+ NVIC 95 * mux (intrSrc). 96 * 97 * For CM4/CM33 core, system interrupt source 'n' is connected to the 98 * corresponding IRQn. Deep-sleep capable interrupts are allocated to Deep Sleep 99 * capable IRQn channels. 100 * 101 * For CM0+ core, deep Sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR 102 * parameter, where the first N number of muxes (NvicMux0 ... NvicMuxN-1) have the 103 * capability to trigger Deep Sleep interrupts. A Deep Sleep capable interrupt source 104 * must be connected to one of these muxes to be able to trigger in Deep Sleep. 105 * Refer to the IRQn_Type definition in the device header. 106 * 107 * 1. For CPUSS_ver1 the CM0+ core supports up to 32 interrupt channels (IRQn 0-31). To allow all device 108 * interrupts to be routable to the NVIC of this core, there is a 240:1 multiplexer 109 * at each of the 32 NVIC channels. 110 * 111 * 2. For CPUSS_ver2 the CM0+ core supports up to 8 hardware interrupt channels (IRQn 0-7) and software-only 112 * interrupt channels (IRQn 8-15). The device has up to 1023 interrupts that can be connected to any of the 113 * hardware interrupt channels. In this structure, multiple interrupt sources can be connected 114 * simultaneously to one NVIC channel. The application must then query the interrupt source on the 115 * channel and service the active interrupt(s). The priority of these interrupts is determined by the 116 * interrupt number as defined in the cy_en_intr_t enum, where the lower number denotes higher priority 117 * over the higher number. 118 * 119 * \subsection group_sysint_enable Enable 120 * 121 * After initializing an interrupt, use the CMSIS Core 122 * <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ()</a> function 123 * to enable it. Given an initialization structure named config, 124 * the function should be called as follows: 125 * \code 126 * NVIC_EnableIRQ(config.intrSrc) 127 * \endcode 128 * 129 * \subsection group_sysint_service Writing an interrupt service routine 130 * 131 * Servicing interrupts in the Peripheral Drivers should follow a prescribed 132 * recipe to ensure all interrupts are serviced and duplicate interrupts are not 133 * received. Any peripheral-specific register that must be written to clear the 134 * source of the interrupt should be written as soon as possible in the interrupt 135 * service routine. However, note that due to buffering on the output bus to the 136 * peripherals, the write clearing of the interrupt may be delayed. After performing 137 * the normal interrupt service that should respond to the interrupting 138 * condition, the interrupt register that was initially written to clear the 139 * register should be read before returning from the interrupt service routine. 140 * This read ensures that the initial write has been flushed out to the hardware. 141 * Note, no additional processing should be performed based on the result of this 142 * read, as this read is intended only to ensure the write operation is flushed. 143 * 144 * This final read may indicate a pending interrupt. What this means is that in 145 * the interval between when the write actually happened at the peripheral and 146 * when the read actually happened at the peripheral, an interrupting condition 147 * occurred. This is ok and a return from the interrupt is still the correct 148 * action. As soon as conditions warrant, meaning interrupts are enabled and 149 * there are no higher priority interrupts pending, the interrupt will be 150 * triggered again to service the additional condition. 151 * 152 * \section group_sysint_section_configuration_considerations Configuration Considerations 153 * 154 * Certain CM0+ <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">NVIC IRQn</a> 155 * channels are reserved for system use: 156 * <table class="doxtable"> 157 * <tr><th>NVIC channel (\ref IRQn_Type)</th><th>Interrupt source (\ref cy_en_intr_t)</th><th>Purpose</th></tr> 158 * <tr><td>#0 (NvicMux0_IRQn)</td><td>IPC Interrupt #0 (cpuss_interrupts_ipc_0_IRQn)</td><td>System Calls to ROM</td></tr> 159 * <tr><td>#1 (NvicMux1_IRQn)</td><td>IPC Interrupt #3 (cpuss_interrupts_ipc_3_IRQn)</td><td>System IPC pipe in the default startup</td></tr> 160 * </table> 161 * 162 * \note For CPUSS_ver2, each NVIC channel can be shared between multiple interrupt sources. 163 * However it is not recommended to share the application NVIC channel with the reserved channels. 164 * 165 * \section group_sysint_more_information More Information 166 * 167 * Refer to the technical reference manual (TRM) and the device datasheet. 168 * 169 * \section group_sysint_changelog Changelog 170 * <table class="doxtable"> 171 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 172 * <tr> 173 * <td>1.60</td> 174 * <td>Support for CM33.</td> 175 * <td>New devices support.</td> 176 * </tr> 177 * <tr> 178 * <td>1.50</td> 179 * <td>Fixed MISRA 2012 violations.</td> 180 * <td>MISRA 2012 compliance.</td> 181 * </tr> 182 * <tr> 183 * <td>1.40</td> 184 * <td>Updated the CY_SYSINT_IS_PC_0 macro to access the protected register 185 * for the secure CYB06xx7 devices via \ref group_pra driver. 186 * </td> 187 * <td>Added PSoC 64 devices support.</td> 188 * </tr> 189 * <tr> 190 * <td>1.30.1</td> 191 * <td>Minor documentation updates.</td> 192 * <td>Documentation enhancement.</td> 193 * </tr> 194 * <tr> 195 * <td>1.30</td> 196 * <td>The Cy_SysInt_SetNmiSource is updated with Protection Context check for CM0+.</td> 197 * <td>User experience enhancement.</td> 198 * </tr> 199 * <tr> 200 * <td>1.20.1</td> 201 * <td>The Vector Table section is extended with a code snippet.</td> 202 * <td>Documentation enhancement.</td> 203 * </tr> 204 * <tr> 205 * <td rowspan="3">1.20</td> 206 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td> 207 * <td>Driver library directory-structure simplification.</td> 208 * </tr> 209 * <tr> 210 * <td>Added CPUSS_ver2 support to the following API functions: 211 * - \ref Cy_SysInt_SetInterruptSource 212 * - \ref Cy_SysInt_SetNmiSource 213 * - \ref Cy_SysInt_GetNmiSource 214 * 215 * Added new API functions: 216 * - \ref Cy_SysInt_DisconnectInterruptSource 217 * - \ref Cy_SysInt_GetNvicConnection 218 * - \ref Cy_SysInt_GetInterruptActive 219 * 220 * Deprecated following functions: 221 * - Cy_SysInt_SetIntSource 222 * - Cy_SysInt_GetIntSource 223 * - Cy_SysInt_SetIntSourceNMI 224 * - Cy_SysInt_GetIntSourceNMI 225 * </td> 226 * <td>New devices support.</td> 227 * </tr> 228 * <tr> 229 * <td>Added register access layer. Use register access macros instead 230 * of direct register access using dereferenced pointers.</td> 231 * <td>Makes register access device-independent, so that the PDL does 232 * not need to be recompiled for each supported part number.</td> 233 * </tr> 234 * <tr> 235 * <td>1.10</td> 236 * <td>Cy_SysInt_GetState() function is redefined to call NVIC_GetEnableIRQ()</td> 237 * <td></td> 238 * </tr> 239 * <tr> 240 * <td>1.0</td> 241 * <td>Initial version</td> 242 * <td></td> 243 * </tr> 244 * </table> 245 * 246 * \defgroup group_sysint_macros Macros 247 * \defgroup group_sysint_globals Global variables 248 * \defgroup group_sysint_functions Functions 249 * \defgroup group_sysint_data_structures Data Structures 250 * \defgroup group_sysint_enums Enumerated Types 251 */ 252 253 254 #if !defined (CY_SYSINT_H) 255 #define CY_SYSINT_H 256 257 #include "cy_device.h" 258 259 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS) 260 261 #include <stddef.h> 262 #include "cy_syslib.h" 263 #if defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) 264 #include "cy_pra.h" 265 #endif /* defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */ 266 #include "cy_device_headers.h" 267 268 #if defined(__cplusplus) 269 extern "C" { 270 #endif 271 272 /*************************************** 273 * Global Variable 274 ***************************************/ 275 276 /** 277 * \addtogroup group_sysint_globals 278 * \{ 279 */ 280 281 #if defined (CY_IP_M4CPUSS) 282 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 8.6', 2, \ 283 'Coverity does not check the .S assembly files, the definition is a part of startup_psoc6_04_cm4.s file.'); 284 extern const cy_israddress __Vectors[]; /**< Vector table in flash */ 285 extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */ 286 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6'); 287 #endif /* CY_IP_M4CPUSS */ 288 289 #if defined (CY_SECURE_WORLD) || defined (CY_DOXYGEN) 290 extern uint32_t *__s_vector_table_rw; /**< Secure vector table in flash/ROM */ 291 #endif 292 #if !defined (CY_SECURE_WORLD) || defined (CY_DOXYGEN) 293 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 8.6', 2, \ 294 'Coverity does not check the .S assembly files, the definition is a part of startup_psoc6_04_cm4.s file.'); 295 extern uint32_t *__ns_vector_table_rw; /**< Non-secure vector table in flash/ROM */ 296 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6'); 297 #endif 298 299 /** \} group_sysint_globals */ 300 301 302 /*************************************** 303 * Global Interrupt 304 ***************************************/ 305 306 /** 307 * \addtogroup group_sysint_macros 308 * \{ 309 */ 310 311 /** Driver major version */ 312 #define CY_SYSINT_DRV_VERSION_MAJOR 2 313 314 /** Driver minor version */ 315 #define CY_SYSINT_DRV_VERSION_MINOR 0 316 317 /** SysInt driver ID */ 318 #define CY_SYSINT_ID CY_PDL_DRV_ID (0x15U) 319 320 /** \} group_sysint_macros */ 321 322 323 /*************************************** 324 * Enumeration 325 ***************************************/ 326 327 /** 328 * \addtogroup group_sysint_enums 329 * \{ 330 */ 331 332 /** 333 * SysInt Driver error codes 334 */ 335 typedef enum 336 { 337 CY_SYSINT_SUCCESS = 0x0UL, /**< Returned successful */ 338 CY_SYSINT_BAD_PARAM = CY_SYSINT_ID | CY_PDL_STATUS_ERROR | 0x1UL, /**< Bad parameter was passed */ 339 } cy_en_sysint_status_t; 340 341 /** NMI connection input */ 342 typedef enum 343 { 344 CY_SYSINT_NMI1 = 1UL, /**< NMI source input 1 */ 345 CY_SYSINT_NMI2 = 2UL, /**< NMI source input 2 */ 346 CY_SYSINT_NMI3 = 3UL, /**< NMI source input 3 */ 347 CY_SYSINT_NMI4 = 4UL, /**< NMI source input 4 */ 348 } cy_en_sysint_nmi_t; 349 350 /** \} group_sysint_enums */ 351 352 353 /*************************************** 354 * Configuration Structure 355 ***************************************/ 356 357 /** 358 * \addtogroup group_sysint_data_structures 359 * \{ 360 */ 361 362 /** 363 * Initialization configuration structure for a single interrupt channel 364 */ 365 typedef struct { 366 IRQn_Type intrSrc; /**< Interrupt source */ 367 #if (CY_CPU_CORTEX_M0P) 368 cy_en_intr_t cm0pSrc; /**< Maps cm0pSrc device interrupt to intrSrc */ 369 #endif /* CY_CPU_CORTEX_M0P */ 370 uint32_t intrPriority; /**< Interrupt priority number (Refer to __NVIC_PRIO_BITS) */ 371 } cy_stc_sysint_t; 372 373 /** \} group_sysint_data_structures */ 374 375 376 /*************************************** 377 * Constants 378 ***************************************/ 379 380 /** \cond INTERNAL */ 381 382 #define CY_INT_IRQ_BASE (16U) /**< Start location of interrupts in the vector table */ 383 #define CY_SYSINT_STATE_MASK (1UL) /**< Mask for interrupt state */ 384 #define CY_SYSINT_STIR_MASK (0xFFUL) /**< Mask for software trigger interrupt register */ 385 #define CY_SYSINT_DISABLE (0UL) /**< Disable interrupt */ 386 #define CY_SYSINT_ENABLE (1UL) /**< Enable interrupt */ 387 #define CY_SYSINT_INT_STATUS_MSK (0x7UL) 388 389 #if defined (CY_IP_M4CPUSS) 390 /*(CY_IP_M4CPUSS_VERSION == 1u) */ 391 #define CY_SYSINT_CM0P_MUX_MASK (0xFFUL) /**< CM0+ NVIC multiplexer mask */ 392 #define CY_SYSINT_CM0P_MUX_SHIFT (2U) /**< CM0+ NVIC multiplexer shift */ 393 #define CY_SYSINT_CM0P_MUX_SCALE (3U) /**< CM0+ NVIC multiplexer scaling value */ 394 #define CY_SYSINT_CM0P_MUX0 (0U) /**< CM0+ NVIC multiplexer register 0 */ 395 #define CY_SYSINT_CM0P_MUX1 (1U) /**< CM0+ NVIC multiplexer register 1 */ 396 #define CY_SYSINT_CM0P_MUX2 (2U) /**< CM0+ NVIC multiplexer register 2 */ 397 #define CY_SYSINT_CM0P_MUX3 (3U) /**< CM0+ NVIC multiplexer register 3 */ 398 #define CY_SYSINT_CM0P_MUX4 (4U) /**< CM0+ NVIC multiplexer register 4 */ 399 #define CY_SYSINT_CM0P_MUX5 (5U) /**< CM0+ NVIC multiplexer register 5 */ 400 #define CY_SYSINT_CM0P_MUX6 (6U) /**< CM0+ NVIC multiplexer register 6 */ 401 #define CY_SYSINT_CM0P_MUX7 (7U) /**< CM0+ NVIC multiplexer register 7 */ 402 #define CY_SYSINT_MUX_REG_MSK (0x7UL) 403 #endif /* CY_IP_M4CPUSS */ 404 405 /* Parameter validation macros */ 406 #define CY_SYSINT_IS_PRIORITY_VALID(intrPriority) ((uint32_t)(1UL << __NVIC_PRIO_BITS) > (intrPriority)) 407 #define CY_SYSINT_IS_VECTOR_VALID(userIsr) (NULL != (userIsr)) 408 #define CY_SYSINT_IS_NMI_NUM_VALID(nmiNum) (((nmiNum) == CY_SYSINT_NMI1) || \ 409 ((nmiNum) == CY_SYSINT_NMI2) || \ 410 ((nmiNum) == CY_SYSINT_NMI3) || \ 411 ((nmiNum) == CY_SYSINT_NMI4)) 412 #if defined (CY_IP_M4CPUSS) 413 #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) 414 #define CY_SYSINT_IS_PC_0 (0UL == _FLD2VAL(PROT_MPU_MS_CTL_PC, \ 415 CY_PRA_REG32_GET(CY_PRA_INDX_PROT_MPU_MS_CTL))) 416 #else 417 #define CY_SYSINT_IS_PC_0 (0UL == _FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(0U))) 418 #endif 419 #endif /* CY_IP_M4CPUSS */ 420 /** \endcond */ 421 422 423 /*************************************** 424 * Function Prototypes 425 ***************************************/ 426 427 /** 428 * \addtogroup group_sysint_functions 429 * \{ 430 */ 431 432 433 /******************************************************************************* 434 * Function Name: Cy_SysInt_Init 435 ****************************************************************************//** 436 * 437 * \brief Initializes the referenced interrupt by setting the priority and the 438 * interrupt vector. 439 * In case of CM33 with Security Extension eanbled, if this function is called 440 * from secure world then, the parameters are used to configure secure interrupt. 441 * If it is called form non-secure world then the parameters are used to configure 442 * non-secure interrupt. In case of CM33 without Security Extension, this function 443 * alwasys configures the non-secure interrupt. 444 * 445 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 446 * 447 * \param config 448 * Interrupt configuration structure 449 * 450 * \param userIsr 451 * Address of the ISR 452 * 453 * \return 454 * Initialization status 455 * 456 * \note CM0+/CM4 <br/> 457 * The interrupt vector will be relocated only if the vector table was 458 * moved to __ramVectors in SRAM. Otherwise it is ignored. 459 * 460 * \note CM33<br/> 461 * The interrupt vector will be relocated only if the vector table was 462 * moved to __s_vector_table_rw and __ns_vector_table_rw for secure and 463 * non-secure world respectively. 464 * \funcusage 465 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_Init 466 * 467 *******************************************************************************/ 468 cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr); 469 470 471 /******************************************************************************* 472 * Function Name: Cy_SysInt_SetVector 473 ****************************************************************************//** 474 * 475 * \brief Changes the ISR vector for the interrupt. 476 * 477 * CM0+/CM4:<br/> 478 * This function relies on the assumption that the vector table is 479 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 480 * return the address of the default ISR location in the flash vector table. 481 * 482 * CM33:<br/> 483 * When called from secure world. this function relies on the assumption that the 484 * vector table is relocated to __s_vector_table_rw[] in secure SRAM. Otherwise it will 485 * return the address of the default ISR location in the secure flash/ROM vector table. 486 * 487 * When called from non-secure world. this function relies on the assumption that 488 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 489 * Otherwise it will return the address of the default ISR location in the non-secure 490 * flash/ROM vector table. 491 * 492 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 493 * \param IRQn 494 * Interrupt source 495 * 496 * \param userIsr 497 * Address of the ISR to set in the interrupt vector table 498 * 499 * \return 500 * Previous address of the ISR in the interrupt vector table 501 * 502 * \note For CM0+, this function sets the interrupt vector for the interrupt 503 * channel on the NVIC. 504 * 505 * \note In case of CM33 with Security Extension eanbled, if this function is called 506 * from secure world then, it sets the interrupt vector for the secure world. 507 * If it is called form non-secure world then it sets the interrupt vector for the 508 * non-secure world. 509 * 510 * \funcusage 511 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector 512 * 513 *******************************************************************************/ 514 cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr); 515 516 517 /******************************************************************************* 518 * Function Name: Cy_SysInt_GetVector 519 ****************************************************************************//** 520 * 521 * \brief Gets the address of the current ISR vector for the interrupt. 522 * 523 * CM0+/CM4:<br/> 524 * This function relies on the assumption that the vector table is 525 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 526 * return the address of the default ISR location in the flash vector table. 527 * 528 * CM33:<br/> 529 * When called from the secure world, this function relies on the assumption that 530 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 531 * Otherwise it will return the address of the default ISR location in the 532 * flash/ROM vector table. 533 * 534 * \param IRQn 535 * Interrupt source 536 * 537 * \return 538 * Address of the ISR in the interrupt vector table 539 * 540 * \note CM0+:<br/> This function returns the interrupt vector for the interrupt 541 * channel on the NVIC. 542 * 543 * \note CM33:<br/>In case of CM33 with Security Extension eanbled, if this function is called 544 * from secure world then, it returns the interrupt vector for the secure world. 545 * If it is called form non-secure world then it returns the interrupt vector 546 * for the non-secure world. 547 * 548 * \funcusage 549 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector 550 * 551 *******************************************************************************/ 552 cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn); 553 554 555 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 556 /******************************************************************************* 557 * Function Name: Cy_SysInt_SetInterruptSource 558 ****************************************************************************//** 559 * 560 * \brief Configures the interrupt selection for the specified NVIC channel. 561 * 562 * To disconnect the interrupt source from the NVIC channel 563 * use the \ref Cy_SysInt_DisconnectInterruptSource. 564 * 565 * \param IRQn 566 * NVIC channel number connected to the CPU core. 567 * 568 * \param devIntrSrc 569 * Device interrupt to be routed to the NVIC channel. 570 * 571 * \note This function is available for CM0+ core only. 572 * 573 * \funcusage 574 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 575 * 576 *******************************************************************************/ 577 void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc); 578 579 580 /******************************************************************************* 581 * Function Name: Cy_SysInt_GetInterruptSource 582 ****************************************************************************//** 583 * 584 * \brief Gets the interrupt source of the NVIC channel. 585 * 586 * \param IRQn 587 * NVIC channel number connected to the CPU core 588 * 589 * \return 590 * Device interrupt connected to the NVIC channel. A returned value of 591 * "disconnected_IRQn" indicates that the interrupt source is disconnected. 592 * 593 * \note This function is available for CM0+ core only. 594 * 595 * \note This function supports only devices using CPUSS_ver1. For all 596 * other devices, use the Cy_SysInt_GetNvicConnection() function. 597 * 598 * \funcusage 599 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 600 * 601 *******************************************************************************/ 602 cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn); 603 604 605 /******************************************************************************* 606 * Function Name: Cy_SysInt_GetNvicConnection 607 ****************************************************************************//** 608 * 609 * \brief Gets the NVIC channel to which the interrupt source is connected. 610 * 611 * \param devIntrSrc 612 * Device interrupt that is potentially connected to the NVIC channel. 613 * 614 * \return 615 * NVIC channel number connected to the CPU core. A returned value of 616 * "unconnected_IRQn" indicates that the interrupt source is disabled. 617 * 618 * \note This function is available for CM0+ core only. 619 * 620 * \note This function supports only devices using CPUSS_ver2 or higher. 621 * 622 * \funcusage 623 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 624 * 625 *******************************************************************************/ 626 IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc); 627 628 629 /******************************************************************************* 630 * Function Name: Cy_SysInt_GetInterruptActive 631 ****************************************************************************//** 632 * 633 * \brief Gets the highest priority active interrupt for the selected NVIC channel. 634 * 635 * The priority of the interrupt in a given channel is determined by the index 636 * value of the interrupt in the cy_en_intr_t enum. The lower the index, the 637 * higher the priority. E.g. Consider a case where an interrupt source with value 638 * 29 and an interrupt source with value 46 both source the same NVIC channel. If 639 * both are active (triggered) at the same time, calling Cy_SysInt_GetInterruptActive() 640 * will return 29 as the active interrupt. 641 * 642 * \param IRQn 643 * NVIC channel number connected to the CPU core 644 * 645 * \return 646 * Device interrupt connected to the NVIC channel. A returned value of 647 * "disconnected_IRQn" indicates that there are no active (pending) interrupts 648 * on this NVIC channel. 649 * 650 * \note This function is available for CM0+ core only. 651 * 652 * \note This function supports only devices using CPUSS_ver2 or higher. 653 * 654 * \funcusage 655 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_GetInterruptActive 656 * 657 *******************************************************************************/ 658 cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn); 659 660 661 /******************************************************************************* 662 * Function Name: Cy_SysInt_DisconnectInterruptSource 663 ****************************************************************************//** 664 * 665 * \brief Disconnect the interrupt source from the specified NVIC channel. 666 * 667 * \param IRQn 668 * NVIC channel number connected to the CPU core. 669 * This parameter is ignored for devices using CPUSS_ver2. 670 * 671 * \param devIntrSrc 672 * Device interrupt routed to the NVIC channel. 673 * This parameter is ignored for devices using CPUSS_ver1. 674 * 675 * \note This function is available for CM0+ core only. 676 * 677 * \funcusage 678 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_DisconnectInterruptSource 679 * 680 *******************************************************************************/ 681 void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc); 682 #endif 683 684 685 /*************************************** 686 * Functions 687 ***************************************/ 688 689 /******************************************************************************* 690 * Function Name: Cy_SysInt_SetNmiSource 691 ****************************************************************************//** 692 * 693 * \brief Sets the interrupt source of the CPU core NMI. 694 * 695 * The interrupt source must be a positive number. Setting the value to 696 * "unconnected_IRQn" or "disconnected_IRQn" disconnects the interrupt source 697 * from the NMI. Depending on the device, the number of interrupt sources that 698 * can provide the NMI trigger signal to the core can vary. 699 * 700 * \param nmiNum 701 * NMI source number. 702 * CPUSS_ver2 allows up to 4 sources to trigger the core NMI. 703 * CPUSS_ver1 allows only one source to trigger the core NMI and 704 * the specified NMI number is ignored. 705 * 706 * \param intrSrc 707 * Interrupt source. This parameter can either be of type cy_en_intr_t or IRQn_Type 708 * for CM0+ and CM4/CM33 respectively. 709 * 710 * \note CM0+ may call this function only at PC=0, CM4 may set its NMI handler at any PC. 711 * \note The CM0+ NMI is used for performing system calls that execute out of ROM. 712 * 713 * \funcusage 714 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource 715 * 716 *******************************************************************************/ 717 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 2, 'Only one prototype will be pciked for compilation'); 718 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.5', 2, 'Only one prototype will be pciked for compilation'); 719 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.3', 2, 'Only one prototype will be pciked for compilation'); 720 #if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 721 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, IRQn_Type intrSrc); 722 #else 723 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_intr_t devIntrSrc); 724 #endif 725 726 /******************************************************************************* 727 * Function Name: Cy_SysInt_GetIntSourceNMI 728 ****************************************************************************//** 729 * 730 * \brief Gets the interrupt source of the CPU core NMI for the given NMI source 731 * number. 732 * 733 * \param nmiNum 734 * NMI source number. 735 * CPUSS_ver2 allows up to 4 sources to trigger the core NMI (i.e. #1, 2, 3, 4). 736 * CPUSS_ver1 allows only 1 source to trigger the core NMI (i.e #1). 737 * 738 * \return 739 * Interrupt Source. This parameter can either be of type cy_en_intr_t or IRQn_Type 740 * for CM0+ and CM4/CM33 respectively. 741 * 742 * \funcusage 743 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource 744 * 745 *******************************************************************************/ 746 #if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 747 IRQn_Type Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum); 748 #else 749 cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum); 750 #endif 751 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.3'); 752 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.5'); 753 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6'); 754 755 /******************************************************************************* 756 * Function Name: Cy_SysInt_SoftwareTrig 757 ****************************************************************************//** 758 * 759 * \brief Triggers an interrupt using software (Not applicable for CM0+). 760 * 761 * \param IRQn 762 * Interrupt source 763 * 764 * \funcusage 765 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SoftwareTrig 766 * 767 * \note Only privileged software can enable unprivileged access to the 768 * Software Trigger Interrupt Register (STIR). 769 * 770 *******************************************************************************/ 771 void Cy_SysInt_SoftwareTrig(IRQn_Type IRQn); 772 773 774 /** \} group_sysint_functions */ 775 776 /** \cond INTERNAL */ 777 778 /*************************************** 779 * Deprecated functions 780 ***************************************/ 781 782 /******************************************************************************* 783 * Function Name: Cy_SysInt_GetState 784 ****************************************************************************//** 785 * 786 * This function is deprecated. It invokes the NVIC_GetEnableIRQ() function. 787 * 788 *******************************************************************************/ 789 #define Cy_SysInt_GetState NVIC_GetEnableIRQ 790 791 792 /******************************************************************************* 793 * Function Name: Cy_SysInt_SetIntSource 794 ****************************************************************************//** 795 * 796 * This function is deprecated. It invokes the Cy_SysInt_SetInterruptSource() function. 797 * 798 *******************************************************************************/ 799 #define Cy_SysInt_SetIntSource(intrSrc, devIntrSrc) Cy_SysInt_SetInterruptSource(intrSrc, devIntrSrc) 800 801 802 /******************************************************************************* 803 * Function Name: Cy_SysInt_GetIntSource 804 ****************************************************************************//** 805 * 806 * This function is deprecated. It invokes the Cy_SysInt_GetInterruptSource() function. 807 * 808 *******************************************************************************/ 809 #define Cy_SysInt_GetIntSource(intrSrc) Cy_SysInt_GetInterruptSource(intrSrc) 810 811 812 /******************************************************************************* 813 * Function Name: Cy_SysInt_SetIntSourceNMI 814 ****************************************************************************//** 815 * 816 * This function is deprecated. It invokes the Cy_SysInt_SetNmiSource() function. 817 * 818 *******************************************************************************/ 819 #define Cy_SysInt_SetIntSourceNMI(srcParam) Cy_SysInt_SetNmiSource(CY_SYSINT_NMI1, srcParam) 820 821 822 /******************************************************************************* 823 * Function Name: Cy_SysInt_GetIntSourceNMI 824 ****************************************************************************//** 825 * 826 * This function is deprecated. It invokes the Cy_SysInt_GetNmiSource() function. 827 * 828 *******************************************************************************/ 829 #define Cy_SysInt_GetIntSourceNMI() Cy_SysInt_GetNmiSource(CY_SYSINT_NMI1) 830 831 /** \endcond */ 832 833 #if defined(__cplusplus) 834 } 835 #endif 836 837 #endif /* CY_IP_M33SYSCPUSS */ 838 839 #endif /* CY_SYSINT_H */ 840 841 /** \} group_sysint */ 842 843 /* [] END OF FILE */ 844
