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Searched refs:CY_PRA_CLKPLL_2 (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c727 …if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (devConfig->pll1Enable) && (devConfig->pll1OutputMode … in Cy_PRA_GetInputSourceFreq()
1350 else if (pll == CY_PRA_CLKPLL_2) in Cy_PRA_ValidatePLL()
1443 …if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) && (devConfig->pll1Enable) && (retStatus == CY_PRA_STATUS… in Cy_PRA_ValidateAllPLL()
1446 if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)) in Cy_PRA_ValidateAllPLL()
1448 retStatus = Cy_PRA_ValidatePLL(devConfig, CY_PRA_CLKPLL_2); in Cy_PRA_ValidateAllPLL()
2484 else if (pll == CY_PRA_CLKPLL_2) in Cy_PRA_CalculatePLLOutFreq()
2872 if (CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) in Cy_PRA_SystemConfig()
2874 if(Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)) in Cy_PRA_SystemConfig()
2877 oldFreq = Cy_SysClk_PllGetFrequency(CY_PRA_CLKPLL_2); in Cy_PRA_SystemConfig()
2878 newFreq = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_2, devConfig); in Cy_PRA_SystemConfig()
[all …]
Dcy_pra.c2146 … structCpy.pll1OutFreqHz = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_2, &structCpy); in Cy_PRA_ProcessCmd()
2292 … || (((message->praData1) == CY_PRA_CLKPLL_2) && (structCpy.pll1Enable == true)) in Cy_PRA_ProcessCmd()
2308 … structCpy.pll1OutFreqHz = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_2, &structCpy); in Cy_PRA_ProcessCmd()
3142 if (CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_2) in Cy_PRA_ClocksReset()
3144 sysClkStatus = Cy_SysClk_PllDisable(CY_PRA_CLKPLL_2); in Cy_PRA_ClocksReset()
/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/include/
Dcy_pra_cfg.h127 #define CY_PRA_CLKPLL_2 2U macro