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Searched refs:CY_PRA_CLKPLL_1 (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c709 …if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (devConfig->pll0Enable) && (devConfig->pll0OutputMode … in Cy_PRA_GetInputSourceFreq()
1342 if (pll == CY_PRA_CLKPLL_1) in Cy_PRA_ValidatePLL()
1429 if ((CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) && (devConfig->pll0Enable)) in Cy_PRA_ValidateAllPLL()
1432 if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)) in Cy_PRA_ValidateAllPLL()
1434 retStatus = Cy_PRA_ValidatePLL(devConfig, CY_PRA_CLKPLL_1); in Cy_PRA_ValidateAllPLL()
2476 if (pll == CY_PRA_CLKPLL_1) in Cy_PRA_CalculatePLLOutFreq()
2828 if (CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) in Cy_PRA_SystemConfig()
2830 if(Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)) in Cy_PRA_SystemConfig()
2833 oldFreq = Cy_SysClk_PllGetFrequency(CY_PRA_CLKPLL_1); in Cy_PRA_SystemConfig()
2834 newFreq = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_1, devConfig); in Cy_PRA_SystemConfig()
[all …]
Dcy_pra.c1077 …((message->praData1) == CY_PRA_CLKPLL_1) ? (pllEnable = structCpy.pll0Enable) : (pllEnable = struc… in Cy_PRA_ProcessCmd()
1079 …((message->praData1) == CY_PRA_CLKPLL_1) ? (structCpy.pll0Enable = false) : (structCpy.pll1Enable … in Cy_PRA_ProcessCmd()
1087 …((message->praData1) == CY_PRA_CLKPLL_1) ? (structCpy.pll0Enable = pllEnable) : (structCpy.pll1Ena… in Cy_PRA_ProcessCmd()
2131 … structCpy.pll0OutFreqHz = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_1, &structCpy); in Cy_PRA_ProcessCmd()
2291 … if ((((message->praData1) == CY_PRA_CLKPLL_1) && (structCpy.pll0Enable == true)) in Cy_PRA_ProcessCmd()
2301 if ((message->praData1) == CY_PRA_CLKPLL_1) in Cy_PRA_ProcessCmd()
2303 … structCpy.pll0OutFreqHz = Cy_PRA_CalculatePLLOutFreq(CY_PRA_CLKPLL_1, &structCpy); in Cy_PRA_ProcessCmd()
2317 if ((message->praData1) == CY_PRA_CLKPLL_1) in Cy_PRA_ProcessCmd()
3132 if (CY_SRSS_NUM_PLL >= CY_PRA_CLKPLL_1) in Cy_PRA_ClocksReset()
3134 sysClkStatus = Cy_SysClk_PllDisable(CY_PRA_CLKPLL_1); in Cy_PRA_ClocksReset()
/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/include/
Dcy_pra_cfg.h126 #define CY_PRA_CLKPLL_1 1U macro