1 /***************************************************************************//** 2 * \file cyip_csd.h 3 * 4 * \brief 5 * CSD IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_CSD_H_ 29 #define _CYIP_CSD_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * CSD 35 *******************************************************************************/ 36 37 #define CSD_SECTION_SIZE 0x00001000UL 38 39 /** 40 * \brief Capsense Controller (CSD) 41 */ 42 typedef struct { 43 __IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */ 44 __IOM uint32_t SPARE; /*!< 0x00000004 Spare MMIO */ 45 __IM uint32_t RESERVED[30]; 46 __IM uint32_t STATUS; /*!< 0x00000080 Status Register */ 47 __IM uint32_t STAT_SEQ; /*!< 0x00000084 Current Sequencer status */ 48 __IM uint32_t STAT_CNTS; /*!< 0x00000088 Current status counts */ 49 __IM uint32_t STAT_HCNT; /*!< 0x0000008C Current count of the HSCMP counter */ 50 __IM uint32_t RESERVED1[16]; 51 __IM uint32_t RESULT_VAL1; /*!< 0x000000D0 Result CSD/CSX accumulation counter value 1 */ 52 __IM uint32_t RESULT_VAL2; /*!< 0x000000D4 Result CSX accumulation counter value 2 */ 53 __IM uint32_t RESERVED2[2]; 54 __IM uint32_t ADC_RES; /*!< 0x000000E0 ADC measurement */ 55 __IM uint32_t RESERVED3[3]; 56 __IOM uint32_t INTR; /*!< 0x000000F0 CSD Interrupt Request Register */ 57 __IOM uint32_t INTR_SET; /*!< 0x000000F4 CSD Interrupt set register */ 58 __IOM uint32_t INTR_MASK; /*!< 0x000000F8 CSD Interrupt mask register */ 59 __IM uint32_t INTR_MASKED; /*!< 0x000000FC CSD Interrupt masked register */ 60 __IM uint32_t RESERVED4[32]; 61 __IOM uint32_t HSCMP; /*!< 0x00000180 High Speed Comparator configuration */ 62 __IOM uint32_t AMBUF; /*!< 0x00000184 Reference Generator configuration */ 63 __IOM uint32_t REFGEN; /*!< 0x00000188 Reference Generator configuration */ 64 __IOM uint32_t CSDCMP; /*!< 0x0000018C CSD Comparator configuration */ 65 __IM uint32_t RESERVED5[24]; 66 __IOM uint32_t SW_RES; /*!< 0x000001F0 Switch Resistance configuration */ 67 __IM uint32_t RESERVED6[3]; 68 __IOM uint32_t SENSE_PERIOD; /*!< 0x00000200 Sense clock period */ 69 __IOM uint32_t SENSE_DUTY; /*!< 0x00000204 Sense clock duty cycle */ 70 __IM uint32_t RESERVED7[30]; 71 __IOM uint32_t SW_HS_P_SEL; /*!< 0x00000280 HSCMP Pos input switch Waveform selection */ 72 __IOM uint32_t SW_HS_N_SEL; /*!< 0x00000284 HSCMP Neg input switch Waveform selection */ 73 __IOM uint32_t SW_SHIELD_SEL; /*!< 0x00000288 Shielding switches Waveform selection */ 74 __IM uint32_t RESERVED8; 75 __IOM uint32_t SW_AMUXBUF_SEL; /*!< 0x00000290 Amuxbuffer switches Waveform selection */ 76 __IOM uint32_t SW_BYP_SEL; /*!< 0x00000294 AMUXBUS bypass switches Waveform selection */ 77 __IM uint32_t RESERVED9[2]; 78 __IOM uint32_t SW_CMP_P_SEL; /*!< 0x000002A0 CSDCMP Pos Switch Waveform selection */ 79 __IOM uint32_t SW_CMP_N_SEL; /*!< 0x000002A4 CSDCMP Neg Switch Waveform selection */ 80 __IOM uint32_t SW_REFGEN_SEL; /*!< 0x000002A8 Reference Generator Switch Waveform selection */ 81 __IM uint32_t RESERVED10; 82 __IOM uint32_t SW_FW_MOD_SEL; /*!< 0x000002B0 Full Wave Cmod Switch Waveform selection */ 83 __IOM uint32_t SW_FW_TANK_SEL; /*!< 0x000002B4 Full Wave Csh_tank Switch Waveform selection */ 84 __IM uint32_t RESERVED11[2]; 85 __IOM uint32_t SW_DSI_SEL; /*!< 0x000002C0 DSI output switch control Waveform selection */ 86 __IM uint32_t RESERVED12[3]; 87 __IOM uint32_t IO_SEL; /*!< 0x000002D0 IO output control Waveform selection */ 88 __IM uint32_t RESERVED13[11]; 89 __IOM uint32_t SEQ_TIME; /*!< 0x00000300 Sequencer Timing */ 90 __IM uint32_t RESERVED14[3]; 91 __IOM uint32_t SEQ_INIT_CNT; /*!< 0x00000310 Sequencer Initial conversion and sample counts */ 92 __IOM uint32_t SEQ_NORM_CNT; /*!< 0x00000314 Sequencer Normal conversion and sample counts */ 93 __IM uint32_t RESERVED15[2]; 94 __IOM uint32_t ADC_CTL; /*!< 0x00000320 ADC Control */ 95 __IM uint32_t RESERVED16[7]; 96 __IOM uint32_t SEQ_START; /*!< 0x00000340 Sequencer start */ 97 __IM uint32_t RESERVED17[47]; 98 __IOM uint32_t IDACA; /*!< 0x00000400 IDACA Configuration */ 99 __IM uint32_t RESERVED18[63]; 100 __IOM uint32_t IDACB; /*!< 0x00000500 IDACB Configuration */ 101 } CSD_V1_Type; /*!< Size = 1284 (0x504) */ 102 103 104 /* CSD.CONFIG */ 105 #define CSD_CONFIG_IREF_SEL_Pos 0UL 106 #define CSD_CONFIG_IREF_SEL_Msk 0x1UL 107 #define CSD_CONFIG_FILTER_DELAY_Pos 4UL 108 #define CSD_CONFIG_FILTER_DELAY_Msk 0x1F0UL 109 #define CSD_CONFIG_SHIELD_DELAY_Pos 10UL 110 #define CSD_CONFIG_SHIELD_DELAY_Msk 0xC00UL 111 #define CSD_CONFIG_SENSE_EN_Pos 12UL 112 #define CSD_CONFIG_SENSE_EN_Msk 0x1000UL 113 #define CSD_CONFIG_FULL_WAVE_Pos 17UL 114 #define CSD_CONFIG_FULL_WAVE_Msk 0x20000UL 115 #define CSD_CONFIG_MUTUAL_CAP_Pos 18UL 116 #define CSD_CONFIG_MUTUAL_CAP_Msk 0x40000UL 117 #define CSD_CONFIG_CSX_DUAL_CNT_Pos 19UL 118 #define CSD_CONFIG_CSX_DUAL_CNT_Msk 0x80000UL 119 #define CSD_CONFIG_DSI_COUNT_SEL_Pos 24UL 120 #define CSD_CONFIG_DSI_COUNT_SEL_Msk 0x1000000UL 121 #define CSD_CONFIG_DSI_SAMPLE_EN_Pos 25UL 122 #define CSD_CONFIG_DSI_SAMPLE_EN_Msk 0x2000000UL 123 #define CSD_CONFIG_SAMPLE_SYNC_Pos 26UL 124 #define CSD_CONFIG_SAMPLE_SYNC_Msk 0x4000000UL 125 #define CSD_CONFIG_DSI_SENSE_EN_Pos 27UL 126 #define CSD_CONFIG_DSI_SENSE_EN_Msk 0x8000000UL 127 #define CSD_CONFIG_LP_MODE_Pos 30UL 128 #define CSD_CONFIG_LP_MODE_Msk 0x40000000UL 129 #define CSD_CONFIG_ENABLE_Pos 31UL 130 #define CSD_CONFIG_ENABLE_Msk 0x80000000UL 131 /* CSD.SPARE */ 132 #define CSD_SPARE_SPARE_Pos 0UL 133 #define CSD_SPARE_SPARE_Msk 0xFUL 134 /* CSD.STATUS */ 135 #define CSD_STATUS_CSD_SENSE_Pos 1UL 136 #define CSD_STATUS_CSD_SENSE_Msk 0x2UL 137 #define CSD_STATUS_HSCMP_OUT_Pos 2UL 138 #define CSD_STATUS_HSCMP_OUT_Msk 0x4UL 139 #define CSD_STATUS_CSDCMP_OUT_Pos 3UL 140 #define CSD_STATUS_CSDCMP_OUT_Msk 0x8UL 141 /* CSD.STAT_SEQ */ 142 #define CSD_STAT_SEQ_SEQ_STATE_Pos 0UL 143 #define CSD_STAT_SEQ_SEQ_STATE_Msk 0x7UL 144 #define CSD_STAT_SEQ_ADC_STATE_Pos 16UL 145 #define CSD_STAT_SEQ_ADC_STATE_Msk 0x70000UL 146 /* CSD.STAT_CNTS */ 147 #define CSD_STAT_CNTS_NUM_CONV_Pos 0UL 148 #define CSD_STAT_CNTS_NUM_CONV_Msk 0xFFFFUL 149 /* CSD.STAT_HCNT */ 150 #define CSD_STAT_HCNT_CNT_Pos 0UL 151 #define CSD_STAT_HCNT_CNT_Msk 0xFFFFUL 152 /* CSD.RESULT_VAL1 */ 153 #define CSD_RESULT_VAL1_VALUE_Pos 0UL 154 #define CSD_RESULT_VAL1_VALUE_Msk 0xFFFFUL 155 #define CSD_RESULT_VAL1_BAD_CONVS_Pos 16UL 156 #define CSD_RESULT_VAL1_BAD_CONVS_Msk 0xFF0000UL 157 /* CSD.RESULT_VAL2 */ 158 #define CSD_RESULT_VAL2_VALUE_Pos 0UL 159 #define CSD_RESULT_VAL2_VALUE_Msk 0xFFFFUL 160 /* CSD.ADC_RES */ 161 #define CSD_ADC_RES_VIN_CNT_Pos 0UL 162 #define CSD_ADC_RES_VIN_CNT_Msk 0xFFFFUL 163 #define CSD_ADC_RES_HSCMP_POL_Pos 16UL 164 #define CSD_ADC_RES_HSCMP_POL_Msk 0x10000UL 165 #define CSD_ADC_RES_ADC_OVERFLOW_Pos 30UL 166 #define CSD_ADC_RES_ADC_OVERFLOW_Msk 0x40000000UL 167 #define CSD_ADC_RES_ADC_ABORT_Pos 31UL 168 #define CSD_ADC_RES_ADC_ABORT_Msk 0x80000000UL 169 /* CSD.INTR */ 170 #define CSD_INTR_SAMPLE_Pos 1UL 171 #define CSD_INTR_SAMPLE_Msk 0x2UL 172 #define CSD_INTR_INIT_Pos 2UL 173 #define CSD_INTR_INIT_Msk 0x4UL 174 #define CSD_INTR_ADC_RES_Pos 8UL 175 #define CSD_INTR_ADC_RES_Msk 0x100UL 176 /* CSD.INTR_SET */ 177 #define CSD_INTR_SET_SAMPLE_Pos 1UL 178 #define CSD_INTR_SET_SAMPLE_Msk 0x2UL 179 #define CSD_INTR_SET_INIT_Pos 2UL 180 #define CSD_INTR_SET_INIT_Msk 0x4UL 181 #define CSD_INTR_SET_ADC_RES_Pos 8UL 182 #define CSD_INTR_SET_ADC_RES_Msk 0x100UL 183 /* CSD.INTR_MASK */ 184 #define CSD_INTR_MASK_SAMPLE_Pos 1UL 185 #define CSD_INTR_MASK_SAMPLE_Msk 0x2UL 186 #define CSD_INTR_MASK_INIT_Pos 2UL 187 #define CSD_INTR_MASK_INIT_Msk 0x4UL 188 #define CSD_INTR_MASK_ADC_RES_Pos 8UL 189 #define CSD_INTR_MASK_ADC_RES_Msk 0x100UL 190 /* CSD.INTR_MASKED */ 191 #define CSD_INTR_MASKED_SAMPLE_Pos 1UL 192 #define CSD_INTR_MASKED_SAMPLE_Msk 0x2UL 193 #define CSD_INTR_MASKED_INIT_Pos 2UL 194 #define CSD_INTR_MASKED_INIT_Msk 0x4UL 195 #define CSD_INTR_MASKED_ADC_RES_Pos 8UL 196 #define CSD_INTR_MASKED_ADC_RES_Msk 0x100UL 197 /* CSD.HSCMP */ 198 #define CSD_HSCMP_HSCMP_EN_Pos 0UL 199 #define CSD_HSCMP_HSCMP_EN_Msk 0x1UL 200 #define CSD_HSCMP_HSCMP_INVERT_Pos 4UL 201 #define CSD_HSCMP_HSCMP_INVERT_Msk 0x10UL 202 #define CSD_HSCMP_AZ_EN_Pos 31UL 203 #define CSD_HSCMP_AZ_EN_Msk 0x80000000UL 204 /* CSD.AMBUF */ 205 #define CSD_AMBUF_PWR_MODE_Pos 0UL 206 #define CSD_AMBUF_PWR_MODE_Msk 0x3UL 207 /* CSD.REFGEN */ 208 #define CSD_REFGEN_REFGEN_EN_Pos 0UL 209 #define CSD_REFGEN_REFGEN_EN_Msk 0x1UL 210 #define CSD_REFGEN_BYPASS_Pos 4UL 211 #define CSD_REFGEN_BYPASS_Msk 0x10UL 212 #define CSD_REFGEN_VDDA_EN_Pos 5UL 213 #define CSD_REFGEN_VDDA_EN_Msk 0x20UL 214 #define CSD_REFGEN_RES_EN_Pos 6UL 215 #define CSD_REFGEN_RES_EN_Msk 0x40UL 216 #define CSD_REFGEN_GAIN_Pos 8UL 217 #define CSD_REFGEN_GAIN_Msk 0x1F00UL 218 #define CSD_REFGEN_VREFLO_SEL_Pos 16UL 219 #define CSD_REFGEN_VREFLO_SEL_Msk 0x1F0000UL 220 #define CSD_REFGEN_VREFLO_INT_Pos 23UL 221 #define CSD_REFGEN_VREFLO_INT_Msk 0x800000UL 222 /* CSD.CSDCMP */ 223 #define CSD_CSDCMP_CSDCMP_EN_Pos 0UL 224 #define CSD_CSDCMP_CSDCMP_EN_Msk 0x1UL 225 #define CSD_CSDCMP_POLARITY_SEL_Pos 4UL 226 #define CSD_CSDCMP_POLARITY_SEL_Msk 0x30UL 227 #define CSD_CSDCMP_CMP_PHASE_Pos 8UL 228 #define CSD_CSDCMP_CMP_PHASE_Msk 0x300UL 229 #define CSD_CSDCMP_CMP_MODE_Pos 28UL 230 #define CSD_CSDCMP_CMP_MODE_Msk 0x10000000UL 231 #define CSD_CSDCMP_FEEDBACK_MODE_Pos 29UL 232 #define CSD_CSDCMP_FEEDBACK_MODE_Msk 0x20000000UL 233 #define CSD_CSDCMP_AZ_EN_Pos 31UL 234 #define CSD_CSDCMP_AZ_EN_Msk 0x80000000UL 235 /* CSD.SW_RES */ 236 #define CSD_SW_RES_RES_HCAV_Pos 0UL 237 #define CSD_SW_RES_RES_HCAV_Msk 0x3UL 238 #define CSD_SW_RES_RES_HCAG_Pos 2UL 239 #define CSD_SW_RES_RES_HCAG_Msk 0xCUL 240 #define CSD_SW_RES_RES_HCBV_Pos 4UL 241 #define CSD_SW_RES_RES_HCBV_Msk 0x30UL 242 #define CSD_SW_RES_RES_HCBG_Pos 6UL 243 #define CSD_SW_RES_RES_HCBG_Msk 0xC0UL 244 #define CSD_SW_RES_RES_F1PM_Pos 16UL 245 #define CSD_SW_RES_RES_F1PM_Msk 0x30000UL 246 #define CSD_SW_RES_RES_F2PT_Pos 18UL 247 #define CSD_SW_RES_RES_F2PT_Msk 0xC0000UL 248 /* CSD.SENSE_PERIOD */ 249 #define CSD_SENSE_PERIOD_SENSE_DIV_Pos 0UL 250 #define CSD_SENSE_PERIOD_SENSE_DIV_Msk 0xFFFUL 251 #define CSD_SENSE_PERIOD_LFSR_SIZE_Pos 16UL 252 #define CSD_SENSE_PERIOD_LFSR_SIZE_Msk 0x70000UL 253 #define CSD_SENSE_PERIOD_LFSR_SCALE_Pos 20UL 254 #define CSD_SENSE_PERIOD_LFSR_SCALE_Msk 0xF00000UL 255 #define CSD_SENSE_PERIOD_LFSR_CLEAR_Pos 24UL 256 #define CSD_SENSE_PERIOD_LFSR_CLEAR_Msk 0x1000000UL 257 #define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Pos 25UL 258 #define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Msk 0x2000000UL 259 #define CSD_SENSE_PERIOD_LFSR_BITS_Pos 26UL 260 #define CSD_SENSE_PERIOD_LFSR_BITS_Msk 0xC000000UL 261 /* CSD.SENSE_DUTY */ 262 #define CSD_SENSE_DUTY_SENSE_WIDTH_Pos 0UL 263 #define CSD_SENSE_DUTY_SENSE_WIDTH_Msk 0xFFFUL 264 #define CSD_SENSE_DUTY_SENSE_POL_Pos 16UL 265 #define CSD_SENSE_DUTY_SENSE_POL_Msk 0x10000UL 266 #define CSD_SENSE_DUTY_OVERLAP_PHI1_Pos 18UL 267 #define CSD_SENSE_DUTY_OVERLAP_PHI1_Msk 0x40000UL 268 #define CSD_SENSE_DUTY_OVERLAP_PHI2_Pos 19UL 269 #define CSD_SENSE_DUTY_OVERLAP_PHI2_Msk 0x80000UL 270 /* CSD.SW_HS_P_SEL */ 271 #define CSD_SW_HS_P_SEL_SW_HMPM_Pos 0UL 272 #define CSD_SW_HS_P_SEL_SW_HMPM_Msk 0x1UL 273 #define CSD_SW_HS_P_SEL_SW_HMPT_Pos 4UL 274 #define CSD_SW_HS_P_SEL_SW_HMPT_Msk 0x10UL 275 #define CSD_SW_HS_P_SEL_SW_HMPS_Pos 8UL 276 #define CSD_SW_HS_P_SEL_SW_HMPS_Msk 0x100UL 277 #define CSD_SW_HS_P_SEL_SW_HMMA_Pos 12UL 278 #define CSD_SW_HS_P_SEL_SW_HMMA_Msk 0x1000UL 279 #define CSD_SW_HS_P_SEL_SW_HMMB_Pos 16UL 280 #define CSD_SW_HS_P_SEL_SW_HMMB_Msk 0x10000UL 281 #define CSD_SW_HS_P_SEL_SW_HMCA_Pos 20UL 282 #define CSD_SW_HS_P_SEL_SW_HMCA_Msk 0x100000UL 283 #define CSD_SW_HS_P_SEL_SW_HMCB_Pos 24UL 284 #define CSD_SW_HS_P_SEL_SW_HMCB_Msk 0x1000000UL 285 #define CSD_SW_HS_P_SEL_SW_HMRH_Pos 28UL 286 #define CSD_SW_HS_P_SEL_SW_HMRH_Msk 0x10000000UL 287 /* CSD.SW_HS_N_SEL */ 288 #define CSD_SW_HS_N_SEL_SW_HCCC_Pos 16UL 289 #define CSD_SW_HS_N_SEL_SW_HCCC_Msk 0x10000UL 290 #define CSD_SW_HS_N_SEL_SW_HCCD_Pos 20UL 291 #define CSD_SW_HS_N_SEL_SW_HCCD_Msk 0x100000UL 292 #define CSD_SW_HS_N_SEL_SW_HCRH_Pos 24UL 293 #define CSD_SW_HS_N_SEL_SW_HCRH_Msk 0x7000000UL 294 #define CSD_SW_HS_N_SEL_SW_HCRL_Pos 28UL 295 #define CSD_SW_HS_N_SEL_SW_HCRL_Msk 0x70000000UL 296 /* CSD.SW_SHIELD_SEL */ 297 #define CSD_SW_SHIELD_SEL_SW_HCAV_Pos 0UL 298 #define CSD_SW_SHIELD_SEL_SW_HCAV_Msk 0x7UL 299 #define CSD_SW_SHIELD_SEL_SW_HCAG_Pos 4UL 300 #define CSD_SW_SHIELD_SEL_SW_HCAG_Msk 0x70UL 301 #define CSD_SW_SHIELD_SEL_SW_HCBV_Pos 8UL 302 #define CSD_SW_SHIELD_SEL_SW_HCBV_Msk 0x700UL 303 #define CSD_SW_SHIELD_SEL_SW_HCBG_Pos 12UL 304 #define CSD_SW_SHIELD_SEL_SW_HCBG_Msk 0x7000UL 305 #define CSD_SW_SHIELD_SEL_SW_HCCV_Pos 16UL 306 #define CSD_SW_SHIELD_SEL_SW_HCCV_Msk 0x10000UL 307 #define CSD_SW_SHIELD_SEL_SW_HCCG_Pos 20UL 308 #define CSD_SW_SHIELD_SEL_SW_HCCG_Msk 0x100000UL 309 /* CSD.SW_AMUXBUF_SEL */ 310 #define CSD_SW_AMUXBUF_SEL_SW_IRBY_Pos 4UL 311 #define CSD_SW_AMUXBUF_SEL_SW_IRBY_Msk 0x10UL 312 #define CSD_SW_AMUXBUF_SEL_SW_IRLB_Pos 8UL 313 #define CSD_SW_AMUXBUF_SEL_SW_IRLB_Msk 0x100UL 314 #define CSD_SW_AMUXBUF_SEL_SW_ICA_Pos 12UL 315 #define CSD_SW_AMUXBUF_SEL_SW_ICA_Msk 0x1000UL 316 #define CSD_SW_AMUXBUF_SEL_SW_ICB_Pos 16UL 317 #define CSD_SW_AMUXBUF_SEL_SW_ICB_Msk 0x70000UL 318 #define CSD_SW_AMUXBUF_SEL_SW_IRLI_Pos 20UL 319 #define CSD_SW_AMUXBUF_SEL_SW_IRLI_Msk 0x100000UL 320 #define CSD_SW_AMUXBUF_SEL_SW_IRH_Pos 24UL 321 #define CSD_SW_AMUXBUF_SEL_SW_IRH_Msk 0x1000000UL 322 #define CSD_SW_AMUXBUF_SEL_SW_IRL_Pos 28UL 323 #define CSD_SW_AMUXBUF_SEL_SW_IRL_Msk 0x10000000UL 324 /* CSD.SW_BYP_SEL */ 325 #define CSD_SW_BYP_SEL_SW_BYA_Pos 12UL 326 #define CSD_SW_BYP_SEL_SW_BYA_Msk 0x1000UL 327 #define CSD_SW_BYP_SEL_SW_BYB_Pos 16UL 328 #define CSD_SW_BYP_SEL_SW_BYB_Msk 0x10000UL 329 #define CSD_SW_BYP_SEL_SW_CBCC_Pos 20UL 330 #define CSD_SW_BYP_SEL_SW_CBCC_Msk 0x100000UL 331 /* CSD.SW_CMP_P_SEL */ 332 #define CSD_SW_CMP_P_SEL_SW_SFPM_Pos 0UL 333 #define CSD_SW_CMP_P_SEL_SW_SFPM_Msk 0x7UL 334 #define CSD_SW_CMP_P_SEL_SW_SFPT_Pos 4UL 335 #define CSD_SW_CMP_P_SEL_SW_SFPT_Msk 0x70UL 336 #define CSD_SW_CMP_P_SEL_SW_SFPS_Pos 8UL 337 #define CSD_SW_CMP_P_SEL_SW_SFPS_Msk 0x700UL 338 #define CSD_SW_CMP_P_SEL_SW_SFMA_Pos 12UL 339 #define CSD_SW_CMP_P_SEL_SW_SFMA_Msk 0x1000UL 340 #define CSD_SW_CMP_P_SEL_SW_SFMB_Pos 16UL 341 #define CSD_SW_CMP_P_SEL_SW_SFMB_Msk 0x10000UL 342 #define CSD_SW_CMP_P_SEL_SW_SFCA_Pos 20UL 343 #define CSD_SW_CMP_P_SEL_SW_SFCA_Msk 0x100000UL 344 #define CSD_SW_CMP_P_SEL_SW_SFCB_Pos 24UL 345 #define CSD_SW_CMP_P_SEL_SW_SFCB_Msk 0x1000000UL 346 /* CSD.SW_CMP_N_SEL */ 347 #define CSD_SW_CMP_N_SEL_SW_SCRH_Pos 24UL 348 #define CSD_SW_CMP_N_SEL_SW_SCRH_Msk 0x7000000UL 349 #define CSD_SW_CMP_N_SEL_SW_SCRL_Pos 28UL 350 #define CSD_SW_CMP_N_SEL_SW_SCRL_Msk 0x70000000UL 351 /* CSD.SW_REFGEN_SEL */ 352 #define CSD_SW_REFGEN_SEL_SW_IAIB_Pos 0UL 353 #define CSD_SW_REFGEN_SEL_SW_IAIB_Msk 0x1UL 354 #define CSD_SW_REFGEN_SEL_SW_IBCB_Pos 4UL 355 #define CSD_SW_REFGEN_SEL_SW_IBCB_Msk 0x10UL 356 #define CSD_SW_REFGEN_SEL_SW_SGMB_Pos 16UL 357 #define CSD_SW_REFGEN_SEL_SW_SGMB_Msk 0x10000UL 358 #define CSD_SW_REFGEN_SEL_SW_SGRP_Pos 20UL 359 #define CSD_SW_REFGEN_SEL_SW_SGRP_Msk 0x100000UL 360 #define CSD_SW_REFGEN_SEL_SW_SGRE_Pos 24UL 361 #define CSD_SW_REFGEN_SEL_SW_SGRE_Msk 0x1000000UL 362 #define CSD_SW_REFGEN_SEL_SW_SGR_Pos 28UL 363 #define CSD_SW_REFGEN_SEL_SW_SGR_Msk 0x10000000UL 364 /* CSD.SW_FW_MOD_SEL */ 365 #define CSD_SW_FW_MOD_SEL_SW_F1PM_Pos 0UL 366 #define CSD_SW_FW_MOD_SEL_SW_F1PM_Msk 0x1UL 367 #define CSD_SW_FW_MOD_SEL_SW_F1MA_Pos 8UL 368 #define CSD_SW_FW_MOD_SEL_SW_F1MA_Msk 0x700UL 369 #define CSD_SW_FW_MOD_SEL_SW_F1CA_Pos 16UL 370 #define CSD_SW_FW_MOD_SEL_SW_F1CA_Msk 0x70000UL 371 #define CSD_SW_FW_MOD_SEL_SW_C1CC_Pos 20UL 372 #define CSD_SW_FW_MOD_SEL_SW_C1CC_Msk 0x100000UL 373 #define CSD_SW_FW_MOD_SEL_SW_C1CD_Pos 24UL 374 #define CSD_SW_FW_MOD_SEL_SW_C1CD_Msk 0x1000000UL 375 #define CSD_SW_FW_MOD_SEL_SW_C1F1_Pos 28UL 376 #define CSD_SW_FW_MOD_SEL_SW_C1F1_Msk 0x10000000UL 377 /* CSD.SW_FW_TANK_SEL */ 378 #define CSD_SW_FW_TANK_SEL_SW_F2PT_Pos 4UL 379 #define CSD_SW_FW_TANK_SEL_SW_F2PT_Msk 0x10UL 380 #define CSD_SW_FW_TANK_SEL_SW_F2MA_Pos 8UL 381 #define CSD_SW_FW_TANK_SEL_SW_F2MA_Msk 0x700UL 382 #define CSD_SW_FW_TANK_SEL_SW_F2CA_Pos 12UL 383 #define CSD_SW_FW_TANK_SEL_SW_F2CA_Msk 0x7000UL 384 #define CSD_SW_FW_TANK_SEL_SW_F2CB_Pos 16UL 385 #define CSD_SW_FW_TANK_SEL_SW_F2CB_Msk 0x70000UL 386 #define CSD_SW_FW_TANK_SEL_SW_C2CC_Pos 20UL 387 #define CSD_SW_FW_TANK_SEL_SW_C2CC_Msk 0x100000UL 388 #define CSD_SW_FW_TANK_SEL_SW_C2CD_Pos 24UL 389 #define CSD_SW_FW_TANK_SEL_SW_C2CD_Msk 0x1000000UL 390 #define CSD_SW_FW_TANK_SEL_SW_C2F2_Pos 28UL 391 #define CSD_SW_FW_TANK_SEL_SW_C2F2_Msk 0x10000000UL 392 /* CSD.SW_DSI_SEL */ 393 #define CSD_SW_DSI_SEL_DSI_CSH_TANK_Pos 0UL 394 #define CSD_SW_DSI_SEL_DSI_CSH_TANK_Msk 0xFUL 395 #define CSD_SW_DSI_SEL_DSI_CMOD_Pos 4UL 396 #define CSD_SW_DSI_SEL_DSI_CMOD_Msk 0xF0UL 397 /* CSD.IO_SEL */ 398 #define CSD_IO_SEL_CSD_TX_OUT_Pos 0UL 399 #define CSD_IO_SEL_CSD_TX_OUT_Msk 0xFUL 400 #define CSD_IO_SEL_CSD_TX_OUT_EN_Pos 4UL 401 #define CSD_IO_SEL_CSD_TX_OUT_EN_Msk 0xF0UL 402 #define CSD_IO_SEL_CSD_TX_AMUXB_EN_Pos 12UL 403 #define CSD_IO_SEL_CSD_TX_AMUXB_EN_Msk 0xF000UL 404 #define CSD_IO_SEL_CSD_TX_N_OUT_Pos 16UL 405 #define CSD_IO_SEL_CSD_TX_N_OUT_Msk 0xF0000UL 406 #define CSD_IO_SEL_CSD_TX_N_OUT_EN_Pos 20UL 407 #define CSD_IO_SEL_CSD_TX_N_OUT_EN_Msk 0xF00000UL 408 #define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Pos 24UL 409 #define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Msk 0xF000000UL 410 /* CSD.SEQ_TIME */ 411 #define CSD_SEQ_TIME_AZ_TIME_Pos 0UL 412 #define CSD_SEQ_TIME_AZ_TIME_Msk 0xFFUL 413 /* CSD.SEQ_INIT_CNT */ 414 #define CSD_SEQ_INIT_CNT_CONV_CNT_Pos 0UL 415 #define CSD_SEQ_INIT_CNT_CONV_CNT_Msk 0xFFFFUL 416 /* CSD.SEQ_NORM_CNT */ 417 #define CSD_SEQ_NORM_CNT_CONV_CNT_Pos 0UL 418 #define CSD_SEQ_NORM_CNT_CONV_CNT_Msk 0xFFFFUL 419 /* CSD.ADC_CTL */ 420 #define CSD_ADC_CTL_ADC_TIME_Pos 0UL 421 #define CSD_ADC_CTL_ADC_TIME_Msk 0xFFUL 422 #define CSD_ADC_CTL_ADC_MODE_Pos 16UL 423 #define CSD_ADC_CTL_ADC_MODE_Msk 0x30000UL 424 /* CSD.SEQ_START */ 425 #define CSD_SEQ_START_START_Pos 0UL 426 #define CSD_SEQ_START_START_Msk 0x1UL 427 #define CSD_SEQ_START_SEQ_MODE_Pos 1UL 428 #define CSD_SEQ_START_SEQ_MODE_Msk 0x2UL 429 #define CSD_SEQ_START_ABORT_Pos 3UL 430 #define CSD_SEQ_START_ABORT_Msk 0x8UL 431 #define CSD_SEQ_START_DSI_START_EN_Pos 4UL 432 #define CSD_SEQ_START_DSI_START_EN_Msk 0x10UL 433 #define CSD_SEQ_START_AZ0_SKIP_Pos 8UL 434 #define CSD_SEQ_START_AZ0_SKIP_Msk 0x100UL 435 #define CSD_SEQ_START_AZ1_SKIP_Pos 9UL 436 #define CSD_SEQ_START_AZ1_SKIP_Msk 0x200UL 437 /* CSD.IDACA */ 438 #define CSD_IDACA_VAL_Pos 0UL 439 #define CSD_IDACA_VAL_Msk 0x7FUL 440 #define CSD_IDACA_POL_DYN_Pos 7UL 441 #define CSD_IDACA_POL_DYN_Msk 0x80UL 442 #define CSD_IDACA_POLARITY_Pos 8UL 443 #define CSD_IDACA_POLARITY_Msk 0x300UL 444 #define CSD_IDACA_BAL_MODE_Pos 10UL 445 #define CSD_IDACA_BAL_MODE_Msk 0xC00UL 446 #define CSD_IDACA_LEG1_MODE_Pos 16UL 447 #define CSD_IDACA_LEG1_MODE_Msk 0x30000UL 448 #define CSD_IDACA_LEG2_MODE_Pos 18UL 449 #define CSD_IDACA_LEG2_MODE_Msk 0xC0000UL 450 #define CSD_IDACA_DSI_CTRL_EN_Pos 21UL 451 #define CSD_IDACA_DSI_CTRL_EN_Msk 0x200000UL 452 #define CSD_IDACA_RANGE_Pos 22UL 453 #define CSD_IDACA_RANGE_Msk 0xC00000UL 454 #define CSD_IDACA_LEG1_EN_Pos 24UL 455 #define CSD_IDACA_LEG1_EN_Msk 0x1000000UL 456 #define CSD_IDACA_LEG2_EN_Pos 25UL 457 #define CSD_IDACA_LEG2_EN_Msk 0x2000000UL 458 /* CSD.IDACB */ 459 #define CSD_IDACB_VAL_Pos 0UL 460 #define CSD_IDACB_VAL_Msk 0x7FUL 461 #define CSD_IDACB_POL_DYN_Pos 7UL 462 #define CSD_IDACB_POL_DYN_Msk 0x80UL 463 #define CSD_IDACB_POLARITY_Pos 8UL 464 #define CSD_IDACB_POLARITY_Msk 0x300UL 465 #define CSD_IDACB_BAL_MODE_Pos 10UL 466 #define CSD_IDACB_BAL_MODE_Msk 0xC00UL 467 #define CSD_IDACB_LEG1_MODE_Pos 16UL 468 #define CSD_IDACB_LEG1_MODE_Msk 0x30000UL 469 #define CSD_IDACB_LEG2_MODE_Pos 18UL 470 #define CSD_IDACB_LEG2_MODE_Msk 0xC0000UL 471 #define CSD_IDACB_DSI_CTRL_EN_Pos 21UL 472 #define CSD_IDACB_DSI_CTRL_EN_Msk 0x200000UL 473 #define CSD_IDACB_RANGE_Pos 22UL 474 #define CSD_IDACB_RANGE_Msk 0xC00000UL 475 #define CSD_IDACB_LEG1_EN_Pos 24UL 476 #define CSD_IDACB_LEG1_EN_Msk 0x1000000UL 477 #define CSD_IDACB_LEG2_EN_Pos 25UL 478 #define CSD_IDACB_LEG2_EN_Msk 0x2000000UL 479 #define CSD_IDACB_LEG3_EN_Pos 26UL 480 #define CSD_IDACB_LEG3_EN_Msk 0x4000000UL 481 482 483 #endif /* _CYIP_CSD_H_ */ 484 485 486 /* [] END OF FILE */ 487
