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Searched refs:CPUSS_ROM_TRIM_DEFAULT (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.4.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_04_config.h1375 #define CPUSS_ROM_TRIM_DEFAULT 18u macro
Dpsoc6_03_config.h1408 #define CPUSS_ROM_TRIM_DEFAULT 18u macro
Dpsoc6_02_config.h1882 #define CPUSS_ROM_TRIM_DEFAULT 18u macro