Searched refs:CPUSS_DW0_CH_NR (Results 1 – 6 of 6) sorted by relevance
43 #define _CYHAL_DMA_DW_NUM_CHANNELS (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)45 #define _CYHAL_DMA_DW_NUM_CHANNELS (CPUSS_DW0_CH_NR)53 #define CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ CPUSS_DW0_CH_NR143 …_cyhal_dma_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num… in _cyhal_dma_dw_set_obj()149 …_cyhal_dma_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num… in _cyhal_dma_dw_free_obj()155 return _cyhal_dma_dw_config_structs[block * CPUSS_DW0_CH_NR + channel]; in _cyhal_dma_dw_get_obj()165 #if (CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ != CPUSS_DW0_CH_NR) in _cyhal_dma_dw_get_block_from_irqn()167 …pe)(_CYHAL_DMA_GET_CPUSS_IRQN(0, CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ) + CPUSS_DW0_CH_NR - CYHAL_DMA_D… in _cyhal_dma_dw_get_block_from_irqn()191 #if (CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ != CPUSS_DW0_CH_NR) in _cyhal_dma_dw_get_channel_from_irqn()193 …pe)(_CYHAL_DMA_GET_CPUSS_IRQN(0, CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ) + CPUSS_DW0_CH_NR - CYHAL_DMA_D… in _cyhal_dma_dw_get_channel_from_irqn()[all …]
154 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)158 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR)160 #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR)746 CPUSS_DW0_CH_NR,
1387 #define CPUSS_DW0_CH_NR 30u macro
1729 #define CPUSS_DW0_CH_NR 16u macro
1420 #define CPUSS_DW0_CH_NR 29u macro
1894 #define CPUSS_DW0_CH_NR 29u macro
