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Searched refs:event (Results 1 – 25 of 44) sorted by relevance

12

/hal_infineon-2.7.6/XMCLib/drivers/src/
Dxmc1_scu.c295 __STATIC_INLINE bool XMC_SCU_INTERRUPT_IsValidEvent(XMC_SCU_INTERRUPT_EVENT_t event) in XMC_SCU_INTERRUPT_IsValidEvent() argument
297 return ((event == XMC_SCU_INTERRUPT_EVENT_WDT_WARN) || in XMC_SCU_INTERRUPT_IsValidEvent()
298 (event == XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC) || in XMC_SCU_INTERRUPT_IsValidEvent()
299 (event == XMC_SCU_INTERRUPT_EVENT_RTC_ALARM) || in XMC_SCU_INTERRUPT_IsValidEvent()
300 (event == XMC_SCU_INTERRUPT_EVENT_VDDPI) || in XMC_SCU_INTERRUPT_IsValidEvent()
302 (event == XMC_SCU_INTERRUPT_EVENT_PEUSIC1) || in XMC_SCU_INTERRUPT_IsValidEvent()
305 (event == XMC_SCU_INTERRUPT_EVENT_PEMCAN) || in XMC_SCU_INTERRUPT_IsValidEvent()
308 (event == XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK) || in XMC_SCU_INTERRUPT_IsValidEvent()
309 (event == XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC) || in XMC_SCU_INTERRUPT_IsValidEvent()
312 (event == XMC_SCU_INTERRUPT_EVENT_ACMP0) || in XMC_SCU_INTERRUPT_IsValidEvent()
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Dxmc_sdmmc.c225 void XMC_SDMMC_EnableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event) in XMC_SDMMC_EnableEventStatus() argument
230 sdmmc->EN_INT_STATUS_NORM |= (uint16_t)event; in XMC_SDMMC_EnableEventStatus()
231 sdmmc->EN_INT_STATUS_ERR |= (uint16_t)(event >> 16U); in XMC_SDMMC_EnableEventStatus()
235 void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event) in XMC_SDMMC_DisableEventStatus() argument
240 sdmmc->EN_INT_STATUS_NORM &= (uint16_t)~event; in XMC_SDMMC_DisableEventStatus()
241 sdmmc->EN_INT_STATUS_ERR &= (uint16_t)~(event >> 16U); in XMC_SDMMC_DisableEventStatus()
245 void XMC_SDMMC_EnableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) in XMC_SDMMC_EnableEvent() argument
249 XMC_SDMMC_EnableEventStatus(sdmmc, event); in XMC_SDMMC_EnableEvent()
251 sdmmc->EN_INT_SIGNAL_NORM |= (uint16_t)event; in XMC_SDMMC_EnableEvent()
252 sdmmc->EN_INT_SIGNAL_ERR |= (uint16_t)(event >> 16U); in XMC_SDMMC_EnableEvent()
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Dxmc4_scu.c226 void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event) in XMC_SCU_INTERRUPT_EnableEvent() argument
228 SCU_INTERRUPT->SRMSK |= (uint32_t)event; in XMC_SCU_INTERRUPT_EnableEvent()
232 void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event) in XMC_SCU_INTERRUPT_DisableEvent() argument
234 SCU_INTERRUPT->SRMSK &= (uint32_t)~event; in XMC_SCU_INTERRUPT_DisableEvent()
238 void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event) in XMC_SCU_INTERRUPT_TriggerEvent() argument
240 SCU_INTERRUPT->SRSET |= (uint32_t)event; in XMC_SCU_INTERRUPT_TriggerEvent()
250 void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event) in XMC_SCU_INTERRUPT_ClearEventStatus() argument
252 SCU_INTERRUPT->SRCLR = (uint32_t)event; in XMC_SCU_INTERRUPT_ClearEventStatus()
1268 void XMC_SCU_HIB_ClearEventStatus(int32_t event) in XMC_SCU_HIB_ClearEventStatus() argument
1274 SCU_HIBERNATE->HDCLR = event; in XMC_SCU_HIB_ClearEventStatus()
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Dxmc4_rtc.c141 void XMC_RTC_EnableEvent(const uint32_t event) in XMC_RTC_EnableEvent() argument
147 RTC->MSKSR |= event; in XMC_RTC_EnableEvent()
153 void XMC_RTC_DisableEvent(const uint32_t event) in XMC_RTC_DisableEvent() argument
159 RTC->MSKSR &= ~event; in XMC_RTC_DisableEvent()
165 void XMC_RTC_ClearEvent(const uint32_t event) in XMC_RTC_ClearEvent() argument
171 RTC->CLRSR = event; in XMC_RTC_ClearEvent()
174 void XMC_RTC_EnableHibernationWakeUp(const uint32_t event) in XMC_RTC_EnableHibernationWakeUp() argument
180 RTC->CTR |= event; in XMC_RTC_EnableHibernationWakeUp()
183 void XMC_RTC_DisableHibernationWakeUp(const uint32_t event) in XMC_RTC_DisableHibernationWakeUp() argument
189 RTC->CTR &= ~event; in XMC_RTC_DisableHibernationWakeUp()
Dxmc_ccu4.c407 const XMC_CCU4_SLICE_EVENT_t event, in XMC_CCU4_SLICE_StartConfig() argument
414 XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); in XMC_CCU4_SLICE_StartConfig()
421 cmc |= ((uint32_t) event) << CCU4_CC4_CMC_STRTS_Pos; in XMC_CCU4_SLICE_StartConfig()
441 const XMC_CCU4_SLICE_EVENT_t event, in XMC_CCU4_SLICE_StopConfig() argument
448 XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); in XMC_CCU4_SLICE_StopConfig()
454 cmc |= ((uint32_t) event) << CCU4_CC4_CMC_ENDS_Pos; in XMC_CCU4_SLICE_StopConfig()
467 void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) in XMC_CCU4_SLICE_LoadConfig() argument
472 XMC_ASSERT("XMC_CCU4_SLICE_LoadConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); in XMC_CCU4_SLICE_LoadConfig()
477 cmc |= ((uint32_t) event) << CCU4_CC4_CMC_LDS_Pos; in XMC_CCU4_SLICE_LoadConfig()
484 const XMC_CCU4_SLICE_EVENT_t event, in XMC_CCU4_SLICE_ModulationConfig() argument
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Dxmc_dma.c489 void XMC_DMA_CH_EnableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) in XMC_DMA_CH_EnableEvent() argument
495 if (event & ((uint32_t)0x1UL << event_idx)) in XMC_DMA_CH_EnableEvent()
503 void XMC_DMA_CH_DisableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) in XMC_DMA_CH_DisableEvent() argument
509 if (event & ((uint32_t)0x1UL << event_idx)) in XMC_DMA_CH_DisableEvent()
517 void XMC_DMA_CH_ClearEventStatus(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event) in XMC_DMA_CH_ClearEventStatus() argument
523 if (event & (uint32_t)((uint32_t)0x1UL << event_idx)) in XMC_DMA_CH_ClearEventStatus()
673 uint32_t event; in XMC_DMA_IRQHandler() local
692 event = XMC_DMA_GetEventStatus(dma); in XMC_DMA_IRQHandler()
695 if ((event & (uint32_t)XMC_DMA_CH_EVENT_ERROR) != (uint32_t)0UL) in XMC_DMA_IRQHandler()
697 event = XMC_DMA_GetChannelsErrorStatus(dma); in XMC_DMA_IRQHandler()
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Dxmc_ccu8.c419 const XMC_CCU8_SLICE_EVENT_t event, in XMC_CCU8_SLICE_StartConfig() argument
426 XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); in XMC_CCU8_SLICE_StartConfig()
433 cmc |= ((uint32_t) event) << CCU8_CC8_CMC_STRTS_Pos; in XMC_CCU8_SLICE_StartConfig()
453 const XMC_CCU8_SLICE_EVENT_t event, in XMC_CCU8_SLICE_StopConfig() argument
460 XMC_ASSERT("XMC_CCU8_SLICE_StopConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); in XMC_CCU8_SLICE_StopConfig()
466 cmc |= ((uint32_t) event) << CCU8_CC8_CMC_ENDS_Pos; in XMC_CCU8_SLICE_StopConfig()
479 void XMC_CCU8_SLICE_LoadConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event) in XMC_CCU8_SLICE_LoadConfig() argument
484 XMC_ASSERT("XMC_CCU8_SLICE_LoadConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); in XMC_CCU8_SLICE_LoadConfig()
490 cmc |= ((uint32_t) event) << CCU8_CC8_CMC_LDS_Pos; in XMC_CCU8_SLICE_LoadConfig()
514 const XMC_CCU8_SLICE_EVENT_t event, in XMC_CCU8_SLICE_ModulationConfig() argument
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Dxmc1_rtc.c131 void XMC_RTC_EnableEvent(const uint32_t event) in XMC_RTC_EnableEvent() argument
133 RTC->MSKSR |= event; in XMC_RTC_EnableEvent()
139 void XMC_RTC_DisableEvent(const uint32_t event) in XMC_RTC_DisableEvent() argument
141 RTC->MSKSR &= ~event; in XMC_RTC_DisableEvent()
147 void XMC_RTC_ClearEvent(const uint32_t event) in XMC_RTC_ClearEvent() argument
149 RTC->CLRSR = event; in XMC_RTC_ClearEvent()
Dxmc_eth_mac.c188 __STATIC_INLINE bool XCM_ETH_MAC_IsNormalEvent(uint32_t event) in XCM_ETH_MAC_IsNormalEvent() argument
190 return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT | in XCM_ETH_MAC_IsNormalEvent()
197 __STATIC_INLINE bool XCM_ETH_MAC_IsAbnormalEvent(uint32_t event) in XCM_ETH_MAC_IsAbnormalEvent() argument
199 return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED | in XCM_ETH_MAC_IsAbnormalEvent()
681 void XMC_ETH_MAC_EnableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) in XMC_ETH_MAC_EnableEvent() argument
685 eth_mac->regs->INTERRUPT_MASK &= ~(event >> 16U); in XMC_ETH_MAC_EnableEvent()
687 event &= (uint16_t)0x7fffU; in XMC_ETH_MAC_EnableEvent()
688 if (XCM_ETH_MAC_IsNormalEvent(event)) in XMC_ETH_MAC_EnableEvent()
690 event |= (uint32_t)ETH_INTERRUPT_ENABLE_NIE_Msk; in XMC_ETH_MAC_EnableEvent()
693 if (XCM_ETH_MAC_IsAbnormalEvent(event)) in XMC_ETH_MAC_EnableEvent()
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Dxmc_uart.c246 void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_UART_CH_EnableEvent() argument
248 channel->CCR |= (event&0x1fc00U); in XMC_UART_CH_EnableEvent()
249 channel->PCR_ASCMode |= (event&0xf8U); in XMC_UART_CH_EnableEvent()
252 void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_UART_CH_DisableEvent() argument
254 channel->CCR &= (uint32_t)~(event&0x1fc00U); in XMC_UART_CH_DisableEvent()
255 channel->PCR_ASCMode &= (uint32_t)~(event&0xf8U); in XMC_UART_CH_DisableEvent()
Dxmc_i2s.c291 void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_I2S_CH_EnableEvent() argument
293 channel->CCR |= (event&0x1fc00U); in XMC_I2S_CH_EnableEvent()
294 channel->PCR_IISMode |= ((event >> 2U) & 0x8070U); in XMC_I2S_CH_EnableEvent()
297 void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_I2S_CH_DisableEvent() argument
299 channel->CCR &= (uint32_t)~(event&0x1fc00U); in XMC_I2S_CH_DisableEvent()
300 channel->PCR_IISMode &= (uint32_t)~((event >> 2U) & 0x8070U); in XMC_I2S_CH_DisableEvent()
Dxmc_spi.c307 void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_SPI_CH_EnableEvent() argument
309 channel->CCR |= (event&0x1fc00U); in XMC_SPI_CH_EnableEvent()
310 channel->PCR_SSCMode |= ((event << 13U) & 0xe000U); in XMC_SPI_CH_EnableEvent()
313 void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_SPI_CH_DisableEvent() argument
315 channel->CCR &= (uint32_t)~(event&0x1fc00U); in XMC_SPI_CH_DisableEvent()
316 channel->PCR_SSCMode &= (uint32_t)~((event << 13U) & 0xe000U); in XMC_SPI_CH_DisableEvent()
Dxmc_i2c.c440 void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_I2C_CH_EnableEvent() argument
442 channel->CCR |= (event&0x1fc00U); in XMC_I2C_CH_EnableEvent()
443 channel->PCR_IICMode |= ((event) & 0x41fc0000U); in XMC_I2C_CH_EnableEvent()
446 void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_I2C_CH_DisableEvent() argument
448 channel->CCR &= (uint32_t)~(event&0x1fc00U); in XMC_I2C_CH_DisableEvent()
449 channel->PCR_IICMode &= (uint32_t)~((event) & 0x41fc0000U); in XMC_I2C_CH_DisableEvent()
Dxmc_ecat.c123 void XMC_ECAT_EnableEvent(uint32_t event) in XMC_ECAT_EnableEvent() argument
125 ECAT0->AL_EVENT_MASK |= event; in XMC_ECAT_EnableEvent()
128 void XMC_ECAT_DisableEvent(uint32_t event) in XMC_ECAT_DisableEvent() argument
130 ECAT0->AL_EVENT_MASK &= ~event; in XMC_ECAT_DisableEvent()
Dxmc_posif.c262 void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event, c… in XMC_POSIF_SetInterruptNode() argument
267 XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong IRQ event", (event <= XMC_POSIF_IRQ_EVENT_PCLK) ); in XMC_POSIF_SetInterruptNode()
271 reg &= ~((uint32_t)1 << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos)); in XMC_POSIF_SetInterruptNode()
272 reg |= (uint32_t)sr << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos); in XMC_POSIF_SetInterruptNode()
/hal_infineon-2.7.6/XMCLib/drivers/inc/
Dxmc_ccu4.h1083 const XMC_CCU4_SLICE_EVENT_t event,
1102 const XMC_CCU4_SLICE_EVENT_t event,
1120 void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1143 const XMC_CCU4_SLICE_EVENT_t event,
1162 void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1178 void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1194 …d XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1210 …d XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1289 … XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1369 const XMC_CCU4_SLICE_EVENT_t event,
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Dxmc_ccu8.h1565 const XMC_CCU8_SLICE_EVENT_t event,
1584 const XMC_CCU8_SLICE_EVENT_t event,
1604 void XMC_CCU8_SLICE_LoadConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event);
1644 const XMC_CCU8_SLICE_EVENT_t event,
1665 void XMC_CCU8_SLICE_CountConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event);
1681 void XMC_CCU8_SLICE_GateConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event);
1697 …d XMC_CCU8_SLICE_Capture0Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event);
1713 …d XMC_CCU8_SLICE_Capture1Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event);
1791 … XMC_CCU8_SLICE_DirectionConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event);
1871 const XMC_CCU8_SLICE_EVENT_t event,
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Dxmc_math.h338 bool XMC_MATH_GetEventStatus(const XMC_MATH_EVENT_t event);
355 __STATIC_INLINE void XMC_MATH_EnableEvent(const XMC_MATH_EVENT_t event) in XMC_MATH_EnableEvent() argument
357 MATH->EVIER |= (uint32_t) event; in XMC_MATH_EnableEvent()
375 __STATIC_INLINE void XMC_MATH_DisableEvent(const XMC_MATH_EVENT_t event) in XMC_MATH_DisableEvent() argument
377 MATH->EVIER &= ~((uint32_t) event); in XMC_MATH_DisableEvent()
395 __STATIC_INLINE void XMC_MATH_SetEvent(const XMC_MATH_EVENT_t event) in XMC_MATH_SetEvent() argument
397 MATH->EVFSR |= (uint32_t) event; in XMC_MATH_SetEvent()
415 __STATIC_INLINE void XMC_MATH_ClearEvent(const XMC_MATH_EVENT_t event) in XMC_MATH_ClearEvent() argument
417 MATH->EVFCR |= (uint32_t) event; in XMC_MATH_ClearEvent()
Dxmc_posif.h940 …INLINE void XMC_POSIF_EnableEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) in XMC_POSIF_EnableEvent() argument
942 peripheral->PFLGE |= (uint32_t)1 << (uint8_t)event; in XMC_POSIF_EnableEvent()
958 …NLINE void XMC_POSIF_DisableEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) in XMC_POSIF_DisableEvent() argument
960 peripheral->PFLGE &= ~((uint32_t)1 << (uint8_t)event); in XMC_POSIF_DisableEvent()
975 …IC_INLINE void XMC_POSIF_SetEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) in XMC_POSIF_SetEvent() argument
977 peripheral->SPFLG = (uint32_t)1 << (uint8_t)event; in XMC_POSIF_SetEvent()
992 …_INLINE void XMC_POSIF_ClearEvent(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) in XMC_POSIF_ClearEvent() argument
994 peripheral->RPFLG = (uint32_t)1 << (uint8_t)event; in XMC_POSIF_ClearEvent()
1009 … uint8_t XMC_POSIF_GetEventStatus(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event) in XMC_POSIF_GetEventStatus() argument
1011 return ((uint8_t)((peripheral->PFLG >> (uint8_t)event) & 1U)); in XMC_POSIF_GetEventStatus()
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Dxmc_fce.h380 __STATIC_INLINE void XMC_FCE_EnableEvent(const XMC_FCE_t *const engine, uint32_t event) in XMC_FCE_EnableEvent() argument
382 engine->kernel_ptr->CFG |= (uint32_t)event; in XMC_FCE_EnableEvent()
396 __STATIC_INLINE void XMC_FCE_DisableEvent(const XMC_FCE_t *const engine, uint32_t event) in XMC_FCE_DisableEvent() argument
398 engine->kernel_ptr->CFG &= ~(uint32_t)event; in XMC_FCE_DisableEvent()
413 __STATIC_INLINE bool XMC_FCE_GetEventStatus(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event) in XMC_FCE_GetEventStatus() argument
415 return (bool) (engine->kernel_ptr->STS & (uint32_t)event); in XMC_FCE_GetEventStatus()
430 __STATIC_INLINE void XMC_FCE_ClearEvent(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event) in XMC_FCE_ClearEvent() argument
432 engine->kernel_ptr->STS |= (uint32_t)event; in XMC_FCE_ClearEvent()
Dxmc_scu.h307 void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
323 void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
339 void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
372 void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event);
568 XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, const XMC…
Dxmc_usic.h1194 __STATIC_INLINE void XMC_USIC_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_USIC_CH_EnableEvent() argument
1196 channel->CCR |= event; in XMC_USIC_CH_EnableEvent()
1215 __STATIC_INLINE void XMC_USIC_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_USIC_CH_DisableEvent() argument
1217 channel->CCR &= (uint32_t)~event; in XMC_USIC_CH_DisableEvent()
1539 …ATIC_INLINE void XMC_USIC_CH_TXFIFO_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_USIC_CH_TXFIFO_EnableEvent() argument
1541 channel->TBCTR |= event; in XMC_USIC_CH_TXFIFO_EnableEvent()
1561 …TIC_INLINE void XMC_USIC_CH_TXFIFO_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) in XMC_USIC_CH_TXFIFO_DisableEvent() argument
1563 channel->TBCTR &= (uint32_t)~event; in XMC_USIC_CH_TXFIFO_DisableEvent()
1779 const uint32_t event) in XMC_USIC_CH_TXFIFO_ClearEvent() argument
1781 channel->TRBSCR = event; in XMC_USIC_CH_TXFIFO_ClearEvent()
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Dxmc_sdmmc.h706 void XMC_SDMMC_EnableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event);
726 void XMC_SDMMC_DisableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event);
742 void XMC_SDMMC_ClearEvent(XMC_SDMMC_t *const sdmmc, uint32_t event);
756 bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event);
771 void XMC_SDMMC_EnableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event);
786 void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event);
807 __STATIC_INLINE void XMC_SDMMC_TriggerEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) in XMC_SDMMC_TriggerEvent() argument
811 sdmmc->FORCE_EVENT_ERR_STATUS |= (uint16_t)(event >> 16U); in XMC_SDMMC_TriggerEvent()
937 __STATIC_INLINE void XMC_SDMMC_EnableWakeupEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) in XMC_SDMMC_EnableWakeupEvent() argument
941 sdmmc->WAKEUP_CTRL |= (uint8_t)event; in XMC_SDMMC_EnableWakeupEvent()
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Dxmc_usbd.h314 typedef void (*XMC_USBD_SignalDeviceEvent_t) (XMC_USBD_EVENT_t event);/**< Pointer to USB device …
542 void XMC_USBD_ClearEvent(XMC_USBD_EVENT_t event);
564 void XMC_USBD_ClearEventINEP(uint32_t event,uint8_t ep_num);
586 void XMC_USBD_ClearEventOUTEP(uint32_t event,uint8_t ep_num);
604 void XMC_USBD_EnableEventOUTEP(uint32_t event);
622 void XMC_USBD_EnableEventINEP(uint32_t event);
Dxmc_hrpwm.h2033 void XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_IRQ_ID_t event,
2227 …TIC_INLINE void XMC_HRPWM_CSG_EnableEvent(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) in XMC_HRPWM_CSG_EnableEvent() argument
2230 csg->SRE |= event; in XMC_HRPWM_CSG_EnableEvent()
2250 …IC_INLINE void XMC_HRPWM_CSG_DisableEvent(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) in XMC_HRPWM_CSG_DisableEvent() argument
2253 csg->SRE &= ~event; in XMC_HRPWM_CSG_DisableEvent()
2274 …ATIC_INLINE void XMC_HRPWM_CSG_SetEventSW(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) in XMC_HRPWM_CSG_SetEventSW() argument
2277 csg->SWS = event; in XMC_HRPWM_CSG_SetEventSW()
2297 …ATIC_INLINE void XMC_HRPWM_CSG_ClrEventSW(XMC_HRPWM_CSG_t *const csg, XMC_HRPWM_CSG_IRQ_ID_t event) in XMC_HRPWM_CSG_ClrEventSW() argument
2300 csg->SWC = event; in XMC_HRPWM_CSG_ClrEventSW()

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