1 /**
2 * @file xmc4_scu.h
3 * @date 2019-02-18
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-06-20:
40 * - Initial version
41 * - Documentation improved
42 *
43 * 2015-11-30:
44 * - Documentation improved
45 *
46 * 2016-03-09:
47 * - Added XMC_SCU_POWER_EnableMonitor/XMC_SCU_POWER_DisableMonitor
48 * XMC_SCU_POWER_GetEVRStatus, XMC_SCU_POWER_GetEVR13Voltage, XMC_SCU_POWER_GetEVR33Voltage
49 * - Added XMC_SCU_HIB_GetHibernateControlStatus,
50 * XMC_SCU_HIB_GetEventStatus, XMC_SCU_HIB_ClearEventStatus, XMC_SCU_HIB_TriggerEvent,
51 * XMC_SCU_HIB_EnableEvent, XMC_SCU_HIB_DisableEvent
52 * - Added XMC_SCU_HIB_SetWakeupTriggerInput, XMC_SCU_HIB_SetPinMode, XMC_SCU_HIB_SetOutputPinLevel,
53 * XMC_SCU_HIB_SetInput0, XMC_SCU_HIB_EnterHibernateState
54 *
55 * 2016-04-15:
56 * - Fixed naming of XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG peripheral clock.
57 * Added enable and disable for peripheral clocks
58 *
59 * 2016-05-19:
60 * - Added XMC_SCU_CLOCK_IsLowPowerOscillatorStable() and XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable()
61 * - Added XMC_SCU_POWER_WaitForInterrupt() and XMC_SCU_POWER_WaitForEvent()
62 * - Added XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(),
63 * XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(),
64 * XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus()
65 * - Added XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(),
66 * XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(),
67 * XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus()
68 * - Removed XMC_SCU_INTERRUPT_EVENT_OSCULSTAT_UPDATED, XMC_SCU_INTERRUPT_EVENT_HDSTAT_UPDATED
69 *
70 * 2016-06-14:
71 * - Added XMC_SCU_HIB_IsWakeupEventDetected() and XMC_SCU_HIB_ClearWakeupEventDetectionStatus()
72 *
73 * 2016-06-15:
74 * - Added XMC_SCU_HIB_EnterHibernateStateEx() which allows to select between external or internal hibernate mode. This last mode only available in XMC44, XMC42 and XMC41 series.
75 * - Extended wakeup hibernate events using LPAC wakeup on events. Only available in XMC44, XMC42 and XMC41 series.
76 * - Added LPAC APIs. Only available in XMC44, XMC42 and XMC41 series.
77 *
78 * 2019-02-18:
79 * - Fix conditional definition of XMC_SCU_PARITY_t elements
80 * - Added XMC_SCU_PARITY_OverrideParityBitLogic(uint32_t memory)
81 * XMC_SCU_PARITY_SelectMemoryTest(const XMC_SCU_PARITY_t memory)
82 * XMC_SCU_PARITY_SetParityWriteValue(uint8_t val)
83 * XMC_SCU_PARITY_GetParityReadValue(void)
84 *
85 * @endcond
86 *
87 */
88
89 #ifndef XMC4_SCU_H
90 #define XMC4_SCU_H
91
92 /*********************************************************************************************************************
93 * HEADER FILES
94 ********************************************************************************************************************/
95
96 #include "xmc_common.h"
97
98 #if UC_FAMILY == XMC4
99
100 /**
101 * @addtogroup XMClib XMC Peripheral Library
102 * @{
103 */
104
105 /**
106 * @addtogroup SCU
107 * @{
108 */
109
110 /*********************************************************************************************************************
111 * MACROS
112 ********************************************************************************************************************/
113 #define PLL_PDIV_XTAL_8MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */
114 #define PLL_NDIV_XTAL_8MHZ (89U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */
115 #define PLL_K2DIV_XTAL_8MHZ (2U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 8MHz */
116
117 #define PLL_PDIV_XTAL_12MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */
118 #define PLL_NDIV_XTAL_12MHZ (79U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */
119 #define PLL_K2DIV_XTAL_12MHZ (3U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 12MHz */
120
121 #define PLL_PDIV_XTAL_16MHZ (1U) /* PDIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */
122 #define PLL_NDIV_XTAL_16MHZ (59U) /* NDIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */
123 #define PLL_K2DIV_XTAL_16MHZ (3U) /* K2DIV value for main PLL settings, fPLL = 120MHz with fOSC = 16MHz */
124
125 #define XMC_SCU_INTERRUPT_EVENT_WDT_WARN SCU_INTERRUPT_SRSTAT_PRWARN_Msk /**< Watchdog prewarning event. */
126 #define XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC SCU_INTERRUPT_SRSTAT_PI_Msk /**< RTC periodic interrupt. */
127 #define XMC_SCU_INTERRUPT_EVENT_RTC_ALARM SCU_INTERRUPT_SRSTAT_AI_Msk /**< RTC alarm event. */
128 #define XMC_SCU_INTERRUPT_EVENT_DLR_OVERRUN SCU_INTERRUPT_SRSTAT_DLROVR_Msk /**< DLR overrun event. */
129 #if defined(SCU_INTERRUPT_SRSTAT_LPACCR_Msk)
130 #define XMC_SCU_INTERRUPT_EVENT_LPACCR_UPDATED SCU_INTERRUPT_SRSTAT_LPACCR_Msk /**< LPAC Control register update event. */
131 #endif
132 #if defined(SCU_INTERRUPT_SRSTAT_LPACTH0_Msk)
133 #define XMC_SCU_INTERRUPT_EVENT_LPACTH0_UPDATED SCU_INTERRUPT_SRSTAT_LPACTH0_Msk /**< LPAC Threshold-0 register update event. */
134 #endif
135 #if defined(SCU_INTERRUPT_SRSTAT_LPACTH1_Msk)
136 #define XMC_SCU_INTERRUPT_EVENT_LPACTH1_UPDATED SCU_INTERRUPT_SRSTAT_LPACTH1_Msk /**< LPAC Threshold-1 register update event. */
137 #endif
138 #if defined(SCU_INTERRUPT_SRSTAT_LPACST_Msk)
139 #define XMC_SCU_INTERRUPT_EVENT_LPACST_UPDATED SCU_INTERRUPT_SRSTAT_LPACST_Msk /**< LPAC Status register update event. */
140 #endif
141 #if defined(SCU_INTERRUPT_SRSTAT_LPACCLR_Msk)
142 #define XMC_SCU_INTERRUPT_EVENT_LPACCLR_UPDATED SCU_INTERRUPT_SRSTAT_LPACCLR_Msk /**< LPAC event clear register update event. */
143 #endif
144 #if defined(SCU_INTERRUPT_SRSTAT_LPACSET_Msk)
145 #define XMC_SCU_INTERRUPT_EVENT_LPACSET_UPDATED SCU_INTERRUPT_SRSTAT_LPACSET_Msk /**< LPAC event set register update event. */
146 #endif
147 #if defined(SCU_INTERRUPT_SRSTAT_HINTST_Msk)
148 #define XMC_SCU_INTERRUPT_EVENT_HINTST_UPDATED SCU_INTERRUPT_SRSTAT_HINTST_Msk /**< HIB HINTST register update event. */
149 #endif
150 #if defined(SCU_INTERRUPT_SRSTAT_HINTCLR_Msk)
151 #define XMC_SCU_INTERRUPT_EVENT_HINTCLR_UPDATED SCU_INTERRUPT_SRSTAT_HINTCLR_Msk /**< HIB HINTCLR register update event. */
152 #endif
153 #if defined(SCU_INTERRUPT_SRSTAT_HINTSET_Msk)
154 #define XMC_SCU_INTERRUPT_EVENT_HINTSET_UPDATED SCU_INTERRUPT_SRSTAT_HINTSET_Msk /**< HIB HINTSET register update event. */
155 #endif
156 #define XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED SCU_INTERRUPT_SRSTAT_HDCLR_Msk /**< HIB HDCLR register update event. */
157 #define XMC_SCU_INTERRUPT_EVENT_HDSET_UPDATED SCU_INTERRUPT_SRSTAT_HDSET_Msk /**< HIB HDSET register update event. */
158 #define XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED SCU_INTERRUPT_SRSTAT_HDCR_Msk /**< HIB HDCR register update event. */
159 #define XMC_SCU_INTERRUPT_EVENT_OSCSICTRL_UPDATED SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk /**< HIB OSCSICTRL register update event. */
160 #define XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk /**< HIB OSCULCTRL register update event. */
161 #define XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk /**< HIB RTCCTR register update event. */
162 #define XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk /**< HIB RTCATIM0 register update event. */
163 #define XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk /**< HIB RTCATIM1 register update event. */
164 #define XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk /**< HIB TIM0 register update event. */
165 #define XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk /**< HIB TIM1 register update event. */
166 #define XMC_SCU_INTERRUPT_EVENT_RMX_UPDATED SCU_INTERRUPT_SRSTAT_RMX_Msk /**< HIB RMX register update event. */
167
168 /*********************************************************************************************************************
169 * ENUMS
170 ********************************************************************************************************************/
171 /**
172 * Defines Capture/Compare unit timer slice trigger, that enables synchronous start function available on the \a SCU,
173 * CCUCON register. Use type \a XMC_SCU_CCU_TRIGGER_t for accessing these enum parameters.
174 */
175 typedef enum XMC_SCU_CCU_TRIGGER
176 {
177 #if defined(CCU40)
178 XMC_SCU_CCU_TRIGGER_CCU40 = SCU_GENERAL_CCUCON_GSC40_Msk, /**< Trigger mask used for Global Start Control of
179 CCU40 peripheral. */
180 #endif
181 #if defined(CCU41)
182 XMC_SCU_CCU_TRIGGER_CCU41 = SCU_GENERAL_CCUCON_GSC41_Msk, /**< Trigger mask used for Global Start Control of
183 CCU41 peripheral. */
184 #endif
185 #if defined(CCU42)
186 XMC_SCU_CCU_TRIGGER_CCU42 = SCU_GENERAL_CCUCON_GSC42_Msk, /**< Trigger mask used for Global Start Control of
187 CCU42 peripheral. */
188 #endif
189 #if defined(CCU43)
190 XMC_SCU_CCU_TRIGGER_CCU43 = SCU_GENERAL_CCUCON_GSC43_Msk, /**< Trigger mask used for Global Start Control of
191 CCU43 peripheral. */
192 #endif
193 #if defined(CCU80)
194 XMC_SCU_CCU_TRIGGER_CCU80 = SCU_GENERAL_CCUCON_GSC80_Msk, /**< Trigger mask used for Global Start Control of
195 CCU80 peripheral. */
196 #endif
197 #if defined(CCU81)
198 XMC_SCU_CCU_TRIGGER_CCU81 = SCU_GENERAL_CCUCON_GSC81_Msk /**< Trigger mask used for Global Start Control of
199 CCU81 peripheral. */
200 #endif
201 } XMC_SCU_CCU_TRIGGER_t;
202
203 /**
204 * Defines enumerations representing the status of trap cause. The cause of the trap gets automatically stored in
205 * the \a TRAPSTAT register and can be checked by user software to determine the state of the system and for debug
206 * purpose.
207 * Use type \a XMC_SCU_TRAP_t for accessing these enum parameters.
208 */
209 typedef enum XMC_SCU_TRAP
210 {
211 XMC_SCU_TRAP_OSC_WDG = SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk, /**< OSC_HP Oscillator Watchdog trap. */
212 XMC_SCU_TRAP_VCO_LOCK = SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk, /**< PLL loss of lock trap. */
213 XMC_SCU_TRAP_USB_VCO_LOCK = SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk, /**< USB PLL loss of lock trap. */
214 XMC_SCU_TRAP_PARITY_ERROR = SCU_TRAP_TRAPSTAT_PET_Msk, /**< Memory Parity error trap. */
215 XMC_SCU_TRAP_BROWNOUT = SCU_TRAP_TRAPSTAT_BRWNT_Msk, /**< Brownout trap. */
216 XMC_SCU_TRAP_ULP_WDG = SCU_TRAP_TRAPSTAT_ULPWDGT_Msk, /**< Unstable 32KHz clock trap. */
217 XMC_SCU_TRAP_PER_BRIDGE0 = SCU_TRAP_TRAPSTAT_BWERR0T_Msk, /**< Bad memory access of peripherals on Bridge-0. */
218 XMC_SCU_TRAP_PER_BRIDGE1 = SCU_TRAP_TRAPSTAT_BWERR1T_Msk, /**< Bad memory access of peripherals on Bridge-1. */
219 #if defined(SCU_TRAP_TRAPSTAT_TEMPHIT_Msk)
220 XMC_SCU_TRAP_DIETEMP_HIGH = SCU_TRAP_TRAPSTAT_TEMPHIT_Msk, /**< Die temperature higher than expected. */
221 #endif
222 #if defined(SCU_TRAP_TRAPSTAT_TEMPLOT_Msk)
223 XMC_SCU_TRAP_DIETEMP_LOW = SCU_TRAP_TRAPSTAT_TEMPLOT_Msk, /**< Die temperature lower than expected. */
224 #endif
225 #if defined(ECAT0)
226 XMC_SCU_TRAP_ECAT_RESET = SCU_TRAP_TRAPSTAT_ECAT0RST_Msk, /**< EtherCat Reset */
227 #endif
228 } XMC_SCU_TRAP_t;
229
230 /**
231 * Defines enumerations for different parity event generating modules that in turn generate a trap.
232 * Parity can be enabled with \a PETE register in order to get the trap flag reflected in \a TRAPRAW register. These enums are used to
233 * configure parity error trap generation mechanism bits of \a PETE register.
234 * All the enum items are tabulated as per bits present in \a PETE register.
235 * Use type \a XMC_SCU_PARITY_t for accessing these enum parameters.
236 */
237 typedef enum XMC_SCU_PARITY
238 {
239 XMC_SCU_PARITY_PSRAM_MEM = SCU_PARITY_PEEN_PEENPS_Msk, /**< Program SRAM parity error trap. */
240 XMC_SCU_PARITY_DSRAM1_MEM = SCU_PARITY_PEEN_PEENDS1_Msk, /**< Data SRAM-1 parity error trap. */
241 #if defined(SCU_PARITY_PEEN_PEENDS2_Msk)
242 XMC_SCU_PARITY_DSRAM2_MEM = SCU_PARITY_PEEN_PEENDS2_Msk, /**< Data SRAM-2 parity error trap. */
243 #endif
244 XMC_SCU_PARITY_USIC0_MEM = SCU_PARITY_PEEN_PEENU0_Msk, /**< USIC0 memory parity error trap. */
245 #if defined(SCU_PARITY_PEEN_PEENU1_Msk)
246 XMC_SCU_PARITY_USIC1_MEM = SCU_PARITY_PEEN_PEENU1_Msk, /**< USIC1 memory parity error trap. */
247 #endif
248 #if defined(SCU_PARITY_PEEN_PEENU2_Msk)
249 XMC_SCU_PARITY_USIC2_MEM = SCU_PARITY_PEEN_PEENU2_Msk, /**< USIC2 memory parity error trap. */
250 #endif
251 XMC_SCU_PARITY_MCAN_MEM = SCU_PARITY_PEEN_PEENMC_Msk, /**< CAN memory parity error trap. */
252 XMC_SCU_PARITY_PMU_MEM = SCU_PARITY_PEEN_PEENPPRF_Msk, /**< PMU Prefetch memory parity error trap. */
253 XMC_SCU_PARITY_USB_MEM = SCU_PARITY_PEEN_PEENUSB_Msk, /**< USB memory parity error trap. */
254 #if defined(SCU_PARITY_PEEN_PEENETH0TX_Msk)
255 XMC_SCU_PARITY_ETH_TXMEM = SCU_PARITY_PEEN_PEENETH0TX_Msk, /**< Ethernet transmit memory parity error trap. */
256 #endif
257 #if defined(SCU_PARITY_PEEN_PEENETH0RX_Msk)
258 XMC_SCU_PARITY_ETH_RXMEM = SCU_PARITY_PEEN_PEENETH0RX_Msk, /**< Ethernet receive memory parity error trap. */
259 #endif
260 #if defined(SCU_PARITY_PEEN_PEENSD0_Msk)
261 XMC_SCU_PARITY_SDMMC_MEM0 = SCU_PARITY_PEEN_PEENSD0_Msk, /**< SDMMC Memory-0 parity error trap. */
262 #endif
263 #if defined(SCU_PARITY_PEEN_PEENSD1_Msk)
264 XMC_SCU_PARITY_SDMMC_MEM1 = SCU_PARITY_PEEN_PEENSD1_Msk, /**< SDMMC Memory-1 parity error trap. */
265 #endif
266 #if defined(SCU_PARITY_PEEN_PEENECAT0_Msk)
267 XMC_SCU_PARITY_ECAT_MEM = SCU_PARITY_PEEN_PEENECAT0_Msk, /**< ECAT0 SRAM parity error trap. */
268 #endif
269 } XMC_SCU_PARITY_t;
270
271 /**
272 * Defines the different causes for last reset. The cause of the last reset gets automatically stored in
273 * the \a SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debuggging
274 * purpose. All the enum items are tabulated as per bits present in \a SCU_RSTSTAT register.
275 * Use type \a XMC_SCU_RESET_REASON_t for accessing these enum parameters.
276 */
277 typedef enum XMC_SCU_RESET_REASON
278 {
279 XMC_SCU_RESET_REASON_PORST = (1UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power on reset. */
280 XMC_SCU_RESET_REASON_SWD = (2UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Supply Watchdog reset. */
281 XMC_SCU_RESET_REASON_PV = (4UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power Validation reset. */
282 XMC_SCU_RESET_REASON_SW = (8UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Software reset. */
283 XMC_SCU_RESET_REASON_LOCKUP = (16UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to reset due to CPU lockup. */
284 XMC_SCU_RESET_REASON_WATCHDOG = (32UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Watchdog timer initiated reset. */
285 XMC_SCU_RESET_REASON_PARITY_ERROR = (128UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to reset due to memory parity error. */
286 } XMC_SCU_RESET_REASON_t;
287
288 /**
289 * Defines enumerations for events which can lead to interrupt. These enumeration values represent the
290 * status of one of the bits in \a SRSTAT register.
291 * Use type \a XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters.
292 */
293 typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t;
294
295
296 /**
297 * Defines enumeration for the events that can generate non maskable interrupt(NMI).
298 * The NMI generation can be enabled with \a NMIREQEN register. The event will be reflected in \a SRSTAT or will be
299 * mirrored in the TRAPSTAT register. These enums can be used to configure NMI request generation bits of \a
300 * NMIREQEN register. Once configured, these events can generate non maskable interrupt.
301 * All the enum items are tabulated as per bits present in \a NMIREQEN register.
302 * Use type \a XMC_SCU_NMIREQ_t for accessing these enum parameters.
303 */
304 typedef enum XMC_SCU_NMIREQ
305 {
306 XMC_SCU_NMIREQ_WDT_WARN = SCU_INTERRUPT_NMIREQEN_PRWARN_Msk, /**< Watchdog timer Pre-Warning event */
307 XMC_SCU_NMIREQ_RTC_PI = SCU_INTERRUPT_NMIREQEN_PI_Msk, /**< RTC Periodic event */
308 XMC_SCU_NMIREQ_RTC_AI = SCU_INTERRUPT_NMIREQEN_AI_Msk, /**< RTC Alarm event */
309 XMC_SCU_NMIREQ_ERU0_0 = SCU_INTERRUPT_NMIREQEN_ERU00_Msk, /**< Channel 0 event of ERU0 */
310 XMC_SCU_NMIREQ_ERU0_1 = SCU_INTERRUPT_NMIREQEN_ERU01_Msk, /**< Channel 1 event of ERU0 */
311 XMC_SCU_NMIREQ_ERU0_2 = SCU_INTERRUPT_NMIREQEN_ERU02_Msk, /**< Channel 2 event of ERU0 */
312 XMC_SCU_NMIREQ_ERU0_3 = SCU_INTERRUPT_NMIREQEN_ERU03_Msk /**< Channel 3 event of ERU0 */
313 } XMC_SCU_NMIREQ_t;
314
315
316 /**
317 * Defines enumeration representing different peripheral reset bits in the \a PRSTAT registers.
318 * All the enum items are tabulated as per bits present in \a PRSTAT0, \a PRSTAT1, \a PRSTAT2,
319 * \a PRSTAT3 registers. Use type \a XMC_SCU_PERIPHERAL_RESET_t for accessing these enum parameters.
320 * Note: Release of reset should be prevented when the peripheral clock is gated in cases where kernel
321 * clock and bus interface clocks are shared, in order to avoid system hang-up.
322 */
323 typedef enum XMC_SCU_PERIPHERAL_RESET
324 {
325 XMC_SCU_PERIPHERAL_RESET_VADC = SCU_RESET_PRSTAT0_VADCRS_Msk, /**< VADC reset. */
326 #if defined(DSD)
327 XMC_SCU_PERIPHERAL_RESET_DSD = SCU_RESET_PRSTAT0_DSDRS_Msk, /**< DSD reset. */
328 #endif
329 XMC_SCU_PERIPHERAL_RESET_CCU40 = SCU_RESET_PRSTAT0_CCU40RS_Msk, /**< CCU40 reset. */
330 #if defined(CCU41)
331 XMC_SCU_PERIPHERAL_RESET_CCU41 = SCU_RESET_PRSTAT0_CCU41RS_Msk, /**< CCU41 reset. */
332 #endif
333 #if defined(CCU42)
334 XMC_SCU_PERIPHERAL_RESET_CCU42 = SCU_RESET_PRSTAT0_CCU42RS_Msk, /**< CCU42 reset. */
335 #endif
336 #if defined(CCU80)
337 XMC_SCU_PERIPHERAL_RESET_CCU80 = SCU_RESET_PRSTAT0_CCU80RS_Msk, /**< CCU80 reset. */
338 #endif
339 #if defined(CCU81)
340 XMC_SCU_PERIPHERAL_RESET_CCU81 = SCU_RESET_PRSTAT0_CCU81RS_Msk, /**< CCU81 reset. */
341 #endif
342 #if defined(POSIF0)
343 XMC_SCU_PERIPHERAL_RESET_POSIF0 = SCU_RESET_PRSTAT0_POSIF0RS_Msk, /**< POSIF0 reset. */
344 #endif
345 #if defined(POSIF1)
346 XMC_SCU_PERIPHERAL_RESET_POSIF1 = SCU_RESET_PRSTAT0_POSIF1RS_Msk, /**< POSIF1 reset.*/
347 #endif
348 XMC_SCU_PERIPHERAL_RESET_USIC0 = SCU_RESET_PRSTAT0_USIC0RS_Msk, /**< USIC0 reset. */
349 XMC_SCU_PERIPHERAL_RESET_ERU1 = SCU_RESET_PRSTAT0_ERU1RS_Msk, /**< ERU1 reset. */
350 #if defined(HRPWM0)
351 XMC_SCU_PERIPHERAL_RESET_HRPWM0 = SCU_RESET_PRSTAT0_HRPWM0RS_Msk, /**< HRPWM0 reset. */
352 #endif
353 #if defined(CCU43)
354 XMC_SCU_PERIPHERAL_RESET_CCU43 = (SCU_RESET_PRSTAT1_CCU43RS_Msk | 0x10000000UL), /**< CCU43 reset. */
355 #endif
356 #if defined(LEDTS0)
357 XMC_SCU_PERIPHERAL_RESET_LEDTS0 = (SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk | 0x10000000UL), /**< LEDTS0 reset. */
358 #endif
359 #if defined(CAN)
360 XMC_SCU_PERIPHERAL_RESET_MCAN = (SCU_RESET_PRSTAT1_MCAN0RS_Msk | 0x10000000UL), /**< MCAN reset. */
361 #endif
362 #if defined(DAC)
363 XMC_SCU_PERIPHERAL_RESET_DAC = (SCU_RESET_PRSTAT1_DACRS_Msk | 0x10000000UL), /**< DAC reset. */
364 #endif
365 #if defined(SDMMC)
366 XMC_SCU_PERIPHERAL_RESET_SDMMC = (SCU_RESET_PRSTAT1_MMCIRS_Msk | 0x10000000UL), /**< SDMMC reset. */
367 #endif
368 #if defined(USIC1)
369 XMC_SCU_PERIPHERAL_RESET_USIC1 = (SCU_RESET_PRSTAT1_USIC1RS_Msk | 0x10000000UL), /**< USIC1 reset. */
370 #endif
371 #if defined(USIC2)
372 XMC_SCU_PERIPHERAL_RESET_USIC2 = (SCU_RESET_PRSTAT1_USIC2RS_Msk | 0x10000000UL), /**< USIC2 reset. */
373 #endif
374 XMC_SCU_PERIPHERAL_RESET_PORTS = (SCU_RESET_PRSTAT1_PPORTSRS_Msk | 0x10000000UL), /**< PORTS reset. */
375 XMC_SCU_PERIPHERAL_RESET_WDT = (SCU_RESET_PRSTAT2_WDTRS_Msk | 0x20000000UL), /**< WDT reset. */
376 #if defined(ETH0)
377 XMC_SCU_PERIPHERAL_RESET_ETH0 = (SCU_RESET_PRSTAT2_ETH0RS_Msk | 0x20000000UL), /**< ETH0 reset. */
378 #endif
379 XMC_SCU_PERIPHERAL_RESET_GPDMA0 = (SCU_RESET_PRSTAT2_DMA0RS_Msk | 0x20000000UL), /**< DMA0 reset. */
380 #if defined(GPDMA1)
381 XMC_SCU_PERIPHERAL_RESET_GPDMA1 = (SCU_RESET_PRSTAT2_DMA1RS_Msk | 0x20000000UL), /**< DMA1 reset. */
382 #endif
383 #if defined(FCE)
384 XMC_SCU_PERIPHERAL_RESET_FCE = (SCU_RESET_PRSTAT2_FCERS_Msk | 0x20000000UL), /**< FCE reset. */
385 #endif
386 #if defined(USB0)
387 XMC_SCU_PERIPHERAL_RESET_USB0 = (SCU_RESET_PRSTAT2_USBRS_Msk | 0x20000000UL), /**< USB0 reset. */
388 #endif
389 #if defined(ECAT0)
390 XMC_SCU_PERIPHERAL_RESET_ECAT0 = (SCU_RESET_PRSTAT2_ECAT0RS_Msk | 0x20000000UL), /**< ECAT0 reset. */
391 #endif
392 #if defined(EBU)
393 XMC_SCU_PERIPHERAL_RESET_EBU = (SCU_RESET_PRSTAT3_EBURS_Msk | 0x30000000UL) /**< EBU reset. */
394 #endif
395 } XMC_SCU_PERIPHERAL_RESET_t;
396
397 /**
398 * Defines enumerations for disabling the clocks sources of peripherals. Disabling of the peripheral
399 * clock is configured via the \a CLKCLR registers.
400 * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters.
401 */
402 typedef enum XMC_SCU_CLOCK
403 {
404 XMC_SCU_CLOCK_USB = SCU_CLK_CLKCLR_USBCDI_Msk, /**< USB module clock. */
405 #if defined(SDMMC)
406 XMC_SCU_CLOCK_MMC = SCU_CLK_CLKCLR_MMCCDI_Msk, /**< MMC module clock. */
407 #endif
408 #if defined(ETH0)
409 XMC_SCU_CLOCK_ETH = SCU_CLK_CLKCLR_ETH0CDI_Msk, /**< Ethernet module clock. */
410 #endif
411 #if defined(EBU)
412 XMC_SCU_CLOCK_EBU = SCU_CLK_CLKCLR_EBUCDI_Msk, /**< EBU module clock. */
413 #endif
414 XMC_SCU_CLOCK_CCU = SCU_CLK_CLKCLR_CCUCDI_Msk, /**< CCU module clock. */
415 XMC_SCU_CLOCK_WDT = SCU_CLK_CLKCLR_WDTCDI_Msk /**< WDT module clock. */
416 } XMC_SCU_CLOCK_t;
417
418 #if(UC_SERIES != XMC45)
419 /**
420 * Defines enumeration for peripherals that support clock gating.
421 * The enumerations can be used for gating or ungating the peripheral clocks.
422 * All the enum items are tabulated as per bits present in \a CGATSTAT0 register.
423 * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters.
424 */
425 typedef enum XMC_SCU_PERIPHERAL_CLOCK
426 {
427 XMC_SCU_PERIPHERAL_CLOCK_VADC = SCU_CLK_CGATSTAT0_VADC_Msk, /**< VADC peripheral gating. */
428 #if defined(DSD)
429 XMC_SCU_PERIPHERAL_CLOCK_DSD = SCU_CLK_CGATSTAT0_DSD_Msk, /**< DSD peripheral gating. */
430 #endif
431 XMC_SCU_PERIPHERAL_CLOCK_CCU40 = SCU_CLK_CGATSTAT0_CCU40_Msk, /**< CCU40 peripheral gating. */
432 #if defined(CCU41)
433 XMC_SCU_PERIPHERAL_CLOCK_CCU41 = SCU_CLK_CGATSTAT0_CCU41_Msk, /**< CCU41 peripheral gating. */
434 #endif
435 #if defined(CCU42)
436 XMC_SCU_PERIPHERAL_CLOCK_CCU42 = SCU_CLK_CGATSTAT0_CCU42_Msk, /**< CCU42 peripheral gating. */
437 #endif
438 #if defined(CCU80)
439 XMC_SCU_PERIPHERAL_CLOCK_CCU80 = SCU_CLK_CGATSTAT0_CCU80_Msk, /**< CCU80 peripheral gating. */
440 #endif
441 #if defined(CCU81)
442 XMC_SCU_PERIPHERAL_CLOCK_CCU81 = SCU_CLK_CGATSTAT0_CCU81_Msk, /**< CCU81 peripheral gating. */
443 #endif
444 #if defined(POSIF0)
445 XMC_SCU_PERIPHERAL_CLOCK_POSIF0 = SCU_CLK_CGATSTAT0_POSIF0_Msk, /**< POSIF0 peripheral gating. */
446 #endif
447 #if defined(POSIF1)
448 XMC_SCU_PERIPHERAL_CLOCK_POSIF1 = SCU_CLK_CGATSTAT0_POSIF1_Msk, /**< POSIF1 peripheral gating. */
449 #endif
450 XMC_SCU_PERIPHERAL_CLOCK_USIC0 = SCU_CLK_CGATSTAT0_USIC0_Msk, /**< USIC0 peripheral gating. */
451 XMC_SCU_PERIPHERAL_CLOCK_ERU1 = SCU_CLK_CGATSTAT0_ERU1_Msk, /**< ERU1 peripheral gating. */
452 #if defined(HRPWM0)
453 XMC_SCU_PERIPHERAL_CLOCK_HRPWM0 = SCU_CLK_CGATSTAT0_HRPWM0_Msk, /**< HRPWM0 peripheral gating. */
454 #endif
455 #if defined(CCU43)
456 XMC_SCU_PERIPHERAL_CLOCK_CCU43 = (SCU_CLK_CGATSTAT1_CCU43_Msk | 0x10000000UL), /**< CCU43 peripheral gating. */
457 #endif
458 #if defined(LEDTS0)
459 XMC_SCU_PERIPHERAL_CLOCK_LEDTS0 = (SCU_CLK_CGATSTAT1_LEDTSCU0_Msk | 0x10000000UL), /**< LEDTS0 peripheral gating. */
460 #endif
461 #if defined(CAN)
462 XMC_SCU_PERIPHERAL_CLOCK_MCAN = (SCU_CLK_CGATSTAT1_MCAN0_Msk | 0x10000000UL), /**< MCAN peripheral gating. */
463 #endif
464 #if defined(DAC)
465 XMC_SCU_PERIPHERAL_CLOCK_DAC = (SCU_CLK_CGATSTAT1_DAC_Msk | 0x10000000UL), /**< DAC peripheral gating. */
466 #endif
467 #if defined(SDMMC)
468 XMC_SCU_PERIPHERAL_CLOCK_SDMMC = (SCU_CLK_CGATSTAT1_MMCI_Msk | 0x10000000UL), /**< SDMMC peripheral gating. */
469 #endif
470 #if defined(USIC1)
471 XMC_SCU_PERIPHERAL_CLOCK_USIC1 = (SCU_CLK_CGATSTAT1_USIC1_Msk | 0x10000000UL), /**< USIC1 peripheral gating. */
472 #endif
473 #if defined(USIC2)
474 XMC_SCU_PERIPHERAL_CLOCK_USIC2 = (SCU_CLK_CGATSTAT1_USIC2_Msk | 0x10000000UL), /**< USIC2 peripheral gating. */
475 #endif
476 XMC_SCU_PERIPHERAL_CLOCK_PORTS = (SCU_CLK_CGATSTAT1_PPORTS_Msk | 0x10000000UL), /**< PORTS peripheral gating. */
477 XMC_SCU_PERIPHERAL_CLOCK_WDT = (SCU_CLK_CGATSTAT2_WDT_Msk | 0x20000000UL), /**< WDT peripheral gating. */
478 #if defined(ETH0)
479 XMC_SCU_PERIPHERAL_CLOCK_ETH0 = (SCU_CLK_CGATSTAT2_ETH0_Msk | 0x20000000UL), /**< ETH0 peripheral gating. */
480 #endif
481 XMC_SCU_PERIPHERAL_CLOCK_GPDMA0 = (SCU_CLK_CGATSTAT2_DMA0_Msk | 0x20000000UL), /**< DMA0 peripheral gating. */
482 #if defined(GPDMA1)
483 XMC_SCU_PERIPHERAL_CLOCK_GPDMA1 = (SCU_CLK_CGATSTAT2_DMA1_Msk | 0x20000000UL), /**< DMA1 peripheral gating. */
484 #endif
485 #if defined(FCE)
486 XMC_SCU_PERIPHERAL_CLOCK_FCE = (SCU_CLK_CGATSTAT2_FCE_Msk | 0x20000000UL), /**< FCE peripheral gating. */
487 #endif
488 #if defined(USB0)
489 XMC_SCU_PERIPHERAL_CLOCK_USB0 = (SCU_CLK_CGATSTAT2_USB_Msk | 0x20000000UL), /**< USB0 peripheral gating. */
490 #endif
491 #if defined(ECAT0)
492 XMC_SCU_PERIPHERAL_CLOCK_ECAT0 = (SCU_CLK_CGATSTAT2_ECAT0_Msk | 0x20000000UL), /**< ECAT0 peripheral gating. */
493 #endif
494 #if defined(EBU)
495 XMC_SCU_PERIPHERAL_CLOCK_EBU = (SCU_CLK_CGATSTAT3_EBU_Msk | 0x30000000UL) /**< EBU peripheral gating. */
496 #endif
497 } XMC_SCU_PERIPHERAL_CLOCK_t;
498 #endif
499
500 /**
501 * Defines options for system clock (fSYS) source. These enums are used to configure \a SYSSEL bits of \a SYSCLKCR
502 * Clock Control Register.
503 * Use type \a XMC_SCU_CLOCK_SYSCLKSRC_t for accessing these enum parameters.
504 */
505 typedef enum XMC_SCU_CLOCK_SYSCLKSRC
506 {
507 XMC_SCU_CLOCK_SYSCLKSRC_OFI = (0UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos), /**< Internal Fast Clock (fOFI) as a
508 source for system clock (fSYS). */
509 XMC_SCU_CLOCK_SYSCLKSRC_PLL = (1UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos) /**< PLL output (fPLL) as a
510 source for system clock (fSYS). */
511 } XMC_SCU_CLOCK_SYSCLKSRC_t;
512
513 /**
514 * Defines options for selecting the P-Divider input frequency. These enums are used to configure \a PINSEL bits of \a PLLCON2
515 * register.
516 * Use type \a XMC_SCU_CLOCK_OSCCLKSRC_t for accessing these enum parameters.
517 */
518 typedef enum XMC_SCU_CLOCK_SYSPLLCLKSRC
519 {
520 XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP = 0UL, /**< External crystal oscillator
521 (fOHP) as the source for P-Divider. */
522 XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI = SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk /**< Backup clock(fOFI)
523 as the source for P-Divider. */
524 } XMC_SCU_CLOCK_SYSPLLCLKSRC_t;
525
526 /**
527 * Defines options for selecting the USB clock source(fUSB/fSDMMC).
528 * These enums are used to configure \a USBSEL bits of \a USBCLKCR
529 * register. User can choose either fPLL or fUSBPLL clock as a source for USB clock.
530 * Use type \a XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters.
531 */
532 typedef enum XMC_SCU_CLOCK_USBCLKSRC
533 {
534 XMC_SCU_CLOCK_USBCLKSRC_USBPLL = (0UL << SCU_CLK_USBCLKCR_USBSEL_Pos), /**< USB PLL(fUSB PLL) as a
535 source for USB clock (fUSB/fSDMMC). */
536 XMC_SCU_CLOCK_USBCLKSRC_SYSPLL = (1UL << SCU_CLK_USBCLKCR_USBSEL_Pos) /**< Main PLL output (fPLL) as a
537 source for USB clock (fUSB/fSDMMC). */
538 } XMC_SCU_CLOCK_USBCLKSRC_t;
539
540 #if defined(ECAT0)
541 /**
542 * Defines options for selecting the ECAT clock source.
543 */
544 typedef enum XMC_SCU_CLOCK_ECATCLKSRC
545 {
546 XMC_SCU_CLOCK_ECATCLKSRC_USBPLL = (0UL << SCU_CLK_ECATCLKCR_ECATSEL_Pos), /**< USB PLL (fUSBPLL) as a source for ECAT clock. */
547 XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL = (1UL << SCU_CLK_ECATCLKCR_ECATSEL_Pos) /**< Main PLL output (fPLL) as a source for ECAT clock. */
548 } XMC_SCU_CLOCK_ECATCLKSRC_t;
549 #endif
550
551 /**
552 * Defines options for selecting the source of WDT clock(fWDT). These enums are used to configure \a WDTSEL bits of \a WDTCLKCR
553 * register. User can choose either fOFI or fPLL or fSTDBY clock as a source for WDT clock.
554 * Use type \a XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters.
555 */
556 typedef enum XMC_SCU_CLOCK_WDTCLKSRC
557 {
558 XMC_SCU_CLOCK_WDTCLKSRC_OFI = (0UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Internal Fast Clock
559 (fOFI) as the source for WDT clock (fWDT). */
560 XMC_SCU_CLOCK_WDTCLKSRC_STDBY = (1UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Standby clock
561 (fSTDBY) as the source for WDT clock (fWDT). */
562 XMC_SCU_CLOCK_WDTCLKSRC_PLL = (2UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos) /**< PLL output (fPLL) as the
563 source for WDT clock (fWDT). */
564 } XMC_SCU_CLOCK_WDTCLKSRC_t;
565
566 /**
567 * Defines options for selecting the source of external clock out (fEXT). These enums are used to configure \a ECKSEL bits of \a EXTCLKCR
568 * register. User can choose either fSYS or fPLL or fUSBPLL clock as a source for external clock out (fEXT).
569 * Use type \a XMC_SCU_CLOCK_EXTOUTCLKSRC_t for accessing these enum parameters.
570 */
571 typedef enum XMC_SCU_CLOCK_EXTOUTCLKSRC
572 {
573 XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS = (0UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< System clock (fSYS) as
574 the source for external clock out (fEXT). */
575 XMC_SCU_CLOCK_EXTOUTCLKSRC_USB = (2UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< USB PLL output(fUSB PLL) as the
576 source for external clock out (fEXT). */
577 XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL = (3UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< Main PLL output(fPLL) as the
578 source for external clock out (fEXT). */
579 #if ((UC_SERIES == XMC42) || (UC_SERIES == XMC41))
580 XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY = (4UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< Standby clock(fSTDBY) as the
581 source for external clock out (fEXT). */
582 #endif
583 } XMC_SCU_CLOCK_EXTOUTCLKSRC_t;
584
585 /**
586 * Defines options for selecting the source of RTC Clock (fRTC). These enums are used to configure \a RCS bit of \a HDCR register.
587 * User can choose either fOSI or fULP clock as a source for RTC Clock (fRTC).
588 * Use type \a XMC_SCU_HIB_RTCCLKSRC_t for accessing these enum parameters.
589 */
590 typedef enum XMC_SCU_HIB_RTCCLKSRC
591 {
592 XMC_SCU_HIB_RTCCLKSRC_OSI = (0UL << SCU_HIBERNATE_HDCR_RCS_Pos), /**< Internal Slow Clock
593 (fOSI) as the source for RTC Clock (fRTC). */
594 XMC_SCU_HIB_RTCCLKSRC_ULP = (1UL << SCU_HIBERNATE_HDCR_RCS_Pos) /**< Ultra Low Power Clock (fULP)
595 as the source for RTC Clock (fRTC). */
596 } XMC_SCU_HIB_RTCCLKSRC_t;
597
598 /**
599 * Defines options for selecting the source of Standby Clock (fSTDBY). These enums are used to configure \a STDBYSEL bit of \a HDCR
600 * register. User can choose either fOSI or fULP clock as a source for Standby Clock (fSTDBY).
601 * Use type \a XMC_SCU_HIB_STDBYCLKSRC_t for accessing these enum parameters.
602 */
603 typedef enum XMC_SCU_HIB_STDBYCLKSRC
604 {
605 XMC_SCU_HIB_STDBYCLKSRC_OSI = (0UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos), /**< Internal Slow Clock
606 (fOSI) as the source for Standby Clock
607 (fSTDBY). */
608 XMC_SCU_HIB_STDBYCLKSRC_OSCULP = (1UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos) /**< Ultra Low Power Clock
609 (fULP) as the source for Standby Clock
610 (fSTDBY). */
611 } XMC_SCU_HIB_STDBYCLKSRC_t;
612
613 /**
614 * Defines options for backup clock trimming. These enums are used to configure \a AOTREN \a FOTR bits of \a
615 * PLLCON0 register. Use type \a XMC_SCU_CLOCK_BACKUP_TRIM_t for accessing these enum parameters.
616 */
617 typedef enum XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE
618 {
619 XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY = 0UL, /**< Factory Oscillator Calibration:
620 Force adjustment of the internal oscillator with the firmware defined values.*/
621 XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC = 1UL /**< Automatic Oscillator Calibration adjustment of the fOFI clock with fSTDBY clock. */
622 } XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t;
623
624
625 /**
626 * Defines options for selecting device boot mode. These enums are used to configure \a SWCON bits of \a STCON register.
627 * User can choose among various boot modes by configuring SWCON bits.
628 * Use type \a XMC_SCU_BOOTMODE_t for accessing these enum parameters.
629 */
630 typedef enum XMC_SCU_BOOTMODE
631 {
632 XMC_SCU_BOOTMODE_NORMAL = (0UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from start of flash. */
633 XMC_SCU_BOOTMODE_ASC_BSL = (1UL << SCU_GENERAL_STCON_SWCON_Pos), /**< UART bootstrap. */
634 XMC_SCU_BOOTMODE_BMI = (2UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot Mode Index - Customized boot
635 sequence. */
636 XMC_SCU_BOOTMODE_CAN_BSL = (3UL << SCU_GENERAL_STCON_SWCON_Pos), /**< CAN bootstrap. */
637 XMC_SCU_BOOTMODE_PSRAM_BOOT = (4UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from PSRAM. */
638 XMC_SCU_BOOTMODE_ABM0 = (8UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative
639 address 0. */
640 XMC_SCU_BOOTMODE_ABM1 = (12UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative
641 address 1. */
642 XMC_SCU_BOOTMODE_FABM = (14UL << SCU_GENERAL_STCON_SWCON_Pos), /**< fallback Alternate Boot Mode (ABM) -
643 Try ABM-0 then try ABM-1. */
644 } XMC_SCU_BOOTMODE_t;
645
646
647 /**
648 * Defines various PLL modes of operation. These enums are used to configure \a VCOBYP bit of \a PLLCON0 register.
649 * User can choose either normal or prescalar mode by configuring VCOBYP bit.
650 * Use type \a XMC_SCU_PLL_MODE_t for accessing these enum parameters.
651 */
652 typedef enum XMC_SCU_CLOCK_SYSPLL_MODE
653 {
654 XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED, /**< fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed). */
655 XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL, /**< fPLL derived from fVCO and PLL operating in normal mode. */
656 XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR /**< fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed). */
657 } XMC_SCU_CLOCK_SYSPLL_MODE_t;
658
659 /**
660 * Defines the source of the system clock and peripherals clock gating in SLEEP state.
661 * Use this enum as parameter of XMC_SCU_CLOCK_SetSleepConfig before going to SLEEP state.
662 *
663 * The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is
664 * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is
665 * stopped. Peripherals are only clocked when configured to stay enabled.
666 *
667 * Peripherals can continue to operate unaffected and eventually generate an event to
668 * wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The
669 * clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP
670 * state.
671 *
672 */
673 typedef enum XMC_SCU_CLOCK_SLEEP_MODE_CONFIG
674 {
675 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI = 0, /**< fOFI used as system clock source in SLEEP state */
676 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FPLL = SCU_CLK_SLEEPCR_SYSSEL_Msk, /**< fPLL used as system clock source in SLEEP state */
677 #if defined(USB0)
678 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_USB = 0, /**< USB clock disabled in SLEEP state */
679 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_USB = SCU_CLK_SLEEPCR_USBCR_Msk, /**< USB clock enabled in SLEEP state */
680 #endif
681 #if defined(SDMMC)
682 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_SDMMC = 0,/**< SDMMC clock disabled in SLEEP state */
683 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_SDMMC = SCU_CLK_SLEEPCR_MMCCR_Msk,/**< SDMMC clock enabled in SLEEP state */
684 #endif
685 #if defined(ETH0)
686 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_ETH = 0, /**< ETH clock disabled in SLEEP state */
687 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH = SCU_CLK_SLEEPCR_ETH0CR_Msk, /**< ETH clock enabled in SLEEP state */
688 #endif
689 #if defined(EBU)
690 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_EBU = 0, /**< EBU clock disabled in SLEEP state */
691 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_EBU = SCU_CLK_SLEEPCR_EBUCR_Msk, /**< EBU clock enabled in SLEEP state */
692 #endif
693 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_CCU = 0, /**< CCU clock disabled in SLEEP state */
694 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU = SCU_CLK_SLEEPCR_CCUCR_Msk, /**< CCU clock enabled in SLEEP state */
695 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_WDT = 0, /**< WDT clock disabled in SLEEP state */
696 XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT = SCU_CLK_SLEEPCR_WDTCR_Msk, /**< WDT clock enabled in SLEEP state */
697 } XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t;
698
699 /**
700 * Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state.
701 * In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state.
702 * Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state.
703 *
704 * The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is
705 * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is
706 * stopped.
707 *
708 * In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked
709 * by a free-running clock. Peripherals are only clocked when configured to stay enabled.
710 * Configuration of peripherals and any SRAM content is preserved.
711 * The Flash module can be put into low-power mode to achieve a further power reduction.
712 * On wake-up Flash module will be restarted again before instructions or data access is possible.
713 * Any interrupt will bring the system back to operation via the NVIC.The clock setup before
714 * entering Deep Sleep state is restored upon wake-up.
715 */
716 typedef enum XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG
717 {
718 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FOFI = 0, /**< fOFI used as system clock source in DEEPSLEEP state */
719 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FPLL = SCU_CLK_DSLEEPCR_SYSSEL_Msk, /**< fPLL used as system clock source in DEEPSLEEP state */
720 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN = SCU_CLK_DSLEEPCR_FPDN_Msk,/**< Flash power down in DEEPSLEEP state */
721 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN = SCU_CLK_DSLEEPCR_PLLPDN_Msk, /**< Switch off main PLL in DEEPSLEEP state */
722 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_VCO_POWERDOWN = SCU_CLK_DSLEEPCR_VCOPDN_Msk, /**< Switch off VCO of main PLL in DEEPSLEEP state */
723 #if defined(USB0)
724 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_USB = 0, /**< USB clock disabled in DEEPSLEEP state */
725 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_USB = SCU_CLK_DSLEEPCR_USBCR_Msk, /**< USB clock enabled in DEEPSLEEP state */
726 #endif
727 #if defined(SDMMC)
728 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_SDMMC = 0,/**< SDMMC clock disabled in DEEPSLEEP state */
729 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_SDMMC = SCU_CLK_DSLEEPCR_MMCCR_Msk,/**< SDMMC clock enabled in DEEPSLEEP state */
730 #endif
731 #if defined(ETH0)
732 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_ETH = 0, /**< ETH clock disabled in DEEPSLEEP state */
733 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_ETH = SCU_CLK_DSLEEPCR_ETH0CR_Msk, /**< ETH clock enabled in DEEPSLEEP state */
734 #endif
735 #if defined(EBU)
736 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_EBU = 0, /**< EBU clock disabled in DEEPSLEEP state */
737 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_EBU = SCU_CLK_DSLEEPCR_EBUCR_Msk, /**< EBU clock enabled in DEEPSLEEP state */
738 #endif
739 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_CCU = 0, /**< CCU clock disabled in DEEPSLEEP state */
740 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_CCU = SCU_CLK_DSLEEPCR_CCUCR_Msk, /**< CCU clock enabled in DEEPSLEEP state */
741 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_WDT = 0, /**< WDT clock disabled in DEEPSLEEP state */
742 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_WDT = SCU_CLK_DSLEEPCR_WDTCR_Msk, /**< WDT clock enabled in DEEPSLEEP state */
743 } XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t;
744
745 /**
746 * Defines status of EVR13 regulator
747 */
748 typedef enum XMC_SCU_POWER_EVR_STATUS
749 {
750 XMC_SCU_POWER_EVR_STATUS_OK = 0, /**< EVR13 regulator No overvoltage condition */
751 XMC_SCU_POWER_EVR_STATUS_EVR13_OVERVOLTAGE = SCU_POWER_EVRSTAT_OV13_Msk /**< EVR13 regulator is in overvoltage */
752 } XMC_SCU_POWER_EVR_STATUS_t;
753
754 /**
755 * Define status of external hibernate control
756 */
757 typedef enum XMC_SCU_HIB_CTRL_STATUS
758 {
759 XMC_SCU_HIB_CTRL_STATUS_NO_ACTIVE = 0, /**< Hibernate not driven active to pads */
760 XMC_SCU_HIB_CTRL_STATUS_ACTIVE = SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk, /**< Hibernate driven active to pads */
761 } XMC_SCU_HIB_CTRL_STATUS_t;
762
763 /**
764 * Hibernate domain event status
765 */
766 typedef enum XMC_SCU_HIB_EVENT
767 {
768 XMC_SCU_HIB_EVENT_WAKEUP_ON_POS_EDGE = SCU_HIBERNATE_HDCR_WKPEP_Msk, /**< Wake-up on positive edge pin event */
769 XMC_SCU_HIB_EVENT_WAKEUP_ON_NEG_EDGE = SCU_HIBERNATE_HDCR_WKPEN_Msk, /**< Wake-up on negative edge pin event */
770 XMC_SCU_HIB_EVENT_WAKEUP_ON_RTC = SCU_HIBERNATE_HDCR_RTCE_Msk, /**< Wake-up on RTC event */
771 XMC_SCU_HIB_EVENT_ULPWDG = SCU_HIBERNATE_HDCR_ULPWDGEN_Msk, /**< ULP watchdog alarm status */
772 #if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
773 XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE = SCU_HIBERNATE_HDSTAT_VBATPEV_Msk, /**< Wake-up on LPAC positive edge of VBAT threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */
774 XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE = SCU_HIBERNATE_HDSTAT_VBATNEV_Msk, /**< Wake-up on LPAC negative edge of VBAT threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */
775 XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk, /**< Wake-up on LPAC positive edge of HIB_IO_0 threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */
776 XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk, /**< Wake-up on LPAC negative edge of HIB_IO_0 threshold crossing. @note Only available in XMC44, XMC42 and XMC41 series */
777 #if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)))
778 XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Msk, /**< Wake-up on LPAC positive edge of HIB_IO_1 threshold crossing. @note Only available in XMC44 series and LQFP100. */
779 XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Msk, /**< Wake-up on LPAC negative edge of HIB_IO_1 threshold crossing. @note Only available in XMC44 series and LQFP100. */
780 #endif
781 #endif
782 } XMC_SCU_HIB_EVENT_t;
783
784 /**
785 * Hibernate domain dedicated pins
786 */
787 typedef enum XMC_SCU_HIB_IO
788 {
789 XMC_SCU_HIB_IO_0 = 0, /**< HIB_IO_0 pin.
790 At the first power-up and with every reset of the hibernate domain this pin is configured as opendrain output and drives "0". As output the medium driver mode is active. */
791 #if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100))
792 XMC_SCU_HIB_IO_1 = 1 /**< HIB_IO_1 pin.
793 At the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. As output the medium driver mode is active.
794 @note : Only available in certain packages*/
795 #endif
796 } XMC_SCU_HIB_IO_t;
797
798 /**
799 * HIB_IOx pin I/O control
800 */
801 typedef enum XMC_SCU_HIB_PIN_MODE
802 {
803 XMC_SCU_HIB_PIN_MODE_INPUT_PULL_NONE = 0 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, no input pull device connected */
804 XMC_SCU_HIB_PIN_MODE_INPUT_PULL_DOWN = 1 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, input pull down device connected */
805 XMC_SCU_HIB_PIN_MODE_INPUT_PULL_UP = 2 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Direct input, input pull up device connected */
806 XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_HIBCTRL = 8 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull HIB control output */
807 XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_WDTSRV = 9 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull WDT service output */
808 XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_GPIO = 10 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull GPIO output */
809 XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_HIBCTRL = 12 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain HIB control output */
810 XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_WDTSRV = 13 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain WDT service output */
811 XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_GPIO = 14 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain GPIO output */
812 } XMC_SCU_HIB_PIN_MODE_t;
813
814 /**
815 * Selects the output polarity of the HIB_IOx
816 */
817 typedef enum XMC_SCU_HIB_IO_OUTPUT_LEVEL
818 {
819 XMC_SCU_HIB_IO_OUTPUT_LEVEL_LOW = 0 << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos, /**< Direct value */
820 XMC_SCU_HIB_IO_OUTPUT_LEVEL_HIGH = 1 << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos /**< Inverted value */
821 } XMC_SCU_HIB_IO_OUTPUT_LEVEL_t;
822
823 /**
824 * Selects hibernate mode
825 */
826 typedef enum XMC_SCU_HIB_HIBERNATE_MODE
827 {
828 XMC_SCU_HIB_HIBERNATE_MODE_EXTERNAL = 0, /**< Request external hibernate mode */
829 #if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
830 XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL = 1, /**< Request internal hibernate mode. @note Only available in XMC44, XMC42 and XMC41 series */
831 #endif
832 } XMC_SCU_HIB_HIBERNATE_MODE_t;
833
834 /**
835 * Selects input signal HIB_SR0 of ERU0
836 */
837 typedef enum XMC_SCU_HIB_SR0_INPUT
838 {
839 XMC_SCU_HIB_SR0_INPUT_HIB_IO_0 = SCU_HIBERNATE_HDCR_GPI0SEL_Msk, /**< Set HIB_SR0 to HIB_IO_0 digital input */
840 #if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100))
841 XMC_SCU_HIB_SR0_INPUT_HIB_IO_1 = 0, /**< Set HIB_SR0 to HIB_IO_1 digital input. @note Only available in certain packages. */
842 #endif
843 #if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
844 XMC_SCU_HIB_SR0_INPUT_ACMP0 = SCU_HIBERNATE_HDCR_ADIG0SEL_Msk, /**< Set HIB_SR0 to LPAC CMP0. @note Only available in XMC44, XMC42 and XMC41 series. */
845 #endif
846 } XMC_SCU_HIB_SR0_INPUT_t;
847
848 #if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
849
850 #if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))
851 /**
852 * Selects input signal HIB_SR1 of ERU0. @note Only available in XMC44 in certain packages.
853 */
854 typedef enum XMC_SCU_HIB_SR1_INPUT
855 {
856 XMC_SCU_HIB_SR1_INPUT_HIB_IO_0 = SCU_HIBERNATE_HDCR_GPI1SEL_Msk, /**< Set HIB_SR1 to HIB_IO_0 digital input */
857 XMC_SCU_HIB_SR1_INPUT_HIB_IO_1 = 0, /**< Set HIB_SR1 to HIB_IO_1 digital input. */
858 XMC_SCU_HIB_SR1_INPUT_ACMP1 = SCU_HIBERNATE_HDCR_ADIG1SEL_Msk, /**< Set HIB_SR0 to LPAC CMP1. */
859 XMC_SCU_HIB_SR1_INPUT_XTAL_GPI = SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk, /**< Set HIB_SR0 to RTC_XTAL_1 digital input */
860 } XMC_SCU_HIB_SR1_INPUT_t;
861 #endif
862
863 /**
864 * HIB LPAC input selection
865 */
866 typedef enum XMC_SCU_HIB_LPAC_INPUT
867 {
868 XMC_SCU_HIB_LPAC_INPUT_DISABLED = 0 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator permanently in power down */
869 XMC_SCU_HIB_LPAC_INPUT_VBAT = 0x1 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for VBAT input */
870 XMC_SCU_HIB_LPAC_INPUT_HIB_IO_0 = 0x2 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for HIB_IO_0 input */
871 #if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)))
872 XMC_SCU_HIB_LPAC_INPUT_HIB_IO_1 = 0x4 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for HIB_IO_1 input. @note Only available in XMC44 series and LQFP100 package. */
873 #endif
874 } XMC_SCU_HIB_LPAC_INPUT_t;
875
876 /**
877 * HIB LPAC start trigger selection for selected inputs
878 */
879 typedef enum XMC_SCU_HIB_LPAC_TRIGGER
880 {
881 XMC_SCU_HIB_LPAC_TRIGGER_SUBSECOND_INTERVAL_COUNTER = 0 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Sub-second interval counter */
882 XMC_SCU_HIB_LPAC_TRIGGER_RTC_ALARM_EVENT = 0x1 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< RTC alarm event */
883 XMC_SCU_HIB_LPAC_TRIGGER_RTC_PERIODIC_EVENT = 0x2 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< RTC periodic event */
884 XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_POSITIVE_EDGE_EVENT = 0x3 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< On digital wakeup input positive edge event */
885 XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_NEGATIVE_EDGE_EVENT = 0x5 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< On digital wakeup input negative edge event */
886 XMC_SCU_HIB_LPAC_TRIGGER_CONTINOUS = 0x6 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Continuous measurement */
887 XMC_SCU_HIB_LPAC_TRIGGER_SINGLE_SHOT = 0x7 << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos, /**< Single shot on software request */
888 } XMC_SCU_HIB_LPAC_TRIGGER_t;
889
890 /**
891 * HIB LPAC status
892 */
893 typedef enum XMC_SCU_HIB_LPAC_STATUS
894 {
895 XMC_SCU_HIB_LPAC_STATUS_VBAT_COMPARE_DONE = SCU_HIBERNATE_LPACST_VBATSCMP_Msk, /**< VBAT compare operation completed */
896 XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_COMPARE_DONE = SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk, /**< HBI_IO_0 compare operation completed */
897 #if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)))
898 XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_COMPARE_DONE = SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Msk, /**< HBI_IO_1 compare operation completed. @note Only available in XMC44 series and LQFP100 package. */
899 #endif
900 XMC_SCU_HIB_LPAC_STATUS_VBAT_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_VBATVAL_Msk, /**< VBAT comparison result above programmed threshold */
901 XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk, /**< HBI_IO_0 comparison result above programmed threshold */
902 #if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)))
903 XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_AHIBIO1VAL_Msk, /**< HBI_IO_1 comparison result above programmed threshold. @note Only available in XMC44 series and LQFP100 package. */
904 #endif
905 } XMC_SCU_HIB_LPAC_STATUS_t;
906
907 #endif /* (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) */
908
909 /*********************************************************************************************************************
910 * DATA STRUCTURES
911 ********************************************************************************************************************/
912
913 /**
914 * Defines a data structure for initializing the PLL functional block.
915 * Structure holds divider values for N-DIV, P-DIV, K1-DIV, K2-DIV in order to generate desired
916 * frequency using VCO. It holds the PLL mode of operation either normal or prescaler (VCO bypassed).
917 * Use type \a XMC_SCU_CLOCK_PLL_CONFIG_t for accessing these structure parameters.
918 */
919 typedef struct XMC_SCU_CLOCK_SYSPLL_CONFIG
920 {
921 uint8_t n_div; /**< PLL N-Divider value. */
922 uint8_t p_div; /**< PLL P-Divider value. */
923 uint8_t k_div; /**< K1-Divider(Prescalar mode) or K2-Divider (Normal mode). */
924 XMC_SCU_CLOCK_SYSPLL_MODE_t mode; /**< PLL mode of operation. */
925 XMC_SCU_CLOCK_SYSPLLCLKSRC_t clksrc; /**< PLL divider input frequency. */
926 } XMC_SCU_CLOCK_SYSPLL_CONFIG_t;
927
928 /**
929 * Defines a data structure used for initializing the clock functional block.
930 * Clock functional block configures clock source needed for various peripheral and its divider values.
931 * Use type \a XMC_SCU_CLOCK_CONFIG_t for accessing these structure parameters.
932 */
933 typedef struct XMC_SCU_CLOCK_CONFIG
934 {
935 XMC_SCU_CLOCK_SYSPLL_CONFIG_t syspll_config; /**< PLL configuration */
936 bool enable_oschp; /**< Enable external high precision oscillator.
937 Should be enabled when fOHP has to be source of system clock. */
938 bool enable_osculp; /**< Enable external ultra low power oscillator.
939 Should be enabled when fULP has to be source of standby clock(fSTDBY). */
940 XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t calibration_mode; /**< Backup clock trimming mode. */
941 XMC_SCU_HIB_STDBYCLKSRC_t fstdby_clksrc; /**< Standby clock source. */
942 XMC_SCU_CLOCK_SYSCLKSRC_t fsys_clksrc; /**< Choice of system clock. */
943 uint8_t fsys_clkdiv; /**< Ratio of fPLL to fSYS. */
944 uint8_t fcpu_clkdiv; /**< Ratio of fSys to fCPU. */
945 uint8_t fccu_clkdiv; /**< Ratio of fSys to fCCU. */
946 uint8_t fperipheral_clkdiv; /**< Ratio of fSYS to fPERI. */
947 } const XMC_SCU_CLOCK_CONFIG_t;
948
949 /**
950 * Low power modes
951 */
952 typedef enum XMC_SCU_POWER_MODE_t
953 {
954 XMC_SCU_POWER_MODE_SLEEP = 0, /**< sleep mode stops the processor clock */
955 XMC_SCU_POWER_MODE_DEEPSLEEP = SCB_SCR_SLEEPDEEP_Msk /**< deep sleep mode stops the system clock and switches off the PLL and flash memory. */
956 } XMC_SCU_POWER_MODE_t;
957
958 /*********************************************************************************************************************
959 * API PROTOTYPES
960 ********************************************************************************************************************/
961
962 #ifdef __cplusplus
963 extern "C" {
964 #endif
965
966 /**
967 *
968 * @param group ADC Group to which the channel being monitored belongs to.\n
969 * \b Range: 0 or 1.
970 * @param channel The channel whose voltage range has to be monitored.\n
971 * \b Range: 6 or 7. Value identifies the channel in the selected ADC group.
972 *
973 * @return None
974 *
975 * \par<b>Description</b><br>
976 * Enables out of range comparator for the selected ADC group and channel. \n\n
977 * The ADC channel input is compared by Out of Range Comparator (ORC) for overvoltage monitoring
978 * or for detection of out of range analog inputs. ORC must be turned on explicitly
979 * to leverage the auditing feature. ORC is enabled by setting the enable bit in the GORCEN register.
980 * \par<b>Related APIs:</b><BR>
981 * XMC_SCU_DisableOutOfRangeComparator()\n\n\n
982 */
983 void XMC_SCU_EnableOutOfRangeComparator(const uint32_t group, const uint32_t channel);
984
985 /**
986 *
987 * @param group ADC Group to which the channel being monitored belongs to.\n
988 * \b Range: 0 or 1.
989 * @param channel The channel whose voltage range has to be monitored.\n
990 * \b Range: 6 or 7. Value identifies the channel in the selected ADC group.
991 *
992 * @return None
993 *
994 * \par<b>Description</b><br>
995 * Disables the out of range comparator for the selected ADC group and the channel. \n\n
996 * Out of range comparator is disabled by clearing the enable bit in the GORCEN register.
997 * \par<b>Related APIs:</b><BR>
998 * XMC_SCU_EnableOutOfRangeComparator()\n\n\n
999 */
1000 void XMC_SCU_DisableOutOfRangeComparator(const uint32_t group, const uint32_t channel);
1001
1002 /**
1003 * @return None
1004 *
1005 * \par<b>Description</b><br>
1006 * Enables die temperature measurement by powering the DTS module.\n\n
1007 * Die temperature sensor is enabled by setting the PWD bit of DTSCON register.
1008 * \par<b>Related APIs:</b><BR>
1009 * XMC_SCU_DisableTemperatureSensor(), XMC_SCU_IsTemperatureSensorEnabled(), XMC_SCU_CalibrateTemperatureSensor(),
1010 * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n
1011 */
1012 void XMC_SCU_EnableTemperatureSensor(void);
1013
1014 /**
1015 * @return None
1016 *
1017 * \par<b>Description</b><br>
1018 * Disables die temperature measurement by powering the DTS module off.\n\n
1019 * Die temperature sensor is disabled by clearing the PWD bit of DTSCON register.
1020 * \par<b>Related APIs:</b><BR>
1021 * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_IsTemperatureSensorEnabled(), XMC_SCU_CalibrateTemperatureSensor(),
1022 * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n
1023 */
1024 void XMC_SCU_DisableTemperatureSensor(void);
1025
1026 /**
1027 * @return Status of die temperature sensor. \n
1028 * \b Range: true - if temperature sensor is enabled.\n
1029 * false - if temperature sensor is disabled.
1030 *
1031 * \par<b>Description</b><br>
1032 * Provides the die temperature sensor power status.\n\n
1033 * The status is obtained by reading the PWD bit of DTSCON register.
1034 * \par<b>Related APIs:</b><BR>
1035 * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor(),
1036 * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n
1037 */
1038 bool XMC_SCU_IsTemperatureSensorEnabled(void);
1039
1040 /**
1041 *
1042 * @param offset Offset value for calibrating the DTS result.\n
1043 * \b Range: 0 to 127.
1044 * @param gain Gain value for calibrating the DTS conversion result.\n
1045 * \b Range: 0 to 63.
1046 *
1047 * @return None
1048 *
1049 * \par<b>Description</b><br>
1050 * Calibrates the measurement of temperature by configuring the values of offset and gain of \a DTSCON register. \n\n
1051 * Allows to improve the accuracy of the temperature measurement with the adjustment of \a OFFSET and \a GAIN bit fields
1052 * in the \a DTSCON register.
1053 * Offset adjustment is defined as a shift of the conversion result. The range of the offset adjustment is 7 bits with a
1054 * resolution that corresponds to +/- 12.5�C. The offset value gets added to the measure result.
1055 * Offset is considered as a signed value.
1056 * Gain adjustment helps in minimizing gain error. When the \a gain value is 0, result is generated with maximum gain.
1057 * When the \a gain value is 63, result is generated with least gain, i.e, \a RESULT - 63 at the highest measured temperature.\n
1058 * It is recommended to use following steps:\n
1059 * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n
1060 * - Call \a XMC_SCU_CalibrateTempMonitor with desired offset and gain calibration values to the DTS.\n
1061 * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\n
1062 * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n
1063 * - Check whether Die Temperature Sensor (DTS) is busy in conversion by calling \a XMC_SCU_IsTemperatureSensorBusy() and wait till
1064 * conversion complete.\n
1065 * - Read the die temperature value using \a XMC_SCU_GetTemperatureMeasurement API.
1066 * \par<b>Related APIs:</b><BR>
1067 * XMC_SCU_EnableTemperatureSensor(),
1068 * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement() \n\n\n
1069 */
1070 void XMC_SCU_CalibrateTemperatureSensor(uint32_t offset, uint32_t gain);
1071
1072 /**
1073 * @return XMC_SCU_STATUS_t Result of starting the temperature measurement.\n
1074 * \b Range: \n
1075 * XMC_SCU_STATUS_OK if the measurement is started successfully.\n
1076 * XMC_SCU_STATUS_ERROR if temperature sensor is not enabled.\n
1077 * XMC_SCU_STATUS_BUSY if temperature sensor is busy measuring the temperature.\n
1078 *
1079 *
1080 * \par<b>Description</b><br>
1081 * Starts die temperature measurement using internal temperature sensor.\n\n
1082 * The API checks if the temperature sensor is enabled and is not busy in measurement.\n
1083 * It is recommended to use following steps:\n
1084 * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n
1085 * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\n
1086 * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n
1087 * - Check whether Die Temperature Sensor (DTS) is busy in conversion by calling \a XMC_SCU_IsTemperatureSensorBusy() and wait till
1088 * conversion complete.\n
1089 * - Read the die temperature value using \a XMC_SCU_GetTemperatureMeasurement API.
1090 * \par<b>Related APIs:</b><BR>
1091 * XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor(),
1092 * XMC_SCU_GetTemperatureMeasurement() \n\n\n
1093 */
1094 XMC_SCU_STATUS_t XMC_SCU_StartTemperatureMeasurement(void);
1095
1096
1097 /**
1098 *
1099 * @return uint32_t Measured temperature value.\n
1100 * \b Range: Valid temperature range is 0 to 1023. \n
1101 * If sensor is not enabled, 0x7FFFFFFFH is returned.
1102 *
1103 * \par<b>Description</b><br>
1104 * Reads the measured value of die temperature.\n\n
1105 * Temperature measurement result is read from \a RESULT bit field of \a DTSSTAT register.
1106 * The temperature measured in �C is given by (RESULT - 605) / 2.05 [�C]
1107 * \par<b>Related APIs:</b><BR>
1108 * XMC_SCU_IsTemperatureSensorBusy() \n\n\n
1109 */
1110 uint32_t XMC_SCU_GetTemperatureMeasurement(void);
1111
1112 /**
1113 * @return bool Indicates if the die temperature sensor is busy.\n
1114 * \b Range: \a true if sensor is busy in temperature measurement.
1115 * \a false if sensor is free and can accept a new request for measurement.
1116 *
1117 * \par<b>Description</b><br>
1118 * Checks whether Die Temperature Sensor (DTS) is busy in temperature measurement.\n\n
1119 * The status is read from the \a BUSY bit field of the \a DTSSTAT register.
1120 * \par<b>Related APIs:</b><BR>
1121 * XMC_SCU_GetTemperatureMeasurement() \n\n\n
1122 */
1123 bool XMC_SCU_IsTemperatureSensorBusy(void);
1124
1125 /**
1126 * @return bool Status of die temperature sensor whether it is ready to start measurement. \n
1127 * \b Range: \n \a true if temperature sensor is ready to start measurement. \n
1128 * \a false if temperature sensor is not ready to start measurement.
1129 *
1130 * \par<b>Description</b><br>
1131 * Checks if the die temperature sensor is ready to start a measurement\n\n
1132 * The status is obtained by reading \a RDY bit of \a DTSSTAT register. It is recommended
1133 * to check the ready status of die temperature sensor before starting it.
1134 * \par<b>Related APIs:</b><BR>
1135 * XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_IsTemperatureSensorBusy() \n\n\n
1136 */
1137 bool XMC_SCU_IsTemperatureSensorReady(void);
1138
1139 #if (UC_SERIES != XMC45)
1140 /**
1141 * @return bool Indicates if the measured die temperature value has exceeded the configured upper limit.\n
1142 * \b Range: \a true if the temperature value has exceeded the configured upper limit. \a false
1143 * if the temperature value is less than the configured upper limit.
1144 *
1145 * \par<b>Description</b><br>
1146 * Checks if the measured temperature has exceeded the configured upper limit of temperature.\n\n
1147 * The API checks \a OVERFL bit (Upper Limit Overflow Status bit) of \a DTEMPALARM register.
1148 * The \a OVERFL bit will be set if the measured temperature has exceeded the limit configured in
1149 * the bitfield \a UPPER in the \a DTEMPLIM register.
1150 * \par<b>Related APIs:</b><BR>
1151 * XMC_SCU_SetRawTempLimits(),XMC_SCU_LowTemperature() \n\n\n
1152 */
1153 bool XMC_SCU_HighTemperature(void);
1154
1155 /**
1156 *
1157 * @param lower_temp Lower threshold of die temperature. If measured temperature falls below this value,
1158 * alarm bit will be set in \a UNDERFL bit field of \a DTEMPALARM register.
1159 * @param upper_temp Upper threshold of die temperature. If measured temperature exceeds this value,
1160 * alarm bit will be set in \a OVERFL bit field of \a DTEMPALARM register.
1161 *
1162 * @return None
1163 *
1164 * \par<b>Description</b><br>
1165 * Configures the lower and upper threshold of die temperature.\n\n
1166 * API configures \a DTEMPLIM register for upper and lower die temperature threshold limits.
1167 * When the measured temperature is outside the range defined by the limits, alarm bits \a UNDERFL or \a OVERFL
1168 * will be set in the register \a DTEMPALARM.\n
1169 * It is recommended to use following steps:\n
1170 * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n
1171 * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values.\n
1172 * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n
1173 * - Use \a XMC_SCU_HighTemperature() and XMC_SCU_LowTemperature() to monitor the temperature.\n
1174 * \par<b>Related APIs:</b><BR>
1175 * XMC_SCU_HighTemperature(), XMC_SCU_LowTemperature() \n\n\n
1176 */
1177 void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp);
1178
1179 /**
1180 * @return bool Indicates if the measured die temperature value has dropped below the configured lower limit.\n
1181 * \b Range: \a true if the temperature value has dropped below the configured lower limit. \a false
1182 * if the temperature value is higher than the configured lower limit.
1183 *
1184 * \par<b>Description</b><br>
1185 * Checks if the measured temperature has dropped below the configured lower limit of temperature.\n\n
1186 * The API checks \a UNDERFL bit (Lower LimitUnderflow Status bit) of \a DTEMPALARM register.
1187 * The \a UNDERFL bit will be set if the measured temperature has dropped below the limit configured in
1188 * the bitfield \a LOWER in the \a DTEMPLIM register.
1189 * \par<b>Related APIs:</b><BR>
1190 * XMC_SCU_SetRawTempLimits(),XMC_SCU_HighTemperature() \n\n\n
1191 */
1192 bool XMC_SCU_LowTemperature(void);
1193 #endif
1194
1195 /**
1196 * @return uint32_t Configured boot mode for the device.\n
1197 * \b Range: Use type @ref XMC_SCU_BOOTMODE_t for enumeration of different boot modes.
1198 *
1199 * \par<b>Description</b><br>
1200 * Provides the boot mode configured for the device.\n\n
1201 * The boot mode is read from the \a STCON register bit field \a SWCON.
1202 *
1203 * \par<b>Related APIs:</b><BR>
1204 * XMC_SCU_SetBootMode() \n\n\n
1205 */
1206 uint32_t XMC_SCU_GetBootMode(void);
1207
1208 /**
1209 *
1210 * @param mode Boot mode to be configured for the device.\n
1211 * \b Range: Use type @ref XMC_SCU_BOOTMODE_t for selecting the boot mode.
1212 *
1213 * @return None
1214 *
1215 * \par<b>Description</b><br>
1216 * Configures the desired boot mode for the device.\n\n
1217 * The XMC4 series devices support multiple boot modes. A running application can set a desired bootmode and
1218 * launch it by means of software reset. Switching of boot modes should be handled carefully. User should ensure that
1219 * the initial boot sequence is executed. A stable execution environment should be maintained when program control is
1220 * eventually handed over to the application program.\n
1221 * It is recommended to use following steps to launch requested bootmode:\n
1222 * - Call \a XMC_SCU_SetBootMode() with desired boot mode value.\n
1223 * - Trigger a software reset using system reset request by enabling a bit \a SYSRESETREQ of AIRCR register
1224 * (PPB->AIRCR |= PPB_AIRCR_SYSRESETREQ_Msk).\n
1225 * \par<b>Related APIs:</b><BR>
1226 * XMC_SCU_GetBootMode() \n\n\n
1227 */
1228 void XMC_SCU_SetBootMode(const XMC_SCU_BOOTMODE_t mode);
1229
1230 /**
1231 *
1232 * @param index The SCU general purpose register to be read.\n
1233 * \b Range: 0 and 1 corresponding to GPR0 and GPR1.
1234 *
1235 * @return uint32_t Data read from the selected general purpose register.
1236 *
1237 * \par<b>Description</b><br>
1238 * Provides stored data from general purpose SCU register.\n\n
1239 * SCU consists of 2 general purpose registers. These registers can be used for storing
1240 * data. The API reads from either GPR0 or GPR1 based on the \a index value.
1241 * \par<b>Related APIs:</b><BR>
1242 * XMC_SCU_WriteGPR()\n\n\n
1243 */
1244 uint32_t XMC_SCU_ReadGPR(const uint32_t index);
1245
1246 /**
1247 *
1248 * @param index The SCU general purpose register to be written.\n
1249 * \b Range: 0 and 1 corresponding to GPR0 and GPR1.
1250 * @param data Data to be written to the selected general purpose register.
1251 *
1252 * @return None
1253 *
1254 * \par<b>Description</b><br>
1255 * Stores data in the selected general purpose SCU register.\n\n
1256 * SCU consists of 2 general purpose registers. These registers can be used for storing
1257 * data. The API writes data to either GPR0 or GPR1 based on the \a index value.
1258 * \par<b>Related APIs:</b><BR>
1259 * XMC_SCU_ReadGPR()\n\n\n
1260 */
1261 void XMC_SCU_WriteGPR(const uint32_t index, const uint32_t data);
1262
1263 /**
1264 *
1265 * @param address Location in the retention memory to be written.\n
1266 * \b Range: 4 bit address space is provided for selecting 16 words of 32 bits.
1267 * equivalent to 64 bytes of data. \a address value should be from
1268 * 0 to 15.
1269 * @param data 32 bit data to be written into retention memory. The API writes
1270 * one word(4 bytes) of data to the address specified.\n
1271 * \b Range: 32 bit data.
1272 *
1273 * @return None
1274 *
1275 * \par<b>Description</b><br>
1276 * Writes input data to the selected address of Retention memory in hibernate domain.\n\n
1277 * The retention memory is located in hibernate domain.
1278 * It is used for the purpose of store/restore of context information.
1279 * Access to the retention memory space is served over shared serial interface.
1280 * Retention memory content is retained even in hibernate mode.
1281 * \par<b>Related APIs:</b><BR>
1282 * XMC_SCU_ReadFromRetentionMemory() \n\n\n
1283 */
1284 void XMC_SCU_WriteToRetentionMemory(uint32_t address, uint32_t data);
1285
1286 /**
1287 *
1288 * @param address Location in the retention memory to be read.\n
1289 * \b Range: 4 bit address space is provided for selecting 16 words of 32 bits.
1290 * equivalent to 64 bytes of data. \a address value should be from
1291 * 0 to 15.
1292 *
1293 * @return uint32_t 32 bit data read from retention memory. The API reads
1294 * one word(4 bytes) of data from the address specified.\n
1295 * \b Range: 32 bit data.
1296 *
1297 * \par<b>Description</b><br>
1298 * Reads data from selected address of retention memory in hibernate domain.\n\n
1299 * The retention memory is located in hibernate domain.
1300 * It is used for the purpose of store/restore of context information.
1301 * Access to the retention memory space is served over shared serial interface.
1302 * Retention memory content is retained even in hibernate mode.
1303 * \par<b>Related APIs:</b><BR>
1304 * XMC_SCU_WriteToRetentionMemory() \n\n\n
1305 */
1306 uint32_t XMC_SCU_ReadFromRetentionMemory(uint32_t address);
1307
1308 /**
1309 *
1310 * @param request Non-maskable interrupt (NMI) request source to be enabled.\n
1311 * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple
1312 * sources can be combined using \a OR operation.
1313 *
1314 * @return None
1315 *
1316 * \par<b>Description</b><br>
1317 * Selectively enables interrupt sources to generate non maskable interrupt(NMI).\n\n
1318 * NMI assertion can be individually enabled by setting corresponding bit of an interrupt in the
1319 * \a NMIREQEN register.
1320 * \par<b>Related APIs:</b><BR>
1321 * XMC_SCU_INTERRUPT_DisableNmiRequest() \n\n\n
1322 */
1323 void XMC_SCU_INTERRUPT_EnableNmiRequest(const uint32_t request);
1324
1325 /**
1326 *
1327 * @param request Non-maskable interrupt (NMI) request source to be disabled.\n
1328 * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple
1329 * sources can be combined using \a OR operation.
1330 *
1331 * @return None
1332 *
1333 * \par<b>Description</b><br>
1334 * Selectively disables interrupt sources from generating non maskable interrupt(NMI).\n\n
1335 * NMI assertion can be individually disabled by clearing corresponding bits in the \a NMIREQEN register.
1336 * \par<b>Related APIs:</b><BR>
1337 * XMC_SCU_INTERRUPT_EnableNmiRequest() \n\n\n
1338 */
1339 void XMC_SCU_INTERRUPT_DisableNmiRequest(const uint32_t request);
1340
1341 /**
1342 *
1343 * @param trap The event for which, trap generation has to be enabled.\n
1344 * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event.
1345 *
1346 * @return None
1347 *
1348 * \par<b>Description</b><br>
1349 * Enables assertion of trap for the selected trap event.\n\n
1350 * Trap assertion can be individually enabled by clearing respective bit of the
1351 * event in \a TRAPDIS register in order to get an exception.
1352 * \par<b>Related APIs:</b><BR>
1353 * XMC_SCU_TRAP_Disable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus() \n\n\n
1354 */
1355 void XMC_SCU_TRAP_Enable(const uint32_t trap);
1356
1357 /**
1358 *
1359 * @param trap The event for which, trap generation has to be disabled.\n
1360 * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event.
1361 *
1362 * @return None
1363 *
1364 * \par<b>Description</b><br>
1365 * Disables assertion of trap for the selected trap event.\n\n
1366 * Trap assertion can be individually disabled by setting the respective event bit
1367 * in the \a TRAPDIS register in order to suppress trap generation.
1368 * \par<b>Related APIs:</b><BR>
1369 * XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus() \n\n\n
1370 */
1371 void XMC_SCU_TRAP_Disable(const uint32_t trap);
1372
1373 /**
1374 *
1375 * @param trap The event for which, trap status bit has to be cleared.\n
1376 * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event.
1377 *
1378 * @return None
1379 *
1380 * \par<b>Description</b><br>
1381 * Clears the trap status of input event.\n\n
1382 * Once a trap event is detected, it will have to be acknowledged and later serviced.
1383 * The trap status bit should be cleared to detect the occurence of trap next time.
1384 * This is useful while polling for TRAPSTAT without enabling the NMI for trap.
1385 * Trap status can be cleared by setting the event bit in the \a TRAPCLR register.
1386 * \par<b>Related APIs:</b><BR>
1387 * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_GetStatus() \n\n\n
1388 */
1389 void XMC_SCU_TRAP_ClearStatus(const uint32_t trap);
1390
1391 /**
1392 * @return uint32_t Status of trap generating events.\n
1393 * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. The returned
1394 * value indicates the status of multiple events at their respective bit positions.
1395 * User should mask the bits of the events of interest using the type specified.
1396 *
1397 * \par<b>Description</b><br>
1398 * Provides the status of trap generating events. \n\n
1399 * The status is read from \a TRAPRAW register. Status of the specific events can be checked
1400 * using their respective bits in the \a TRAPRAW register. The bit masks can be obtained from
1401 * the enumeration type @ref XMC_SCU_TRAP_t. Multiple events can be combined using \a OR operation.
1402 * A trap event is considered to be asserted if the respective bit of the event is set to 1.
1403 * \par<b>Related APIs:</b><BR>
1404 * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_ClearStatus() \n\n\n
1405 */
1406 uint32_t XMC_SCU_TRAP_GetStatus(void);
1407
1408 /**
1409 *
1410 * @param trap The event for which, trap has to be triggered.\n
1411 * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event.
1412 *
1413 * @return None
1414 *
1415 * \par<b>Description</b><br>
1416 * Triggers trap generation for the event specified. \n\n
1417 * The trap source has to be enabled before invocation of this API.
1418 * Trap event can be triggered by setting its respective bit in the \a TRAPSET register.
1419 * Trap event can be configured to generate a non maskable interrupt by using the API XMC_SCU_INTERRUPT_EnableNmiRequest().\n
1420 * It is recommended to use following steps to manually assert a trap event:\n
1421 * - Call \a XMC_SCU_TRAP_EnableEvent with desired trap request source ID.\n
1422 * - Call \a XMC_SCU_TRAP_SetEvent with same trap request source ID to manually assert a trap event.\n
1423 * \par<b>Related APIs:</b><BR>
1424 * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_GetStatus() \n\n\n
1425 */
1426 void XMC_SCU_TRAP_Trigger(const uint32_t trap);
1427
1428 /**
1429 *
1430 * @param peripheral The peripheral to be reset.\n
1431 * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals that can be reset.
1432 *
1433 * @return None
1434 *
1435 * \par<b>Description</b><br>
1436 * Puts the specified peripheral in to reset state. \n\n
1437 * The API achieves reset of peripherals by setting the respective bit in the \a PRSET0, \a PRSET1 or \a PRSET2
1438 * register. Status of reset assertion automatically stored in the \a PRSTATn register and can be checked by
1439 * user software to determine the state of the system and for debug purpose.\n
1440 * It is recommended to use following steps to assert a peripheral reset:\n
1441 * - Call \a XMC_SCU_RESET_AssertPeripheralReset() with desired peripheral identifier.\n
1442 * - Call \a XMC_SCU_RESET_IsPeripheralResetAsserted with same peripheral identifier to verify whether peripheral
1443 * is in reset state.\n
1444 * \par<b>Related APIs:</b><BR>
1445 * XMC_SCU_RESET_IsPeripheralResetAsserted() \n\n\n
1446 */
1447 void XMC_SCU_RESET_AssertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral);
1448
1449 /**
1450 *
1451 * @param peripheral The peripheral to be moved out of reset state.\n
1452 * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals that can be reset.
1453 *
1454 * @return None
1455 *
1456 * \par<b>Description</b><br>
1457 * Enables the specified peripheral by moving it out of reset state. \n\n
1458 * Any peripheral should be moved out of reset state for executing its functionality.
1459 * The API enables the peripheral by setting its respective bit in the \a PRCLR0, \a PRCLR1 or \a PRCLR2
1460 * register. Status of reset deassertion is automatically stored in the \a PRSTATn register and can be checked by
1461 * the user software to determine the state of the system and for debug purpose.\n
1462 * It is recommended to use following steps to deassert a peripheral reset:\n
1463 * - Call \a XMC_SCU_RESET_DeassertPeripheralReset() with desired peripheral identifier.\n
1464 * - Call \a XMC_SCU_RESET_IsPeripheralResetAsserted() with desired peripheral identifier to verify whether peripheral
1465 * has been enabled.\n
1466 * \par<b>Related APIs:</b><BR>
1467 * XMC_SCU_RESET_AssertPeripheralReset() \n\n\n
1468 */
1469 void XMC_SCU_RESET_DeassertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peripheral);
1470
1471 /**
1472 *
1473 * @param peripheral The peripheral, whose reset status has to be checked.\n
1474 * \b Range: Type @ref XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals.
1475 *
1476 * @return bool Status of peripheral reset. \n
1477 * \b Range: \a true if peripheral is in reset state. \a false if peripheral is enabled and out of reset state.
1478 *
1479 * \par<b>Description</b><br>
1480 * Checks the reset status of the selected peripheral.\n\n
1481 * The API reads the reset status from \a PRSTATn register. Returns true if the peripheral is in
1482 * reset state. On power up of the device, all the peripherals will be in reset state.
1483 * If the peripheral is enabled, \a false will be returned as the status.
1484 * \par<b>Related APIs:</b><BR>
1485 * XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset() \n\n\n
1486 */
1487 bool XMC_SCU_RESET_IsPeripheralResetAsserted(const XMC_SCU_PERIPHERAL_RESET_t peripheral);
1488
1489 /**
1490 *
1491 * @param memory The on-chip RAM type, for which the parity error status has to be cleared.\n
1492 * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple
1493 * memory status bits can be cleared by using the \a OR operation.
1494 *
1495 * @return None
1496 *
1497 * \par<b>Description</b><br>
1498 * Clears the parity error status bit. \n\n
1499 * When a memory parity error is detected using the status bits in \a PEFLAG register. It has to
1500 * be cleared by software to detect the parity error from the same memory next time.
1501 * The API clears the parity error status bit of the selected peripheral by setting the
1502 * respective bit in the \a PEFLAG register. Status of multiple memory parity errors
1503 * can be cleared by combining the enum values using \a OR operation.
1504 * \par<b>Related APIs:</b><BR>
1505 * XMC_SCU_PARITY_GetStatus(), XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_EnableTrapGeneration() \n\n\n
1506 */
1507 void XMC_SCU_PARITY_ClearStatus(const uint32_t memory);
1508
1509 /**
1510 *
1511 * @param memory The on-chip RAM type, for which the parity error checking has to be enabled.\n
1512 * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple
1513 * memory types can be combined using the \a OR operation.
1514 *
1515 * @return None
1516 *
1517 * \par<b>Description</b><br>
1518 * Enables parity error checking for the selected on-chip RAM type.\n\n
1519 * Parity error checking can be enabled by setting respective bits in the \a PEEN register.
1520 * Additionally parity error can be configured to generate trap when the error is detected,
1521 * using the API XMC_SCU_PARITY_EnableTrapGeneration(). Such a trap can be further configured
1522 * to generate non maskable interrupt(NMI) using the API XMC_SCU_INTERRUPT_EnableNmiRequest().
1523 * \par<b>Related APIs:</b><BR>
1524 * XMC_SCU_PARITY_EnableTrapGeneration(), XMC_SCU_INTERRUPT_EnableNmiRequest() \n\n\n
1525 */
1526 void XMC_SCU_PARITY_Enable(const uint32_t memory);
1527
1528 /**
1529 *
1530 * @param memory The on-chip RAM type, for which the parity error checking has to be disabled.\n
1531 * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple
1532 * memory types can be combined using the \a OR operation.
1533 *
1534 * @return None
1535 *
1536 * \par<b>Description</b><br>
1537 * Disables parity error checking for the selected on-chip RAM type.\n\n
1538 * Parity error detection can be disabled by clearing the respective bit in the \a PEEN register.
1539 * \par<b>Related APIs:</b><BR>
1540 * XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_DisableTrapGeneration() \n\n\n
1541 */
1542 void XMC_SCU_PARITY_Disable(const uint32_t memory);
1543
1544 /**
1545 *
1546 * @param memory The on-chip RAM type, for which the parity error trap generation has to be enabled.\n
1547 * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple
1548 * memory types can be combined using the \a OR operation.
1549 *
1550 * @return None
1551 *
1552 * \par<b>Description</b><br>
1553 * Enables trap assertion for the parity error source.\n\n
1554 * Parity error detection for different types of on-chip RAM can generate trap.
1555 * Trap assertion for parity error can be individually enabled by setting the respective bits
1556 * in the \a PETE register. The generated trap can be additionally configured to generate
1557 * non maskable interrupt(NMI) using the API XMC_SCU_INTERRUPT_EnableNmiRequest().
1558 * \par<b>Related APIs:</b><BR>
1559 * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_PARITY_DisableTrapGeneration() \n\n\n
1560 */
1561 void XMC_SCU_PARITY_EnableTrapGeneration(const uint32_t memory);
1562
1563 /**
1564 *
1565 * @param memory The on-chip RAM type, for which the parity error trap generation has to be disabled.\n
1566 * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple
1567 * memory types can be combined using the \a OR operation.
1568 *
1569 * @return None
1570 *
1571 * \par<b>Description</b><br>
1572 * Disables the assertion of trap for the parity error source.\n\n
1573 * Trap assertion can be disabled by clearing the respective bit of the RAM type in the \a PETE register.
1574 *
1575 * \par<b>Related APIs:</b><BR>
1576 * XMC_SCU_PARITY_EnableTrapGeneration() \n\n\n
1577 */
1578 void XMC_SCU_PARITY_DisableTrapGeneration(const uint32_t memory);
1579
1580 /**
1581 *
1582 * @return uint32_t Status of parity error detection for the on-chip RAM modules.\n
1583 * \b Range: Use type @ref XMC_SCU_PARITY_t to get the bit mask of each RAM module type.
1584 *
1585 * \par<b>Description</b><br>
1586 * Provides the status of parity error detection for the on-chip RAM modules.\n\n
1587 * Parity error status information is obtained from the \a PEFLAG register.
1588 * If a particular RAM module has parity error, its respective bit field will be set to 1 in the
1589 * returned value. A check for the status of a particular RAM module can be done by
1590 * masking the returned value with the RAM module identifier from the type @ref XMC_SCU_PARITY_t.
1591 * \par<b>Related APIs:</b><BR>
1592 * XMC_SCU_PARITY_ClearStatus() \n\n\n
1593 */
1594 uint32_t XMC_SCU_PARITY_GetStatus(void);
1595
1596 /**
1597 *
1598 * @param memory The on-chip RAM type, for which the parity logic should be overriden.\n
1599 * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple
1600 * memory types can be combined using the \a OR operation.
1601 *
1602 * @return None
1603 *
1604 * \par<b>Description</b><br>
1605 * Enable access to parity bits of SRAM modules for various types of peripherals.
1606 * Enable direct write to parity bits using value selected using XMC_SCU_PARITY_SetParityWriteValue()\n\n
1607 * \par<b>Related APIs:</b><BR>
1608 * XMC_SCU_PARITY_SetParityWriteValue() \n\n\n
1609 *
1610 */
XMC_SCU_PARITY_OverrideParityBitLogic(uint32_t memory)1611 __STATIC_INLINE void XMC_SCU_PARITY_OverrideParityBitLogic(uint32_t memory)
1612 {
1613 SCU_PARITY->MCHKCON = memory;
1614 }
1615
1616 /**
1617 * @param memory The on-chip RAM type, for which the parity test has to be enabled.\n
1618 * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type.
1619 * \b Only a single memory type should be specified.
1620 *
1621 * @return None
1622 *
1623 * \par<b>Description</b><br>
1624 * Selects parity test output from a memory instance that can be inspected using XMC_SCU_PARITY_GetParityReadValue()
1625 * \par<b>Related APIs:</b><BR>
1626 * XMC_SCU_PARITY_GetParityReadValue() \n\n\n
1627 *
1628 */
XMC_SCU_PARITY_SelectMemoryTest(const XMC_SCU_PARITY_t memory)1629 __STATIC_INLINE void XMC_SCU_PARITY_SelectMemoryTest(const XMC_SCU_PARITY_t memory)
1630 {
1631 SCU_PARITY->PMTSR = memory;
1632 }
1633
1634 /**
1635 * @param write_value parity bits value stored with next write access\n
1636 *
1637 * @return None
1638 *
1639 * \par<b>Description</b><br>
1640 * For each byte of a memory module the parity bits corresponding to the next write access are selected here.
1641 *
1642 * \par<b>Related APIs:</b><BR>
1643 * XMC_SCU_PARITY_OverrideParityBitLogic() \n\n\n
1644 *
1645 */
XMC_SCU_PARITY_SetParityWriteValue(uint8_t write_value)1646 __STATIC_INLINE void XMC_SCU_PARITY_SetParityWriteValue(uint8_t write_value)
1647 {
1648 SCU_PARITY->PMTPR = ((write_value << SCU_PARITY_PMTPR_PWR_Pos) & SCU_PARITY_PMTPR_PWR_Msk);
1649 }
1650
1651 /**
1652 * @return parity bits generated during last read access
1653 *
1654 * \par<b>Description</b><br>
1655 * For each byte of a memory module the parity bits generated during the most recent read access can be read.
1656 *
1657 * \par<b>Related APIs:</b><BR>
1658 * XMC_SCU_PARITY_OverrideParityBitLogic() \n\n\n
1659 *
1660 */
XMC_SCU_PARITY_GetParityReadValue(void)1661 __STATIC_INLINE uint8_t XMC_SCU_PARITY_GetParityReadValue(void)
1662 {
1663 return ((SCU_PARITY->PMTPR & SCU_PARITY_PMTPR_PRD_Msk) >> SCU_PARITY_PMTPR_PRD_Pos);
1664 }
1665
1666 /**
1667 *
1668 * @param clock Peripheral for which the clock has to be enabled. \n
1669 * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral.
1670 *
1671 * @return None
1672 *
1673 * \par<b>Description</b><br>
1674 * Enables the source clock for selected peripheral.\n\n
1675 * The various outputs of Clock Generation Unit (CGU) can be individually enabled by setting the peripheral
1676 * specific bit in the \a CLKSET register.\n
1677 * It is recommended to use following steps to verify whether a source clock of peripheral is enabled/disabled:\n
1678 * - Call \a XMC_SCU_CLOCK_EnableClock() with desired peripheral identifier.\n
1679 * - Call \a XMC_SCU_CLOCK_IsClockEnabled() with same peripheral identifier to verify whether the clock is enabled.\n
1680 * \par<b>Related APIs:</b><BR>
1681 * XMC_SCU_CLOCK_DisableClock(), XMC_SCU_RESET_DeassertPeripheralReset() \n\n\n
1682 */
1683 void XMC_SCU_CLOCK_EnableClock(const XMC_SCU_CLOCK_t clock);
1684
1685 /**
1686 *
1687 * @param clock Peripheral for which the clock has to be disabled. \n
1688 * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral.
1689 *
1690 * @return None
1691 *
1692 * \par<b>Description</b><br>
1693 * Disables source clock for the peripheral selected.\n\n
1694 * The various outputs of Clock Generation Unit (CGU) can be individually disabled by setting the peripheral
1695 * specific bits in the \a CLKCLR register.\n
1696 * It is recommended to use following steps to verify whether clock source of the peripheral is enabled/disabled:\n
1697 * - Call \a XMC_SCU_CLOCK_DisableClock with desired peripheral identifier.\n
1698 * - Call \a XMC_SCU_CLOCK_IsClockEnabled with same peripheral identifier to verify whether peripheral is enabled/disabled.\n
1699 * \par<b>Related APIs:</b><BR>
1700 * XMC_SCU_CLOCK_EnableClock(), XMC_SCU_RESET_AssertPeripheralReset() \n\n\n
1701 */
1702 void XMC_SCU_CLOCK_DisableClock(const XMC_SCU_CLOCK_t clock);
1703
1704 /**
1705 *
1706 * @param clock Peripheral for which the clock status has to be checked. \n
1707 * \b Range: Use type @ref XMC_SCU_CLOCK_t to select the peripheral.
1708 *
1709 * @return bool Status of peripheral clock.\n
1710 * \b Range: \a true if peripheral clock is enabled. \a false if peripheral clock is disabled.
1711 *
1712 * \par<b>Description</b><br>
1713 * Checks the status of peripheral source clock.\n\n
1714 * The status of peripheral source clock is read from the \a CLKSTATn register.
1715 * Returns \a true if clock is enabled and returns \a false otherwise.
1716 * \par<b>Related APIs:</b><BR>
1717 * XMC_SCU_CLOCK_EnableClock(), XMC_SCU_CLOCK_DisableClock() \n\n\n
1718 */
1719 bool XMC_SCU_CLOCK_IsClockEnabled(const XMC_SCU_CLOCK_t clock);
1720
1721 /**
1722 *
1723 * @param source Source of clock for fSYS.\n
1724 * \b Range: Use type @ref XMC_SCU_CLOCK_SYSCLKSRC_t to select the source of clock.\n
1725 * XMC_SCU_CLOCK_SYSCLKSRC_OFI for selecting internal fast clock as fSYS.\n
1726 * XMC_SCU_CLOCK_SYSCLKSRC_PLL for selecting the output of PLL fPLL as fSYS.
1727 *
1728 * @return None
1729 *
1730 * \par<b>Description</b><br>
1731 * Selects the source for system clock (fSYS).\n\n
1732 * System clock is selected by setting \a SYSSEL bits in the \a SYSCLKCR register.
1733 * If \a XMC_SCU_CLOCK_SYSCLKSRC_PLL is selected, then the dividers of the PLL have to be
1734 * additionally configured to achieve the required system clock frequency.
1735 * \par<b>Related APIs:</b><BR>
1736 * XMC_SCU_CLOCK_StartSystemPll(), XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n
1737 */
1738 void XMC_SCU_CLOCK_SetSystemClockSource(const XMC_SCU_CLOCK_SYSCLKSRC_t source);
1739
1740 /**
1741 * @return XMC_SCU_CLOCK_SYSCLKSRC_t Source of clock for fSYS.\n
1742 * \b Range: Use type @ref XMC_SCU_CLOCK_SYSCLKSRC_t to select the source of clock.\n
1743 * XMC_SCU_CLOCK_SYSCLKSRC_OFI - internal fast clock selected as fSYS.\n
1744 * XMC_SCU_CLOCK_SYSCLKSRC_PLL - output of PLL fPLL selected as fSYS.
1745 *
1746 * \par<b>Description</b><br>
1747 * Provides the selected source of system clock (fSYS). \n\n
1748 * Selected source of fSYS is obtained by reading \a SYSSEL bits of \a SYSCLKCR register.
1749 * \par<b>Related APIs:</b><BR>
1750 * XMC_SCU_CLOCK_SetSystemClockSource(), XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency() \n\n\n
1751 */
XMC_SCU_CLOCK_GetSystemClockSource(void)1752 __STATIC_INLINE XMC_SCU_CLOCK_SYSCLKSRC_t XMC_SCU_CLOCK_GetSystemClockSource(void)
1753 {
1754 return (XMC_SCU_CLOCK_SYSCLKSRC_t)(SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk);
1755 }
1756
1757 /**
1758 *
1759 * @param source Source of clock for USB and SDMMC(fUSB/SDMMC).\n
1760 * \b Range: Use type @ref XMC_SCU_CLOCK_USBCLKSRC_t to select the source of clock.\n
1761 * XMC_SCU_CLOCK_USBCLKSRC_USBPLL - output of USB PLL as source of USB clock(fUSB/SDMMC).\n
1762 * XMC_SCU_CLOCK_USBCLKSRC_SYSPLL - output of PLL fPLL as source of USB clock(fUSB/SDMMC).
1763 *
1764 * @return None
1765 *
1766 * \par<b>Description</b><br>
1767 * Selects the source of USB/SDMMC clock (fUSB/SDMMC).\n\n
1768 * USB and SDMMC use a common clock source. They can either use fUSB PLL or fPLL as the source of clock.
1769 * The selection is done by configuring the \a USBSEL bits of \a USBCLKCR register.
1770 * \par<b>Related APIs:</b><BR>
1771 * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n
1772 */
1773 void XMC_SCU_CLOCK_SetUsbClockSource(const XMC_SCU_CLOCK_USBCLKSRC_t source);
1774
1775 /**
1776 * @return XMC_SCU_CLOCK_USBCLKSRC_t Source of clock for USB and SDMMC(fUSB/SDMMC).\n
1777 * \b Range: Use type @ref XMC_SCU_CLOCK_USBCLKSRC_t to identify the source of clock.\n
1778 * XMC_SCU_CLOCK_USBCLKSRC_USBPLL - output of USB PLL is selected as source of USB clock(fUSB/SDMMC).\n
1779 * XMC_SCU_CLOCK_USBCLKSRC_SYSPLL - output of PLL fPLL is selected as source of USB clock(fUSB/SDMMC).
1780 *
1781 * \par<b>Description</b><br>
1782 * Provides the selected source of USB and SDMMC clock frequency.\n\n
1783 * The clock source is read from from the \a USBSEL bits of \a USBCLKCR register.
1784 * \par<b>Related APIs:</b><BR>
1785 * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n
1786 */
XMC_SCU_CLOCK_GetUsbClockSource(void)1787 __STATIC_INLINE XMC_SCU_CLOCK_USBCLKSRC_t XMC_SCU_CLOCK_GetUsbClockSource(void)
1788 {
1789 return (XMC_SCU_CLOCK_USBCLKSRC_t)(SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk);
1790 }
1791
1792 /**
1793 *
1794 * @param source Clock source for watchdog timer.\n
1795 * \b Range: Use type XMC_SCU_CLOCK_WDTCLKSRC_t to identify the clock source.\n
1796 * XMC_SCU_CLOCK_WDTCLKSRC_OFI - internal fast oscillator (fOFI)\n
1797 * XMC_SCU_CLOCK_WDTCLKSRC_STDBY - backup standby clock (fSTDBY)\n
1798 * XMC_SCU_CLOCK_WDTCLKSRC_PLL - PLL output clock (fPLL)
1799 *
1800 * @return None
1801 *
1802 * \par<b>Description</b><br>
1803 * Selects the source of WDT clock (fWDT).\n\n
1804 * The selected value is configured to the \a WDTSEL bits of \a WDTCLKCR register.
1805 * The watchdog timer counts at the frequency selected using this API. So the time for
1806 * timeout or pre-warning of watchdog has to be calculated based on this selection.
1807 *
1808 * \par<b>Related APIs:</b><BR>
1809 * XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_GetWdtClockFrequency() \n\n\n
1810 */
1811 void XMC_SCU_CLOCK_SetWdtClockSource(const XMC_SCU_CLOCK_WDTCLKSRC_t source);
1812
1813 /**
1814 * @return XMC_SCU_CLOCK_WDTCLKSRC_t Clock source configured for watchdog timer.\n
1815 * \b Range: Use type XMC_SCU_CLOCK_WDTCLKSRC_t to identify the clock source.\n
1816 * XMC_SCU_CLOCK_WDTCLKSRC_OFI - internal fast oscillator (fOFI)\n
1817 * XMC_SCU_CLOCK_WDTCLKSRC_STDBY - backup standby clock (fSTDBY)\n
1818 * XMC_SCU_CLOCK_WDTCLKSRC_PLL - PLL output clock (fPLL)
1819 *
1820 * \par<b>Description</b><br>
1821 * Provides the source of clock used for watchdog timer.\n\n
1822 * The value is obtained by reading \a WDTSEL bits of \a WDTCLKCR register.
1823 * The time for timeout or pre-warning of watchdog has to be calculated based on
1824 * the clock source selected.
1825 * \par<b>Related APIs:</b><BR>
1826 * XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetWdtClockSource() \n\n\n
1827 */
XMC_SCU_CLOCK_GetWdtClockSource(void)1828 __STATIC_INLINE XMC_SCU_CLOCK_WDTCLKSRC_t XMC_SCU_CLOCK_GetWdtClockSource(void)
1829 {
1830 return (XMC_SCU_CLOCK_WDTCLKSRC_t)(SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTSEL_Msk);
1831 }
1832
1833 /**
1834 *
1835 * @param source Source for standby clock.\n
1836 * \b Range: Use type @ref XMC_SCU_HIB_STDBYCLKSRC_t to identify the clock source.\n
1837 * XMC_SCU_HIB_STDBYCLKSRC_OSI - internal slow oscillator (fOSI) \n
1838 * XMC_SCU_HIB_STDBYCLKSRC_OSCULP - ultra low power osciallator (fULP) \n
1839 *
1840 * @return None
1841 *
1842 * \par<b>Description</b><br>
1843 * Selects the source of Standby clock (fSTDBY).\n\n
1844 * Clock source is configured by setting the \a STDBYSEL bits of \a HDCR register.
1845 * Hibernate domain should be enabled explicitly before using the API.
1846 *
1847 * \note
1848 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
1849 *
1850 * \par<b>Related APIs:</b><BR>
1851 * XMC_SCU_HIB_GetStdbyClockSource(), XMC_SCU_HIB_EnableHibernateDomain() \n\n\n
1852 */
1853 void XMC_SCU_HIB_SetStandbyClockSource(const XMC_SCU_HIB_STDBYCLKSRC_t source);
1854
1855 /**
1856 * @return XMC_SCU_HIB_RTCCLKSRC_t Source clock of standby clock(fSTDBY).\n
1857 * \b Range: Use type @ref XMC_SCU_HIB_STDBYCLKSRC_t to identify the clock source.\n
1858 * XMC_SCU_HIB_STDBYCLKSRC_OSI - internal slow oscillator (fOSI) \n
1859 * XMC_SCU_HIB_STDBYCLKSRC_OSCULP - ultra low power osciallator (fULP) \n
1860 *
1861 * \par<b>Description</b><br>
1862 * Provides the source of standby clock (fSTDBY).\n\n
1863 * The value is obtained by reading \a STDBYSEL bits of \a HDCR register.\n
1864 * \par<b>Related APIs:</b><BR>
1865 * XMC_SCU_HIB_SetStandbyClockSource(), XMC_SCU_HIB_EnableHibernateDomain() \n\n\n
1866 */
XMC_SCU_HIB_GetStdbyClockSource(void)1867 __STATIC_INLINE XMC_SCU_HIB_RTCCLKSRC_t XMC_SCU_HIB_GetStdbyClockSource(void)
1868 {
1869 return (XMC_SCU_HIB_RTCCLKSRC_t)(SCU_HIBERNATE->HDCR & SCU_HIBERNATE_HDCR_STDBYSEL_Msk);
1870 }
1871
1872 /**
1873 *
1874 * @param source Source of RTC clock.\n
1875 * \b Range: Use type @ref XMC_SCU_HIB_RTCCLKSRC_t to identify the clock source.\n
1876 * XMC_SCU_HIB_RTCCLKSRC_OSI - internal slow oscillator(fOSI). \n
1877 * XMC_SCU_HIB_RTCCLKSRC_ULP - ultra low power oscillator(fULP). \n
1878 *
1879 * @return None
1880 *
1881 * \par<b>Description</b><br>
1882 * Selects the source of RTC clock (fRTC).\n\n
1883 * The value is configured to \a RCS bit of \a HDCR register.
1884 * fULP needs external input powered by VBAT or VDDP. fOSI is internal clock.
1885 * The frequency of the clock will be 32.768 kHz.
1886 *
1887 * \note
1888 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
1889 *
1890 * \par<b>Related APIs:</b><BR>
1891 * XMC_SCU_HIB_GetRtcClockSource() \n\n\n
1892 */
1893 void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source);
1894
1895 /**
1896 * @return XMC_SCU_HIB_RTCCLKSRC_t Source of RTC clock.\n
1897 * \b Range: Use type @ref XMC_SCU_HIB_RTCCLKSRC_t to identify the clock source.\n
1898 * XMC_SCU_HIB_RTCCLKSRC_OSI - internal slow oscillator(fOSI). \n
1899 * XMC_SCU_HIB_RTCCLKSRC_ULP - ultra low power oscillator(fULP). \n
1900 *
1901 * \par<b>Description</b><br>
1902 * Provides the source of RTC clock (fRTC).
1903 * The value is obtained by reading \a RCS bit of \a HDCR register.
1904 * The frequency of the clock will be 32.768 kHz.
1905 * \par<b>Related APIs:</b><BR>
1906 * XMC_SCU_HIB_SetRtcClockSource() \n\n\n
1907 */
XMC_SCU_HIB_GetRtcClockSource(void)1908 __STATIC_INLINE XMC_SCU_HIB_RTCCLKSRC_t XMC_SCU_HIB_GetRtcClockSource(void)
1909 {
1910 return (XMC_SCU_HIB_RTCCLKSRC_t)(SCU_HIBERNATE->HDCR & SCU_HIBERNATE_HDCR_RCS_Msk);
1911 }
1912
1913 /**
1914 *
1915 * @param clock Source of external clock output(fEXT).\n
1916 * \b Range: Use type @ref XMC_SCU_CLOCK_EXTOUTCLKSRC_t to identify the clock.\n
1917 * XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS - system clock fSYS. \n
1918 * XMC_SCU_CLOCK_EXTOUTCLKSRC_USB - USB clock fUSB. \n
1919 * XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL - PLL output fPLL. \n
1920 * \if XMC42
1921 * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n
1922 *
1923 * \endif
1924 * \if XMC41
1925 * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n
1926 * \endif
1927 *
1928 * @return None
1929 *
1930 * \par<b>Description</b><br>
1931 * Selects the source of external clock out (fEXT).\n\n
1932 * The value will be configured to \a ECKSEL bits of \a EXTCLKCR register.
1933 * \par<b>Related APIs:</b><BR>
1934 * XMC_SCU_CLOCK_GetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n
1935 */
1936 void XMC_SCU_CLOCK_SetExternalOutputClockSource(const XMC_SCU_CLOCK_EXTOUTCLKSRC_t clock);
1937
1938 /**
1939 * @return XMC_SCU_CLOCK_EXTOUTCLKSRC_t Source of external clock output(fEXT).\n
1940 * \b Range: Use type @ref XMC_SCU_CLOCK_EXTOUTCLKSRC_t to identify the clock.\n
1941 * XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS - system clock fSYS. \n
1942 * XMC_SCU_CLOCK_EXTOUTCLKSRC_USB - USB clock fUSB. \n
1943 * XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL - PLL output fPLL. \n
1944 * \if XMC42
1945 * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n
1946 * \endif
1947 * \if XMC41
1948 * XMC_SCU_CLOCK_EXTOUTCLKSRC_STDBY - Standby clock fSTDBY. \n
1949 * \endif
1950 *
1951 * \par<b>Description</b><br>
1952 * Provides the source of external clock output(fEXT).\n\n
1953 * The value is obtained by reading \a ECKSEL bits of \a EXTCLKCR register.
1954 * \par<b>Related APIs:</b><BR>
1955 * XMC_SCU_CLOCK_SetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n
1956 */
XMC_SCU_CLOCK_GetExternalOutputClockSource(void)1957 __STATIC_INLINE XMC_SCU_CLOCK_EXTOUTCLKSRC_t XMC_SCU_CLOCK_GetExternalOutputClockSource(void)
1958 {
1959 return (XMC_SCU_CLOCK_EXTOUTCLKSRC_t)(SCU_CLK->EXTCLKCR & SCU_CLK_EXTCLKCR_ECKSEL_Msk);
1960 }
1961
1962 /**
1963 *
1964 * @param source Source of clock for system PLL.\n
1965 * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t for identifying the clock source.\n
1966 * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP - External High performance oscillator(fOHP).\n
1967 * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI - Internal fast clock (fOFI).
1968 *
1969 * @return None
1970 *
1971 * \par<b>Description</b><br>
1972 * Selects the source of system PLL.\n\n
1973 * The value is configured to \a VCOBYP bit of \a PLLCON0 register.
1974 * If \a XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP is selected, ensure that the high performance oscillator is
1975 * enabled by using the API XMC_SCU_CLOCK_EnableHighPerformanceOscillator().
1976 * \par<b>Related APIs:</b><BR>
1977 * XMC_SCU_CLOCK_EnableHighPerformanceOscillator()\n\n\n
1978 */
1979 void XMC_SCU_CLOCK_SetSystemPllClockSource(const XMC_SCU_CLOCK_SYSPLLCLKSRC_t source);
1980
1981 /**
1982 * @return XMC_SCU_CLOCK_OSCCLKSRC_t Source of clock for system PLL.\n
1983 * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t for identifying the clock source.\n
1984 * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP - External High performance oscillator(fOHP).\n
1985 * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI - Internal fast clock (fOFI).
1986 *
1987 * \par<b>Description</b><br>
1988 * Provides the source of system PLL clock (fPLL). \n\n
1989 * The value is obtained by reading \a VCOBYP bit of \a PLLCON0 register.
1990 * \par<b>Related APIs:</b><BR>
1991 * XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_SetSystemPllClockSource()\n\n\n
1992 */
XMC_SCU_CLOCK_GetSystemPllClockSource(void)1993 __STATIC_INLINE XMC_SCU_CLOCK_SYSPLLCLKSRC_t XMC_SCU_CLOCK_GetSystemPllClockSource(void)
1994 {
1995 return (XMC_SCU_CLOCK_SYSPLLCLKSRC_t)(SCU_PLL->PLLCON0 & SCU_PLL_PLLCON0_VCOBYP_Msk);
1996 }
1997
1998 #if defined(ECAT0)
1999 /**
2000 *
2001 * @param source Source of ECAT clock.\n
2002 * \b Range: Use type @ref XMC_SCU_CLOCK_ECATCLKSRC_t to identify the clock source.\n
2003 * XMC_SCU_CLOCK_ECATCLKSRC_USBPLL - USB PLL (fUSBPLL) as a source for ECAT clock. \n
2004 * XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL - Main PLL output (fPLL) as a source for ECAT clock. \n
2005 *
2006 * @return None
2007 *
2008 * \par<b>Description</b><br>
2009 * Selects the source of ECAT clock (fECAT).\n\n
2010 * The value is configured to \a ECATSEL bit of \a ECATCLKCR register.
2011 * \par<b>Related APIs:</b><BR>
2012 * XMC_SCU_CLOCK_GetECATClockSource() \n\n\n
2013 */
XMC_SCU_CLOCK_SetECATClockSource(const XMC_SCU_CLOCK_ECATCLKSRC_t source)2014 __STATIC_INLINE void XMC_SCU_CLOCK_SetECATClockSource(const XMC_SCU_CLOCK_ECATCLKSRC_t source)
2015 {
2016 SCU_CLK->ECATCLKCR = (SCU_CLK->ECATCLKCR & ((uint32_t)~SCU_CLK_ECATCLKCR_ECATSEL_Msk)) |
2017 ((uint32_t)source);
2018 }
2019
2020 /**
2021 * @return XMC_SCU_CLOCK_ECATCLKSRC_t Source of ECAT clock.\n
2022 * \b Range: Use type @ref XMC_SCU_CLOCK_ECATCLKSRC_t to identify the clock source.\n
2023 * XMC_SCU_CLOCK_ECATCLKSRC_USBPLL - USB PLL (fUSBPLL) as a source for ECAT clock. \n
2024 * XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL - Main PLL output (fPLL) as a source for ECAT clock. \n
2025 *
2026 * \par<b>Description</b><br>
2027 * Provides the source of ECAT clock (fECAT).
2028 * The value is obtained by reading \a ECATSEL bit of \a ECATCLKCR register.
2029 * \par<b>Related APIs:</b><BR>
2030 * XMC_SCU_HIB_SetRtcClockSource() \n\n\n
2031 */
XMC_SCU_CLOCK_GetECATClockSource(void)2032 __STATIC_INLINE XMC_SCU_CLOCK_ECATCLKSRC_t XMC_SCU_CLOCK_GetECATClockSource(void)
2033 {
2034 return (XMC_SCU_CLOCK_ECATCLKSRC_t)((SCU_CLK->ECATCLKCR & SCU_CLK_ECATCLKCR_ECATSEL_Msk) >> SCU_CLK_ECATCLKCR_ECATSEL_Pos);
2035 }
2036 #endif
2037
2038 /**
2039 *
2040 * @param divider Ratio of fSYS clock source to the value of fSYS.
2041 * \b Range: 1 to 256.
2042 *
2043 * @return None
2044 *
2045 * \par<b>Description</b><br>
2046 * Configures the ratio of system clock source to the value of system clock frequency.\n\n
2047 * The value is configured as \a SYSDIV bits of \a SYSCLKCR register. The divider value is
2048 * decremented by 1 before configuring.
2049 * \par<b>Related APIs:</b><BR>
2050 * XMC_SCU_CLOCK_GetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n
2051 */
2052 void XMC_SCU_CLOCK_SetSystemClockDivider(const uint32_t divider);
2053
2054 /**
2055 * @return uint32_t Ratio of fSYS clock source to the value of fSYS.
2056 * \b Range: 0 to 255.
2057 *
2058 * \par<b>Description</b><br>
2059 * Provides the value of ratio between the source of system clock to the the value of system clock frequency. \n\n
2060 * The value is obtained by reading \a SYSDIV bits of \a SYSCLKCR register.
2061 * \par<b>Related APIs:</b><BR>
2062 * XMC_SCU_CLOCK_SetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n
2063 */
XMC_SCU_CLOCK_GetSystemClockDivider(void)2064 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetSystemClockDivider(void)
2065 {
2066 return (uint32_t)((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) >> SCU_CLK_SYSCLKCR_SYSDIV_Pos);
2067 }
2068
2069 /**
2070 *
2071 * @param ratio Ratio of fCCU clock source to the value of fCCU.
2072 * \b Range: 1 or 2.\n
2073 * 1-> fCCU= fSYS \n
2074 * 2-> fCCU= fSYS/2.
2075 *
2076 * @return None
2077 *
2078 * \par<b>Description</b><br>
2079 * Configures the divider for CCU clock source. \n\n
2080 * Capture compare unit(CCU) can take either fSYS or fSYS/2 as the source of clock.
2081 * The configuration is set to \a CCUDIV bit of \a CCUCLKCR register. The CCUDIV bit is 1 bit wide.
2082 *
2083 * \par<b>Related APIs:</b><BR>
2084 * XMC_SCU_CLOCK_GetCcuClockDivider() \n\n\n
2085 */
2086 void XMC_SCU_CLOCK_SetCcuClockDivider(const uint32_t ratio);
2087
2088 /**
2089 * @return uint32_t Ratio of fCCU clock source to the value of fCCU.
2090 * \b Range: 0 or 1.\n
2091 * 0-> fCCU= fSYS \n
2092 * 1-> fCCU= fSYS/2.
2093 *
2094 * \par<b>Description</b><br>
2095 * Provides the ratio of CCU clock(fCCU) to system clock(fSYS).\n\n
2096 * The value is obtained by reading \a CCUDIV bit of \a CCUCLKCR register.
2097 *
2098 * \par<b>Related APIs:</b><BR>
2099 * XMC_SCU_CLOCK_SetCcuClockDivider() \n\n\n
2100 */
XMC_SCU_CLOCK_GetCcuClockDivider(void)2101 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCcuClockDivider(void)
2102 {
2103 return (uint32_t)((SCU_CLK->CCUCLKCR & SCU_CLK_CCUCLKCR_CCUDIV_Msk) >> SCU_CLK_CCUCLKCR_CCUDIV_Pos);
2104 }
2105
2106 /**
2107 *
2108 * @param ratio Ratio between system clock(fSYS) and CPU clock(fCPU).
2109 * \b Range: 1 or 2.\n
2110 * 1-> fCPU= fSYS. \n
2111 * 2-> fCPU= fSYS/2.
2112 *
2113 * @return None
2114 *
2115 * \par<b>Description</b><br>
2116 * Configures the CPU clock by setting the divider value for the system clock. \n\n
2117 * The value is set to the \a CPUDIV bit of \a CPUCLKCR register.
2118 * \par<b>Related APIs:</b><BR>
2119 * XMC_SCU_CLOCK_GetCpuClockDivider() \n\n\n
2120 */
2121 void XMC_SCU_CLOCK_SetCpuClockDivider(const uint32_t ratio);
2122
2123 /**
2124 * @return uint32_t Ratio between system clock(fSYS) and CPU clock(fCPU).
2125 * \b Range: 0 or 1.\n
2126 * 0-> fCPU= fSYS. \n
2127 * 1-> fCPU= fSYS/2.
2128 *
2129 * \par<b>Description</b><br>
2130 * Provides the ratio between system clock(fSYS) and CPU clock(fCPU). \n\n
2131 * The value is obtained by reading \a CPUDIV bit of \a CPUCLKCR register.
2132 * \par<b>Related APIs:</b><BR>
2133 * XMC_SCU_CLOCK_SetCpuClockDivider() \n\n\n
2134 */
XMC_SCU_CLOCK_GetCpuClockDivider(void)2135 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockDivider(void)
2136 {
2137 return (uint32_t)((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) >> SCU_CLK_CPUCLKCR_CPUDIV_Pos);
2138 }
2139
2140 /**
2141 *
2142 * @param ratio Ratio of peripheral clock source to the value of peripheral clock.\n
2143 * \b Range: 1 or 2.\n
2144 * 1-> fPERIPH= fCPU.\n
2145 * 2-> fPERIPH= fCPU/2.
2146 *
2147 * @return None
2148 *
2149 * \par<b>Description</b><br>
2150 * Configures the peripheral clock by setting the divider for CPU clock(fCPU).\n\n
2151 * The peripheral clock can be equal to either fCPU or fCPU/2. The value is configured to \a PBDIV bit of \a PBCLKCR register.
2152 *
2153 * \par<b>Related APIs:</b><BR>
2154 * XMC_SCU_CLOCK_GetPeripheralClockDivider() \n\n\n
2155 */
2156 void XMC_SCU_CLOCK_SetPeripheralClockDivider(const uint32_t ratio);
2157
2158 /**
2159 * @return uint32_t Ratio of peripheral clock source to the value of peripheral clock.\n
2160 * \b Range: 0 or 1.\n
2161 * 0-> fPERIPH= fCPU.\n
2162 * 1-> fPERIPH= fCPU/2.
2163 *
2164 * \par<b>Description</b><br>
2165 * Provides the ratio of CPU clock(fCPU) to peripheral clock(fPERIPH).\n\n
2166 * The value is obtained by reading \a PBDIV bit of \a PBCLKCR register.
2167 * \par<b>Related APIs:</b><BR>
2168 * XMC_SCU_CLOCK_SetPeripheralClockDivider() \n\n\n
2169 */
XMC_SCU_CLOCK_GetPeripheralClockDivider(void)2170 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetPeripheralClockDivider(void)
2171 {
2172 return (uint32_t)((SCU_CLK->PBCLKCR & SCU_CLK_PBCLKCR_PBDIV_Msk) >> SCU_CLK_PBCLKCR_PBDIV_Pos);
2173 }
2174
2175 /**
2176 *
2177 * @param ratio Ratio of PLL output clock(fPLL) to USB clock(fUSB).
2178 * \b Range: 1 to 8.
2179 *
2180 * @return None
2181 *
2182 * \par<b>Description</b><br>
2183 * Configures the USB clock(fUSB) by setting the USB clock divider. \n\n
2184 * The value is decremented by 1 before setting it to \a USBDIV bits of \a USBCLKCR register.
2185 *
2186 * \par<b>Related APIs:</b><BR>
2187 * XMC_SCU_CLOCK_GetUsbClockDivider(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n
2188 */
2189 void XMC_SCU_CLOCK_SetUsbClockDivider(const uint32_t ratio);
2190
2191 /**
2192 *
2193 * @return uint32_t Ratio of PLL output clock(fPLL) to USB clock(fUSB).
2194 * \b Range: 0 to 7.
2195 *
2196 * \par<b>Description</b><br>
2197 * Provides the ratio between PLL output frequency(fPLL) and USB clock(fUSB).\n\n
2198 * The value is obtained by reading \a USBDIV bit of \a USBCLKCR register.
2199 * \par<b>Related APIs:</b><BR>
2200 * XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbClockSource() \n\n\n
2201 */
XMC_SCU_CLOCK_GetUsbClockDivider(void)2202 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetUsbClockDivider(void)
2203 {
2204 return (uint32_t)((SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBDIV_Msk) >> SCU_CLK_USBCLKCR_USBDIV_Pos);
2205 }
2206
2207
2208
2209 #if defined(EBU)
2210 /**
2211 *
2212 * @param ratio Ratio of PLL clock(fPLL) to EBU clock(fEBU).\n
2213 * \b Range: 1 to 64.
2214 *
2215 * @return None
2216 *
2217 * \par<b>Description</b><br>
2218 * Configures the EBU clock(fEBU) by setting the divider value.\n\n
2219 * The clock divider is configured to the \a EBUDIV bits of \a EBUCLKCR register.
2220 * \par<b>Related APIs:</b><BR>
2221 * XMC_SCU_CLOCK_GetEbuClockDivider() \n\n\n
2222 */
2223 void XMC_SCU_CLOCK_SetEbuClockDivider(const uint32_t ratio);
2224
2225 /**
2226 *
2227 * @return uint32_t Ratio of PLL clock(fPLL) to EBU clock(fEBU).\n
2228 * \b Range: 0 to 63.
2229 *
2230 * \par<b>Description</b><br>
2231 * Provides the ratio between PLL clock(fPLL) and EBU clock(fEBU).\n\n
2232 * The value is obtained by reading \a EBUDIV bits of \a EBUCLKCR register.
2233 * \par<b>Related APIs:</b><BR>
2234 * XMC_SCU_CLOCK_SetEbuClockDivider() \n\n\n
2235 */
XMC_SCU_CLOCK_GetEbuClockDivider(void)2236 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetEbuClockDivider(void)
2237 {
2238 return (uint32_t)((SCU_CLK->EBUCLKCR & SCU_CLK_EBUCLKCR_EBUDIV_Msk) >> SCU_CLK_EBUCLKCR_EBUDIV_Pos);
2239 }
2240 #endif
2241
2242 /**
2243 *
2244 * @param ratio Ratio between the source of WDT clock and the WDT clock.\n
2245 * \b Range: 1 to 256.
2246 *
2247 * @return None
2248 *
2249 * \par<b>Description</b><br>
2250 * Configures the WDT clock by setting the clock divider for the WDT clock source.\n\n
2251 * The value is configured to \a WDTDIV bits of \a WDTCLKCR register. The value of divider
2252 * is decremented by 1 before configuring. Check the selected clock source for the WDT clock
2253 * before configuring the divider using the API XMC_SCU_CLOCK_SetWdtClockSource().
2254 * \par<b>Related APIs:</b><BR>
2255 * XMC_SCU_CLOCK_SetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider() \n\n\n
2256 */
2257 void XMC_SCU_CLOCK_SetWdtClockDivider(const uint32_t ratio);
2258
2259 /**
2260 *
2261 * @return uint32_t Ratio between the source of WDT clock and the WDT clock.\n
2262 * \b Range: 0 to 255.
2263 *
2264 * \par<b>Description</b><br>
2265 * Provides the ratio between the WDT parent clock and the WDT clock. \n\n
2266 * The value is obtained by reading \a WDTDIV bits of \a WDTCLKCR register.
2267 * Ensure that the WDT parent clock is considered before using the value of
2268 * the divider value.
2269 * \par<b>Related APIs:</b><BR>
2270 * XMC_SCU_CLOCK_SetWdtClockSource(), XMC_SCU_CLOCK_SetWdtClockDivider() \n\n\n
2271 */
XMC_SCU_CLOCK_GetWdtClockDivider(void)2272 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetWdtClockDivider(void)
2273 {
2274 return (uint32_t)((SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTDIV_Msk) >> SCU_CLK_WDTCLKCR_WDTDIV_Pos);
2275 }
2276
2277 /**
2278 *
2279 * @param ratio Ratio between the external output parent clock selected and the output clock.\n
2280 * \b Range: 1 to 512.
2281 *
2282 * @return None
2283 *
2284 * \par<b>Description</b><br>
2285 * Configures the external output clock by setting the divider value for the parent clock. \n\n
2286 * The value will be configured to \a ECKDIV bits of \a EXTCLKCR register.
2287 * The divider value is decremented by 1 before storing it to the bit fields.
2288 * Ensure that the source of external output clock is configured appropriately using the API
2289 * XMC_SCU_CLOCK_SetExternalOutputClockSource().
2290 * \par<b>Related APIs:</b><BR>
2291 * XMC_SCU_CLOCK_SetExternalOutputClockSource(), XMC_SCU_CLOCK_GetExternalOutputClockDivider() \n\n\n
2292 */
2293 void XMC_SCU_CLOCK_SetExternalOutputClockDivider(const uint32_t ratio);
2294
2295 /**
2296 *
2297 * @return uint32_t Ratio between the external output parent clock selected and the output clock.\n
2298 * \b Range: 0 to 511.
2299 *
2300 * \par<b>Description</b><br>
2301 * Provides the divider value applied on parent clock before the generation of external output clock. \n\n
2302 * The value is obtained by reading \a EXTDIV bit of \a EXTCLKCR register.
2303 * \par<b>Related APIs:</b><BR>
2304 * XMC_SCU_CLOCK_GetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider() \n\n\n
2305 */
XMC_SCU_CLOCK_GetExternalOutputClockDivider(void)2306 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetExternalOutputClockDivider(void)
2307 {
2308 return (uint32_t)((SCU_CLK->EXTCLKCR & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> SCU_CLK_EXTCLKCR_ECKDIV_Pos);
2309 }
2310
2311 #if defined(ECAT0)
2312 /**
2313 *
2314 * @param ratio Ratio between the source of ECAT clock and the ECAT clock.\n
2315 * \b Range: 1 to 4.
2316 *
2317 * @return None
2318 *
2319 * \par<b>Description</b><br>
2320 * Configures the ECAT clock by setting the clock divider for the ECAT clock source.\n\n
2321 * The value is configured to \a ECADIV bits of \a ECATCLKCR register. The value of divider
2322 * is decremented by 1 before configuring.
2323 * \par<b>Related APIs:</b><BR>
2324 * XMC_SCU_CLOCK_SetECATClockSource(), XMC_SCU_CLOCK_GetECATClockDivider() \n\n\n
2325 */
2326 void XMC_SCU_CLOCK_SetECATClockDivider(const uint32_t divider);
2327
2328 /**
2329 *
2330 * @return uint32_t Ratio between the source of ECAT clock and the ECAT clock.\n
2331 * \b Range: 0 to 3.
2332 *
2333 * \par<b>Description</b><br>
2334 * Provides the ratio between the ECAT parent clock and the ECAT clock. \n\n
2335 * The value is obtained by reading \a ECADIV bits of \a ECATCLKCR register.
2336 * \par<b>Related APIs:</b><BR>
2337 * XMC_SCU_CLOCK_SetECATClockSource(), XMC_SCU_CLOCK_SetECATClockDivider() \n\n\n
2338 */
XMC_SCU_CLOCK_GetECATClockDivider(void)2339 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetECATClockDivider(void)
2340 {
2341 return (uint32_t)((SCU_CLK->ECATCLKCR & SCU_CLK_ECATCLKCR_ECADIV_Msk) >> SCU_CLK_ECATCLKCR_ECADIV_Pos);
2342 }
2343 #endif
2344
2345 /**
2346 *
2347 * @return None
2348 *
2349 * \par<b>Description</b><br>
2350 * Enables the high precision oscillator by configuring external crystal mode.\n\n
2351 * The API configures \a MODE bits of \a OSCHPCTRL register to 0, there by configuring the
2352 * external clock input.
2353 * The System Oscillator Watchdog is enabled. The user should check the status
2354 * of the oscillator using XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable()
2355 * \par<b>Related APIs:</b><BR>
2356 * XMC_SCU_CLOCK_DisableHighPerformanceOscillator() \n\n\n
2357 */
2358 void XMC_SCU_CLOCK_EnableHighPerformanceOscillator(void);
2359
2360 /**
2361 * @return None
2362 *
2363 * \par<b>Description</b><br>
2364 * Disables the high precision oscillator by disabling the external oscillator.\n\n
2365 * The API configures \a MODE bits of \a OSCHPCTRL register to 1, there by disabling the
2366 * external oscillator.
2367 * \par<b>Related APIs:</b><BR>
2368 * XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n
2369 */
2370 void XMC_SCU_CLOCK_DisableHighPerformanceOscillator(void);
2371
2372 /**
2373 *
2374 * @return Status of high performance oscillator
2375 *
2376 * \par<b>Description</b><br>
2377 * Checks if the OSC_HP oscillator is stable and usable
2378 * \par<b>Related APIs:</b><BR>
2379 * XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n
2380 */
2381 bool XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable(void);
2382
2383 /**
2384 *
2385 * @return None
2386 *
2387 * \par<b>Description</b><br>
2388 * Enables XTAL1 input of OSC_ULP as general purpose input.
2389 * Use XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus to monitor the status of OSC_HP XTAL1 pin.
2390 * @Note OSC_ULP should be disabled previously using XMC_SCU_CLOCK_DisableHighPerformanceOscillator().
2391 * \par<b>Related APIs:</b><BR>
2392 * XMC_SCU_CLOCK_DisableHighPerformanceOscillator() \n\n\n
2393 */
2394 void XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(void);
2395
2396 /**
2397 *
2398 * @return None
2399 *
2400 * \par<b>Description</b><br>
2401 * Disables XTAL1 input of OSC_ULP as general purpose input.
2402 * \par<b>Related APIs:</b><BR>
2403 * XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput() \n\n\n
2404 */
2405 void XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(void);
2406
2407 /**
2408 *
2409 * @return Status OSC_HP XTAL1 pin
2410 *
2411 * \par<b>Description</b><br>
2412 * Monitor the status of OSC_HP XTAL1 pin.
2413 * \par<b>Related APIs:</b><BR>
2414 * XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput() \n\n\n
2415 */
2416 uint32_t XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus(void);
2417
2418 /**
2419 *
2420 * @return None
2421 *
2422 * \par<b>Description</b><br>
2423 * Enables ultra low power oscillator(ULP). \n\n
2424 * It enables the hibernate domain, configures the ultra low power oscillator
2425 * uisng the \a MODE bits of the \a OSCULCTRL register. The \a Mode bits will be
2426 * reset to 0 to enable the low power oscillator. Mirror register update delays
2427 * are handled internally.
2428 * The OSC_ULP Oscillator Watchdog is enabled. The user should check the status
2429 * of the oscillator using XMC_SCU_CLOCK_IsLowPowerOscillatorStable()
2430 * \par<b>Related APIs:</b><BR>
2431 * XMC_SCU_CLOCK_DisableLowPowerOscillator()
2432 * XMC_SCU_CLOCK_IsLowPowerOscillatorStable() \n\n\n
2433 */
2434 void XMC_SCU_CLOCK_EnableLowPowerOscillator(void);
2435
2436 /**
2437 *
2438 * @return None
2439 *
2440 * \par<b>Description</b><br>
2441 * Disables ultra low power oscillator.\n\n
2442 * It is disabled by setting the \a MODE bits of \a OSCULCTRL register to value 2.
2443 * By default on power up, the ultra low power osciallator is disabled.
2444 * \par<b>Related APIs:</b><BR>
2445 * XMC_SCU_CLOCK_EnableLowPowerOscillator() \n\n\n
2446 */
2447 void XMC_SCU_CLOCK_DisableLowPowerOscillator(void);
2448
2449 /**
2450 *
2451 * @return Status of low power oscillator
2452 *
2453 * \par<b>Description</b><br>
2454 * Checks if the OSC_ULP oscillator is stable and usable
2455 * \par<b>Related APIs:</b><BR>
2456 * XMC_SCU_CLOCK_EnableLowPowerOscillator() \n\n\n
2457 */
2458 bool XMC_SCU_CLOCK_IsLowPowerOscillatorStable(void);
2459
2460 /**
2461 *
2462 * @return None
2463 *
2464 * \par<b>Description</b><br>
2465 * Enables XTAL1 input of OSC_ULP as general purpose input.
2466 * Use XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus to monitor the status of OSC_ULP XTAL1 pin.
2467 * @Note OSC_ULP should be disabled previously using XMC_SCU_CLOCK_DisableLowPowerOscillator().
2468 *
2469 * \note
2470 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
2471 *
2472 * \par<b>Related APIs:</b><BR>
2473 * XMC_SCU_CLOCK_DisableLowPowerOscillator() \n\n\n
2474 */
2475 void XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(void);
2476
2477 /**
2478 *
2479 * @return None
2480 *
2481 * \par<b>Description</b><br>
2482 * Disables XTAL1 input of OSC_ULP as general purpose input.
2483 * \par<b>Related APIs:</b><BR>
2484 *
2485 * \note
2486 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
2487 *
2488 * XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput() \n\n\n
2489 */
2490 void XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(void);
2491
2492 /**
2493 *
2494 * @return Status OSC_ULP XTAL1 pin
2495 *
2496 * \par<b>Description</b><br>
2497 * Monitor the status of OSC_ULP XTAL1 pin.
2498 * \par<b>Related APIs:</b><BR>
2499 * XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput() \n\n\n
2500 */
2501 uint32_t XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus(void);
2502
2503 /**
2504 *
2505 * @return uint32_t System frequency in Hertz.\n
2506 * \b Range: clock frequency in Hertz. Range of the value depends on the source clock frequency
2507 * and the configured values of dividers.
2508 *
2509 * \par<b>Description</b><br>
2510 * Provides the value of system PLL output clock frequency(fPLL).\n\n
2511 * The API uses \a N-DIV, \a P-DIV, \a K1-DIV, \a K2-DIV bits information from \a PLLCON1 register and
2512 * VCOBYP bit information from \a PLLCON0 register. It calculates frequency of system pll clock using following formula:
2513 * If normal Mode : fPLL = (fOSC * N)/(P * K2).
2514 * If prescaler mode: fPLL = fOSC/ K1.
2515 * \par<b>Related APIs:</b><BR>
2516 * XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n
2517 */
2518 uint32_t XMC_SCU_CLOCK_GetSystemPllClockFrequency(void);
2519
2520 /**
2521 *
2522 * @return uint32_t Source clock used for deriving system clock.\n
2523 * \b Range: fOHP frequency if external high precision frequency is used. \n
2524 * fOFI fast internal clock frequency.
2525 *
2526 * \par<b>Description</b><br>
2527 * Provides the value of the input clock frequency for deriving the system clock.
2528 * The API retrieves frequency of system PLL input clock (fPLLin).
2529 * Based on \a PINSEL bits information from \a PLLCON2 register, the parent clock source is obtained.
2530 * This bit field specifies if fOHP or fOFI is used for deriving system clock.
2531 * System clock frequency is obtained by dividing the source clock frequency with different divider values.
2532 * \par<b>Related APIs:</b><BR>
2533 * XMC_SCU_CLOCK_GetSystemPllClockFrequency() \n\n\n
2534 */
2535 uint32_t XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(void);
2536
2537 /**
2538 *
2539 * @return uint32_t USB PLL output clock frequency.
2540 *
2541 * \par<b>Description</b><br>
2542 * Provides the frequency of USB PLL output clock (fUSBPLL).\n\n
2543 * It obtains the \a VCOBYP bits information from \a USBPLLCON register and decides if USB PLL mode is used.
2544 * If USB PLL mode is used, the USB clock frequency is obtained by dividing the source clock by USB PLL dividers.\n
2545 * The frequency is obtained using following formula:\n
2546 * If Normal Mode : fUSBPLL = (fOSC * N)/(P * 2).\n
2547 * If Prescaler mode: fPLL = fOSC.
2548 * \par<b>Related APIs:</b><BR>
2549 * XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency() \n\n\n
2550 */
2551 uint32_t XMC_SCU_CLOCK_GetUsbPllClockFrequency(void);
2552
2553 /**
2554 *
2555 * @return uint32_t System clock frequency in Hertz.
2556 *
2557 * \par<b>Description</b><br>
2558 * Provides the frequency of system clock (fSYS).\n\n
2559 * The value obtained by dividing \a CPUDIV bits information of \a CPUCLKCR register with SystemCoreClock (fCPU) value.\n
2560 * Based on these values, fSYS clock frequency is derived using the following formula:\n
2561 * fSYS = fCPU << CPUDIV.
2562 * \par<b>Related APIs:</b><BR>
2563 * XMC_SCU_CLOCK_GetUsbPllClockFrequency() \n\n\n
2564 */
XMC_SCU_CLOCK_GetSystemClockFrequency(void)2565 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetSystemClockFrequency(void)
2566 {
2567 return SystemCoreClock << ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) >> SCU_CLK_CPUCLKCR_CPUDIV_Pos);
2568 }
2569
2570
2571 /**
2572 *
2573 * @return uint32_t CCU clock frequency in Hertz.
2574 *
2575 * \par<b>Description</b><br>
2576 * Provides the frequency of clock(fCPU) used for CCU4, CCU8, POSIF and HRPWM.\n\n
2577 * The value is obtained from \a CCUDIV bits of \a CCUCLKCR register and system clock (fSYS) frequency.
2578 * Based on these values, fCCU clock frequency is calculated using following formula:\n
2579 * fCCU = fSYS >> CCUDIV.\n
2580 * \par<b>Related APIs:</b><BR>
2581 * XMC_SCU_CLOCK_GetCcuClockDivider(), XMC_SCU_CLOCK_GetSystemClockFrequency() \n\n\n
2582 */
2583 uint32_t XMC_SCU_CLOCK_GetCcuClockFrequency(void);
2584
2585 /**
2586 * @return uint32_t USB clock frequency in Hertz.
2587 *
2588 * \par<b>Description</b><br>
2589 * Provides the frequency of USB and SDMMC clock(fUSB/fSDMMC).\n\n
2590 * The value is obtained from \a USBDIV bits of \a USBCLKCR register and USB clock source.
2591 * Based on these values fUSB/fSDMMC clock frequency is calculated using following formula:\n
2592 * if USB clock source = USBPLL: fUSB/fSDMMC = fUSBPLL/(USBDIV + 1).\n
2593 * if USB clock source = PLL: fUSB/fSDMMC = fPLL/(USBDIV + 1).\n
2594 *
2595 * \par<b>Related APIs:</b><BR>
2596 * XMC_SCU_CLOCK_GetUsbClockSource(), XMC_SCU_CLOCK_GetUsbClockDivider() \n\n\n
2597 */
2598 uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void);
2599
2600 /**
2601 * @return uint32_t Ethernet clock frequency in Hertz.
2602 *
2603 * \par<b>Description</b><br>
2604 * Provides the frequency of Ethernet clock(fETH).\n\n
2605 * The value is derived from system clock frequency(fSYS). It is calculated using
2606 * the following formula:\n
2607 * fETH = fSYS >> 1;
2608 * \par<b>Related APIs:</b><BR>
2609 * XMC_SCU_CLOCK_GetSystemClockFrequency() \n\n\n
2610 */
XMC_SCU_CLOCK_GetEthernetClockFrequency(void)2611 __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetEthernetClockFrequency(void)
2612 {
2613 return XMC_SCU_CLOCK_GetSystemClockFrequency() >> 1U;
2614 }
2615
2616 #if defined(EBU)
2617 /**
2618 * @return uint32_t EBU clock frequency in Hertz.
2619 *
2620 * \par<b>Description</b><br>
2621 * Provides the frequency of EBU clock(fEBU).\n\n
2622 * The value is derived from system PLL clock frequency(fPLL) by applying the EBU divider.
2623 * It is calculated using the following formula:\n
2624 * fETH = fPLL /(EBUDIV+1)
2625 * \par<b>Related APIs:</b><BR>
2626 * XMC_SCU_CLOCK_GetEbuClockDivider(), XMC_SCU_CLOCK_GetSystemPllClockFrequency() \n\n\n
2627 */
2628 uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void);
2629 #endif
2630
2631 /**
2632 * @return uint32_t WDT clock frequency in Hertz.
2633 *
2634 * \par<b>Description</b><br>
2635 * Provides the frequency of WDT clock(fWDT).\n\n
2636 * The value is derived using \a WDTDIV bits of \a WDTCLKCR register and WDT clock source.
2637 * Based on these values it is calculated using the following formula:\n
2638 * if WDT clock source = PLL: fWDT = fUSBPLL/(WDTDIV + 1).\n
2639 * if WDT clock source = OFI: fWDT = fOFI/(WDTDIV + 1).\n
2640 * if WDT clock source = Standby: fWDT = fSTDBY/(WDTDIV + 1).\n
2641 *
2642 * \par<b>Related APIs:</b><BR>
2643 * XMC_SCU_CLOCK_GetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider() \n\n\n
2644 */
2645 uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void);
2646
2647 /**
2648 *
2649 * @return uint32_t External clock out frequency in Hertz.
2650 *
2651 * \par<b>Description</b><br>
2652 * Provides the frequency of external output clock(fEXT).\n\n
2653 * The value is derived using \a ECKDIV bits of \a EXCLKCR register and external clock out source.
2654 * Based on these values, it is calculated using the following formula:\n
2655 * if external clock out source = System clock: fEXT = fSYS.\n
2656 * if external clock out source = PLL: fEXT = fPLL/(ECKDIV + 1).\n
2657 * if external clock out source = USBPLL: fEXT = fUSBPLL/(ECKDIV + 1).\n
2658 *
2659 * \par<b>Related APIs:</b><BR>
2660 * XMC_SCU_CLOCK_GetExternalOutputClockDivider(), XMC_SCU_CLOCK_GetExternalOutputClockSource() \n\n\n
2661 */
2662 uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void);
2663
2664 #if defined(ECAT)
2665 /**
2666 * @return uint32_t ECAT clock frequency in Hertz.
2667 *
2668 * \par<b>Description</b><br>
2669 * Provides the frequency of ECAT clock(fECAT).\n\n
2670 * The value is derived using \a ECADIV bits of \a ECATCLKCR register and ECAT clock source.
2671 * Based on these values it is calculated using the following formula:\n
2672 * if ECAT clock source = PLL: fECAT = fPLL/(ECADIV + 1).\n
2673 * if ECAT clock source = USBPLL: fECAT = fUSBPLL/(ECADIV + 1).\n
2674 *
2675 * \par<b>Related APIs:</b><BR>
2676 * XMC_SCU_CLOCK_GetECATClockSource(), XMC_SCU_CLOCK_GetECATClockDivider() \n\n\n
2677 */
2678 uint32_t XMC_SCU_CLOCK_GetECATClockFrequency(void);
2679 #endif
2680
2681 /**
2682 * @return None
2683 *
2684 * \par<b>Description</b><br>
2685 * Enables main PLL for system clock. \n\n
2686 * System PLL is enabled by clearing the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register.
2687 * By default the system PLL is in power saving mode. The API enables the PLL and the voltage
2688 * controlled oscillator associated with it.
2689 * \par<b>Related APIs:</b><BR>
2690 * XMC_SCU_CLOCK_DisableSystemPll(), XMC_SCU_CLOCK_StartSystemPll() \n\n\n
2691 */
2692 void XMC_SCU_CLOCK_EnableSystemPll(void);
2693
2694 /**
2695 * @return None
2696 *
2697 * \par<b>Description</b><br>
2698 * Disables main PLL for system clock. \n\n
2699 * System PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register.
2700 * By default the system PLL is in power saving mode. If the system PLL is explicitly enabled,
2701 * the API disables the PLL and the voltage controlled oscillator(VCO) associated with it.
2702 * \par<b>Related APIs:</b><BR>
2703 * XMC_SCU_CLOCK_EnableSystemPll(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n
2704 */
2705 void XMC_SCU_CLOCK_DisableSystemPll(void);
2706
2707 /**
2708 * @param source PLL clock source. \n
2709 * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLLCLKSRC_t to identify the clock source.\n
2710 * XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP- External high precision oscillator input.
2711 * XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI- Internal fast clock input.
2712 * @param mode Mode of PLL operation.\n
2713 * \b Range: Use type @ref XMC_SCU_CLOCK_SYSPLL_MODE_t to identify the PLL mode. \n
2714 * XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL- PLL frequency obtained from output of VCO(fVCO).\n
2715 * XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR- VCO is bypassed. Frequency obtained from fOSC.\n
2716 * @param pdiv Input divider. Represents (PDIV+1) applied to external reference frequency. \n
2717 * \b Range: 1 to 16.\n
2718 * @param ndiv Feedback divider. Represents(NDIV+1) \n
2719 * \b Range: 1 to 128. \n
2720 * @param kdiv Output divider. Represents (K2DIV+1) in normal PLL mode or (K1DIV+1) in prescaler mode.\n
2721 * \b Range: 1 to 128. \n
2722 * @return None
2723 *
2724 * \par<b>Description</b><br>
2725 * Enables system PLL.\n\n
2726 * Based on the selected source of clock, either external frequency fOHP or internal clock fOFI will be used.
2727 * Based on the selected PLL mode, either voltage controlled oscillator(VCO) output(fVCO) or direct input frequency
2728 * is used for the output dividers.\n
2729 * The API implements the following sequence:\n
2730 * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n
2731 * - Clear all PLL related traps.\n
2732 * - If external fOHP is selected as source, wait for the external oscillator to stabilize.\n
2733 * - If PLL normal mode is selected, calculate the value of K2DIV and configure the PDIV, NDIV and K2DIV values.\n
2734 * - Ramp up the PLL frequency in steps. \n
2735 * - If prescaler mode is selected, configure the value of K1DIV.\n
2736 * - Wait for LOCK.\n
2737 * - Restore the trap configuration from stored temporary variable.\n
2738 *
2739 * \par<b>Related APIs:</b><BR>
2740 * XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n
2741 */
2742 void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source,
2743 XMC_SCU_CLOCK_SYSPLL_MODE_t mode,
2744 uint32_t pdiv,
2745 uint32_t ndiv,
2746 uint32_t kdiv);
2747
2748 /**
2749 *
2750 * @return None
2751 *
2752 * \par<b>Description</b><br>
2753 * Disables the system PLL.
2754 * PLL is placed in power saving mode. It disables the PLL by setting the \a PLLPWD bit of \a PLLCON0 register.
2755 * If the PLL is put to power saving mode, it can no longer be used.
2756 * It is recommended to ensure following steps before using \a XMC_SCU_CLOCK_StopSystemPll API:\n
2757 * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n
2758 * - Clear all PLL related traps.\n
2759 * - Ramp down frequency until fPLL reaches backup clock frequency (fOFI).\n
2760 * - Disable PLL.\n
2761 * - Restore the trap configuration from stored temporary variable.\n
2762 *
2763 * \par<b>Related APIs:</b><BR>
2764 * XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StartSystemPll() \n\n\n
2765 */
2766 void XMC_SCU_CLOCK_StopSystemPll(void);
2767
2768 /**
2769 * @param kdiv PLL output divider K2DIV. \n
2770 * \b Range: 1 to 128. Represents (K2DIV+1).
2771 * @return None
2772 *
2773 * \par<b>Description</b><br>
2774 * Ramps up or ramps down the PLL output frequency in provided step. \n\n
2775 * The PLL output frequency is divided by the \a kdiv value. This generates a step of ramp
2776 * for the PLL output frequency. The API waits for the clock to stabilize before the completing its
2777 * execution.
2778 * \par<b>Related APIs:</b><BR>
2779 * XMC_SCU_CLOCK_StartSystemPll() \n\n\n
2780 */
2781 void XMC_SCU_CLOCK_StepSystemPllFrequency(uint32_t kdiv);
2782
2783 /**
2784 * @param None
2785 * @return Boolean value indicating if System PLL is locked
2786 *
2787 * \par<b>Description</b><br>
2788 * Return status of System PLL VCO.
2789 * \par<b>Related APIs:</b><BR>
2790 * XMC_SCU_CLOCK_StartSystemPll() \n\n\n
2791 */
2792 bool XMC_SCU_CLOCK_IsSystemPllLocked(void);
2793
2794 /**
2795 * @return None
2796 *
2797 * \par<b>Description</b><br>
2798 * Enables USB PLL for USB clock. \n\n
2799 * USB PLL is enabled by clearing the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register.
2800 * By default the USB PLL is in power saving mode. The API enables the PLL and the voltage
2801 * controlled oscillator associated with it.
2802 * \par<b>Related APIs:</b><BR>
2803 * XMC_SCU_CLOCK_DisableUsbPll(), XMC_SCU_CLOCK_StartUsbPll() \n\n\n
2804 */
2805 void XMC_SCU_CLOCK_EnableUsbPll(void);
2806
2807 /**
2808 * @return None
2809 *
2810 * \par<b>Description</b><br>
2811 * Disables USB PLL for USB clock. \n\n
2812 * USB PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register.
2813 * By default the USB PLL is in power saving mode. If the USB PLL is explicitly enabled,
2814 * the API disables the PLL and the voltage controlled oscillator(VCO) associated with it.
2815 * \par<b>Related APIs:</b><BR>
2816 * XMC_SCU_CLOCK_EnableUsbPll(), XMC_SCU_CLOCK_StopUsbPll() \n\n\n
2817 */
2818 void XMC_SCU_CLOCK_DisableUsbPll(void);
2819
2820 /**
2821 *
2822 * @param pdiv Input divider value. Represents (PDIV+1) divider for the USB PLL.\n
2823 * \b Range: 1 to 16.
2824 * @param ndiv VCO feedback divider for USB PLL. Represents (NDIV+1) feedback divider.\n
2825 * \b Range: 1 to 128.
2826 *
2827 * @return None
2828 *
2829 * \par<b>Description</b><br>
2830 * Configures USB PLL dividers and enables the PLL.\n\n
2831 * The API follows the required sequence for safely configuring the divider values of USB PLL.
2832 * Checks for PLL stabilization before enabling the same. After the configuring the dividers,
2833 * it waits till the VCO lock is achieved.
2834 * The sequence followed is as follows:\n
2835 * - Enable the USB PLL and configure VCO to be bypassed.\n
2836 * - Set up the HP oscillator clock input.\n
2837 * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n
2838 * - Clear all USBPLL related traps.\n
2839 * - Disconnect the oscillator from USB PLL and configure the dividers PDIV and NDIV. \n
2840 * - Connect the oscillator to USB PLL and enable VCO.\n
2841 * - Wait for LOCK.\n
2842 * - Restore the trap configuration from stored temporary variable.\n
2843 * \par<b>Related APIs:</b><BR>
2844 * XMC_SCU_CLOCK_StopUsbPll() \n\n\n
2845 */
2846 void XMC_SCU_CLOCK_StartUsbPll(uint32_t pdiv, uint32_t ndiv);
2847
2848 /**
2849 *
2850 * @return None
2851 *
2852 * \par<b>Description</b><br>
2853 * Disables USB PLL operation.\n\n
2854 * USB PLL is disabled by placing the USB PLL in power saving mode. The VCO and USB PLL are put in power saving mode
2855 * by setting the \a PLLPWD bit and \a VCOPWD bit of \a USBLLCON register to 1. VCO bypass mode is enabled by setting the
2856 * \a VCOBYP bit of \a USBLLCON register to 1.
2857 * It is recommended to ensure following steps before using \a XMC_SCU_CLOCK_StopUsbPll API:\n
2858 * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n
2859 * - Clear all USBPLL related traps.\n
2860 * - Ramp down frequency.\n
2861 * - Disable PLL.\n
2862 * - Restore the trap configuration from stored temporary variable.\n
2863 * \par<b>Related APIs:</b><BR>
2864 * XMC_SCU_CLOCK_StartUsbPll() \n\n\n
2865 */
2866 void XMC_SCU_CLOCK_StopUsbPll(void);
2867
2868 /**
2869 * @param None
2870 * @return Boolean value indicating if USB PLL is locked
2871 *
2872 * \par<b>Description</b><br>
2873 * Return status of USB PLL VCO.
2874 * \par<b>Related APIs:</b><BR>
2875 * XMC_SCU_CLOCK_StartUsbPll() \n\n\n
2876 */
2877 bool XMC_SCU_CLOCK_IsUsbPllLocked(void);
2878
2879 /**
2880 * @param mode Backup clock calibration mode.\n
2881 * \b Range: Use type @ref XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t to identify the calibration mode.\n
2882 * XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY- Force trimming of internal oscillator with firmware configured values.\n
2883 * XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC- Calibrate internal oscillator automatically using standby clock(fSTDBY).\n
2884 *
2885 * @return None
2886 *
2887 * \par<b>Description</b><br>
2888 * Configures the calibration mode of internal oscillator.\n\n
2889 * Based on the calibration mode selected, the internal oscillator calibration will be configured.
2890 * The calibration is useful while using fast internal clock(fOFI). When factory mode calibration is used,
2891 * the internal oscillator is trimmed using the firmware configured values. If automatic calibration is
2892 * selected, the internal oscillator will be monitored using the backup clock.
2893 *
2894 * \par<b>Related APIs:</b><BR>
2895 * XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n
2896 */
2897 void XMC_SCU_CLOCK_SetBackupClockCalibrationMode(XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t mode);
2898
2899 /**
2900 * @param mode Low power mode\n
2901 * @param sleep_on_exit Enter sleep, or deep sleep, on return from an ISR
2902 *
2903 * @return None
2904 *
2905 * \par<b>Description</b><br>
2906 * Enter selected low power mode and wait for interrupt
2907 *
2908 * \par<b>Related APIs:</b><BR>
2909 * XMC_SCU_CLOCK_SetSleepConfig(), XMC_SCU_CLOCK_SetDeepSleepConfig() \n\n\n
2910 */
XMC_SCU_POWER_WaitForInterrupt(XMC_SCU_POWER_MODE_t mode,bool sleep_on_exit)2911 __STATIC_INLINE void XMC_SCU_POWER_WaitForInterrupt(XMC_SCU_POWER_MODE_t mode, bool sleep_on_exit)
2912 {
2913 SCB->SCR = mode | (sleep_on_exit ? SCB_SCR_SLEEPONEXIT_Msk : 0);
2914
2915 __WFI();
2916 }
2917
2918 /**
2919 * @param mode Low power mode\n
2920 *
2921 * @return None
2922 *
2923 * \par<b>Description</b><br>
2924 * Enter selected low power mode and wait for event
2925 *
2926 * \par<b>Related APIs:</b><BR>
2927 * XMC_SCU_CLOCK_SetSleepConfig(), XMC_SCU_CLOCK_SetDeepSleepConfig() \n\n\n
2928 */
XMC_SCU_POWER_WaitForEvent(XMC_SCU_POWER_MODE_t mode)2929 __STATIC_INLINE void XMC_SCU_POWER_WaitForEvent(XMC_SCU_POWER_MODE_t mode)
2930 {
2931 SCB->SCR = mode | SCB_SCR_SEVONPEND_Msk;
2932
2933 __WFE();
2934 }
2935
2936 /**
2937 * @param threshold Threshold value for comparison to VDDP for brownout detection. LSB33V is 22.5mV
2938 * @param interval Interval value for comparison to VDDP expressed in cycles of system clock
2939 * @return None
2940 *
2941 * Enable power monitoring control register for brown-out detection.
2942 * Brown Out Trap need to be enabled using XMC_SCU_TRAP_Enable() and event handling done in NMI_Handler.
2943 *
2944 * \par<b>Related APIs:</b><BR>
2945 * XMC_SCU_TRAP_Enable() \n\n\n
2946 *
2947 */
XMC_SCU_POWER_EnableMonitor(uint8_t threshold,uint8_t interval)2948 __STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(uint8_t threshold, uint8_t interval)
2949 {
2950 SCU_POWER->PWRMON = SCU_POWER_PWRMON_ENB_Msk |
2951 ((uint32_t)threshold << SCU_POWER_PWRMON_THRS_Pos) |
2952 ((uint32_t)interval << SCU_POWER_PWRMON_INTV_Pos);
2953 }
2954
2955 /**
2956 * @return None
2957 *
2958 * Disable power monitoring control register for brown-out detection.
2959 *
2960 */
XMC_SCU_POWER_DisableMonitor(void)2961 __STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void)
2962 {
2963 SCU_POWER->PWRMON &= ~SCU_POWER_PWRMON_ENB_Msk;
2964 }
2965
2966 /**
2967 * @return ::XMC_SCU_POWER_EVR_STATUS_t
2968 *
2969 * \par<b>Description</b><br>
2970 * Returns status of the EVR13.
2971 *
2972 */
XMC_SCU_POWER_GetEVRStatus(void)2973 __STATIC_INLINE int32_t XMC_SCU_POWER_GetEVRStatus(void)
2974 {
2975 return SCU_POWER->EVRSTAT;
2976 }
2977
2978 /**
2979 * @return EVR13 voltage in volts
2980 *
2981 * \par<b>Description</b><br>
2982 * Returns EVR13 voltage in volts.
2983 *
2984 */
2985 float XMC_SCU_POWER_GetEVR13Voltage(void);
2986
2987 /**
2988 * @return EVR33 voltage in volts
2989 *
2990 * \par<b>Description</b><br>
2991 * Returns EVR33 voltage in volts
2992 *
2993 */
2994 float XMC_SCU_POWER_GetEVR33Voltage(void);
2995
2996 /**
2997 * @return None
2998 *
2999 * \par<b>Description</b><br>
3000 * Enables the USB PHY and also OTG comparator if available.\n\n
3001 * Configures the \a USBPHYPDQ bit of \a PWRSET register to move the USB PHY from power down state.
3002 * If USB OTG is available in the device, the \a USBOTGEN bit of \a PWRSET register is set to 1. This
3003 * enables the USB on the go comparators.
3004 *
3005 * \par<b>Related APIs:</b><BR>
3006 * XMC_SCU_POWER_DisableUsb(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n
3007 */
3008 void XMC_SCU_POWER_EnableUsb(void);
3009
3010 /**
3011 * @return None
3012 *
3013 * \par<b>Description</b><br>
3014 * Disables the USB PHY and also OTG comparator if available.\n\n
3015 * Configures the \a USBPHYPDQ bit of \a PWRSET register to move the USB PHY to power down state.
3016 * If USB OTG is available in the device, the \a USBOTGEN bit of \a PWRSET register is set to 0. This
3017 * disables the USB on the go comparators.
3018 *
3019 * \par<b>Related APIs:</b><BR>
3020 * XMC_SCU_POWER_EnableUsb(), XMC_SCU_CLOCK_SetUsbClockSource() \n\n\n
3021 */
3022 void XMC_SCU_POWER_DisableUsb(void);
3023
3024 /**
3025 * @return None
3026 *
3027 * \par<b>Description</b><br>
3028 * Powers up the hibernation domain.\n\n
3029 * Hibernate domain should be enabled before using any peripheral from the hibernate domain.
3030 * It enables the power to the hibernate domain and moves it out of reset state.
3031 * Power to hibernate domain is enabled by setting the \a HIB bit of \a PWRSET register only if it is currently powered down.
3032 * The API will wait until HIB domain is enabled. If hibernate domain is in a state of reset,
3033 * \a HIBRS bit of \a RSTCLR register is set to move it out of reset state.\n
3034 * It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:\n
3035 * - Call \a XMC_SCU_HIB_EnableHibernateDomain .
3036 * - Call \a XMC_SCU_HIB_IsHibernateDomainEnabled and check the return value. If return value is true, it indicates
3037 * that the hibernation domain is enabled otherwise disabled.\n
3038 * \par<b>Related APIs:</b><BR>
3039 * XMC_SCU_HIB_DisableHibernateDomain(), XMC_SCU_HIB_IsHibernateDomainEnabled() \n\n\n
3040 */
3041 void XMC_SCU_HIB_EnableHibernateDomain(void);
3042
3043 /**
3044 *
3045 * @return None
3046 *
3047 * \par<b>Description</b><br>
3048 * Powers down the hibernation domain.\n\n
3049 * After disabling the hibernate domain, none of the peripherals from the hibernte domain can be used.
3050 * Hibernate domain is disabled by setting the \a HIB bit of \a PWRCLR register and \ HIBRS bit of \a RSTSET register.\n
3051 * It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:\n
3052 * - Call \a XMC_SCU_HIB_DisableHibernateDomain .
3053 * - Call \a XMC_SCU_HIB_IsHibernateDomainEnabled and check return value. If return value is true, it indicates
3054 * that the hibernation domain is enabled otherwise disabled.\n
3055 * \par<b>Related APIs:</b><BR>
3056 * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_IsHibernateDomainEnabled() \n\n\n
3057 */
3058 void XMC_SCU_HIB_DisableHibernateDomain(void);
3059
3060 /**
3061 *
3062 * @return bool Power status of hibernate domain.\n
3063 * \b Range: Boolean state value.\n
3064 * \a true if hibernate domain is enabled.\n
3065 * \a false if hibernate domain is disabled.\n
3066 *
3067 *
3068 * \par<b>Description</b><br>
3069 * Checks whether hibernation domain is enabled/disabled.\n\n
3070 * The API can be used before using the peripherals from hibernation domain to ensure that the
3071 * power is supplied to the peripherals and also that the hibernation domain is not in reset state.
3072 * The status is obtained using the \a HIBEN bit of \a PWRSTAT register and \a HIBRS bit of \a RSTSET register.
3073 * \par<b>Related APIs:</b><BR>
3074 * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain() \n\n\n
3075 */
3076 bool XMC_SCU_HIB_IsHibernateDomainEnabled(void);
3077
3078 /**
3079 * @return ::XMC_SCU_HIB_CTRL_STATUS_t
3080 *
3081 * \par<b>Description</b><br>
3082 * Returns status of the external hibernate control.
3083 *
3084 */
XMC_SCU_HIB_GetHibernateControlStatus(void)3085 __STATIC_INLINE int32_t XMC_SCU_HIB_GetHibernateControlStatus(void)
3086 {
3087 return (SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk);
3088 }
3089
3090 /**
3091 * @return ::XMC_SCU_HIB_EVENT_t
3092 *
3093 * \par<b>Description</b><br>
3094 * Returns status of hibernate wakeup events.
3095 *
3096 */
XMC_SCU_HIB_GetEventStatus(void)3097 __STATIC_INLINE int32_t XMC_SCU_HIB_GetEventStatus(void)
3098 {
3099 return SCU_HIBERNATE->HDSTAT;
3100 }
3101
3102 /**
3103 * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t
3104 * @return None
3105 *
3106 * \par<b>Description</b><br>
3107 * Clear hibernate wakeup event status
3108 *
3109 * \note
3110 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3111 *
3112 * \par<b>Related APIs:</b><BR>
3113 * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_EnableEvent(),
3114 * XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus() \n\n\n
3115 *
3116 */
3117 void XMC_SCU_HIB_ClearEventStatus(int32_t event);
3118
3119 /**
3120 * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t
3121 * @return None
3122 *
3123 * \par<b>Description</b><br>
3124 * Trigger hibernate wakeup event
3125 *
3126 *
3127 * \note
3128 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3129 *
3130 * \par<b>Related APIs:</b><BR>
3131 * XMC_SCU_HIB_ClearEventStatus(), XMC_SCU_HIB_EnableEvent(),
3132 * XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus() \n\n\n
3133 *
3134 */
3135 void XMC_SCU_HIB_TriggerEvent(int32_t event);
3136
3137 /**
3138 * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t
3139 * @return None
3140 *
3141 * \par<b>Description</b><br>
3142 * Enable hibernate wakeup event source
3143 *
3144 *
3145 * \note
3146 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3147 *
3148 * \par<b>Related APIs:</b><BR>
3149 * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_ClearEventStatus(),
3150 * XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus() \n\n\n
3151 *
3152 */
3153 void XMC_SCU_HIB_EnableEvent(int32_t event);
3154
3155 /**
3156 * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t
3157 * @return None
3158 *
3159 * \par<b>Description</b><br>
3160 * Disable hibernate wakeup event source
3161 *
3162 *
3163 * \note
3164 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3165 *
3166 * \par<b>Related APIs:</b><BR>
3167 * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_EnableEvent(),
3168 * XMC_SCU_HIB_ClearEventStatus(), XMC_SCU_GetMirrorStatus() \n\n\n
3169 *
3170 */
3171 void XMC_SCU_HIB_DisableEvent(int32_t event);
3172
3173 /**
3174 * @return None
3175 *
3176 * \par<b>Description</b><br>
3177 * Request enter external hibernate state
3178 *
3179 * \note
3180 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3181 *
3182 * \par<b>Related APIs:</b><BR>
3183 * XMC_SCU_GetMirrorStatus() \n\n\n
3184 *
3185 */
3186 void XMC_SCU_HIB_EnterHibernateState(void);
3187
3188 /**
3189 * @param mode hibernate mode ::XMC_SCU_HIB_HIBERNATE_MODE_t
3190 * @return None
3191 *
3192 * \par<b>Description</b><br>
3193 * Request enter external hibernate state
3194 *
3195 * \note
3196 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3197 *
3198 * \par<b>Related APIs:</b><BR>
3199 * XMC_SCU_GetMirrorStatus() \n\n\n
3200 *
3201 */
3202 void XMC_SCU_HIB_EnterHibernateStateEx(XMC_SCU_HIB_HIBERNATE_MODE_t mode);
3203
3204 /**
3205 * @return Detection of a wakeup from hibernate mode
3206 *
3207 * \par<b>Description</b><br>
3208 * Detection of a wakeup from hibernate mode
3209 */
XMC_SCU_HIB_IsWakeupEventDetected(void)3210 __STATIC_INLINE bool XMC_SCU_HIB_IsWakeupEventDetected(void)
3211 {
3212 return ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBWK_Msk) != 0U);
3213 }
3214
3215 /**
3216 * @return None
3217 *
3218 * \par<b>Description</b><br>
3219 * Clear detection status of wakeup from hibernate mode
3220 */
XMC_SCU_HIB_ClearWakeupEventDetectionStatus(void)3221 __STATIC_INLINE void XMC_SCU_HIB_ClearWakeupEventDetectionStatus(void)
3222 {
3223 SCU_RESET->RSTCLR = SCU_RESET_RSTCLR_HIBWK_Msk;
3224 }
3225
3226 /**
3227 * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t
3228 * @return None
3229 *
3230 * \par<b>Description</b><br>
3231 * Selects input for Wake-Up from Hibernate
3232 *
3233 * \note
3234 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3235 *
3236 * \par<b>Related APIs:</b><BR>
3237 * XMC_SCU_GetMirrorStatus() \n\n\n
3238 *
3239 */
3240 void XMC_SCU_HIB_SetWakeupTriggerInput(XMC_SCU_HIB_IO_t pin);
3241
3242 /**
3243 * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t
3244 * @param mode Hibernate domain dedicated pin mode ::XMC_SCU_HIB_PIN_MODE_t
3245 * @return None
3246 *
3247 * \par<b>Description</b><br>
3248 * Selects mode of hibernate domain dedicated pins HIB_IOx
3249 *
3250 * \note
3251 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3252 *
3253 * \par<b>Related APIs:</b><BR>
3254 * XMC_SCU_GetMirrorStatus() \n\n\n
3255 *
3256 */
3257 void XMC_SCU_HIB_SetPinMode(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode);
3258
3259 /**
3260 * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t
3261 * @param level Output polarity of the hibernate domain dedicated pins HIB_IOx ::XMC_SCU_HIB_IO_OUTPUT_LEVEL_t
3262 * @return None
3263 *
3264 * \par<b>Description</b><br>
3265 * Selects the output polarity of the hibernate domain dedicated pins HIB_IOx
3266 *
3267 * \note
3268 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3269 *
3270 * \par<b>Related APIs:</b><BR>
3271 * XMC_SCU_GetMirrorStatus() \n\n\n
3272 *
3273 */
3274 void XMC_SCU_HIB_SetPinOutputLevel(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_LEVEL_t level);
3275
3276 /**
3277 * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t
3278 * @return None
3279 *
3280 * \par<b>Description</b><br>
3281 * Selects input to ERU0 module (HIB_SR0) that optionally can be used with software as a general purpose input.
3282 *
3283 * \note
3284 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3285 *
3286 * \par<b>Related APIs:</b><BR>
3287 * XMC_SCU_HIB_SetSR0Input(), XMC_SCU_GetMirrorStatus() \n\n\n
3288 *
3289 */
3290 void XMC_SCU_HIB_SetInput0(XMC_SCU_HIB_IO_t pin);
3291
3292 /**
3293 * @param input input signal HIB_SR0 of ERU0
3294 * @return None
3295 *
3296 * \par<b>Description</b><br>
3297 * Selects input to ERU0 module (HIB_SR0).
3298 *
3299 * \note
3300 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3301 *
3302 * \par<b>Related APIs:</b><BR>
3303 * XMC_SCU_HIB_SetInput0(),XMC_SCU_GetMirrorStatus() \n\n\n
3304 *
3305 */
3306 void XMC_SCU_HIB_SetSR0Input(XMC_SCU_HIB_SR0_INPUT_t input);
3307
3308 #if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
3309
3310 #if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))
3311 /**
3312 * @param input input signal HIB_SR1 of ERU0
3313 * @return None
3314 *
3315 * \par<b>Description</b><br>
3316 * Configures HIB_SR1 input to ERU0 module.
3317 *
3318 * \note
3319 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3320 *
3321 * @note Only available in XMC44 series and LQFP100 package
3322 *
3323 */
3324 void XMC_SCU_HIB_SetSR1Input(XMC_SCU_HIB_SR1_INPUT_t input);
3325 #endif
3326
3327 /**
3328 * @param input LPAC compare input. Values from ::XMC_SCU_HIB_LPAC_INPUT_t can be ORed.
3329 * @return None
3330 *
3331 * \par<b>Description</b><br>
3332 * Selects inputs to the LPAC comparator. Several inputs can be selected (time multiplexing).
3333 *
3334 * \note
3335 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3336 *
3337 * @note Only available in XMC44, XMC42 and XMC41 series
3338 *
3339 */
3340 void XMC_SCU_HIB_LPAC_SetInput(XMC_SCU_HIB_LPAC_INPUT_t input);
3341
3342 /**
3343 * @param trigger LPAC compare trigger
3344 * @return None
3345 *
3346 * \par<b>Description</b><br>
3347 * Selects trigger mechanism to start a comparison.
3348 *
3349 * \note
3350 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3351 *
3352 * @note Only available in XMC44, XMC42 and XMC41 series
3353 *
3354 */
3355 void XMC_SCU_HIB_LPAC_SetTrigger(XMC_SCU_HIB_LPAC_TRIGGER_t trigger);
3356
3357 /**
3358 * @param enable_delay Enable conversion delay
3359 * @param interval_count compare interval (interval_count + 16) * 1/32768 (s)
3360 * @param settle_count settleing time of LPAC after powered up (triggered) before measurement start (settle_count + 1) * 1/32768 (s)
3361 * @return None
3362 *
3363 * \par<b>Description</b><br>
3364 * Configures timing behavior of comparator.
3365 *
3366 * \note
3367 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3368 *
3369 * @note Only available in XMC44, XMC42 and XMC41 series
3370 *
3371 */
3372 void XMC_SCU_HIB_LPAC_SetTiming(bool enable_delay, uint16_t interval_count, uint8_t settle_count);
3373
3374 /**
3375 * @param low VBAT low threshold
3376 * @param high VBAT high threshold
3377 * @return None
3378 *
3379 * \par<b>Description</b><br>
3380 * Select compare thresholds for VBAT.
3381 * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards.
3382 * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements
3383 * until it has been crossed downwards and the threshold values gets swapped again.
3384 *
3385 * \note
3386 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3387 *
3388 * @note Only available in XMC44, XMC42 and XMC41 series
3389 *
3390 */
3391 void XMC_SCU_HIB_LPAC_SetVBATThresholds(uint8_t lower, uint8_t upper);
3392
3393 /**
3394 * @param low HIB_IO_0 low threshold
3395 * @param high HIB_IO_0 high threshold
3396 * @return None
3397 *
3398 * \par<b>Description</b><br>
3399 * Select compare thresholds for HIB_IO_0.
3400 * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards.
3401 * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements
3402 * until it has been crossed downwards and the threshold values gets swapped again.
3403 *
3404 * \note
3405 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3406 *
3407 * @note Only available in XMC44, XMC42 and XMC41 series
3408 *
3409 */
3410 void XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds(uint8_t lower, uint8_t upper);
3411
3412 #if (defined(DOXYGEN) || (UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))
3413 /**
3414 * @param low HIB_IO_1 low threshold
3415 * @param high HIB_IO_1 high threshold
3416 * @return None
3417 *
3418 * \par<b>Description</b><br>
3419 * Select compare thresholds for HIB_IO_1.
3420 * After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards.
3421 * Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements
3422 * until it has been crossed downwards and the threshold values gets swapped again.
3423 *
3424 * \note
3425 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3426 *
3427 * @note Only available in XMC44 series and LQFP100 package
3428 *
3429 */
3430 void XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds(uint8_t lower, uint8_t upper);
3431 #endif
3432
3433 /**
3434 * @return HIB LPAC status ::XMC_SCU_HIB_LPAC_STATUS_t
3435 *
3436 * \par<b>Description</b><br>
3437 * Return status of HIB LPAC.
3438 * @note Only available in XMC44, XMC42 and XMC41 series and in certain packages
3439 *
3440 */
3441 int32_t XMC_SCU_HIB_LPAC_GetStatus(void);
3442
3443 /**
3444 * @param status HIB LPAC status. Values from ::XMC_SCU_HIB_LPAC_STATUS_t can be ORed.
3445 * @return None
3446 *
3447 * \par<b>Description</b><br>
3448 * Clear status of HIB LPAC.
3449 *
3450 * \note
3451 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3452 *
3453 * @note Only available in XMC44, XMC42 and XMC41 series
3454 *
3455 */
3456 void XMC_SCU_HIB_LPAC_ClearStatus(int32_t status);
3457
3458 /**
3459 * @param input LPAC compare input. Values from ::XMC_SCU_HIB_LPAC_INPUT_t can be ORed.
3460 * @return None
3461 *
3462 * \par<b>Description</b><br>
3463 * Trigger comparasion on the selected inputs.
3464 *
3465 * \note
3466 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3467 *
3468 * @note Only available in XMC44, XMC42 and XMC41 series
3469 *
3470 */
3471 void XMC_SCU_HIB_LPAC_TriggerCompare(XMC_SCU_HIB_LPAC_INPUT_t input);
3472
3473 #endif
3474
3475 /**
3476 *
3477 * @return None
3478 *
3479 * \par<b>Description</b><br>
3480 * Enables slow internal oscillator(fOSI).\n\n
3481 * By default on device power up, the slow internall oscillator is enabled.
3482 * It can be disabled only if the external oscillator(fULP) is enabled and toggling.
3483 * It is recommended to enable fOSI to prevent deadlock if fULP fails.
3484 * fOSI is enabled by clearing the \a PWD bit of \a OSCSICTRL register.
3485 * The API waits for the mirror register update of the configured register.
3486 * The slow internal oscillator registers are in hibernate domain.
3487 * Ensure that the hibernate domain is enabled before changing the configuration.
3488 *
3489 * \note
3490 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3491 *
3492 * \par<b>Related APIs:</b><BR>
3493 * XMC_SCU_HIB_DisableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(),
3494 * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_GetMirrorStatus() \n\n\n
3495 */
3496 void XMC_SCU_HIB_EnableInternalSlowClock(void);
3497
3498 /**
3499 *
3500 * @return None
3501 *
3502 * \par<b>Description</b><br>
3503 * Disables slow internal oscillator(fOSI).\n\n
3504 * By default on device power up, the slow internall oscillator is enabled.
3505 * It can be disabled only if the external oscillator(fULP) is enabled and toggling.
3506 * It is recommended to enable fOSI to prevent deadlock if fULP fails.
3507 * fOSI is disabled by setting the \a PWD bit of \a OSCSICTRL register.
3508 * The API waits for the mirror register update of the configured register.
3509 * The slow internal oscillator registers are in hibernate domain.
3510 * Ensure that the hibernate domain is enabled before changing the configuration.
3511 *
3512 * \note
3513 * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()
3514 *
3515 * \par<b>Related APIs:</b><BR>
3516 * XMC_SCU_HIB_EnableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(),
3517 * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_GetMirrorStatus() \n\n\n
3518 */
3519 void XMC_SCU_HIB_DisableInternalSlowClock(void);
3520
3521 /**
3522 * @param config Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. ::XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t
3523 * @return None
3524 *
3525 * \par<b>Description</b><br>
3526 * Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state.
3527 * In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state.
3528 * Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state.
3529 *
3530 * The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is
3531 * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is
3532 * stopped.
3533 *
3534 * In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked
3535 * by a free-running clock. Peripherals are only clocked when configured to stay enabled.
3536 * Configuration of peripherals and any SRAM content is preserved.
3537 * The Flash module can be put into low-power mode to achieve a further power reduction.
3538 * On wake-up Flash module will be restarted again before instructions or data access is possible.
3539 * Any interrupt will bring the system back to operation via the NVIC.The clock setup before
3540 * entering Deep Sleep state is restored upon wake-up.
3541 *
3542 * @usage
3543 * @code
3544 * // Configure system during SLEEP state
3545 * XMC_SCU_CLOCK_SetDeepSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI |
3546 * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN |
3547 * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN);
3548 *
3549 * // Make sure that SLEEPDEEP bit is set
3550 * SCB->SCR |= SCB_SCR_DEEPSLEEP_Msk;
3551 *
3552 * // Return to SLEEP mode after handling the wakeup event
3553 * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
3554 *
3555 * // Put system in DEEPSLEEP state
3556 * __WFI();
3557 *
3558 * @endcode
3559 *
3560 *\par<b>Related APIs:</b><BR>
3561 * XMC_SCU_CLOCK_Init() \n\n\n
3562 *
3563 */
XMC_SCU_CLOCK_SetDeepSleepConfig(int32_t config)3564 __STATIC_INLINE void XMC_SCU_CLOCK_SetDeepSleepConfig(int32_t config)
3565 {
3566 SCU_CLK->DSLEEPCR = config;
3567 }
3568
3569 /**
3570 * @param config Defines the source of the system clock and peripherals clock gating in SLEEP state. ::XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t
3571 * @return None
3572 *
3573 * \par<b>Description</b><br>
3574 * Defines the source of the system clock and peripherals clock gating in SLEEP state.
3575 *
3576 * The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is
3577 * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is
3578 * stopped. Peripherals are only clocked when configured to stay enabled.
3579 *
3580 * Peripherals can continue to operate unaffected and eventually generate an event to
3581 * wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The
3582 * clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP
3583 * state.
3584 *
3585 * @usage
3586 * @code
3587 * // Configure system during SLEEP state
3588 * XMC_SCU_CLOCK_SetSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI);
3589 *
3590 * // Make sure that SLEEPDEEP bit is cleared
3591 * SCB->SCR &= ~ SCB_SCR_DEEPSLEEP_Msk;
3592 *
3593 * // Return to SLEEP mode after handling the wakeup event
3594 * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
3595 *
3596 * // Put system in SLEEP state
3597 * __WFI();
3598 *
3599 * @endcode
3600 *
3601 *\par<b>Related APIs:</b><BR>
3602 * XMC_SCU_CLOCK_Init() \n\n\n
3603 *
3604 */
XMC_SCU_CLOCK_SetSleepConfig(int32_t config)3605 __STATIC_INLINE void XMC_SCU_CLOCK_SetSleepConfig(int32_t config)
3606 {
3607 SCU_CLK->SLEEPCR = config;
3608 }
3609
3610 /**
3611 * @}
3612 */
3613
3614 /**
3615 * @}
3616 */
3617
3618 #ifdef __cplusplus
3619 }
3620 #endif
3621
3622 #endif /* UC_FAMILY == XMC4 */
3623
3624 #endif /* XMC4_SCU_H */
3625
3626
