1 /********************************************************************************************************************* 2 * Copyright (c) 2011-2017, Infineon Technologies AG 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 6 * following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 9 * disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 12 * disclaimer in the documentation and/or other materials provided with the distribution. 13 * 14 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 15 * products derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 26 * Infineon Technologies AG dave@infineon.com). 27 *********************************************************************************************************************/ 28 29 30 /****************************************************************************************************//** 31 * @file XMC4500.h 32 * 33 * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for 34 * XMC4500 from Infineon. 35 * 36 * @version V1.6.1 (Reference Manual v1.6) 37 * @date 19. June 2017 38 * 39 * @note Generated with SVDConv V2.87l 40 * from CMSIS SVD File 'XMC4500_Processed_SVD.xml' Version 1.6.0 (Reference Manual v1.6), 41 * added support for ARM Compiler 6 (armclang) 42 *******************************************************************************************************/ 43 44 45 46 /** @addtogroup Infineon 47 * @{ 48 */ 49 50 /** @addtogroup XMC4500 51 * @{ 52 */ 53 54 #ifndef XMC4500_H 55 #define XMC4500_H 56 57 #ifdef __cplusplus 58 extern "C" { 59 #endif 60 61 62 /* ------------------------- Interrupt Number Definition ------------------------ */ 63 64 typedef enum { 65 /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ 66 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ 67 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ 68 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ 69 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation 70 and No Match */ 71 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 72 related Fault */ 73 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 74 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ 75 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ 76 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ 77 SysTick_IRQn = -1, /*!< 15 System Tick Timer */ 78 /* --------------------- XMC4500 Specific Interrupt Numbers --------------------- */ 79 SCU_0_IRQn = 0, /*!< 0 System Control */ 80 ERU0_0_IRQn = 1, /*!< 1 External Request Unit 0 */ 81 ERU0_1_IRQn = 2, /*!< 2 External Request Unit 0 */ 82 ERU0_2_IRQn = 3, /*!< 3 External Request Unit 0 */ 83 ERU0_3_IRQn = 4, /*!< 4 External Request Unit 0 */ 84 ERU1_0_IRQn = 5, /*!< 5 External Request Unit 1 */ 85 ERU1_1_IRQn = 6, /*!< 6 External Request Unit 1 */ 86 ERU1_2_IRQn = 7, /*!< 7 External Request Unit 1 */ 87 ERU1_3_IRQn = 8, /*!< 8 External Request Unit 1 */ 88 PMU0_0_IRQn = 12, /*!< 12 Program Management Unit */ 89 VADC0_C0_0_IRQn = 14, /*!< 14 Analog to Digital Converter Common Block 0 */ 90 VADC0_C0_1_IRQn = 15, /*!< 15 Analog to Digital Converter Common Block 0 */ 91 VADC0_C0_2_IRQn = 16, /*!< 16 Analog to Digital Converter Common Block 0 */ 92 VADC0_C0_3_IRQn = 17, /*!< 17 Analog to Digital Converter Common Block 0 */ 93 VADC0_G0_0_IRQn = 18, /*!< 18 Analog to Digital Converter Group 0 */ 94 VADC0_G0_1_IRQn = 19, /*!< 19 Analog to Digital Converter Group 0 */ 95 VADC0_G0_2_IRQn = 20, /*!< 20 Analog to Digital Converter Group 0 */ 96 VADC0_G0_3_IRQn = 21, /*!< 21 Analog to Digital Converter Group 0 */ 97 VADC0_G1_0_IRQn = 22, /*!< 22 Analog to Digital Converter Group 1 */ 98 VADC0_G1_1_IRQn = 23, /*!< 23 Analog to Digital Converter Group 1 */ 99 VADC0_G1_2_IRQn = 24, /*!< 24 Analog to Digital Converter Group 1 */ 100 VADC0_G1_3_IRQn = 25, /*!< 25 Analog to Digital Converter Group 1 */ 101 VADC0_G2_0_IRQn = 26, /*!< 26 Analog to Digital Converter Group 2 */ 102 VADC0_G2_1_IRQn = 27, /*!< 27 Analog to Digital Converter Group 2 */ 103 VADC0_G2_2_IRQn = 28, /*!< 28 Analog to Digital Converter Group 2 */ 104 VADC0_G2_3_IRQn = 29, /*!< 29 Analog to Digital Converter Group 2 */ 105 VADC0_G3_0_IRQn = 30, /*!< 30 Analog to Digital Converter Group 3 */ 106 VADC0_G3_1_IRQn = 31, /*!< 31 Analog to Digital Converter Group 3 */ 107 VADC0_G3_2_IRQn = 32, /*!< 32 Analog to Digital Converter Group 3 */ 108 VADC0_G3_3_IRQn = 33, /*!< 33 Analog to Digital Converter Group 3 */ 109 DSD0_M_0_IRQn = 34, /*!< 34 Delta Sigma Demodulator Main */ 110 DSD0_M_1_IRQn = 35, /*!< 35 Delta Sigma Demodulator Main */ 111 DSD0_M_2_IRQn = 36, /*!< 36 Delta Sigma Demodulator Main */ 112 DSD0_M_3_IRQn = 37, /*!< 37 Delta Sigma Demodulator Main */ 113 DSD0_A_4_IRQn = 38, /*!< 38 Delta Sigma Demodulator Auxiliary */ 114 DSD0_A_5_IRQn = 39, /*!< 39 Delta Sigma Demodulator Auxiliary */ 115 DSD0_A_6_IRQn = 40, /*!< 40 Delta Sigma Demodulator Auxiliary */ 116 DSD0_A_7_IRQn = 41, /*!< 41 Delta Sigma Demodulator Auxiliary */ 117 DAC0_0_IRQn = 42, /*!< 42 Digital to Analog Converter */ 118 DAC0_1_IRQn = 43, /*!< 43 Digital to Analog Converter */ 119 CCU40_0_IRQn = 44, /*!< 44 Capture Compare Unit 4 (Module 0) */ 120 CCU40_1_IRQn = 45, /*!< 45 Capture Compare Unit 4 (Module 0) */ 121 CCU40_2_IRQn = 46, /*!< 46 Capture Compare Unit 4 (Module 0) */ 122 CCU40_3_IRQn = 47, /*!< 47 Capture Compare Unit 4 (Module 0) */ 123 CCU41_0_IRQn = 48, /*!< 48 Capture Compare Unit 4 (Module 1) */ 124 CCU41_1_IRQn = 49, /*!< 49 Capture Compare Unit 4 (Module 1) */ 125 CCU41_2_IRQn = 50, /*!< 50 Capture Compare Unit 4 (Module 1) */ 126 CCU41_3_IRQn = 51, /*!< 51 Capture Compare Unit 4 (Module 1) */ 127 CCU42_0_IRQn = 52, /*!< 52 Capture Compare Unit 4 (Module 2) */ 128 CCU42_1_IRQn = 53, /*!< 53 Capture Compare Unit 4 (Module 2) */ 129 CCU42_2_IRQn = 54, /*!< 54 Capture Compare Unit 4 (Module 2) */ 130 CCU42_3_IRQn = 55, /*!< 55 Capture Compare Unit 4 (Module 2) */ 131 CCU43_0_IRQn = 56, /*!< 56 Capture Compare Unit 4 (Module 3) */ 132 CCU43_1_IRQn = 57, /*!< 57 Capture Compare Unit 4 (Module 3) */ 133 CCU43_2_IRQn = 58, /*!< 58 Capture Compare Unit 4 (Module 3) */ 134 CCU43_3_IRQn = 59, /*!< 59 Capture Compare Unit 4 (Module 3) */ 135 CCU80_0_IRQn = 60, /*!< 60 Capture Compare Unit 8 (Module 0) */ 136 CCU80_1_IRQn = 61, /*!< 61 Capture Compare Unit 8 (Module 0) */ 137 CCU80_2_IRQn = 62, /*!< 62 Capture Compare Unit 8 (Module 0) */ 138 CCU80_3_IRQn = 63, /*!< 63 Capture Compare Unit 8 (Module 0) */ 139 CCU81_0_IRQn = 64, /*!< 64 Capture Compare Unit 8 (Module 1) */ 140 CCU81_1_IRQn = 65, /*!< 65 Capture Compare Unit 8 (Module 1) */ 141 CCU81_2_IRQn = 66, /*!< 66 Capture Compare Unit 8 (Module 1) */ 142 CCU81_3_IRQn = 67, /*!< 67 Capture Compare Unit 8 (Module 1) */ 143 POSIF0_0_IRQn = 68, /*!< 68 Position Interface (Module 0) */ 144 POSIF0_1_IRQn = 69, /*!< 69 Position Interface (Module 0) */ 145 POSIF1_0_IRQn = 70, /*!< 70 Position Interface (Module 1) */ 146 POSIF1_1_IRQn = 71, /*!< 71 Position Interface (Module 1) */ 147 CAN0_0_IRQn = 76, /*!< 76 MultiCAN */ 148 CAN0_1_IRQn = 77, /*!< 77 MultiCAN */ 149 CAN0_2_IRQn = 78, /*!< 78 MultiCAN */ 150 CAN0_3_IRQn = 79, /*!< 79 MultiCAN */ 151 CAN0_4_IRQn = 80, /*!< 80 MultiCAN */ 152 CAN0_5_IRQn = 81, /*!< 81 MultiCAN */ 153 CAN0_6_IRQn = 82, /*!< 82 MultiCAN */ 154 CAN0_7_IRQn = 83, /*!< 83 MultiCAN */ 155 USIC0_0_IRQn = 84, /*!< 84 Universal Serial Interface Channel (Module 0) */ 156 USIC0_1_IRQn = 85, /*!< 85 Universal Serial Interface Channel (Module 0) */ 157 USIC0_2_IRQn = 86, /*!< 86 Universal Serial Interface Channel (Module 0) */ 158 USIC0_3_IRQn = 87, /*!< 87 Universal Serial Interface Channel (Module 0) */ 159 USIC0_4_IRQn = 88, /*!< 88 Universal Serial Interface Channel (Module 0) */ 160 USIC0_5_IRQn = 89, /*!< 89 Universal Serial Interface Channel (Module 0) */ 161 USIC1_0_IRQn = 90, /*!< 90 Universal Serial Interface Channel (Module 1) */ 162 USIC1_1_IRQn = 91, /*!< 91 Universal Serial Interface Channel (Module 1) */ 163 USIC1_2_IRQn = 92, /*!< 92 Universal Serial Interface Channel (Module 1) */ 164 USIC1_3_IRQn = 93, /*!< 93 Universal Serial Interface Channel (Module 1) */ 165 USIC1_4_IRQn = 94, /*!< 94 Universal Serial Interface Channel (Module 1) */ 166 USIC1_5_IRQn = 95, /*!< 95 Universal Serial Interface Channel (Module 1) */ 167 USIC2_0_IRQn = 96, /*!< 96 Universal Serial Interface Channel (Module 2) */ 168 USIC2_1_IRQn = 97, /*!< 97 Universal Serial Interface Channel (Module 2) */ 169 USIC2_2_IRQn = 98, /*!< 98 Universal Serial Interface Channel (Module 2) */ 170 USIC2_3_IRQn = 99, /*!< 99 Universal Serial Interface Channel (Module 2) */ 171 USIC2_4_IRQn = 100, /*!< 100 Universal Serial Interface Channel (Module 2) */ 172 USIC2_5_IRQn = 101, /*!< 101 Universal Serial Interface Channel (Module 2) */ 173 LEDTS0_0_IRQn = 102, /*!< 102 LED and Touch Sense Control Unit (Module 0) */ 174 FCE0_0_IRQn = 104, /*!< 104 Flexible CRC Engine */ 175 GPDMA0_0_IRQn = 105, /*!< 105 General Purpose DMA Unit 0 */ 176 SDMMC0_0_IRQn = 106, /*!< 106 Multi Media Card Interface */ 177 USB0_0_IRQn = 107, /*!< 107 Universal Serial Bus (Module 0) */ 178 ETH0_0_IRQn = 108, /*!< 108 Ethernet (Module 0) */ 179 GPDMA1_0_IRQn = 110 /*!< 110 General Purpose DMA Unit 1 */ 180 } IRQn_Type; 181 182 183 /** @addtogroup Configuration_of_CMSIS 184 * @{ 185 */ 186 187 188 /* ================================================================================ */ 189 /* ================ Processor and Core Peripheral Section ================ */ 190 /* ================================================================================ */ 191 192 /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ 193 #define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ 194 #define __MPU_PRESENT 1 /*!< MPU present or not */ 195 #define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ 196 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 197 #define __FPU_PRESENT 1 /*!< FPU present or not */ 198 /** @} */ /* End of group Configuration_of_CMSIS */ 199 200 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ 201 #include "system_XMC4500.h" /*!< XMC4500 System */ 202 203 204 /* ================================================================================ */ 205 /* ================ Device Specific Peripheral Section ================ */ 206 /* ================================================================================ */ 207 /* Macro to modify desired bitfields of a register */ 208 #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ 209 ((uint32_t)mask)) | \ 210 (reg & ((uint32_t)~((uint32_t)mask))) 211 212 /* Macro to modify desired bitfields of a register */ 213 #define WR_REG_SIZE(reg, mask, pos, val, size) { \ 214 uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ 215 uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ 216 uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ 217 uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ 218 reg = (uint##size##_t) (VAL2 | VAL4);\ 219 } 220 221 /** Macro to read bitfields from a register */ 222 #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) 223 224 /** Macro to read bitfields from a register */ 225 #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ 226 (uint32_t)mask) >> pos) ) 227 228 /** Macro to set a bit in register */ 229 #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos)) 230 231 /** Macro to clear a bit in register */ 232 #define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) ) 233 /* 234 * ========================================================================== 235 * ---------- Interrupt Handler Definition ---------------------------------- 236 * ========================================================================== 237 */ 238 #define IRQ_Hdlr_0 SCU_0_IRQHandler 239 #define IRQ_Hdlr_1 ERU0_0_IRQHandler 240 #define IRQ_Hdlr_2 ERU0_1_IRQHandler 241 #define IRQ_Hdlr_3 ERU0_2_IRQHandler 242 #define IRQ_Hdlr_4 ERU0_3_IRQHandler 243 #define IRQ_Hdlr_5 ERU1_0_IRQHandler 244 #define IRQ_Hdlr_6 ERU1_1_IRQHandler 245 #define IRQ_Hdlr_7 ERU1_2_IRQHandler 246 #define IRQ_Hdlr_8 ERU1_3_IRQHandler 247 #define IRQ_Hdlr_12 PMU0_0_IRQHandler 248 #define IRQ_Hdlr_14 VADC0_C0_0_IRQHandler 249 #define IRQ_Hdlr_15 VADC0_C0_1_IRQHandler 250 #define IRQ_Hdlr_16 VADC0_C0_2_IRQHandler 251 #define IRQ_Hdlr_17 VADC0_C0_3_IRQHandler 252 #define IRQ_Hdlr_18 VADC0_G0_0_IRQHandler 253 #define IRQ_Hdlr_19 VADC0_G0_1_IRQHandler 254 #define IRQ_Hdlr_20 VADC0_G0_2_IRQHandler 255 #define IRQ_Hdlr_21 VADC0_G0_3_IRQHandler 256 #define IRQ_Hdlr_22 VADC0_G1_0_IRQHandler 257 #define IRQ_Hdlr_23 VADC0_G1_1_IRQHandler 258 #define IRQ_Hdlr_24 VADC0_G1_2_IRQHandler 259 #define IRQ_Hdlr_25 VADC0_G1_3_IRQHandler 260 #define IRQ_Hdlr_26 VADC0_G2_0_IRQHandler 261 #define IRQ_Hdlr_27 VADC0_G2_1_IRQHandler 262 #define IRQ_Hdlr_28 VADC0_G2_2_IRQHandler 263 #define IRQ_Hdlr_29 VADC0_G2_3_IRQHandler 264 #define IRQ_Hdlr_30 VADC0_G3_0_IRQHandler 265 #define IRQ_Hdlr_31 VADC0_G3_1_IRQHandler 266 #define IRQ_Hdlr_32 VADC0_G3_2_IRQHandler 267 #define IRQ_Hdlr_33 VADC0_G3_3_IRQHandler 268 #define IRQ_Hdlr_34 DSD0_0_IRQHandler 269 #define IRQ_Hdlr_35 DSD0_1_IRQHandler 270 #define IRQ_Hdlr_36 DSD0_2_IRQHandler 271 #define IRQ_Hdlr_37 DSD0_3_IRQHandler 272 #define IRQ_Hdlr_38 DSD0_4_IRQHandler 273 #define IRQ_Hdlr_39 DSD0_5_IRQHandler 274 #define IRQ_Hdlr_40 DSD0_6_IRQHandler 275 #define IRQ_Hdlr_41 DSD0_7_IRQHandler 276 #define IRQ_Hdlr_42 DAC0_0_IRQHandler 277 #define IRQ_Hdlr_43 DAC0_1_IRQHandler 278 #define IRQ_Hdlr_44 CCU40_0_IRQHandler 279 #define IRQ_Hdlr_45 CCU40_1_IRQHandler 280 #define IRQ_Hdlr_46 CCU40_2_IRQHandler 281 #define IRQ_Hdlr_47 CCU40_3_IRQHandler 282 #define IRQ_Hdlr_48 CCU41_0_IRQHandler 283 #define IRQ_Hdlr_49 CCU41_1_IRQHandler 284 #define IRQ_Hdlr_50 CCU41_2_IRQHandler 285 #define IRQ_Hdlr_51 CCU41_3_IRQHandler 286 #define IRQ_Hdlr_52 CCU42_0_IRQHandler 287 #define IRQ_Hdlr_53 CCU42_1_IRQHandler 288 #define IRQ_Hdlr_54 CCU42_2_IRQHandler 289 #define IRQ_Hdlr_55 CCU42_3_IRQHandler 290 #define IRQ_Hdlr_56 CCU43_0_IRQHandler 291 #define IRQ_Hdlr_57 CCU43_1_IRQHandler 292 #define IRQ_Hdlr_58 CCU43_2_IRQHandler 293 #define IRQ_Hdlr_59 CCU43_3_IRQHandler 294 #define IRQ_Hdlr_60 CCU80_0_IRQHandler 295 #define IRQ_Hdlr_61 CCU80_1_IRQHandler 296 #define IRQ_Hdlr_62 CCU80_2_IRQHandler 297 #define IRQ_Hdlr_63 CCU80_3_IRQHandler 298 #define IRQ_Hdlr_64 CCU81_0_IRQHandler 299 #define IRQ_Hdlr_65 CCU81_1_IRQHandler 300 #define IRQ_Hdlr_66 CCU81_2_IRQHandler 301 #define IRQ_Hdlr_67 CCU81_3_IRQHandler 302 #define IRQ_Hdlr_68 POSIF0_0_IRQHandler 303 #define IRQ_Hdlr_69 POSIF0_1_IRQHandler 304 #define IRQ_Hdlr_70 POSIF1_0_IRQHandler 305 #define IRQ_Hdlr_71 POSIF1_1_IRQHandler 306 #define IRQ_Hdlr_76 CAN0_0_IRQHandler 307 #define IRQ_Hdlr_77 CAN0_1_IRQHandler 308 #define IRQ_Hdlr_78 CAN0_2_IRQHandler 309 #define IRQ_Hdlr_79 CAN0_3_IRQHandler 310 #define IRQ_Hdlr_80 CAN0_4_IRQHandler 311 #define IRQ_Hdlr_81 CAN0_5_IRQHandler 312 #define IRQ_Hdlr_82 CAN0_6_IRQHandler 313 #define IRQ_Hdlr_83 CAN0_7_IRQHandler 314 #define IRQ_Hdlr_84 USIC0_0_IRQHandler 315 #define IRQ_Hdlr_85 USIC0_1_IRQHandler 316 #define IRQ_Hdlr_86 USIC0_2_IRQHandler 317 #define IRQ_Hdlr_87 USIC0_3_IRQHandler 318 #define IRQ_Hdlr_88 USIC0_4_IRQHandler 319 #define IRQ_Hdlr_89 USIC0_5_IRQHandler 320 #define IRQ_Hdlr_90 USIC1_0_IRQHandler 321 #define IRQ_Hdlr_91 USIC1_1_IRQHandler 322 #define IRQ_Hdlr_92 USIC1_2_IRQHandler 323 #define IRQ_Hdlr_93 USIC1_3_IRQHandler 324 #define IRQ_Hdlr_94 USIC1_4_IRQHandler 325 #define IRQ_Hdlr_95 USIC1_5_IRQHandler 326 #define IRQ_Hdlr_96 USIC2_0_IRQHandler 327 #define IRQ_Hdlr_97 USIC2_1_IRQHandler 328 #define IRQ_Hdlr_98 USIC2_2_IRQHandler 329 #define IRQ_Hdlr_99 USIC2_3_IRQHandler 330 #define IRQ_Hdlr_100 USIC2_4_IRQHandler 331 #define IRQ_Hdlr_101 USIC2_5_IRQHandler 332 #define IRQ_Hdlr_102 LEDTS0_0_IRQHandler 333 #define IRQ_Hdlr_104 FCE0_0_IRQHandler 334 #define IRQ_Hdlr_105 GPDMA0_0_IRQHandler 335 #define IRQ_Hdlr_106 SDMMC0_0_IRQHandler 336 #define IRQ_Hdlr_107 USB0_0_IRQHandler 337 #define IRQ_Hdlr_108 ETH0_0_IRQHandler 338 #define IRQ_Hdlr_110 GPDMA1_0_IRQHandler 339 340 /* 341 * ========================================================================== 342 * ---------- Interrupt Handler retrieval macro ----------------------------- 343 * ========================================================================== 344 */ 345 #define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N 346 347 /** @addtogroup Device_Peripheral_Registers 348 * @{ 349 */ 350 351 352 /* ------------------- Start of section using anonymous unions ------------------ */ 353 #if defined(__CC_ARM) 354 #pragma push 355 #pragma anon_unions 356 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 357 #pragma clang diagnostic push 358 #pragma clang diagnostic ignored "-Wc11-extensions" 359 #pragma clang diagnostic ignored "-Wreserved-id-macro" 360 #elif defined(__ICCARM__) 361 #pragma language=extended 362 #elif defined(__GNUC__) 363 /* anonymous unions are enabled by default */ 364 #elif defined(__TMS470__) 365 /* anonymous unions are enabled by default */ 366 #elif defined(__TASKING__) 367 #pragma warning 586 368 #else 369 #warning Not supported compiler type 370 #endif 371 372 373 374 /* ================================================================================ */ 375 /* ================ PPB ================ */ 376 /* ================================================================================ */ 377 378 379 /** 380 * @brief Cortex-M4 Private Peripheral Block (PPB) 381 */ 382 383 typedef struct { /*!< (@ 0xE000E000) PPB Structure */ 384 __I uint32_t RESERVED[2]; 385 __IO uint32_t ACTLR; /*!< (@ 0xE000E008) Auxiliary Control Register */ 386 __I uint32_t RESERVED1; 387 __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */ 388 __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */ 389 __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */ 390 __IO uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register r */ 391 __I uint32_t RESERVED2[56]; 392 __IO uint32_t NVIC_ISER0; /*!< (@ 0xE000E100) Interrupt Set-enable Register 0 */ 393 __IO uint32_t NVIC_ISER1; /*!< (@ 0xE000E104) Interrupt Set-enable Register 1 */ 394 __IO uint32_t NVIC_ISER2; /*!< (@ 0xE000E108) Interrupt Set-enable Register 2 */ 395 __IO uint32_t NVIC_ISER3; /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3 */ 396 __I uint32_t RESERVED3[28]; 397 __IO uint32_t NVIC_ICER0; /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0 */ 398 __IO uint32_t NVIC_ICER1; /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1 */ 399 __IO uint32_t NVIC_ICER2; /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2 */ 400 __IO uint32_t NVIC_ICER3; /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3 */ 401 __I uint32_t RESERVED4[28]; 402 __IO uint32_t NVIC_ISPR0; /*!< (@ 0xE000E200) Interrupt Set-pending Register 0 */ 403 __IO uint32_t NVIC_ISPR1; /*!< (@ 0xE000E204) Interrupt Set-pending Register 1 */ 404 __IO uint32_t NVIC_ISPR2; /*!< (@ 0xE000E208) Interrupt Set-pending Register 2 */ 405 __IO uint32_t NVIC_ISPR3; /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3 */ 406 __I uint32_t RESERVED5[28]; 407 __IO uint32_t NVIC_ICPR0; /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0 */ 408 __IO uint32_t NVIC_ICPR1; /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1 */ 409 __IO uint32_t NVIC_ICPR2; /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2 */ 410 __IO uint32_t NVIC_ICPR3; /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3 */ 411 __I uint32_t RESERVED6[28]; 412 __IO uint32_t NVIC_IABR0; /*!< (@ 0xE000E300) Interrupt Active Bit Register 0 */ 413 __IO uint32_t NVIC_IABR1; /*!< (@ 0xE000E304) Interrupt Active Bit Register 1 */ 414 __IO uint32_t NVIC_IABR2; /*!< (@ 0xE000E308) Interrupt Active Bit Register 2 */ 415 __IO uint32_t NVIC_IABR3; /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3 */ 416 __I uint32_t RESERVED7[60]; 417 __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */ 418 __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */ 419 __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */ 420 __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */ 421 __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */ 422 __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */ 423 __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */ 424 __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */ 425 __IO uint32_t NVIC_IPR8; /*!< (@ 0xE000E420) Interrupt Priority Register 8 */ 426 __IO uint32_t NVIC_IPR9; /*!< (@ 0xE000E424) Interrupt Priority Register 9 */ 427 __IO uint32_t NVIC_IPR10; /*!< (@ 0xE000E428) Interrupt Priority Register 10 */ 428 __IO uint32_t NVIC_IPR11; /*!< (@ 0xE000E42C) Interrupt Priority Register 11 */ 429 __IO uint32_t NVIC_IPR12; /*!< (@ 0xE000E430) Interrupt Priority Register 12 */ 430 __IO uint32_t NVIC_IPR13; /*!< (@ 0xE000E434) Interrupt Priority Register 13 */ 431 __IO uint32_t NVIC_IPR14; /*!< (@ 0xE000E438) Interrupt Priority Register 14 */ 432 __IO uint32_t NVIC_IPR15; /*!< (@ 0xE000E43C) Interrupt Priority Register 15 */ 433 __IO uint32_t NVIC_IPR16; /*!< (@ 0xE000E440) Interrupt Priority Register 16 */ 434 __IO uint32_t NVIC_IPR17; /*!< (@ 0xE000E444) Interrupt Priority Register 17 */ 435 __IO uint32_t NVIC_IPR18; /*!< (@ 0xE000E448) Interrupt Priority Register 18 */ 436 __IO uint32_t NVIC_IPR19; /*!< (@ 0xE000E44C) Interrupt Priority Register 19 */ 437 __IO uint32_t NVIC_IPR20; /*!< (@ 0xE000E450) Interrupt Priority Register 20 */ 438 __IO uint32_t NVIC_IPR21; /*!< (@ 0xE000E454) Interrupt Priority Register 21 */ 439 __IO uint32_t NVIC_IPR22; /*!< (@ 0xE000E458) Interrupt Priority Register 22 */ 440 __IO uint32_t NVIC_IPR23; /*!< (@ 0xE000E45C) Interrupt Priority Register 23 */ 441 __IO uint32_t NVIC_IPR24; /*!< (@ 0xE000E460) Interrupt Priority Register 24 */ 442 __IO uint32_t NVIC_IPR25; /*!< (@ 0xE000E464) Interrupt Priority Register 25 */ 443 __IO uint32_t NVIC_IPR26; /*!< (@ 0xE000E468) Interrupt Priority Register 26 */ 444 __IO uint32_t NVIC_IPR27; /*!< (@ 0xE000E46C) Interrupt Priority Register 27 */ 445 __I uint32_t RESERVED8[548]; 446 __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */ 447 __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */ 448 __IO uint32_t VTOR; /*!< (@ 0xE000ED08) Vector Table Offset Register */ 449 __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */ 450 __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */ 451 __IO uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */ 452 __IO uint32_t SHPR1; /*!< (@ 0xE000ED18) System Handler Priority Register 1 */ 453 __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */ 454 __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */ 455 __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */ 456 __IO uint32_t CFSR; /*!< (@ 0xE000ED28) Configurable Fault Status Register */ 457 __IO uint32_t HFSR; /*!< (@ 0xE000ED2C) HardFault Status Register */ 458 __I uint32_t RESERVED9; 459 __IO uint32_t MMFAR; /*!< (@ 0xE000ED34) MemManage Fault Address Register */ 460 __IO uint32_t BFAR; /*!< (@ 0xE000ED38) BusFault Address Register */ 461 __IO uint32_t AFSR; /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */ 462 __I uint32_t RESERVED10[18]; 463 __IO uint32_t CPACR; /*!< (@ 0xE000ED88) Coprocessor Access Control Register */ 464 __I uint32_t RESERVED11; 465 __I uint32_t MPU_TYPE; /*!< (@ 0xE000ED90) MPU Type Register */ 466 __IO uint32_t MPU_CTRL; /*!< (@ 0xE000ED94) MPU Control Register */ 467 __IO uint32_t MPU_RNR; /*!< (@ 0xE000ED98) MPU Region Number Register */ 468 __IO uint32_t MPU_RBAR; /*!< (@ 0xE000ED9C) MPU Region Base Address Register */ 469 __IO uint32_t MPU_RASR; /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register */ 470 __IO uint32_t MPU_RBAR_A1; /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1 */ 471 __IO uint32_t MPU_RASR_A1; /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1 */ 472 __IO uint32_t MPU_RBAR_A2; /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2 */ 473 __IO uint32_t MPU_RASR_A2; /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2 */ 474 __IO uint32_t MPU_RBAR_A3; /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3 */ 475 __IO uint32_t MPU_RASR_A3; /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3 */ 476 __I uint32_t RESERVED12[81]; 477 __O uint32_t STIR; /*!< (@ 0xE000EF00) Software Trigger Interrupt Register */ 478 __I uint32_t RESERVED13[12]; 479 __IO uint32_t FPCCR; /*!< (@ 0xE000EF34) Floating-point Context Control Register */ 480 __IO uint32_t FPCAR; /*!< (@ 0xE000EF38) Floating-point Context Address Register */ 481 __IO uint32_t FPDSCR; /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register */ 482 } PPB_Type; 483 484 485 /* ================================================================================ */ 486 /* ================ DLR ================ */ 487 /* ================================================================================ */ 488 489 490 /** 491 * @brief DMA Line Router (DLR) 492 */ 493 494 typedef struct { /*!< (@ 0x50004900) DLR Structure */ 495 __I uint32_t OVRSTAT; /*!< (@ 0x50004900) Overrun Status */ 496 __O uint32_t OVRCLR; /*!< (@ 0x50004904) Overrun Clear */ 497 __IO uint32_t SRSEL0; /*!< (@ 0x50004908) Service Request Selection 0 */ 498 __IO uint32_t SRSEL1; /*!< (@ 0x5000490C) Service Request Selection 1 */ 499 __IO uint32_t LNEN; /*!< (@ 0x50004910) Line Enable */ 500 } DLR_GLOBAL_TypeDef; 501 502 503 /* ================================================================================ */ 504 /* ================ ERU [ERU0] ================ */ 505 /* ================================================================================ */ 506 507 508 /** 509 * @brief Event Request Unit 0 (ERU) 510 */ 511 512 typedef struct { /*!< (@ 0x50004800) ERU Structure */ 513 __IO uint32_t EXISEL; /*!< (@ 0x50004800) Event Input Select */ 514 __I uint32_t RESERVED[3]; 515 __IO uint32_t EXICON[4]; /*!< (@ 0x50004810) Event Input Control */ 516 __IO uint32_t EXOCON[4]; /*!< (@ 0x50004820) Event Output Trigger Control */ 517 } ERU_GLOBAL_TypeDef; 518 519 520 /* ================================================================================ */ 521 /* ================ GPDMA0 ================ */ 522 /* ================================================================================ */ 523 524 525 /** 526 * @brief General Purpose DMA Unit 0 (GPDMA0) 527 */ 528 529 typedef struct { /*!< (@ 0x500142C0) GPDMA0 Structure */ 530 __IO uint32_t RAWTFR; /*!< (@ 0x500142C0) Raw IntTfr Status */ 531 __I uint32_t RESERVED; 532 __IO uint32_t RAWBLOCK; /*!< (@ 0x500142C8) Raw IntBlock Status */ 533 __I uint32_t RESERVED1; 534 __IO uint32_t RAWSRCTRAN; /*!< (@ 0x500142D0) Raw IntSrcTran Status */ 535 __I uint32_t RESERVED2; 536 __IO uint32_t RAWDSTTRAN; /*!< (@ 0x500142D8) Raw IntBlock Status */ 537 __I uint32_t RESERVED3; 538 __IO uint32_t RAWERR; /*!< (@ 0x500142E0) Raw IntErr Status */ 539 __I uint32_t RESERVED4; 540 __I uint32_t STATUSTFR; /*!< (@ 0x500142E8) IntTfr Status */ 541 __I uint32_t RESERVED5; 542 __I uint32_t STATUSBLOCK; /*!< (@ 0x500142F0) IntBlock Status */ 543 __I uint32_t RESERVED6; 544 __I uint32_t STATUSSRCTRAN; /*!< (@ 0x500142F8) IntSrcTran Status */ 545 __I uint32_t RESERVED7; 546 __I uint32_t STATUSDSTTRAN; /*!< (@ 0x50014300) IntBlock Status */ 547 __I uint32_t RESERVED8; 548 __I uint32_t STATUSERR; /*!< (@ 0x50014308) IntErr Status */ 549 __I uint32_t RESERVED9; 550 __IO uint32_t MASKTFR; /*!< (@ 0x50014310) Mask for Raw IntTfr Status */ 551 __I uint32_t RESERVED10; 552 __IO uint32_t MASKBLOCK; /*!< (@ 0x50014318) Mask for Raw IntBlock Status */ 553 __I uint32_t RESERVED11; 554 __IO uint32_t MASKSRCTRAN; /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status */ 555 __I uint32_t RESERVED12; 556 __IO uint32_t MASKDSTTRAN; /*!< (@ 0x50014328) Mask for Raw IntBlock Status */ 557 __I uint32_t RESERVED13; 558 __IO uint32_t MASKERR; /*!< (@ 0x50014330) Mask for Raw IntErr Status */ 559 __I uint32_t RESERVED14; 560 __O uint32_t CLEARTFR; /*!< (@ 0x50014338) IntTfr Status */ 561 __I uint32_t RESERVED15; 562 __O uint32_t CLEARBLOCK; /*!< (@ 0x50014340) IntBlock Status */ 563 __I uint32_t RESERVED16; 564 __O uint32_t CLEARSRCTRAN; /*!< (@ 0x50014348) IntSrcTran Status */ 565 __I uint32_t RESERVED17; 566 __O uint32_t CLEARDSTTRAN; /*!< (@ 0x50014350) IntBlock Status */ 567 __I uint32_t RESERVED18; 568 __O uint32_t CLEARERR; /*!< (@ 0x50014358) IntErr Status */ 569 __I uint32_t RESERVED19; 570 __I uint32_t STATUSINT; /*!< (@ 0x50014360) Combined Interrupt Status Register */ 571 __I uint32_t RESERVED20; 572 __IO uint32_t REQSRCREG; /*!< (@ 0x50014368) Source Software Transaction Request Register */ 573 __I uint32_t RESERVED21; 574 __IO uint32_t REQDSTREG; /*!< (@ 0x50014370) Destination Software Transaction Request Register */ 575 __I uint32_t RESERVED22; 576 __IO uint32_t SGLREQSRCREG; /*!< (@ 0x50014378) Single Source Transaction Request Register */ 577 __I uint32_t RESERVED23; 578 __IO uint32_t SGLREQDSTREG; /*!< (@ 0x50014380) Single Destination Transaction Request Register */ 579 __I uint32_t RESERVED24; 580 __IO uint32_t LSTSRCREG; /*!< (@ 0x50014388) Last Source Transaction Request Register */ 581 __I uint32_t RESERVED25; 582 __IO uint32_t LSTDSTREG; /*!< (@ 0x50014390) Last Destination Transaction Request Register */ 583 __I uint32_t RESERVED26; 584 __IO uint32_t DMACFGREG; /*!< (@ 0x50014398) GPDMA Configuration Register */ 585 __I uint32_t RESERVED27; 586 __IO uint32_t CHENREG; /*!< (@ 0x500143A0) GPDMA Channel Enable Register */ 587 __I uint32_t RESERVED28; 588 __I uint32_t ID; /*!< (@ 0x500143A8) GPDMA0 ID Register */ 589 __I uint32_t RESERVED29[19]; 590 __I uint32_t TYPE; /*!< (@ 0x500143F8) GPDMA Component Type */ 591 __I uint32_t VERSION; /*!< (@ 0x500143FC) DMA Component Version */ 592 } GPDMA0_GLOBAL_TypeDef; 593 594 595 /* ================================================================================ */ 596 /* ================ GPDMA0_CH0_1 [GPDMA0_CH0] ================ */ 597 /* ================================================================================ */ 598 599 600 /** 601 * @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1) 602 */ 603 604 typedef struct { /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure */ 605 __IO uint32_t SAR; /*!< (@ 0x50014000) Source Address Register */ 606 __I uint32_t RESERVED; 607 __IO uint32_t DAR; /*!< (@ 0x50014008) Destination Address Register */ 608 __I uint32_t RESERVED1; 609 __IO uint32_t LLP; /*!< (@ 0x50014010) Linked List Pointer Register */ 610 __I uint32_t RESERVED2; 611 __IO uint32_t CTLL; /*!< (@ 0x50014018) Control Register Low */ 612 __IO uint32_t CTLH; /*!< (@ 0x5001401C) Control Register High */ 613 __IO uint32_t SSTAT; /*!< (@ 0x50014020) Source Status Register */ 614 __I uint32_t RESERVED3; 615 __IO uint32_t DSTAT; /*!< (@ 0x50014028) Destination Status Register */ 616 __I uint32_t RESERVED4; 617 __IO uint32_t SSTATAR; /*!< (@ 0x50014030) Source Status Address Register */ 618 __I uint32_t RESERVED5; 619 __IO uint32_t DSTATAR; /*!< (@ 0x50014038) Destination Status Address Register */ 620 __I uint32_t RESERVED6; 621 __IO uint32_t CFGL; /*!< (@ 0x50014040) Configuration Register Low */ 622 __IO uint32_t CFGH; /*!< (@ 0x50014044) Configuration Register High */ 623 __IO uint32_t SGR; /*!< (@ 0x50014048) Source Gather Register */ 624 __I uint32_t RESERVED7; 625 __IO uint32_t DSR; /*!< (@ 0x50014050) Destination Scatter Register */ 626 } GPDMA0_CH_TypeDef; 627 628 629 /* ================================================================================ */ 630 /* ================ GPDMA0_CH2_7 [GPDMA0_CH2] ================ */ 631 /* ================================================================================ */ 632 633 634 /** 635 * @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7) 636 */ 637 638 typedef struct { /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure */ 639 __IO uint32_t SAR; /*!< (@ 0x500140B0) Source Address Register */ 640 __I uint32_t RESERVED; 641 __IO uint32_t DAR; /*!< (@ 0x500140B8) Destination Address Register */ 642 __I uint32_t RESERVED1[3]; 643 __IO uint32_t CTLL; /*!< (@ 0x500140C8) Control Register Low */ 644 __IO uint32_t CTLH; /*!< (@ 0x500140CC) Control Register High */ 645 __I uint32_t RESERVED2[8]; 646 __IO uint32_t CFGL; /*!< (@ 0x500140F0) Configuration Register Low */ 647 __IO uint32_t CFGH; /*!< (@ 0x500140F4) Configuration Register High */ 648 } GPDMA0_CH2_7_Type; 649 650 651 /* ================================================================================ */ 652 /* ================ GPDMA1 ================ */ 653 /* ================================================================================ */ 654 655 656 /** 657 * @brief General Purpose DMA Unit 1 (GPDMA1) 658 */ 659 660 typedef struct { /*!< (@ 0x500182C0) GPDMA1 Structure */ 661 __IO uint32_t RAWTFR; /*!< (@ 0x500182C0) Raw IntTfr Status */ 662 __I uint32_t RESERVED; 663 __IO uint32_t RAWBLOCK; /*!< (@ 0x500182C8) Raw IntBlock Status */ 664 __I uint32_t RESERVED1; 665 __IO uint32_t RAWSRCTRAN; /*!< (@ 0x500182D0) Raw IntSrcTran Status */ 666 __I uint32_t RESERVED2; 667 __IO uint32_t RAWDSTTRAN; /*!< (@ 0x500182D8) Raw IntBlock Status */ 668 __I uint32_t RESERVED3; 669 __IO uint32_t RAWERR; /*!< (@ 0x500182E0) Raw IntErr Status */ 670 __I uint32_t RESERVED4; 671 __I uint32_t STATUSTFR; /*!< (@ 0x500182E8) IntTfr Status */ 672 __I uint32_t RESERVED5; 673 __I uint32_t STATUSBLOCK; /*!< (@ 0x500182F0) IntBlock Status */ 674 __I uint32_t RESERVED6; 675 __I uint32_t STATUSSRCTRAN; /*!< (@ 0x500182F8) IntSrcTran Status */ 676 __I uint32_t RESERVED7; 677 __I uint32_t STATUSDSTTRAN; /*!< (@ 0x50018300) IntBlock Status */ 678 __I uint32_t RESERVED8; 679 __I uint32_t STATUSERR; /*!< (@ 0x50018308) IntErr Status */ 680 __I uint32_t RESERVED9; 681 __IO uint32_t MASKTFR; /*!< (@ 0x50018310) Mask for Raw IntTfr Status */ 682 __I uint32_t RESERVED10; 683 __IO uint32_t MASKBLOCK; /*!< (@ 0x50018318) Mask for Raw IntBlock Status */ 684 __I uint32_t RESERVED11; 685 __IO uint32_t MASKSRCTRAN; /*!< (@ 0x50018320) Mask for Raw IntSrcTran Status */ 686 __I uint32_t RESERVED12; 687 __IO uint32_t MASKDSTTRAN; /*!< (@ 0x50018328) Mask for Raw IntBlock Status */ 688 __I uint32_t RESERVED13; 689 __IO uint32_t MASKERR; /*!< (@ 0x50018330) Mask for Raw IntErr Status */ 690 __I uint32_t RESERVED14; 691 __O uint32_t CLEARTFR; /*!< (@ 0x50018338) IntTfr Status */ 692 __I uint32_t RESERVED15; 693 __O uint32_t CLEARBLOCK; /*!< (@ 0x50018340) IntBlock Status */ 694 __I uint32_t RESERVED16; 695 __O uint32_t CLEARSRCTRAN; /*!< (@ 0x50018348) IntSrcTran Status */ 696 __I uint32_t RESERVED17; 697 __O uint32_t CLEARDSTTRAN; /*!< (@ 0x50018350) IntBlock Status */ 698 __I uint32_t RESERVED18; 699 __O uint32_t CLEARERR; /*!< (@ 0x50018358) IntErr Status */ 700 __I uint32_t RESERVED19; 701 __I uint32_t STATUSINT; /*!< (@ 0x50018360) Combined Interrupt Status Register */ 702 __I uint32_t RESERVED20; 703 __IO uint32_t REQSRCREG; /*!< (@ 0x50018368) Source Software Transaction Request Register */ 704 __I uint32_t RESERVED21; 705 __IO uint32_t REQDSTREG; /*!< (@ 0x50018370) Destination Software Transaction Request Register */ 706 __I uint32_t RESERVED22; 707 __IO uint32_t SGLREQSRCREG; /*!< (@ 0x50018378) Single Source Transaction Request Register */ 708 __I uint32_t RESERVED23; 709 __IO uint32_t SGLREQDSTREG; /*!< (@ 0x50018380) Single Destination Transaction Request Register */ 710 __I uint32_t RESERVED24; 711 __IO uint32_t LSTSRCREG; /*!< (@ 0x50018388) Last Source Transaction Request Register */ 712 __I uint32_t RESERVED25; 713 __IO uint32_t LSTDSTREG; /*!< (@ 0x50018390) Last Destination Transaction Request Register */ 714 __I uint32_t RESERVED26; 715 __IO uint32_t DMACFGREG; /*!< (@ 0x50018398) GPDMA Configuration Register */ 716 __I uint32_t RESERVED27; 717 __IO uint32_t CHENREG; /*!< (@ 0x500183A0) GPDMA Channel Enable Register */ 718 __I uint32_t RESERVED28; 719 __I uint32_t ID; /*!< (@ 0x500183A8) GPDMA1 ID Register */ 720 __I uint32_t RESERVED29[19]; 721 __I uint32_t TYPE; /*!< (@ 0x500183F8) GPDMA Component Type */ 722 __I uint32_t VERSION; /*!< (@ 0x500183FC) DMA Component Version */ 723 } GPDMA1_GLOBAL_TypeDef; 724 725 726 /* ================================================================================ */ 727 /* ================ GPDMA1_CH [GPDMA1_CH0] ================ */ 728 /* ================================================================================ */ 729 730 731 /** 732 * @brief General Purpose DMA Unit 1 (GPDMA1_CH) 733 */ 734 735 typedef struct { /*!< (@ 0x50018000) GPDMA1_CH Structure */ 736 __IO uint32_t SAR; /*!< (@ 0x50018000) Source Address Register */ 737 __I uint32_t RESERVED; 738 __IO uint32_t DAR; /*!< (@ 0x50018008) Destination Address Register */ 739 __I uint32_t RESERVED1[3]; 740 __IO uint32_t CTLL; /*!< (@ 0x50018018) Control Register Low */ 741 __IO uint32_t CTLH; /*!< (@ 0x5001801C) Control Register High */ 742 __I uint32_t RESERVED2[8]; 743 __IO uint32_t CFGL; /*!< (@ 0x50018040) Configuration Register Low */ 744 __IO uint32_t CFGH; /*!< (@ 0x50018044) Configuration Register High */ 745 } GPDMA1_CH_TypeDef; 746 747 748 /* ================================================================================ */ 749 /* ================ FCE ================ */ 750 /* ================================================================================ */ 751 752 753 /** 754 * @brief Flexible CRC Engine (FCE) 755 */ 756 757 typedef struct { /*!< (@ 0x50020000) FCE Structure */ 758 __IO uint32_t CLC; /*!< (@ 0x50020000) Clock Control Register */ 759 __I uint32_t RESERVED; 760 __I uint32_t ID; /*!< (@ 0x50020008) Module Identification Register */ 761 } FCE_GLOBAL_TypeDef; 762 763 764 /* ================================================================================ */ 765 /* ================ FCE_KE [FCE_KE0] ================ */ 766 /* ================================================================================ */ 767 768 769 /** 770 * @brief Flexible CRC Engine (FCE_KE) 771 */ 772 773 typedef struct { /*!< (@ 0x50020020) FCE_KE Structure */ 774 __IO uint32_t IR; /*!< (@ 0x50020020) Input Register */ 775 __I uint32_t RES; /*!< (@ 0x50020024) CRC Result Register */ 776 __IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register */ 777 __IO uint32_t STS; /*!< (@ 0x5002002C) CRC Status Register */ 778 __IO uint32_t LENGTH; /*!< (@ 0x50020030) CRC Length Register */ 779 __IO uint32_t CHECK; /*!< (@ 0x50020034) CRC Check Register */ 780 __IO uint32_t CRC; /*!< (@ 0x50020038) CRC Register */ 781 __IO uint32_t CTR; /*!< (@ 0x5002003C) CRC Test Register */ 782 } FCE_KE_TypeDef; 783 784 785 /* ================================================================================ */ 786 /* ================ PBA [PBA0] ================ */ 787 /* ================================================================================ */ 788 789 790 /** 791 * @brief Peripheral Bridge AHB 0 (PBA) 792 */ 793 794 typedef struct { /*!< (@ 0x40000000) PBA Structure */ 795 __IO uint32_t STS; /*!< (@ 0x40000000) Peripheral Bridge Status Register */ 796 __I uint32_t WADDR; /*!< (@ 0x40000004) PBA Write Error Address Register */ 797 } PBA_GLOBAL_TypeDef; 798 799 800 /* ================================================================================ */ 801 /* ================ FLASH [FLASH0] ================ */ 802 /* ================================================================================ */ 803 804 805 /** 806 * @brief Flash Memory Controller (FLASH) 807 */ 808 809 typedef struct { /*!< (@ 0x58001000) FLASH Structure */ 810 __I uint32_t RESERVED[1026]; 811 __I uint32_t ID; /*!< (@ 0x58002008) Flash Module Identification Register */ 812 __I uint32_t RESERVED1; 813 __I uint32_t FSR; /*!< (@ 0x58002010) Flash Status Register */ 814 __IO uint32_t FCON; /*!< (@ 0x58002014) Flash Configuration Register */ 815 __IO uint32_t MARP; /*!< (@ 0x58002018) Margin Control Register PFLASH */ 816 __I uint32_t RESERVED2; 817 __I uint32_t PROCON0; /*!< (@ 0x58002020) Flash Protection Configuration Register User 818 0 */ 819 __I uint32_t PROCON1; /*!< (@ 0x58002024) Flash Protection Configuration Register User 820 1 */ 821 __I uint32_t PROCON2; /*!< (@ 0x58002028) Flash Protection Configuration Register User 822 2 */ 823 } FLASH0_GLOBAL_TypeDef; 824 825 826 /* ================================================================================ */ 827 /* ================ PREF ================ */ 828 /* ================================================================================ */ 829 830 831 /** 832 * @brief Prefetch Unit (PREF) 833 */ 834 835 typedef struct { /*!< (@ 0x58004000) PREF Structure */ 836 __IO uint32_t PCON; /*!< (@ 0x58004000) Prefetch Configuration Register */ 837 } PREF_GLOBAL_TypeDef; 838 839 840 /* ================================================================================ */ 841 /* ================ PMU [PMU0] ================ */ 842 /* ================================================================================ */ 843 844 845 /** 846 * @brief Program Management Unit (PMU) 847 */ 848 849 typedef struct { /*!< (@ 0x58000508) PMU Structure */ 850 __I uint32_t ID; /*!< (@ 0x58000508) PMU0 Identification Register */ 851 } PMU0_GLOBAL_TypeDef; 852 853 854 /* ================================================================================ */ 855 /* ================ WDT ================ */ 856 /* ================================================================================ */ 857 858 859 /** 860 * @brief Watch Dog Timer (WDT) 861 */ 862 863 typedef struct { /*!< (@ 0x50008000) WDT Structure */ 864 __I uint32_t ID; /*!< (@ 0x50008000) WDT ID Register */ 865 __IO uint32_t CTR; /*!< (@ 0x50008004) WDT Control Register */ 866 __O uint32_t SRV; /*!< (@ 0x50008008) WDT Service Register */ 867 __I uint32_t TIM; /*!< (@ 0x5000800C) WDT Timer Register */ 868 __IO uint32_t WLB; /*!< (@ 0x50008010) WDT Window Lower Bound Register */ 869 __IO uint32_t WUB; /*!< (@ 0x50008014) WDT Window Upper Bound Register */ 870 __I uint32_t WDTSTS; /*!< (@ 0x50008018) WDT Status Register */ 871 __O uint32_t WDTCLR; /*!< (@ 0x5000801C) WDT Clear Register */ 872 } WDT_GLOBAL_TypeDef; 873 874 875 /* ================================================================================ */ 876 /* ================ RTC ================ */ 877 /* ================================================================================ */ 878 879 880 /** 881 * @brief Real Time Clock (RTC) 882 */ 883 884 typedef struct { /*!< (@ 0x50004A00) RTC Structure */ 885 __I uint32_t ID; /*!< (@ 0x50004A00) RTC ID Register */ 886 __IO uint32_t CTR; /*!< (@ 0x50004A04) RTC Control Register */ 887 __I uint32_t RAWSTAT; /*!< (@ 0x50004A08) RTC Raw Service Request Register */ 888 __I uint32_t STSSR; /*!< (@ 0x50004A0C) RTC Service Request Status Register */ 889 __IO uint32_t MSKSR; /*!< (@ 0x50004A10) RTC Service Request Mask Register */ 890 __O uint32_t CLRSR; /*!< (@ 0x50004A14) RTC Clear Service Request Register */ 891 __IO uint32_t ATIM0; /*!< (@ 0x50004A18) RTC Alarm Time Register 0 */ 892 __IO uint32_t ATIM1; /*!< (@ 0x50004A1C) RTC Alarm Time Register 1 */ 893 __IO uint32_t TIM0; /*!< (@ 0x50004A20) RTC Time Register 0 */ 894 __IO uint32_t TIM1; /*!< (@ 0x50004A24) RTC Time Register 1 */ 895 } RTC_GLOBAL_TypeDef; 896 897 898 /* ================================================================================ */ 899 /* ================ SCU_CLK ================ */ 900 /* ================================================================================ */ 901 902 903 /** 904 * @brief System Control Unit (SCU_CLK) 905 */ 906 907 typedef struct { /*!< (@ 0x50004600) SCU_CLK Structure */ 908 __I uint32_t CLKSTAT; /*!< (@ 0x50004600) Clock Status Register */ 909 __O uint32_t CLKSET; /*!< (@ 0x50004604) CLK Set Register */ 910 __O uint32_t CLKCLR; /*!< (@ 0x50004608) CLK Clear Register */ 911 __IO uint32_t SYSCLKCR; /*!< (@ 0x5000460C) System Clock Control Register */ 912 __IO uint32_t CPUCLKCR; /*!< (@ 0x50004610) CPU Clock Control Register */ 913 __IO uint32_t PBCLKCR; /*!< (@ 0x50004614) Peripheral Bus Clock Control Register */ 914 __IO uint32_t USBCLKCR; /*!< (@ 0x50004618) USB Clock Control Register */ 915 __IO uint32_t EBUCLKCR; /*!< (@ 0x5000461C) EBU Clock Control Register */ 916 __IO uint32_t CCUCLKCR; /*!< (@ 0x50004620) CCU Clock Control Register */ 917 __IO uint32_t WDTCLKCR; /*!< (@ 0x50004624) WDT Clock Control Register */ 918 __IO uint32_t EXTCLKCR; /*!< (@ 0x50004628) External Clock Control */ 919 __I uint32_t RESERVED; 920 __IO uint32_t SLEEPCR; /*!< (@ 0x50004630) Sleep Control Register */ 921 __IO uint32_t DSLEEPCR; /*!< (@ 0x50004634) Deep Sleep Control Register */ 922 } SCU_CLK_TypeDef; 923 924 925 /* ================================================================================ */ 926 /* ================ SCU_OSC ================ */ 927 /* ================================================================================ */ 928 929 930 /** 931 * @brief System Control Unit (SCU_OSC) 932 */ 933 934 typedef struct { /*!< (@ 0x50004700) SCU_OSC Structure */ 935 __I uint32_t OSCHPSTAT; /*!< (@ 0x50004700) OSC_HP Status Register */ 936 __IO uint32_t OSCHPCTRL; /*!< (@ 0x50004704) OSC_HP Control Register */ 937 __I uint32_t RESERVED; 938 __IO uint32_t CLKCALCONST; /*!< (@ 0x5000470C) Clock Calibration Constant Register */ 939 } SCU_OSC_TypeDef; 940 941 942 /* ================================================================================ */ 943 /* ================ SCU_PLL ================ */ 944 /* ================================================================================ */ 945 946 947 /** 948 * @brief System Control Unit (SCU_PLL) 949 */ 950 951 typedef struct { /*!< (@ 0x50004710) SCU_PLL Structure */ 952 __I uint32_t PLLSTAT; /*!< (@ 0x50004710) PLL Status Register */ 953 __IO uint32_t PLLCON0; /*!< (@ 0x50004714) PLL Configuration 0 Register */ 954 __IO uint32_t PLLCON1; /*!< (@ 0x50004718) PLL Configuration 1 Register */ 955 __IO uint32_t PLLCON2; /*!< (@ 0x5000471C) PLL Configuration 2 Register */ 956 __I uint32_t USBPLLSTAT; /*!< (@ 0x50004720) USB PLL Status Register */ 957 __IO uint32_t USBPLLCON; /*!< (@ 0x50004724) USB PLL Configuration Register */ 958 __I uint32_t RESERVED[4]; 959 __I uint32_t CLKMXSTAT; /*!< (@ 0x50004738) Clock Multiplexing Status Register */ 960 } SCU_PLL_TypeDef; 961 962 963 /* ================================================================================ */ 964 /* ================ SCU_GENERAL ================ */ 965 /* ================================================================================ */ 966 967 968 /** 969 * @brief System Control Unit (SCU_GENERAL) 970 */ 971 972 typedef struct { /*!< (@ 0x50004000) SCU_GENERAL Structure */ 973 __I uint32_t ID; /*!< (@ 0x50004000) SCU Module ID Register */ 974 __I uint32_t IDCHIP; /*!< (@ 0x50004004) Chip ID Register */ 975 __I uint32_t IDMANUF; /*!< (@ 0x50004008) Manufactory ID Register */ 976 __I uint32_t RESERVED; 977 __IO uint32_t STCON; /*!< (@ 0x50004010) Startup Configuration Register */ 978 __I uint32_t RESERVED1[6]; 979 __IO uint32_t GPR[2]; /*!< (@ 0x5000402C) General Purpose Register 0 */ 980 __I uint32_t RESERVED2[6]; 981 __IO uint32_t CCUCON; /*!< (@ 0x5000404C) CCU Control Register */ 982 __I uint32_t RESERVED3[15]; 983 __IO uint32_t DTSCON; /*!< (@ 0x5000408C) Die Temperature Sensor Control Register */ 984 __I uint32_t DTSSTAT; /*!< (@ 0x50004090) Die Temperature Sensor Status Register */ 985 __I uint32_t RESERVED4[2]; 986 __IO uint32_t SDMMCDEL; /*!< (@ 0x5000409C) SD-MMC Delay Control Register */ 987 __IO uint32_t GORCEN[2]; /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0 */ 988 __I uint32_t RESERVED5[7]; 989 __I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register */ 990 __IO uint32_t RMACR; /*!< (@ 0x500040C8) Retention Memory Access Control Register */ 991 __IO uint32_t RMDATA; /*!< (@ 0x500040CC) Retention Memory Access Data Register */ 992 } SCU_GENERAL_TypeDef; 993 994 995 /* ================================================================================ */ 996 /* ================ SCU_INTERRUPT ================ */ 997 /* ================================================================================ */ 998 999 1000 /** 1001 * @brief System Control Unit (SCU_INTERRUPT) 1002 */ 1003 1004 typedef struct { /*!< (@ 0x50004074) SCU_INTERRUPT Structure */ 1005 __I uint32_t SRSTAT; /*!< (@ 0x50004074) SCU Service Request Status */ 1006 __I uint32_t SRRAW; /*!< (@ 0x50004078) SCU Raw Service Request Status */ 1007 __IO uint32_t SRMSK; /*!< (@ 0x5000407C) SCU Service Request Mask */ 1008 __O uint32_t SRCLR; /*!< (@ 0x50004080) SCU Service Request Clear */ 1009 __O uint32_t SRSET; /*!< (@ 0x50004084) SCU Service Request Set */ 1010 __IO uint32_t NMIREQEN; /*!< (@ 0x50004088) SCU Service Request Mask */ 1011 } SCU_INTERRUPT_TypeDef; 1012 1013 1014 /* ================================================================================ */ 1015 /* ================ SCU_PARITY ================ */ 1016 /* ================================================================================ */ 1017 1018 1019 /** 1020 * @brief System Control Unit (SCU_PARITY) 1021 */ 1022 1023 typedef struct { /*!< (@ 0x5000413C) SCU_PARITY Structure */ 1024 __IO uint32_t PEEN; /*!< (@ 0x5000413C) Parity Error Enable Register */ 1025 __IO uint32_t MCHKCON; /*!< (@ 0x50004140) Memory Checking Control Register */ 1026 __IO uint32_t PETE; /*!< (@ 0x50004144) Parity Error Trap Enable Register */ 1027 __IO uint32_t PERSTEN; /*!< (@ 0x50004148) Parity Error Reset Enable Register */ 1028 __I uint32_t RESERVED; 1029 __IO uint32_t PEFLAG; /*!< (@ 0x50004150) Parity Error Flag Register */ 1030 __IO uint32_t PMTPR; /*!< (@ 0x50004154) Parity Memory Test Pattern Register */ 1031 __IO uint32_t PMTSR; /*!< (@ 0x50004158) Parity Memory Test Select Register */ 1032 } SCU_PARITY_TypeDef; 1033 1034 1035 /* ================================================================================ */ 1036 /* ================ SCU_TRAP ================ */ 1037 /* ================================================================================ */ 1038 1039 1040 /** 1041 * @brief System Control Unit (SCU_TRAP) 1042 */ 1043 1044 typedef struct { /*!< (@ 0x50004160) SCU_TRAP Structure */ 1045 __I uint32_t TRAPSTAT; /*!< (@ 0x50004160) Trap Status Register */ 1046 __I uint32_t TRAPRAW; /*!< (@ 0x50004164) Trap Raw Status Register */ 1047 __IO uint32_t TRAPDIS; /*!< (@ 0x50004168) Trap Disable Register */ 1048 __O uint32_t TRAPCLR; /*!< (@ 0x5000416C) Trap Clear Register */ 1049 __O uint32_t TRAPSET; /*!< (@ 0x50004170) Trap Set Register */ 1050 } SCU_TRAP_TypeDef; 1051 1052 1053 /* ================================================================================ */ 1054 /* ================ SCU_HIBERNATE ================ */ 1055 /* ================================================================================ */ 1056 1057 1058 /** 1059 * @brief System Control Unit (SCU_HIBERNATE) 1060 */ 1061 1062 typedef struct { /*!< (@ 0x50004300) SCU_HIBERNATE Structure */ 1063 __I uint32_t HDSTAT; /*!< (@ 0x50004300) Hibernate Domain Status Register */ 1064 __O uint32_t HDCLR; /*!< (@ 0x50004304) Hibernate Domain Status Clear Register */ 1065 __O uint32_t HDSET; /*!< (@ 0x50004308) Hibernate Domain Status Set Register */ 1066 __IO uint32_t HDCR; /*!< (@ 0x5000430C) Hibernate Domain Control Register */ 1067 __I uint32_t RESERVED; 1068 __IO uint32_t OSCSICTRL; /*!< (@ 0x50004314) fOSI Control Register */ 1069 __I uint32_t OSCULSTAT; /*!< (@ 0x50004318) OSC_ULP Status Register */ 1070 __IO uint32_t OSCULCTRL; /*!< (@ 0x5000431C) OSC_ULP Control Register */ 1071 } SCU_HIBERNATE_TypeDef; 1072 1073 1074 /* ================================================================================ */ 1075 /* ================ SCU_POWER ================ */ 1076 /* ================================================================================ */ 1077 1078 1079 /** 1080 * @brief System Control Unit (SCU_POWER) 1081 */ 1082 1083 typedef struct { /*!< (@ 0x50004200) SCU_POWER Structure */ 1084 __I uint32_t PWRSTAT; /*!< (@ 0x50004200) PCU Status Register */ 1085 __O uint32_t PWRSET; /*!< (@ 0x50004204) PCU Set Control Register */ 1086 __O uint32_t PWRCLR; /*!< (@ 0x50004208) PCU Clear Control Register */ 1087 __I uint32_t RESERVED; 1088 __I uint32_t EVRSTAT; /*!< (@ 0x50004210) EVR Status Register */ 1089 __I uint32_t EVRVADCSTAT; /*!< (@ 0x50004214) EVR VADC Status Register */ 1090 __I uint32_t RESERVED1[5]; 1091 __IO uint32_t PWRMON; /*!< (@ 0x5000422C) Power Monitor Control */ 1092 } SCU_POWER_TypeDef; 1093 1094 1095 /* ================================================================================ */ 1096 /* ================ SCU_RESET ================ */ 1097 /* ================================================================================ */ 1098 1099 1100 /** 1101 * @brief System Control Unit (SCU_RESET) 1102 */ 1103 1104 typedef struct { /*!< (@ 0x50004400) SCU_RESET Structure */ 1105 __I uint32_t RSTSTAT; /*!< (@ 0x50004400) RCU Reset Status */ 1106 __O uint32_t RSTSET; /*!< (@ 0x50004404) RCU Reset Set Register */ 1107 __O uint32_t RSTCLR; /*!< (@ 0x50004408) RCU Reset Clear Register */ 1108 __I uint32_t PRSTAT0; /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status */ 1109 __O uint32_t PRSET0; /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set */ 1110 __O uint32_t PRCLR0; /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear */ 1111 __I uint32_t PRSTAT1; /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status */ 1112 __O uint32_t PRSET1; /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set */ 1113 __O uint32_t PRCLR1; /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear */ 1114 __I uint32_t PRSTAT2; /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status */ 1115 __O uint32_t PRSET2; /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set */ 1116 __O uint32_t PRCLR2; /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear */ 1117 __I uint32_t PRSTAT3; /*!< (@ 0x50004430) RCU Peripheral 3 Reset Status */ 1118 __O uint32_t PRSET3; /*!< (@ 0x50004434) RCU Peripheral 3 Reset Set */ 1119 __O uint32_t PRCLR3; /*!< (@ 0x50004438) RCU Peripheral 3 Reset Clear */ 1120 } SCU_RESET_TypeDef; 1121 1122 1123 /* ================================================================================ */ 1124 /* ================ LEDTS [LEDTS0] ================ */ 1125 /* ================================================================================ */ 1126 1127 1128 /** 1129 * @brief LED and Touch Sense Unit 0 (LEDTS) 1130 */ 1131 1132 typedef struct { /*!< (@ 0x48010000) LEDTS Structure */ 1133 __I uint32_t ID; /*!< (@ 0x48010000) Module Identification Register */ 1134 __IO uint32_t GLOBCTL; /*!< (@ 0x48010004) Global Control Register */ 1135 __IO uint32_t FNCTL; /*!< (@ 0x48010008) Function Control Register */ 1136 __O uint32_t EVFR; /*!< (@ 0x4801000C) Event Flag Register */ 1137 __IO uint32_t TSVAL; /*!< (@ 0x48010010) Touch-sense TS-Counter Value */ 1138 __IO uint32_t LINE0; /*!< (@ 0x48010014) Line Pattern Register 0 */ 1139 __IO uint32_t LINE1; /*!< (@ 0x48010018) Line Pattern Register 1 */ 1140 __IO uint32_t LDCMP0; /*!< (@ 0x4801001C) LED Compare Register 0 */ 1141 __IO uint32_t LDCMP1; /*!< (@ 0x48010020) LED Compare Register 1 */ 1142 __IO uint32_t TSCMP0; /*!< (@ 0x48010024) Touch-sense Compare Register 0 */ 1143 __IO uint32_t TSCMP1; /*!< (@ 0x48010028) Touch-sense Compare Register 1 */ 1144 } LEDTS0_GLOBAL_TypeDef; 1145 1146 1147 /* ================================================================================ */ 1148 /* ================ SDMMC ================ */ 1149 /* ================================================================================ */ 1150 1151 1152 /** 1153 * @brief SD and Multimediacard Interface (SDMMC) 1154 */ 1155 1156 typedef struct { /*!< (@ 0x4801C000) SDMMC Structure */ 1157 __I uint32_t RESERVED; 1158 __IO uint16_t BLOCK_SIZE; /*!< (@ 0x4801C004) Block Size Register */ 1159 __IO uint16_t BLOCK_COUNT; /*!< (@ 0x4801C006) Block Count Register */ 1160 __IO uint32_t ARGUMENT1; /*!< (@ 0x4801C008) Argument1 Register */ 1161 __IO uint16_t TRANSFER_MODE; /*!< (@ 0x4801C00C) Transfer Mode Register */ 1162 __IO uint16_t COMMAND; /*!< (@ 0x4801C00E) Command Register */ 1163 __I uint32_t RESPONSE0; /*!< (@ 0x4801C010) Response 0 Register */ 1164 __I uint32_t RESPONSE2; /*!< (@ 0x4801C014) Response 2 Register */ 1165 __I uint32_t RESPONSE4; /*!< (@ 0x4801C018) Response 4 Register */ 1166 __I uint32_t RESPONSE6; /*!< (@ 0x4801C01C) Response 6 Register */ 1167 __IO uint32_t DATA_BUFFER; /*!< (@ 0x4801C020) Data Buffer Register */ 1168 __I uint32_t PRESENT_STATE; /*!< (@ 0x4801C024) Present State Register */ 1169 __IO uint8_t HOST_CTRL; /*!< (@ 0x4801C028) Host Control Register */ 1170 __IO uint8_t POWER_CTRL; /*!< (@ 0x4801C029) Power Control Register */ 1171 __IO uint8_t BLOCK_GAP_CTRL; /*!< (@ 0x4801C02A) Block Gap Control Register */ 1172 __IO uint8_t WAKEUP_CTRL; /*!< (@ 0x4801C02B) Wake-up Control Register */ 1173 __IO uint16_t CLOCK_CTRL; /*!< (@ 0x4801C02C) Clock Control Register */ 1174 __IO uint8_t TIMEOUT_CTRL; /*!< (@ 0x4801C02E) Timeout Control Register */ 1175 __IO uint8_t SW_RESET; /*!< (@ 0x4801C02F) Software Reset Register */ 1176 __IO uint16_t INT_STATUS_NORM; /*!< (@ 0x4801C030) Normal Interrupt Status Register */ 1177 __IO uint16_t INT_STATUS_ERR; /*!< (@ 0x4801C032) Error Interrupt Status Register */ 1178 __IO uint16_t EN_INT_STATUS_NORM; /*!< (@ 0x4801C034) Normal Interrupt Status Enable Register */ 1179 __IO uint16_t EN_INT_STATUS_ERR; /*!< (@ 0x4801C036) Error Interrupt Status Enable Register */ 1180 __IO uint16_t EN_INT_SIGNAL_NORM; /*!< (@ 0x4801C038) Normal Interrupt Signal Enable Register */ 1181 __IO uint16_t EN_INT_SIGNAL_ERR; /*!< (@ 0x4801C03A) Error Interrupt Signal Enable Register */ 1182 __I uint16_t ACMD_ERR_STATUS; /*!< (@ 0x4801C03C) Auto CMD Error Status Register */ 1183 __I uint16_t RESERVED1; 1184 __I uint32_t CAPABILITIES; /*!< (@ 0x4801C040) Capabilities Register */ 1185 __I uint32_t CAPABILITIES_HI; /*!< (@ 0x4801C044) Capabilities Register High */ 1186 __I uint32_t MAX_CURRENT_CAP; /*!< (@ 0x4801C048) Maximum Current Capabilities Register */ 1187 __I uint32_t RESERVED2; 1188 __O uint16_t FORCE_EVENT_ACMD_ERR_STATUS; /*!< (@ 0x4801C050) Force Event Register for Auto CMD Error Status */ 1189 __O uint16_t FORCE_EVENT_ERR_STATUS; /*!< (@ 0x4801C052) Force Event Register for Error Interrupt Status */ 1190 __I uint32_t RESERVED3[8]; 1191 __O uint32_t DEBUG_SEL; /*!< (@ 0x4801C074) Debug Selection Register */ 1192 __I uint32_t RESERVED4[30]; 1193 __IO uint32_t SPI; /*!< (@ 0x4801C0F0) SPI Interrupt Support Register */ 1194 __I uint32_t RESERVED5[2]; 1195 __I uint16_t SLOT_INT_STATUS; /*!< (@ 0x4801C0FC) Slot Interrupt Status Register */ 1196 } SDMMC_GLOBAL_TypeDef; 1197 1198 1199 /* ================================================================================ */ 1200 /* ================ EBU ================ */ 1201 /* ================================================================================ */ 1202 1203 1204 /** 1205 * @brief External Bus Unit (EBU) 1206 */ 1207 1208 typedef struct { /*!< (@ 0x58008000) EBU Structure */ 1209 __IO uint32_t CLC; /*!< (@ 0x58008000) EBU Clock Control Register */ 1210 __IO uint32_t MODCON; /*!< (@ 0x58008004) EBU Configuration Register */ 1211 __I uint32_t ID; /*!< (@ 0x58008008) EBU Module Identification Register */ 1212 __IO uint32_t USERCON; /*!< (@ 0x5800800C) EBU Test/Control Configuration Register */ 1213 __I uint32_t RESERVED[2]; 1214 __IO uint32_t ADDRSEL0; /*!< (@ 0x58008018) EBU Address Select Register 0 */ 1215 __IO uint32_t ADDRSEL1; /*!< (@ 0x5800801C) EBU Address Select Register 1 */ 1216 __IO uint32_t ADDRSEL2; /*!< (@ 0x58008020) EBU Address Select Register 2 */ 1217 __IO uint32_t ADDRSEL3; /*!< (@ 0x58008024) EBU Address Select Register 3 */ 1218 __IO uint32_t BUSRCON0; /*!< (@ 0x58008028) EBU Bus Configuration Register */ 1219 __IO uint32_t BUSRAP0; /*!< (@ 0x5800802C) EBU Bus Read Access Parameter Register */ 1220 __IO uint32_t BUSWCON0; /*!< (@ 0x58008030) EBU Bus Write Configuration Register */ 1221 __IO uint32_t BUSWAP0; /*!< (@ 0x58008034) EBU Bus Write Access Parameter Register */ 1222 __IO uint32_t BUSRCON1; /*!< (@ 0x58008038) EBU Bus Configuration Register */ 1223 __IO uint32_t BUSRAP1; /*!< (@ 0x5800803C) EBU Bus Read Access Parameter Register */ 1224 __IO uint32_t BUSWCON1; /*!< (@ 0x58008040) EBU Bus Write Configuration Register */ 1225 __IO uint32_t BUSWAP1; /*!< (@ 0x58008044) EBU Bus Write Access Parameter Register */ 1226 __IO uint32_t BUSRCON2; /*!< (@ 0x58008048) EBU Bus Configuration Register */ 1227 __IO uint32_t BUSRAP2; /*!< (@ 0x5800804C) EBU Bus Read Access Parameter Register */ 1228 __IO uint32_t BUSWCON2; /*!< (@ 0x58008050) EBU Bus Write Configuration Register */ 1229 __IO uint32_t BUSWAP2; /*!< (@ 0x58008054) EBU Bus Write Access Parameter Register */ 1230 __IO uint32_t BUSRCON3; /*!< (@ 0x58008058) EBU Bus Configuration Register */ 1231 __IO uint32_t BUSRAP3; /*!< (@ 0x5800805C) EBU Bus Read Access Parameter Register */ 1232 __IO uint32_t BUSWCON3; /*!< (@ 0x58008060) EBU Bus Write Configuration Register */ 1233 __IO uint32_t BUSWAP3; /*!< (@ 0x58008064) EBU Bus Write Access Parameter Register */ 1234 __IO uint32_t SDRMCON; /*!< (@ 0x58008068) EBU SDRAM Control Register */ 1235 __IO uint32_t SDRMOD; /*!< (@ 0x5800806C) EBU SDRAM Mode Register */ 1236 __IO uint32_t SDRMREF; /*!< (@ 0x58008070) EBU SDRAM Refresh Control Register */ 1237 __I uint32_t SDRSTAT; /*!< (@ 0x58008074) EBU SDRAM Status Register */ 1238 } EBU_Type; 1239 1240 1241 /* ================================================================================ */ 1242 /* ================ ETH0_CON ================ */ 1243 /* ================================================================================ */ 1244 1245 1246 /** 1247 * @brief Ethernet Control Register (ETH0_CON) 1248 */ 1249 1250 typedef struct { /*!< (@ 0x50004040) ETH0_CON Structure */ 1251 __IO uint32_t CON; /*!< (@ 0x50004040) Ethernet 0 Port Control Register */ 1252 } ETH0_CON_GLOBAL_TypeDef; 1253 1254 1255 /* ================================================================================ */ 1256 /* ================ ETH [ETH0] ================ */ 1257 /* ================================================================================ */ 1258 1259 1260 /** 1261 * @brief Ethernet Unit 0 (ETH) 1262 */ 1263 1264 typedef struct { /*!< (@ 0x5000C000) ETH Structure */ 1265 __IO uint32_t MAC_CONFIGURATION; /*!< (@ 0x5000C000) MAC Configuration Register */ 1266 __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x5000C004) MAC Frame Filter */ 1267 __IO uint32_t HASH_TABLE_HIGH; /*!< (@ 0x5000C008) Hash Table High Register */ 1268 __IO uint32_t HASH_TABLE_LOW; /*!< (@ 0x5000C00C) Hash Table Low Register */ 1269 __IO uint32_t GMII_ADDRESS; /*!< (@ 0x5000C010) MII Address Register */ 1270 __IO uint32_t GMII_DATA; /*!< (@ 0x5000C014) MII Data Register */ 1271 __IO uint32_t FLOW_CONTROL; /*!< (@ 0x5000C018) Flow Control Register */ 1272 __IO uint32_t VLAN_TAG; /*!< (@ 0x5000C01C) VLAN Tag Register */ 1273 __I uint32_t VERSION; /*!< (@ 0x5000C020) Version Register */ 1274 __I uint32_t DEBUG; /*!< (@ 0x5000C024) Debug Register */ 1275 __IO uint32_t REMOTE_WAKE_UP_FRAME_FILTER; /*!< (@ 0x5000C028) Remote Wake Up Frame Filter Register */ 1276 __IO uint32_t PMT_CONTROL_STATUS; /*!< (@ 0x5000C02C) PMT Control and Status Register */ 1277 __I uint32_t RESERVED[2]; 1278 __I uint32_t INTERRUPT_STATUS; /*!< (@ 0x5000C038) Interrupt Register */ 1279 __IO uint32_t INTERRUPT_MASK; /*!< (@ 0x5000C03C) Interrupt Mask Register */ 1280 __IO uint32_t MAC_ADDRESS0_HIGH; /*!< (@ 0x5000C040) MAC Address0 High Register */ 1281 __IO uint32_t MAC_ADDRESS0_LOW; /*!< (@ 0x5000C044) MAC Address0 Low Register */ 1282 __IO uint32_t MAC_ADDRESS1_HIGH; /*!< (@ 0x5000C048) MAC Address1 High Register */ 1283 __IO uint32_t MAC_ADDRESS1_LOW; /*!< (@ 0x5000C04C) MAC Address1 Low Register */ 1284 __IO uint32_t MAC_ADDRESS2_HIGH; /*!< (@ 0x5000C050) MAC Address2 High Register */ 1285 __IO uint32_t MAC_ADDRESS2_LOW; /*!< (@ 0x5000C054) MAC Address2 Low Register */ 1286 __IO uint32_t MAC_ADDRESS3_HIGH; /*!< (@ 0x5000C058) MAC Address3 High Register */ 1287 __IO uint32_t MAC_ADDRESS3_LOW; /*!< (@ 0x5000C05C) MAC Address3 Low Register */ 1288 __I uint32_t RESERVED1[40]; 1289 __IO uint32_t MMC_CONTROL; /*!< (@ 0x5000C100) MMC Control Register */ 1290 __I uint32_t MMC_RECEIVE_INTERRUPT; /*!< (@ 0x5000C104) MMC Receive Interrupt Register */ 1291 __I uint32_t MMC_TRANSMIT_INTERRUPT; /*!< (@ 0x5000C108) MMC Transmit Interrupt Register */ 1292 __IO uint32_t MMC_RECEIVE_INTERRUPT_MASK; /*!< (@ 0x5000C10C) MMC Reveive Interrupt Mask Register */ 1293 __IO uint32_t MMC_TRANSMIT_INTERRUPT_MASK; /*!< (@ 0x5000C110) MMC Transmit Interrupt Mask Register */ 1294 __I uint32_t TX_OCTET_COUNT_GOOD_BAD; /*!< (@ 0x5000C114) Transmit Octet Count for Good and Bad Frames 1295 Register */ 1296 __I uint32_t TX_FRAME_COUNT_GOOD_BAD; /*!< (@ 0x5000C118) Transmit Frame Count for Goodand Bad Frames Register */ 1297 __I uint32_t TX_BROADCAST_FRAMES_GOOD; /*!< (@ 0x5000C11C) Transmit Frame Count for Good Broadcast Frames */ 1298 __I uint32_t TX_MULTICAST_FRAMES_GOOD; /*!< (@ 0x5000C120) Transmit Frame Count for Good Multicast Frames */ 1299 __I uint32_t TX_64OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C124) Transmit Octet Count for Good and Bad 64 Byte 1300 Frames */ 1301 __I uint32_t TX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C128) Transmit Octet Count for Good and Bad 65 to 127 1302 Bytes Frames */ 1303 __I uint32_t TX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C12C) Transmit Octet Count for Good and Bad 128 to 1304 255 Bytes Frames */ 1305 __I uint32_t TX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C130) Transmit Octet Count for Good and Bad 256 to 1306 511 Bytes Frames */ 1307 __I uint32_t TX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C134) Transmit Octet Count for Good and Bad 512 to 1308 1023 Bytes Frames */ 1309 __I uint32_t TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C138) Transmit Octet Count for Good and Bad 1024 to 1310 Maxsize Bytes Frames */ 1311 __I uint32_t TX_UNICAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C13C) Transmit Frame Count for Good and Bad Unicast 1312 Frames */ 1313 __I uint32_t TX_MULTICAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C140) Transmit Frame Count for Good and Bad Multicast 1314 Frames */ 1315 __I uint32_t TX_BROADCAST_FRAMES_GOOD_BAD; /*!< (@ 0x5000C144) Transmit Frame Count for Good and Bad Broadcast 1316 Frames */ 1317 __I uint32_t TX_UNDERFLOW_ERROR_FRAMES; /*!< (@ 0x5000C148) Transmit Frame Count for Underflow Error Frames */ 1318 __I uint32_t TX_SINGLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C14C) Transmit Frame Count for Frames Transmitted after 1319 Single Collision */ 1320 __I uint32_t TX_MULTIPLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C150) Transmit Frame Count for Frames Transmitted after 1321 Multiple Collision */ 1322 __I uint32_t TX_DEFERRED_FRAMES; /*!< (@ 0x5000C154) Tx Deferred Frames Register */ 1323 __I uint32_t TX_LATE_COLLISION_FRAMES; /*!< (@ 0x5000C158) Transmit Frame Count for Late Collision Error 1324 Frames */ 1325 __I uint32_t TX_EXCESSIVE_COLLISION_FRAMES; /*!< (@ 0x5000C15C) Transmit Frame Count for Excessive Collision 1326 Error Frames */ 1327 __I uint32_t TX_CARRIER_ERROR_FRAMES; /*!< (@ 0x5000C160) Transmit Frame Count for Carrier Sense Error 1328 Frames */ 1329 __I uint32_t TX_OCTET_COUNT_GOOD; /*!< (@ 0x5000C164) Tx Octet Count Good Register */ 1330 __I uint32_t TX_FRAME_COUNT_GOOD; /*!< (@ 0x5000C168) Tx Frame Count Good Register */ 1331 __I uint32_t TX_EXCESSIVE_DEFERRAL_ERROR; /*!< (@ 0x5000C16C) Transmit Frame Count for Excessive Deferral Error 1332 Frames */ 1333 __I uint32_t TX_PAUSE_FRAMES; /*!< (@ 0x5000C170) Transmit Frame Count for Good PAUSE Frames */ 1334 __I uint32_t TX_VLAN_FRAMES_GOOD; /*!< (@ 0x5000C174) Transmit Frame Count for Good VLAN Frames */ 1335 __I uint32_t TX_OSIZE_FRAMES_GOOD; /*!< (@ 0x5000C178) Transmit Frame Count for Good Oversize Frames */ 1336 __I uint32_t RESERVED2; 1337 __I uint32_t RX_FRAMES_COUNT_GOOD_BAD; /*!< (@ 0x5000C180) Receive Frame Count for Good and Bad Frames */ 1338 __I uint32_t RX_OCTET_COUNT_GOOD_BAD; /*!< (@ 0x5000C184) Receive Octet Count for Good and Bad Frames */ 1339 __I uint32_t RX_OCTET_COUNT_GOOD; /*!< (@ 0x5000C188) Rx Octet Count Good Register */ 1340 __I uint32_t RX_BROADCAST_FRAMES_GOOD; /*!< (@ 0x5000C18C) Receive Frame Count for Good Broadcast Frames */ 1341 __I uint32_t RX_MULTICAST_FRAMES_GOOD; /*!< (@ 0x5000C190) Receive Frame Count for Good Multicast Frames */ 1342 __I uint32_t RX_CRC_ERROR_FRAMES; /*!< (@ 0x5000C194) Receive Frame Count for CRC Error Frames */ 1343 __I uint32_t RX_ALIGNMENT_ERROR_FRAMES; /*!< (@ 0x5000C198) Receive Frame Count for Alignment Error Frames */ 1344 __I uint32_t RX_RUNT_ERROR_FRAMES; /*!< (@ 0x5000C19C) Receive Frame Count for Runt Error Frames */ 1345 __I uint32_t RX_JABBER_ERROR_FRAMES; /*!< (@ 0x5000C1A0) Receive Frame Count for Jabber Error Frames */ 1346 __I uint32_t RX_UNDERSIZE_FRAMES_GOOD; /*!< (@ 0x5000C1A4) Receive Frame Count for Undersize Frames */ 1347 __I uint32_t RX_OVERSIZE_FRAMES_GOOD; /*!< (@ 0x5000C1A8) Rx Oversize Frames Good Register */ 1348 __I uint32_t RX_64OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1AC) Receive Frame Count for Good and Bad 64 Byte 1349 Frames */ 1350 __I uint32_t RX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B0) Receive Frame Count for Good and Bad 65 to 127 1351 Bytes Frames */ 1352 __I uint32_t RX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B4) Receive Frame Count for Good and Bad 128 to 255 1353 Bytes Frames */ 1354 __I uint32_t RX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B8) Receive Frame Count for Good and Bad 256 to 511 1355 Bytes Frames */ 1356 __I uint32_t RX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1BC) Receive Frame Count for Good and Bad 512 to 1,023 1357 Bytes Frames */ 1358 __I uint32_t RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1C0) Receive Frame Count for Good and Bad 1,024 to 1359 Maxsize Bytes Frames */ 1360 __I uint32_t RX_UNICAST_FRAMES_GOOD; /*!< (@ 0x5000C1C4) Receive Frame Count for Good Unicast Frames */ 1361 __I uint32_t RX_LENGTH_ERROR_FRAMES; /*!< (@ 0x5000C1C8) Receive Frame Count for Length Error Frames */ 1362 __I uint32_t RX_OUT_OF_RANGE_TYPE_FRAMES; /*!< (@ 0x5000C1CC) Receive Frame Count for Out of Range Frames */ 1363 __I uint32_t RX_PAUSE_FRAMES; /*!< (@ 0x5000C1D0) Receive Frame Count for PAUSE Frames */ 1364 __I uint32_t RX_FIFO_OVERFLOW_FRAMES; /*!< (@ 0x5000C1D4) Receive Frame Count for FIFO Overflow Frames */ 1365 __I uint32_t RX_VLAN_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1D8) Receive Frame Count for Good and Bad VLAN Frames */ 1366 __I uint32_t RX_WATCHDOG_ERROR_FRAMES; /*!< (@ 0x5000C1DC) Receive Frame Count for Watchdog Error Frames */ 1367 __I uint32_t RX_RECEIVE_ERROR_FRAMES; /*!< (@ 0x5000C1E0) Receive Frame Count for Receive Error Frames */ 1368 __I uint32_t RX_CONTROL_FRAMES_GOOD; /*!< (@ 0x5000C1E4) Receive Frame Count for Good Control Frames Frames */ 1369 __I uint32_t RESERVED3[6]; 1370 __IO uint32_t MMC_IPC_RECEIVE_INTERRUPT_MASK; /*!< (@ 0x5000C200) MMC Receive Checksum Offload Interrupt Mask Register */ 1371 __I uint32_t RESERVED4; 1372 __I uint32_t MMC_IPC_RECEIVE_INTERRUPT; /*!< (@ 0x5000C208) MMC Receive Checksum Offload Interrupt Register */ 1373 __I uint32_t RESERVED5; 1374 __I uint32_t RXIPV4_GOOD_FRAMES; /*!< (@ 0x5000C210) RxIPv4 Good Frames Register */ 1375 __I uint32_t RXIPV4_HEADER_ERROR_FRAMES; /*!< (@ 0x5000C214) Receive IPV4 Header Error Frame Counter Register */ 1376 __I uint32_t RXIPV4_NO_PAYLOAD_FRAMES; /*!< (@ 0x5000C218) Receive IPV4 No Payload Frame Counter Register */ 1377 __I uint32_t RXIPV4_FRAGMENTED_FRAMES; /*!< (@ 0x5000C21C) Receive IPV4 Fragmented Frame Counter Register */ 1378 __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES;/*!< (@ 0x5000C220) Receive IPV4 UDP Checksum Disabled Frame Counter 1379 Register */ 1380 __I uint32_t RXIPV6_GOOD_FRAMES; /*!< (@ 0x5000C224) RxIPv6 Good Frames Register */ 1381 __I uint32_t RXIPV6_HEADER_ERROR_FRAMES; /*!< (@ 0x5000C228) Receive IPV6 Header Error Frame Counter Register */ 1382 __I uint32_t RXIPV6_NO_PAYLOAD_FRAMES; /*!< (@ 0x5000C22C) Receive IPV6 No Payload Frame Counter Register */ 1383 __I uint32_t RXUDP_GOOD_FRAMES; /*!< (@ 0x5000C230) RxUDP Good Frames Register */ 1384 __I uint32_t RXUDP_ERROR_FRAMES; /*!< (@ 0x5000C234) RxUDP Error Frames Register */ 1385 __I uint32_t RXTCP_GOOD_FRAMES; /*!< (@ 0x5000C238) RxTCP Good Frames Register */ 1386 __I uint32_t RXTCP_ERROR_FRAMES; /*!< (@ 0x5000C23C) RxTCP Error Frames Register */ 1387 __I uint32_t RXICMP_GOOD_FRAMES; /*!< (@ 0x5000C240) RxICMP Good Frames Register */ 1388 __I uint32_t RXICMP_ERROR_FRAMES; /*!< (@ 0x5000C244) RxICMP Error Frames Register */ 1389 __I uint32_t RESERVED6[2]; 1390 __I uint32_t RXIPV4_GOOD_OCTETS; /*!< (@ 0x5000C250) RxIPv4 Good Octets Register */ 1391 __I uint32_t RXIPV4_HEADER_ERROR_OCTETS; /*!< (@ 0x5000C254) Receive IPV4 Header Error Octet Counter Register */ 1392 __I uint32_t RXIPV4_NO_PAYLOAD_OCTETS; /*!< (@ 0x5000C258) Receive IPV4 No Payload Octet Counter Register */ 1393 __I uint32_t RXIPV4_FRAGMENTED_OCTETS; /*!< (@ 0x5000C25C) Receive IPV4 Fragmented Octet Counter Register */ 1394 __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS;/*!< (@ 0x5000C260) Receive IPV4 Fragmented Octet Counter Register */ 1395 __I uint32_t RXIPV6_GOOD_OCTETS; /*!< (@ 0x5000C264) RxIPv6 Good Octets Register */ 1396 __I uint32_t RXIPV6_HEADER_ERROR_OCTETS; /*!< (@ 0x5000C268) Receive IPV6 Header Error Octet Counter Register */ 1397 __I uint32_t RXIPV6_NO_PAYLOAD_OCTETS; /*!< (@ 0x5000C26C) Receive IPV6 No Payload Octet Counter Register */ 1398 __I uint32_t RXUDP_GOOD_OCTETS; /*!< (@ 0x5000C270) Receive UDP Good Octets Register */ 1399 __I uint32_t RXUDP_ERROR_OCTETS; /*!< (@ 0x5000C274) Receive UDP Error Octets Register */ 1400 __I uint32_t RXTCP_GOOD_OCTETS; /*!< (@ 0x5000C278) Receive TCP Good Octets Register */ 1401 __I uint32_t RXTCP_ERROR_OCTETS; /*!< (@ 0x5000C27C) Receive TCP Error Octets Register */ 1402 __I uint32_t RXICMP_GOOD_OCTETS; /*!< (@ 0x5000C280) Receive ICMP Good Octets Register */ 1403 __I uint32_t RXICMP_ERROR_OCTETS; /*!< (@ 0x5000C284) Receive ICMP Error Octets Register */ 1404 __I uint32_t RESERVED7[286]; 1405 __IO uint32_t TIMESTAMP_CONTROL; /*!< (@ 0x5000C700) Timestamp Control Register */ 1406 __IO uint32_t SUB_SECOND_INCREMENT; /*!< (@ 0x5000C704) Sub-Second Increment Register */ 1407 __I uint32_t SYSTEM_TIME_SECONDS; /*!< (@ 0x5000C708) System Time - Seconds Register */ 1408 __I uint32_t SYSTEM_TIME_NANOSECONDS; /*!< (@ 0x5000C70C) System Time Nanoseconds Register */ 1409 __IO uint32_t SYSTEM_TIME_SECONDS_UPDATE; /*!< (@ 0x5000C710) System Time - Seconds Update Register */ 1410 __IO uint32_t SYSTEM_TIME_NANOSECONDS_UPDATE; /*!< (@ 0x5000C714) System Time Nanoseconds Update Register */ 1411 __IO uint32_t TIMESTAMP_ADDEND; /*!< (@ 0x5000C718) Timestamp Addend Register */ 1412 __IO uint32_t TARGET_TIME_SECONDS; /*!< (@ 0x5000C71C) Target Time Seconds Register */ 1413 __IO uint32_t TARGET_TIME_NANOSECONDS; /*!< (@ 0x5000C720) Target Time Nanoseconds Register */ 1414 __IO uint32_t SYSTEM_TIME_HIGHER_WORD_SECONDS; /*!< (@ 0x5000C724) System Time - Higher Word Seconds Register */ 1415 __I uint32_t TIMESTAMP_STATUS; /*!< (@ 0x5000C728) Timestamp Status Register */ 1416 __IO uint32_t PPS_CONTROL; /*!< (@ 0x5000C72C) PPS Control Register */ 1417 __I uint32_t RESERVED8[564]; 1418 __IO uint32_t BUS_MODE; /*!< (@ 0x5000D000) Bus Mode Register */ 1419 __IO uint32_t TRANSMIT_POLL_DEMAND; /*!< (@ 0x5000D004) Transmit Poll Demand Register */ 1420 __IO uint32_t RECEIVE_POLL_DEMAND; /*!< (@ 0x5000D008) Receive Poll Demand Register */ 1421 __IO uint32_t RECEIVE_DESCRIPTOR_LIST_ADDRESS; /*!< (@ 0x5000D00C) Receive Descriptor Address Register */ 1422 __IO uint32_t TRANSMIT_DESCRIPTOR_LIST_ADDRESS; /*!< (@ 0x5000D010) Transmit descripter Address Register */ 1423 __IO uint32_t STATUS; /*!< (@ 0x5000D014) Status Register */ 1424 __IO uint32_t OPERATION_MODE; /*!< (@ 0x5000D018) Operation Mode Register */ 1425 __IO uint32_t INTERRUPT_ENABLE; /*!< (@ 0x5000D01C) Interrupt Enable Register */ 1426 __I uint32_t MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER;/*!< (@ 0x5000D020) Missed Frame and Buffer Overflow Counter Register */ 1427 __IO uint32_t RECEIVE_INTERRUPT_WATCHDOG_TIMER; /*!< (@ 0x5000D024) Receive Interrupt Watchdog Timer Register */ 1428 __I uint32_t RESERVED9; 1429 __I uint32_t AHB_STATUS; /*!< (@ 0x5000D02C) AHB Status Register */ 1430 __I uint32_t RESERVED10[6]; 1431 __I uint32_t CURRENT_HOST_TRANSMIT_DESCRIPTOR; /*!< (@ 0x5000D048) Current Host Transmit Descriptor Register */ 1432 __I uint32_t CURRENT_HOST_RECEIVE_DESCRIPTOR; /*!< (@ 0x5000D04C) Current Host Receive Descriptor Register */ 1433 __I uint32_t CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS;/*!< (@ 0x5000D050) Current Host Transmit Buffer Address Register */ 1434 __I uint32_t CURRENT_HOST_RECEIVE_BUFFER_ADDRESS;/*!< (@ 0x5000D054) Current Host Receive Buffer Address Register */ 1435 __IO uint32_t HW_FEATURE; /*!< (@ 0x5000D058) HW Feature Register */ 1436 } ETH_GLOBAL_TypeDef; 1437 1438 1439 /* ================================================================================ */ 1440 /* ================ USB [USB0] ================ */ 1441 /* ================================================================================ */ 1442 1443 1444 /** 1445 * @brief Universal Serial Bus (USB) 1446 */ 1447 1448 typedef struct { /*!< (@ 0x50040000) USB Structure */ 1449 __IO uint32_t GOTGCTL; /*!< (@ 0x50040000) Control and Status Register */ 1450 __IO uint32_t GOTGINT; /*!< (@ 0x50040004) OTG Interrupt Register */ 1451 __IO uint32_t GAHBCFG; /*!< (@ 0x50040008) AHB Configuration Register */ 1452 __IO uint32_t GUSBCFG; /*!< (@ 0x5004000C) USB Configuration Register */ 1453 __IO uint32_t GRSTCTL; /*!< (@ 0x50040010) Reset Register */ 1454 1455 union { 1456 __IO uint32_t GINTSTS_DEVICEMODE; /*!< (@ 0x50040014) Interrupt Register [DEVICEMODE] */ 1457 __IO uint32_t GINTSTS_HOSTMODE; /*!< (@ 0x50040014) Interrupt Register [HOSTMODE] */ 1458 }; 1459 1460 union { 1461 __IO uint32_t GINTMSK_DEVICEMODE; /*!< (@ 0x50040018) Interrupt Mask Register [DEVICEMODE] */ 1462 __IO uint32_t GINTMSK_HOSTMODE; /*!< (@ 0x50040018) Interrupt Mask Register [HOSTMODE] */ 1463 }; 1464 1465 union { 1466 __I uint32_t GRXSTSR_DEVICEMODE; /*!< (@ 0x5004001C) Receive Status Debug Read Register [DEVICEMODE] */ 1467 __I uint32_t GRXSTSR_HOSTMODE; /*!< (@ 0x5004001C) Receive Status Debug Read Register [HOSTMODE] */ 1468 }; 1469 1470 union { 1471 __I uint32_t GRXSTSP_DEVICEMODE; /*!< (@ 0x50040020) Receive Status Read and Pop Register [DEVICEMODE] */ 1472 __I uint32_t GRXSTSP_HOSTMODE; /*!< (@ 0x50040020) Receive Status Read and Pop Register [HOSTMODE] */ 1473 }; 1474 __IO uint32_t GRXFSIZ; /*!< (@ 0x50040024) Receive FIFO Size Register */ 1475 1476 union { 1477 __IO uint32_t GNPTXFSIZ_DEVICEMODE; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [DEVICEMODE] */ 1478 __IO uint32_t GNPTXFSIZ_HOSTMODE; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [HOSTMODE] */ 1479 }; 1480 __I uint32_t GNPTXSTS; /*!< (@ 0x5004002C) Non-Periodic Transmit FIFO/Queue Status Register */ 1481 __I uint32_t RESERVED[3]; 1482 __IO uint32_t GUID; /*!< (@ 0x5004003C) USB Module Identification Register */ 1483 __I uint32_t RESERVED1[7]; 1484 __IO uint32_t GDFIFOCFG; /*!< (@ 0x5004005C) Global DFIFO Software Config Register */ 1485 __I uint32_t RESERVED2[40]; 1486 __IO uint32_t HPTXFSIZ; /*!< (@ 0x50040100) Host Periodic Transmit FIFO Size Register */ 1487 __IO uint32_t DIEPTXF1; /*!< (@ 0x50040104) Device IN Endpoint 1 Transmit FIFO Size Register */ 1488 __IO uint32_t DIEPTXF2; /*!< (@ 0x50040108) Device IN Endpoint 2 Transmit FIFO Size Register */ 1489 __IO uint32_t DIEPTXF3; /*!< (@ 0x5004010C) Device IN Endpoint 3 Transmit FIFO Size Register */ 1490 __IO uint32_t DIEPTXF4; /*!< (@ 0x50040110) Device IN Endpoint 4 Transmit FIFO Size Register */ 1491 __IO uint32_t DIEPTXF5; /*!< (@ 0x50040114) Device IN Endpoint 5 Transmit FIFO Size Register */ 1492 __IO uint32_t DIEPTXF6; /*!< (@ 0x50040118) Device IN Endpoint 6 Transmit FIFO Size Register */ 1493 __I uint32_t RESERVED3[185]; 1494 __IO uint32_t HCFG; /*!< (@ 0x50040400) Host Configuration Register */ 1495 __IO uint32_t HFIR; /*!< (@ 0x50040404) Host Frame Interval Register */ 1496 __IO uint32_t HFNUM; /*!< (@ 0x50040408) Host Frame Number/Frame Time Remaining Register */ 1497 __I uint32_t RESERVED4; 1498 __IO uint32_t HPTXSTS; /*!< (@ 0x50040410) Host Periodic Transmit FIFO/ Queue Status Register */ 1499 __I uint32_t HAINT; /*!< (@ 0x50040414) Host All Channels Interrupt Register */ 1500 __IO uint32_t HAINTMSK; /*!< (@ 0x50040418) Host All Channels Interrupt Mask Register */ 1501 __IO uint32_t HFLBADDR; /*!< (@ 0x5004041C) Host Frame List Base Address Register */ 1502 __I uint32_t RESERVED5[8]; 1503 __IO uint32_t HPRT; /*!< (@ 0x50040440) Host Port Control and Status Register */ 1504 __I uint32_t RESERVED6[239]; 1505 __IO uint32_t DCFG; /*!< (@ 0x50040800) Device Configuration Register */ 1506 __IO uint32_t DCTL; /*!< (@ 0x50040804) Device Control Register */ 1507 __I uint32_t DSTS; /*!< (@ 0x50040808) Device Status Register */ 1508 __I uint32_t RESERVED7; 1509 __IO uint32_t DIEPMSK; /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register */ 1510 __IO uint32_t DOEPMSK; /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register */ 1511 __I uint32_t DAINT; /*!< (@ 0x50040818) Device All Endpoints Interrupt Register */ 1512 __IO uint32_t DAINTMSK; /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register */ 1513 __I uint32_t RESERVED8[2]; 1514 __IO uint32_t DVBUSDIS; /*!< (@ 0x50040828) Device VBUS Discharge Time Register */ 1515 __IO uint32_t DVBUSPULSE; /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register */ 1516 __I uint32_t RESERVED9; 1517 __IO uint32_t DIEPEMPMSK; /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask 1518 Register */ 1519 __I uint32_t RESERVED10[370]; 1520 __IO uint32_t PCGCCTL; /*!< (@ 0x50040E00) Power and Clock Gating Control Register */ 1521 } USB0_GLOBAL_TypeDef; 1522 1523 1524 /* ================================================================================ */ 1525 /* ================ USB0_EP0 ================ */ 1526 /* ================================================================================ */ 1527 1528 1529 /** 1530 * @brief Universal Serial Bus (USB0_EP0) 1531 */ 1532 1533 typedef struct { /*!< (@ 0x50040900) USB0_EP0 Structure */ 1534 __IO uint32_t DIEPCTL0; /*!< (@ 0x50040900) Device Control IN Endpoint 0 Control Register */ 1535 __I uint32_t RESERVED; 1536 __IO uint32_t DIEPINT0; /*!< (@ 0x50040908) Device Endpoint-0 Interrupt Register */ 1537 __I uint32_t RESERVED1; 1538 __IO uint32_t DIEPTSIZ0; /*!< (@ 0x50040910) Device IN Endpoint 0 Transfer Size Register */ 1539 __IO uint32_t DIEPDMA0; /*!< (@ 0x50040914) Device Endpoint-0 DMA Address Register */ 1540 __I uint32_t DTXFSTS0; /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register */ 1541 __I uint32_t DIEPDMAB0; /*!< (@ 0x5004091C) Device Endpoint-0 DMA Buffer Address Register */ 1542 __I uint32_t RESERVED2[120]; 1543 __IO uint32_t DOEPCTL0; /*!< (@ 0x50040B00) Device Control OUT Endpoint 0 Control Register */ 1544 __I uint32_t RESERVED3; 1545 __IO uint32_t DOEPINT0; /*!< (@ 0x50040B08) Device Endpoint-0 Interrupt Register */ 1546 __I uint32_t RESERVED4; 1547 __IO uint32_t DOEPTSIZ0; /*!< (@ 0x50040B10) Device OUT Endpoint 0 Transfer Size Register */ 1548 __IO uint32_t DOEPDMA0; /*!< (@ 0x50040B14) Device Endpoint-0 DMA Address Register */ 1549 __I uint32_t RESERVED5; 1550 __I uint32_t DOEPDMAB0; /*!< (@ 0x50040B1C) Device Endpoint-0 DMA Buffer Address Register */ 1551 } USB0_EP0_TypeDef; 1552 1553 1554 /* ================================================================================ */ 1555 /* ================ USB_EP [USB0_EP1] ================ */ 1556 /* ================================================================================ */ 1557 1558 1559 /** 1560 * @brief Universal Serial Bus (USB_EP) 1561 */ 1562 1563 typedef struct { /*!< (@ 0x50040920) USB_EP Structure */ 1564 1565 union { 1566 __IO uint32_t DIEPCTL_INTBULK; /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK] */ 1567 __IO uint32_t DIEPCTL_ISOCONT; /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT] */ 1568 }; 1569 __I uint32_t RESERVED; 1570 __IO uint32_t DIEPINT; /*!< (@ 0x50040928) Device Endpoint Interrupt Register */ 1571 __I uint32_t RESERVED1; 1572 __IO uint32_t DIEPTSIZ; /*!< (@ 0x50040930) Device Endpoint Transfer Size Register */ 1573 __IO uint32_t DIEPDMA; /*!< (@ 0x50040934) Device Endpoint DMA Address Register */ 1574 __I uint32_t DTXFSTS; /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register */ 1575 __I uint32_t DIEPDMAB; /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register */ 1576 __I uint32_t RESERVED2[120]; 1577 1578 union { 1579 __IO uint32_t DOEPCTL_INTBULK; /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK] */ 1580 __IO uint32_t DOEPCTL_ISOCONT; /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT] */ 1581 }; 1582 __I uint32_t RESERVED3; 1583 __IO uint32_t DOEPINT; /*!< (@ 0x50040B28) Device Endpoint Interrupt Register */ 1584 __I uint32_t RESERVED4; 1585 1586 union { 1587 __IO uint32_t DOEPTSIZ_CONTROL; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT] */ 1588 __IO uint32_t DOEPTSIZ_ISO; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO] */ 1589 }; 1590 __IO uint32_t DOEPDMA; /*!< (@ 0x50040B34) Device Endpoint DMA Address Register */ 1591 __I uint32_t RESERVED5; 1592 __I uint32_t DOEPDMAB; /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register */ 1593 } USB0_EP_TypeDef; 1594 1595 1596 /* ================================================================================ */ 1597 /* ================ USB_CH [USB0_CH0] ================ */ 1598 /* ================================================================================ */ 1599 1600 1601 /** 1602 * @brief Universal Serial Bus (USB_CH) 1603 */ 1604 1605 typedef struct { /*!< (@ 0x50040500) USB_CH Structure */ 1606 __IO uint32_t HCCHAR; /*!< (@ 0x50040500) Host Channel Characteristics Register */ 1607 __I uint32_t RESERVED; 1608 __IO uint32_t HCINT; /*!< (@ 0x50040508) Host Channel Interrupt Register */ 1609 __IO uint32_t HCINTMSK; /*!< (@ 0x5004050C) Host Channel Interrupt Mask Register */ 1610 1611 union { 1612 __IO uint32_t HCTSIZ_SCATGATHER; /*!< (@ 0x50040510) Host Channel Transfer Size Register [SCATGATHER] */ 1613 __IO uint32_t HCTSIZ_BUFFERMODE; /*!< (@ 0x50040510) Host Channel Transfer Size Register [BUFFERMODE] */ 1614 }; 1615 1616 union { 1617 __IO uint32_t HCDMA_SCATGATHER; /*!< (@ 0x50040514) Host Channel DMA Address Register [SCATGATHER] */ 1618 __IO uint32_t HCDMA_BUFFERMODE; /*!< (@ 0x50040514) Host Channel DMA Address Register [BUFFERMODE] */ 1619 }; 1620 __I uint32_t RESERVED1; 1621 __I uint32_t HCDMAB; /*!< (@ 0x5004051C) Host Channel DMA Buffer Address Register */ 1622 } USB0_CH_TypeDef; 1623 1624 1625 /* ================================================================================ */ 1626 /* ================ USIC [USIC0] ================ */ 1627 /* ================================================================================ */ 1628 1629 1630 /** 1631 * @brief Universal Serial Interface Controller 0 (USIC) 1632 */ 1633 1634 typedef struct { /*!< (@ 0x40030008) USIC Structure */ 1635 __I uint32_t ID; /*!< (@ 0x40030008) Module Identification Register */ 1636 } USIC_GLOBAL_TypeDef; 1637 1638 1639 /* ================================================================================ */ 1640 /* ================ USIC_CH [USIC0_CH0] ================ */ 1641 /* ================================================================================ */ 1642 1643 1644 /** 1645 * @brief Universal Serial Interface Controller 0 (USIC_CH) 1646 */ 1647 1648 typedef struct { /*!< (@ 0x40030000) USIC_CH Structure */ 1649 __I uint32_t RESERVED; 1650 __I uint32_t CCFG; /*!< (@ 0x40030004) Channel Configuration Register */ 1651 __I uint32_t RESERVED1; 1652 __IO uint32_t KSCFG; /*!< (@ 0x4003000C) Kernel State Configuration Register */ 1653 __IO uint32_t FDR; /*!< (@ 0x40030010) Fractional Divider Register */ 1654 __IO uint32_t BRG; /*!< (@ 0x40030014) Baud Rate Generator Register */ 1655 __IO uint32_t INPR; /*!< (@ 0x40030018) Interrupt Node Pointer Register */ 1656 __IO uint32_t DX0CR; /*!< (@ 0x4003001C) Input Control Register 0 */ 1657 __IO uint32_t DX1CR; /*!< (@ 0x40030020) Input Control Register 1 */ 1658 __IO uint32_t DX2CR; /*!< (@ 0x40030024) Input Control Register 2 */ 1659 __IO uint32_t DX3CR; /*!< (@ 0x40030028) Input Control Register 3 */ 1660 __IO uint32_t DX4CR; /*!< (@ 0x4003002C) Input Control Register 4 */ 1661 __IO uint32_t DX5CR; /*!< (@ 0x40030030) Input Control Register 5 */ 1662 __IO uint32_t SCTR; /*!< (@ 0x40030034) Shift Control Register */ 1663 __IO uint32_t TCSR; /*!< (@ 0x40030038) Transmit Control/Status Register */ 1664 1665 union { 1666 __IO uint32_t PCR_IICMode; /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode] */ 1667 __IO uint32_t PCR_IISMode; /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode] */ 1668 __IO uint32_t PCR_SSCMode; /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode] */ 1669 __IO uint32_t PCR; /*!< (@ 0x4003003C) Protocol Control Register */ 1670 __IO uint32_t PCR_ASCMode; /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode] */ 1671 }; 1672 __IO uint32_t CCR; /*!< (@ 0x40030040) Channel Control Register */ 1673 __IO uint32_t CMTR; /*!< (@ 0x40030044) Capture Mode Timer Register */ 1674 1675 union { 1676 __IO uint32_t PSR_IICMode; /*!< (@ 0x40030048) Protocol Status Register [IIC Mode] */ 1677 __IO uint32_t PSR_IISMode; /*!< (@ 0x40030048) Protocol Status Register [IIS Mode] */ 1678 __IO uint32_t PSR_SSCMode; /*!< (@ 0x40030048) Protocol Status Register [SSC Mode] */ 1679 __IO uint32_t PSR; /*!< (@ 0x40030048) Protocol Status Register */ 1680 __IO uint32_t PSR_ASCMode; /*!< (@ 0x40030048) Protocol Status Register [ASC Mode] */ 1681 }; 1682 __O uint32_t PSCR; /*!< (@ 0x4003004C) Protocol Status Clear Register */ 1683 __I uint32_t RBUFSR; /*!< (@ 0x40030050) Receiver Buffer Status Register */ 1684 __I uint32_t RBUF; /*!< (@ 0x40030054) Receiver Buffer Register */ 1685 __I uint32_t RBUFD; /*!< (@ 0x40030058) Receiver Buffer Register for Debugger */ 1686 __I uint32_t RBUF0; /*!< (@ 0x4003005C) Receiver Buffer Register 0 */ 1687 __I uint32_t RBUF1; /*!< (@ 0x40030060) Receiver Buffer Register 1 */ 1688 __I uint32_t RBUF01SR; /*!< (@ 0x40030064) Receiver Buffer 01 Status Register */ 1689 __O uint32_t FMR; /*!< (@ 0x40030068) Flag Modification Register */ 1690 __I uint32_t RESERVED2[5]; 1691 __IO uint32_t TBUF[32]; /*!< (@ 0x40030080) Transmit Buffer */ 1692 __IO uint32_t BYP; /*!< (@ 0x40030100) Bypass Data Register */ 1693 __IO uint32_t BYPCR; /*!< (@ 0x40030104) Bypass Control Register */ 1694 __IO uint32_t TBCTR; /*!< (@ 0x40030108) Transmitter Buffer Control Register */ 1695 __IO uint32_t RBCTR; /*!< (@ 0x4003010C) Receiver Buffer Control Register */ 1696 __I uint32_t TRBPTR; /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register */ 1697 __IO uint32_t TRBSR; /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register */ 1698 __O uint32_t TRBSCR; /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register */ 1699 __I uint32_t OUTR; /*!< (@ 0x4003011C) Receiver Buffer Output Register */ 1700 __I uint32_t OUTDR; /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger */ 1701 __I uint32_t RESERVED3[23]; 1702 __O uint32_t IN[32]; /*!< (@ 0x40030180) Transmit FIFO Buffer */ 1703 } USIC_CH_TypeDef; 1704 1705 1706 /* ================================================================================ */ 1707 /* ================ CAN ================ */ 1708 /* ================================================================================ */ 1709 1710 1711 /** 1712 * @brief Controller Area Networks (CAN) 1713 */ 1714 1715 typedef struct { /*!< (@ 0x48014000) CAN Structure */ 1716 __IO uint32_t CLC; /*!< (@ 0x48014000) CAN Clock Control Register */ 1717 __I uint32_t RESERVED; 1718 __I uint32_t ID; /*!< (@ 0x48014008) Module Identification Register */ 1719 __IO uint32_t FDR; /*!< (@ 0x4801400C) CAN Fractional Divider Register */ 1720 __I uint32_t RESERVED1[60]; 1721 __I uint32_t LIST[8]; /*!< (@ 0x48014100) List Register */ 1722 __I uint32_t RESERVED2[8]; 1723 __IO uint32_t MSPND[8]; /*!< (@ 0x48014140) Message Pending Register */ 1724 __I uint32_t RESERVED3[8]; 1725 __I uint32_t MSID[8]; /*!< (@ 0x48014180) Message Index Register */ 1726 __I uint32_t RESERVED4[8]; 1727 __IO uint32_t MSIMASK; /*!< (@ 0x480141C0) Message Index Mask Register */ 1728 __IO uint32_t PANCTR; /*!< (@ 0x480141C4) Panel Control Register */ 1729 __IO uint32_t MCR; /*!< (@ 0x480141C8) Module Control Register */ 1730 __O uint32_t MITR; /*!< (@ 0x480141CC) Module Interrupt Trigger Register */ 1731 } CAN_GLOBAL_TypeDef; 1732 1733 1734 /* ================================================================================ */ 1735 /* ================ CAN_NODE [CAN_NODE0] ================ */ 1736 /* ================================================================================ */ 1737 1738 1739 /** 1740 * @brief Controller Area Networks (CAN_NODE) 1741 */ 1742 1743 typedef struct { /*!< (@ 0x48014200) CAN_NODE Structure */ 1744 __IO uint32_t NCR; /*!< (@ 0x48014200) Node Control Register */ 1745 __IO uint32_t NSR; /*!< (@ 0x48014204) Node Status Register */ 1746 __IO uint32_t NIPR; /*!< (@ 0x48014208) Node Interrupt Pointer Register */ 1747 __IO uint32_t NPCR; /*!< (@ 0x4801420C) Node Port Control Register */ 1748 __IO uint32_t NBTR; /*!< (@ 0x48014210) Node Bit Timing Register */ 1749 __IO uint32_t NECNT; /*!< (@ 0x48014214) Node Error Counter Register */ 1750 __IO uint32_t NFCR; /*!< (@ 0x48014218) Node Frame Counter Register */ 1751 } CAN_NODE_TypeDef; 1752 1753 1754 /* ================================================================================ */ 1755 /* ================ CAN_MO [CAN_MO0] ================ */ 1756 /* ================================================================================ */ 1757 1758 1759 /** 1760 * @brief Controller Area Networks (CAN_MO) 1761 */ 1762 1763 typedef struct { /*!< (@ 0x48015000) CAN_MO Structure */ 1764 __IO uint32_t MOFCR; /*!< (@ 0x48015000) Message Object Function Control Register */ 1765 __IO uint32_t MOFGPR; /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register */ 1766 __IO uint32_t MOIPR; /*!< (@ 0x48015008) Message Object Interrupt Pointer Register */ 1767 __IO uint32_t MOAMR; /*!< (@ 0x4801500C) Message Object Acceptance Mask Register */ 1768 __IO uint32_t MODATAL; /*!< (@ 0x48015010) Message Object Data Register Low */ 1769 __IO uint32_t MODATAH; /*!< (@ 0x48015014) Message Object Data Register High */ 1770 __IO uint32_t MOAR; /*!< (@ 0x48015018) Message Object Arbitration Register */ 1771 1772 union { 1773 __I uint32_t MOSTAT; /*!< (@ 0x4801501C) Message Object Status Register */ 1774 __O uint32_t MOCTR; /*!< (@ 0x4801501C) Message Object Control Register */ 1775 }; 1776 } CAN_MO_TypeDef; 1777 1778 1779 /* ================================================================================ */ 1780 /* ================ VADC ================ */ 1781 /* ================================================================================ */ 1782 1783 1784 /** 1785 * @brief Analog to Digital Converter (VADC) 1786 */ 1787 1788 typedef struct { /*!< (@ 0x40004000) VADC Structure */ 1789 __IO uint32_t CLC; /*!< (@ 0x40004000) Clock Control Register */ 1790 __I uint32_t RESERVED; 1791 __I uint32_t ID; /*!< (@ 0x40004008) Module Identification Register */ 1792 __I uint32_t RESERVED1[7]; 1793 __IO uint32_t OCS; /*!< (@ 0x40004028) OCDS Control and Status Register */ 1794 __I uint32_t RESERVED2[21]; 1795 __IO uint32_t GLOBCFG; /*!< (@ 0x40004080) Global Configuration Register */ 1796 __I uint32_t RESERVED3[7]; 1797 __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x400040A0) Input Class Register, Global */ 1798 __I uint32_t RESERVED4[4]; 1799 __IO uint32_t GLOBBOUND; /*!< (@ 0x400040B8) Global Boundary Select Register */ 1800 __I uint32_t RESERVED5[9]; 1801 __IO uint32_t GLOBEFLAG; /*!< (@ 0x400040E0) Global Event Flag Register */ 1802 __I uint32_t RESERVED6[23]; 1803 __IO uint32_t GLOBEVNP; /*!< (@ 0x40004140) Global Event Node Pointer Register */ 1804 __I uint32_t RESERVED7[7]; 1805 __IO uint32_t GLOBTF; /*!< (@ 0x40004160) Global Test Functions Register */ 1806 __I uint32_t RESERVED8[7]; 1807 __IO uint32_t BRSSEL[4]; /*!< (@ 0x40004180) Background Request Source Channel Select Register */ 1808 __I uint32_t RESERVED9[12]; 1809 __IO uint32_t BRSPND[4]; /*!< (@ 0x400041C0) Background Request Source Pending Register */ 1810 __I uint32_t RESERVED10[12]; 1811 __IO uint32_t BRSCTRL; /*!< (@ 0x40004200) Background Request Source Control Register */ 1812 __IO uint32_t BRSMR; /*!< (@ 0x40004204) Background Request Source Mode Register */ 1813 __I uint32_t RESERVED11[30]; 1814 __IO uint32_t GLOBRCR; /*!< (@ 0x40004280) Global Result Control Register */ 1815 __I uint32_t RESERVED12[31]; 1816 __IO uint32_t GLOBRES; /*!< (@ 0x40004300) Global Result Register */ 1817 __I uint32_t RESERVED13[31]; 1818 __IO uint32_t GLOBRESD; /*!< (@ 0x40004380) Global Result Register, Debug */ 1819 __I uint32_t RESERVED14[27]; 1820 __IO uint32_t EMUXSEL; /*!< (@ 0x400043F0) External Multiplexer Select Register */ 1821 } VADC_GLOBAL_TypeDef; 1822 1823 1824 /* ================================================================================ */ 1825 /* ================ VADC_G [VADC_G0] ================ */ 1826 /* ================================================================================ */ 1827 1828 1829 /** 1830 * @brief Analog to Digital Converter (VADC_G) 1831 */ 1832 1833 typedef struct { /*!< (@ 0x40004400) VADC_G Structure */ 1834 __I uint32_t RESERVED[32]; 1835 __IO uint32_t ARBCFG; /*!< (@ 0x40004480) Arbitration Configuration Register */ 1836 __IO uint32_t ARBPR; /*!< (@ 0x40004484) Arbitration Priority Register */ 1837 __IO uint32_t CHASS; /*!< (@ 0x40004488) Channel Assignment Register */ 1838 __I uint32_t RESERVED1[5]; 1839 __IO uint32_t ICLASS[2]; /*!< (@ 0x400044A0) Input Class Register */ 1840 __I uint32_t RESERVED2[2]; 1841 __IO uint32_t ALIAS; /*!< (@ 0x400044B0) Alias Register */ 1842 __I uint32_t RESERVED3; 1843 __IO uint32_t BOUND; /*!< (@ 0x400044B8) Boundary Select Register */ 1844 __I uint32_t RESERVED4; 1845 __IO uint32_t SYNCTR; /*!< (@ 0x400044C0) Synchronization Control Register */ 1846 __I uint32_t RESERVED5; 1847 __IO uint32_t BFL; /*!< (@ 0x400044C8) Boundary Flag Register */ 1848 __I uint32_t RESERVED6[13]; 1849 __IO uint32_t QCTRL0; /*!< (@ 0x40004500) Queue 0 Source Control Register */ 1850 __IO uint32_t QMR0; /*!< (@ 0x40004504) Queue 0 Mode Register */ 1851 __I uint32_t QSR0; /*!< (@ 0x40004508) Queue 0 Status Register */ 1852 __I uint32_t Q0R0; /*!< (@ 0x4000450C) Queue 0 Register 0 */ 1853 1854 union { 1855 __I uint32_t QBUR0; /*!< (@ 0x40004510) Queue 0 Backup Register */ 1856 __O uint32_t QINR0; /*!< (@ 0x40004510) Queue 0 Input Register */ 1857 }; 1858 __I uint32_t RESERVED7[3]; 1859 __IO uint32_t ASCTRL; /*!< (@ 0x40004520) Autoscan Source Control Register */ 1860 __IO uint32_t ASMR; /*!< (@ 0x40004524) Autoscan Source Mode Register */ 1861 __IO uint32_t ASSEL; /*!< (@ 0x40004528) Autoscan Source Channel Select Register */ 1862 __IO uint32_t ASPND; /*!< (@ 0x4000452C) Autoscan Source Pending Register */ 1863 __I uint32_t RESERVED8[20]; 1864 __IO uint32_t CEFLAG; /*!< (@ 0x40004580) Channel Event Flag Register */ 1865 __IO uint32_t REFLAG; /*!< (@ 0x40004584) Result Event Flag Register */ 1866 __IO uint32_t SEFLAG; /*!< (@ 0x40004588) Source Event Flag Register */ 1867 __I uint32_t RESERVED9; 1868 __O uint32_t CEFCLR; /*!< (@ 0x40004590) Channel Event Flag Clear Register */ 1869 __O uint32_t REFCLR; /*!< (@ 0x40004594) Result Event Flag Clear Register */ 1870 __O uint32_t SEFCLR; /*!< (@ 0x40004598) Source Event Flag Clear Register */ 1871 __I uint32_t RESERVED10; 1872 __IO uint32_t CEVNP0; /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0 */ 1873 __I uint32_t RESERVED11[3]; 1874 __IO uint32_t REVNP0; /*!< (@ 0x400045B0) Result Event Node Pointer Register 0 */ 1875 __IO uint32_t REVNP1; /*!< (@ 0x400045B4) Result Event Node Pointer Register 1 */ 1876 __I uint32_t RESERVED12[2]; 1877 __IO uint32_t SEVNP; /*!< (@ 0x400045C0) Source Event Node Pointer Register */ 1878 __I uint32_t RESERVED13; 1879 __O uint32_t SRACT; /*!< (@ 0x400045C8) Service Request Software Activation Trigger */ 1880 __I uint32_t RESERVED14[9]; 1881 __IO uint32_t EMUXCTR; /*!< (@ 0x400045F0) External Multiplexer Control Register */ 1882 __I uint32_t RESERVED15; 1883 __IO uint32_t VFR; /*!< (@ 0x400045F8) Valid Flag Register */ 1884 __I uint32_t RESERVED16; 1885 __IO uint32_t CHCTR[8]; /*!< (@ 0x40004600) Channel Ctrl. Reg. */ 1886 __I uint32_t RESERVED17[24]; 1887 __IO uint32_t RCR[16]; /*!< (@ 0x40004680) Result Control Register */ 1888 __I uint32_t RESERVED18[16]; 1889 __IO uint32_t RES[16]; /*!< (@ 0x40004700) Result Register */ 1890 __I uint32_t RESERVED19[16]; 1891 __I uint32_t RESD[16]; /*!< (@ 0x40004780) Result Register, Debug */ 1892 } VADC_G_TypeDef; 1893 1894 1895 /* ================================================================================ */ 1896 /* ================ DSD ================ */ 1897 /* ================================================================================ */ 1898 1899 1900 /** 1901 * @brief Delta Sigma Demodulator (DSD) 1902 */ 1903 1904 typedef struct { /*!< (@ 0x40008000) DSD Structure */ 1905 __IO uint32_t CLC; /*!< (@ 0x40008000) Clock Control Register */ 1906 __I uint32_t RESERVED; 1907 __I uint32_t ID; /*!< (@ 0x40008008) Module Identification Register */ 1908 __I uint32_t RESERVED1[7]; 1909 __IO uint32_t OCS; /*!< (@ 0x40008028) OCDS Control and Status Register */ 1910 __I uint32_t RESERVED2[21]; 1911 __IO uint32_t GLOBCFG; /*!< (@ 0x40008080) Global Configuration Register */ 1912 __I uint32_t RESERVED3; 1913 __IO uint32_t GLOBRC; /*!< (@ 0x40008088) Global Run Control Register */ 1914 __I uint32_t RESERVED4[5]; 1915 __IO uint32_t CGCFG; /*!< (@ 0x400080A0) Carrier Generator Configuration Register */ 1916 __I uint32_t RESERVED5[15]; 1917 __IO uint32_t EVFLAG; /*!< (@ 0x400080E0) Event Flag Register */ 1918 __O uint32_t EVFLAGCLR; /*!< (@ 0x400080E4) Event Flag Clear Register */ 1919 } DSD_GLOBAL_TypeDef; 1920 1921 1922 /* ================================================================================ */ 1923 /* ================ DSD_CH [DSD_CH0] ================ */ 1924 /* ================================================================================ */ 1925 1926 1927 /** 1928 * @brief Delta Sigma Demodulator (DSD_CH) 1929 */ 1930 1931 typedef struct { /*!< (@ 0x40008100) DSD_CH Structure */ 1932 __IO uint32_t MODCFG; /*!< (@ 0x40008100) Modulator Configuration Register */ 1933 __I uint32_t RESERVED; 1934 __IO uint32_t DICFG; /*!< (@ 0x40008108) Demodulator Input Configuration Register */ 1935 __I uint32_t RESERVED1[2]; 1936 __IO uint32_t FCFGC; /*!< (@ 0x40008114) Filter Configuration Register, Main Comb Filter */ 1937 __IO uint32_t FCFGA; /*!< (@ 0x40008118) Filter Configuration Register, Auxiliary Filter */ 1938 __I uint32_t RESERVED2; 1939 __IO uint32_t IWCTR; /*!< (@ 0x40008120) Integration Window Control Register */ 1940 __I uint32_t RESERVED3; 1941 __IO uint32_t BOUNDSEL; /*!< (@ 0x40008128) Boundary Select Register */ 1942 __I uint32_t RESERVED4; 1943 __I uint32_t RESM; /*!< (@ 0x40008130) Result Register, Main Filter */ 1944 __I uint32_t RESERVED5; 1945 __IO uint32_t OFFM; /*!< (@ 0x40008138) Offset Register, Main Filter */ 1946 __I uint32_t RESERVED6; 1947 __I uint32_t RESA; /*!< (@ 0x40008140) Result Register, Auxiliary Filter */ 1948 __I uint32_t RESERVED7[3]; 1949 __I uint32_t TSTMP; /*!< (@ 0x40008150) Time-Stamp Register */ 1950 __I uint32_t RESERVED8[19]; 1951 __IO uint32_t CGSYNC; /*!< (@ 0x400081A0) Carrier Generator Synchronization Register */ 1952 __I uint32_t RESERVED9; 1953 __IO uint32_t RECTCFG; /*!< (@ 0x400081A8) Rectification Configuration Register */ 1954 } DSD_CH_TypeDef; 1955 1956 1957 /* ================================================================================ */ 1958 /* ================ DAC ================ */ 1959 /* ================================================================================ */ 1960 1961 1962 /** 1963 * @brief Digital to Analog Converter (DAC) 1964 */ 1965 1966 typedef struct { /*!< (@ 0x48018000) DAC Structure */ 1967 __I uint32_t ID; /*!< (@ 0x48018000) Module Identification Register */ 1968 __IO uint32_t DAC0CFG0; /*!< (@ 0x48018004) DAC0 Configuration Register 0 */ 1969 __IO uint32_t DAC0CFG1; /*!< (@ 0x48018008) DAC0 Configuration Register 1 */ 1970 __IO uint32_t DAC1CFG0; /*!< (@ 0x4801800C) DAC1 Configuration Register 0 */ 1971 __IO uint32_t DAC1CFG1; /*!< (@ 0x48018010) DAC1 Configuration Register 1 */ 1972 __IO uint32_t DAC0DATA; /*!< (@ 0x48018014) DAC0 Data Register */ 1973 __IO uint32_t DAC1DATA; /*!< (@ 0x48018018) DAC1 Data Register */ 1974 __IO uint32_t DAC01DATA; /*!< (@ 0x4801801C) DAC01 Data Register */ 1975 __IO uint32_t DAC0PATL; /*!< (@ 0x48018020) DAC0 Lower Pattern Register */ 1976 __IO uint32_t DAC0PATH; /*!< (@ 0x48018024) DAC0 Higher Pattern Register */ 1977 __IO uint32_t DAC1PATL; /*!< (@ 0x48018028) DAC1 Lower Pattern Register */ 1978 __IO uint32_t DAC1PATH; /*!< (@ 0x4801802C) DAC1 Higher Pattern Register */ 1979 } DAC_GLOBAL_TypeDef; 1980 1981 1982 /* ================================================================================ */ 1983 /* ================ CCU4 [CCU40] ================ */ 1984 /* ================================================================================ */ 1985 1986 1987 /** 1988 * @brief Capture Compare Unit 4 - Unit 0 (CCU4) 1989 */ 1990 1991 typedef struct { /*!< (@ 0x4000C000) CCU4 Structure */ 1992 __IO uint32_t GCTRL; /*!< (@ 0x4000C000) Global Control Register */ 1993 __I uint32_t GSTAT; /*!< (@ 0x4000C004) Global Status Register */ 1994 __O uint32_t GIDLS; /*!< (@ 0x4000C008) Global Idle Set */ 1995 __O uint32_t GIDLC; /*!< (@ 0x4000C00C) Global Idle Clear */ 1996 __O uint32_t GCSS; /*!< (@ 0x4000C010) Global Channel Set */ 1997 __O uint32_t GCSC; /*!< (@ 0x4000C014) Global Channel Clear */ 1998 __I uint32_t GCST; /*!< (@ 0x4000C018) Global Channel Status */ 1999 __I uint32_t RESERVED[13]; 2000 __I uint32_t ECRD; /*!< (@ 0x4000C050) Extended Capture Mode Read */ 2001 __I uint32_t RESERVED1[11]; 2002 __I uint32_t MIDR; /*!< (@ 0x4000C080) Module Identification */ 2003 } CCU4_GLOBAL_TypeDef; 2004 2005 2006 /* ================================================================================ */ 2007 /* ================ CCU4_CC4 [CCU40_CC40] ================ */ 2008 /* ================================================================================ */ 2009 2010 2011 /** 2012 * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4) 2013 */ 2014 2015 typedef struct { /*!< (@ 0x4000C100) CCU4_CC4 Structure */ 2016 __IO uint32_t INS; /*!< (@ 0x4000C100) Input Selector Configuration */ 2017 __IO uint32_t CMC; /*!< (@ 0x4000C104) Connection Matrix Control */ 2018 __I uint32_t TCST; /*!< (@ 0x4000C108) Slice Timer Status */ 2019 __O uint32_t TCSET; /*!< (@ 0x4000C10C) Slice Timer Run Set */ 2020 __O uint32_t TCCLR; /*!< (@ 0x4000C110) Slice Timer Clear */ 2021 __IO uint32_t TC; /*!< (@ 0x4000C114) Slice Timer Control */ 2022 __IO uint32_t PSL; /*!< (@ 0x4000C118) Passive Level Config */ 2023 __I uint32_t DIT; /*!< (@ 0x4000C11C) Dither Config */ 2024 __IO uint32_t DITS; /*!< (@ 0x4000C120) Dither Shadow Register */ 2025 __IO uint32_t PSC; /*!< (@ 0x4000C124) Prescaler Control */ 2026 __IO uint32_t FPC; /*!< (@ 0x4000C128) Floating Prescaler Control */ 2027 __IO uint32_t FPCS; /*!< (@ 0x4000C12C) Floating Prescaler Shadow */ 2028 __I uint32_t PR; /*!< (@ 0x4000C130) Timer Period Value */ 2029 __IO uint32_t PRS; /*!< (@ 0x4000C134) Timer Shadow Period Value */ 2030 __I uint32_t CR; /*!< (@ 0x4000C138) Timer Compare Value */ 2031 __IO uint32_t CRS; /*!< (@ 0x4000C13C) Timer Shadow Compare Value */ 2032 __I uint32_t RESERVED[12]; 2033 __IO uint32_t TIMER; /*!< (@ 0x4000C170) Timer Value */ 2034 __I uint32_t CV[4]; /*!< (@ 0x4000C174) Capture Register 0 */ 2035 __I uint32_t RESERVED1[7]; 2036 __I uint32_t INTS; /*!< (@ 0x4000C1A0) Interrupt Status */ 2037 __IO uint32_t INTE; /*!< (@ 0x4000C1A4) Interrupt Enable Control */ 2038 __IO uint32_t SRS; /*!< (@ 0x4000C1A8) Service Request Selector */ 2039 __O uint32_t SWS; /*!< (@ 0x4000C1AC) Interrupt Status Set */ 2040 __O uint32_t SWR; /*!< (@ 0x4000C1B0) Interrupt Status Clear */ 2041 } CCU4_CC4_TypeDef; 2042 2043 2044 /* ================================================================================ */ 2045 /* ================ CCU8 [CCU80] ================ */ 2046 /* ================================================================================ */ 2047 2048 2049 /** 2050 * @brief Capture Compare Unit 8 - Unit 0 (CCU8) 2051 */ 2052 2053 typedef struct { /*!< (@ 0x40020000) CCU8 Structure */ 2054 __IO uint32_t GCTRL; /*!< (@ 0x40020000) Global Control Register */ 2055 __I uint32_t GSTAT; /*!< (@ 0x40020004) Global Status Register */ 2056 __O uint32_t GIDLS; /*!< (@ 0x40020008) Global Idle Set */ 2057 __O uint32_t GIDLC; /*!< (@ 0x4002000C) Global Idle Clear */ 2058 __O uint32_t GCSS; /*!< (@ 0x40020010) Global Channel Set */ 2059 __O uint32_t GCSC; /*!< (@ 0x40020014) Global Channel Clear */ 2060 __I uint32_t GCST; /*!< (@ 0x40020018) Global Channel status */ 2061 __IO uint32_t GPCHK; /*!< (@ 0x4002001C) Parity Checker Configuration */ 2062 __I uint32_t RESERVED[12]; 2063 __I uint32_t ECRD; /*!< (@ 0x40020050) Extended Capture Mode Read */ 2064 __I uint32_t RESERVED1[11]; 2065 __I uint32_t MIDR; /*!< (@ 0x40020080) Module Identification */ 2066 } CCU8_GLOBAL_TypeDef; 2067 2068 2069 /* ================================================================================ */ 2070 /* ================ CCU8_CC8 [CCU80_CC80] ================ */ 2071 /* ================================================================================ */ 2072 2073 2074 /** 2075 * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8) 2076 */ 2077 2078 typedef struct { /*!< (@ 0x40020100) CCU8_CC8 Structure */ 2079 __IO uint32_t INS; /*!< (@ 0x40020100) Input Selector Configuration */ 2080 __IO uint32_t CMC; /*!< (@ 0x40020104) Connection Matrix Control */ 2081 __I uint32_t TCST; /*!< (@ 0x40020108) Slice Timer Status */ 2082 __O uint32_t TCSET; /*!< (@ 0x4002010C) Slice Timer Run Set */ 2083 __O uint32_t TCCLR; /*!< (@ 0x40020110) Slice Timer Clear */ 2084 __IO uint32_t TC; /*!< (@ 0x40020114) Slice Timer Control */ 2085 __IO uint32_t PSL; /*!< (@ 0x40020118) Passive Level Config */ 2086 __I uint32_t DIT; /*!< (@ 0x4002011C) Dither Config */ 2087 __IO uint32_t DITS; /*!< (@ 0x40020120) Dither Shadow Register */ 2088 __IO uint32_t PSC; /*!< (@ 0x40020124) Prescaler Control */ 2089 __IO uint32_t FPC; /*!< (@ 0x40020128) Floating Prescaler Control */ 2090 __IO uint32_t FPCS; /*!< (@ 0x4002012C) Floating Prescaler Shadow */ 2091 __I uint32_t PR; /*!< (@ 0x40020130) Timer Period Value */ 2092 __IO uint32_t PRS; /*!< (@ 0x40020134) Timer Shadow Period Value */ 2093 __I uint32_t CR1; /*!< (@ 0x40020138) Channel 1 Compare Value */ 2094 __IO uint32_t CR1S; /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value */ 2095 __I uint32_t CR2; /*!< (@ 0x40020140) Channel 2 Compare Value */ 2096 __IO uint32_t CR2S; /*!< (@ 0x40020144) Channel 2 Compare Shadow Value */ 2097 __IO uint32_t CHC; /*!< (@ 0x40020148) Channel Control */ 2098 __IO uint32_t DTC; /*!< (@ 0x4002014C) Dead Time Control */ 2099 __IO uint32_t DC1R; /*!< (@ 0x40020150) Channel 1 Dead Time Values */ 2100 __IO uint32_t DC2R; /*!< (@ 0x40020154) Channel 2 Dead Time Values */ 2101 __I uint32_t RESERVED[6]; 2102 __IO uint32_t TIMER; /*!< (@ 0x40020170) Timer Value */ 2103 __I uint32_t CV[4]; /*!< (@ 0x40020174) Capture Register 0 */ 2104 __I uint32_t RESERVED1[7]; 2105 __I uint32_t INTS; /*!< (@ 0x400201A0) Interrupt Status */ 2106 __IO uint32_t INTE; /*!< (@ 0x400201A4) Interrupt Enable Control */ 2107 __IO uint32_t SRS; /*!< (@ 0x400201A8) Service Request Selector */ 2108 __O uint32_t SWS; /*!< (@ 0x400201AC) Interrupt Status Set */ 2109 __O uint32_t SWR; /*!< (@ 0x400201B0) Interrupt Status Clear */ 2110 } CCU8_CC8_TypeDef; 2111 2112 2113 /* ================================================================================ */ 2114 /* ================ POSIF [POSIF0] ================ */ 2115 /* ================================================================================ */ 2116 2117 2118 /** 2119 * @brief Position Interface 0 (POSIF) 2120 */ 2121 2122 typedef struct { /*!< (@ 0x40028000) POSIF Structure */ 2123 __IO uint32_t PCONF; /*!< (@ 0x40028000) POSIF configuration */ 2124 __IO uint32_t PSUS; /*!< (@ 0x40028004) POSIF Suspend Config */ 2125 __O uint32_t PRUNS; /*!< (@ 0x40028008) POSIF Run Bit Set */ 2126 __O uint32_t PRUNC; /*!< (@ 0x4002800C) POSIF Run Bit Clear */ 2127 __I uint32_t PRUN; /*!< (@ 0x40028010) POSIF Run Bit Status */ 2128 __I uint32_t RESERVED[3]; 2129 __I uint32_t MIDR; /*!< (@ 0x40028020) Module Identification register */ 2130 __I uint32_t RESERVED1[3]; 2131 __I uint32_t HALP; /*!< (@ 0x40028030) Hall Sensor Patterns */ 2132 __IO uint32_t HALPS; /*!< (@ 0x40028034) Hall Sensor Shadow Patterns */ 2133 __I uint32_t RESERVED2[2]; 2134 __I uint32_t MCM; /*!< (@ 0x40028040) Multi-Channel Pattern */ 2135 __IO uint32_t MCSM; /*!< (@ 0x40028044) Multi-Channel Shadow Pattern */ 2136 __O uint32_t MCMS; /*!< (@ 0x40028048) Multi-Channel Pattern Control set */ 2137 __O uint32_t MCMC; /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear */ 2138 __I uint32_t MCMF; /*!< (@ 0x40028050) Multi-Channel Pattern Control flag */ 2139 __I uint32_t RESERVED3[3]; 2140 __IO uint32_t QDC; /*!< (@ 0x40028060) Quadrature Decoder Control */ 2141 __I uint32_t RESERVED4[3]; 2142 __I uint32_t PFLG; /*!< (@ 0x40028070) POSIF Interrupt Flags */ 2143 __IO uint32_t PFLGE; /*!< (@ 0x40028074) POSIF Interrupt Enable */ 2144 __O uint32_t SPFLG; /*!< (@ 0x40028078) POSIF Interrupt Set */ 2145 __O uint32_t RPFLG; /*!< (@ 0x4002807C) POSIF Interrupt Clear */ 2146 __I uint32_t RESERVED5[32]; 2147 __I uint32_t PDBG; /*!< (@ 0x40028100) POSIF Debug register */ 2148 } POSIF_GLOBAL_TypeDef; 2149 2150 2151 /* ================================================================================ */ 2152 /* ================ PORT0 ================ */ 2153 /* ================================================================================ */ 2154 2155 2156 /** 2157 * @brief Port 0 (PORT0) 2158 */ 2159 2160 typedef struct { /*!< (@ 0x48028000) PORT0 Structure */ 2161 __IO uint32_t OUT; /*!< (@ 0x48028000) Port 0 Output Register */ 2162 __O uint32_t OMR; /*!< (@ 0x48028004) Port 0 Output Modification Register */ 2163 __I uint32_t RESERVED[2]; 2164 __IO uint32_t IOCR0; /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0 */ 2165 __IO uint32_t IOCR4; /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4 */ 2166 __IO uint32_t IOCR8; /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8 */ 2167 __IO uint32_t IOCR12; /*!< (@ 0x4802801C) Port 0 Input/Output Control Register 12 */ 2168 __I uint32_t RESERVED1; 2169 __I uint32_t IN; /*!< (@ 0x48028024) Port 0 Input Register */ 2170 __I uint32_t RESERVED2[6]; 2171 __IO uint32_t PDR0; /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register */ 2172 __IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register */ 2173 __I uint32_t RESERVED3[6]; 2174 __I uint32_t PDISC; /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register */ 2175 __I uint32_t RESERVED4[3]; 2176 __IO uint32_t PPS; /*!< (@ 0x48028070) Port 0 Pin Power Save Register */ 2177 __IO uint32_t HWSEL; /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register */ 2178 } PORT0_Type; 2179 2180 2181 /* ================================================================================ */ 2182 /* ================ PORT1 ================ */ 2183 /* ================================================================================ */ 2184 2185 2186 /** 2187 * @brief Port 1 (PORT1) 2188 */ 2189 2190 typedef struct { /*!< (@ 0x48028100) PORT1 Structure */ 2191 __IO uint32_t OUT; /*!< (@ 0x48028100) Port 1 Output Register */ 2192 __O uint32_t OMR; /*!< (@ 0x48028104) Port 1 Output Modification Register */ 2193 __I uint32_t RESERVED[2]; 2194 __IO uint32_t IOCR0; /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0 */ 2195 __IO uint32_t IOCR4; /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4 */ 2196 __IO uint32_t IOCR8; /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8 */ 2197 __IO uint32_t IOCR12; /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12 */ 2198 __I uint32_t RESERVED1; 2199 __I uint32_t IN; /*!< (@ 0x48028124) Port 1 Input Register */ 2200 __I uint32_t RESERVED2[6]; 2201 __IO uint32_t PDR0; /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register */ 2202 __IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register */ 2203 __I uint32_t RESERVED3[6]; 2204 __I uint32_t PDISC; /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register */ 2205 __I uint32_t RESERVED4[3]; 2206 __IO uint32_t PPS; /*!< (@ 0x48028170) Port 1 Pin Power Save Register */ 2207 __IO uint32_t HWSEL; /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register */ 2208 } PORT1_Type; 2209 2210 2211 /* ================================================================================ */ 2212 /* ================ PORT2 ================ */ 2213 /* ================================================================================ */ 2214 2215 2216 /** 2217 * @brief Port 2 (PORT2) 2218 */ 2219 2220 typedef struct { /*!< (@ 0x48028200) PORT2 Structure */ 2221 __IO uint32_t OUT; /*!< (@ 0x48028200) Port 2 Output Register */ 2222 __O uint32_t OMR; /*!< (@ 0x48028204) Port 2 Output Modification Register */ 2223 __I uint32_t RESERVED[2]; 2224 __IO uint32_t IOCR0; /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0 */ 2225 __IO uint32_t IOCR4; /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4 */ 2226 __IO uint32_t IOCR8; /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8 */ 2227 __IO uint32_t IOCR12; /*!< (@ 0x4802821C) Port 2 Input/Output Control Register 12 */ 2228 __I uint32_t RESERVED1; 2229 __I uint32_t IN; /*!< (@ 0x48028224) Port 2 Input Register */ 2230 __I uint32_t RESERVED2[6]; 2231 __IO uint32_t PDR0; /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register */ 2232 __IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register */ 2233 __I uint32_t RESERVED3[6]; 2234 __I uint32_t PDISC; /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register */ 2235 __I uint32_t RESERVED4[3]; 2236 __IO uint32_t PPS; /*!< (@ 0x48028270) Port 2 Pin Power Save Register */ 2237 __IO uint32_t HWSEL; /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register */ 2238 } PORT2_Type; 2239 2240 2241 /* ================================================================================ */ 2242 /* ================ PORT3 ================ */ 2243 /* ================================================================================ */ 2244 2245 2246 /** 2247 * @brief Port 3 (PORT3) 2248 */ 2249 2250 typedef struct { /*!< (@ 0x48028300) PORT3 Structure */ 2251 __IO uint32_t OUT; /*!< (@ 0x48028300) Port 3 Output Register */ 2252 __O uint32_t OMR; /*!< (@ 0x48028304) Port 3 Output Modification Register */ 2253 __I uint32_t RESERVED[2]; 2254 __IO uint32_t IOCR0; /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0 */ 2255 __IO uint32_t IOCR4; /*!< (@ 0x48028314) Port 3 Input/Output Control Register 4 */ 2256 __IO uint32_t IOCR8; /*!< (@ 0x48028318) Port 3 Input/Output Control Register 8 */ 2257 __IO uint32_t IOCR12; /*!< (@ 0x4802831C) Port 3 Input/Output Control Register 12 */ 2258 __I uint32_t RESERVED1; 2259 __I uint32_t IN; /*!< (@ 0x48028324) Port 3 Input Register */ 2260 __I uint32_t RESERVED2[6]; 2261 __IO uint32_t PDR0; /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register */ 2262 __IO uint32_t PDR1; /*!< (@ 0x48028344) Port 3 Pad Driver Mode 1 Register */ 2263 __I uint32_t RESERVED3[6]; 2264 __I uint32_t PDISC; /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register */ 2265 __I uint32_t RESERVED4[3]; 2266 __IO uint32_t PPS; /*!< (@ 0x48028370) Port 3 Pin Power Save Register */ 2267 __IO uint32_t HWSEL; /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register */ 2268 } PORT3_Type; 2269 2270 2271 /* ================================================================================ */ 2272 /* ================ PORT4 ================ */ 2273 /* ================================================================================ */ 2274 2275 2276 /** 2277 * @brief Port 4 (PORT4) 2278 */ 2279 2280 typedef struct { /*!< (@ 0x48028400) PORT4 Structure */ 2281 __IO uint32_t OUT; /*!< (@ 0x48028400) Port 4 Output Register */ 2282 __O uint32_t OMR; /*!< (@ 0x48028404) Port 4 Output Modification Register */ 2283 __I uint32_t RESERVED[2]; 2284 __IO uint32_t IOCR0; /*!< (@ 0x48028410) Port 4 Input/Output Control Register 0 */ 2285 __IO uint32_t IOCR4; /*!< (@ 0x48028414) Port 4 Input/Output Control Register 4 */ 2286 __I uint32_t RESERVED1[3]; 2287 __I uint32_t IN; /*!< (@ 0x48028424) Port 4 Input Register */ 2288 __I uint32_t RESERVED2[6]; 2289 __IO uint32_t PDR0; /*!< (@ 0x48028440) Port 4 Pad Driver Mode 0 Register */ 2290 __I uint32_t RESERVED3[7]; 2291 __I uint32_t PDISC; /*!< (@ 0x48028460) Port 4 Pin Function Decision Control Register */ 2292 __I uint32_t RESERVED4[3]; 2293 __IO uint32_t PPS; /*!< (@ 0x48028470) Port 4 Pin Power Save Register */ 2294 __IO uint32_t HWSEL; /*!< (@ 0x48028474) Port 4 Pin Hardware Select Register */ 2295 } PORT4_Type; 2296 2297 2298 /* ================================================================================ */ 2299 /* ================ PORT5 ================ */ 2300 /* ================================================================================ */ 2301 2302 2303 /** 2304 * @brief Port 5 (PORT5) 2305 */ 2306 2307 typedef struct { /*!< (@ 0x48028500) PORT5 Structure */ 2308 __IO uint32_t OUT; /*!< (@ 0x48028500) Port 5 Output Register */ 2309 __O uint32_t OMR; /*!< (@ 0x48028504) Port 5 Output Modification Register */ 2310 __I uint32_t RESERVED[2]; 2311 __IO uint32_t IOCR0; /*!< (@ 0x48028510) Port 5 Input/Output Control Register 0 */ 2312 __IO uint32_t IOCR4; /*!< (@ 0x48028514) Port 5 Input/Output Control Register 4 */ 2313 __IO uint32_t IOCR8; /*!< (@ 0x48028518) Port 5 Input/Output Control Register 8 */ 2314 __I uint32_t RESERVED1[2]; 2315 __I uint32_t IN; /*!< (@ 0x48028524) Port 5 Input Register */ 2316 __I uint32_t RESERVED2[6]; 2317 __IO uint32_t PDR0; /*!< (@ 0x48028540) Port 5 Pad Driver Mode 0 Register */ 2318 __IO uint32_t PDR1; /*!< (@ 0x48028544) Port 5 Pad Driver Mode 1 Register */ 2319 __I uint32_t RESERVED3[6]; 2320 __I uint32_t PDISC; /*!< (@ 0x48028560) Port 5 Pin Function Decision Control Register */ 2321 __I uint32_t RESERVED4[3]; 2322 __IO uint32_t PPS; /*!< (@ 0x48028570) Port 5 Pin Power Save Register */ 2323 __IO uint32_t HWSEL; /*!< (@ 0x48028574) Port 5 Pin Hardware Select Register */ 2324 } PORT5_Type; 2325 2326 2327 /* ================================================================================ */ 2328 /* ================ PORT6 ================ */ 2329 /* ================================================================================ */ 2330 2331 2332 /** 2333 * @brief Port 6 (PORT6) 2334 */ 2335 2336 typedef struct { /*!< (@ 0x48028600) PORT6 Structure */ 2337 __IO uint32_t OUT; /*!< (@ 0x48028600) Port 6 Output Register */ 2338 __O uint32_t OMR; /*!< (@ 0x48028604) Port 6 Output Modification Register */ 2339 __I uint32_t RESERVED[2]; 2340 __IO uint32_t IOCR0; /*!< (@ 0x48028610) Port 6 Input/Output Control Register 0 */ 2341 __IO uint32_t IOCR4; /*!< (@ 0x48028614) Port 6 Input/Output Control Register 4 */ 2342 __I uint32_t RESERVED1[3]; 2343 __I uint32_t IN; /*!< (@ 0x48028624) Port 6 Input Register */ 2344 __I uint32_t RESERVED2[6]; 2345 __IO uint32_t PDR0; /*!< (@ 0x48028640) Port 6 Pad Driver Mode 0 Register */ 2346 __I uint32_t RESERVED3[7]; 2347 __I uint32_t PDISC; /*!< (@ 0x48028660) Port 6 Pin Function Decision Control Register */ 2348 __I uint32_t RESERVED4[3]; 2349 __IO uint32_t PPS; /*!< (@ 0x48028670) Port 6 Pin Power Save Register */ 2350 __IO uint32_t HWSEL; /*!< (@ 0x48028674) Port 6 Pin Hardware Select Register */ 2351 } PORT6_Type; 2352 2353 2354 /* ================================================================================ */ 2355 /* ================ PORT14 ================ */ 2356 /* ================================================================================ */ 2357 2358 2359 /** 2360 * @brief Port 14 (PORT14) 2361 */ 2362 2363 typedef struct { /*!< (@ 0x48028E00) PORT14 Structure */ 2364 __IO uint32_t OUT; /*!< (@ 0x48028E00) Port 14 Output Register */ 2365 __O uint32_t OMR; /*!< (@ 0x48028E04) Port 14 Output Modification Register */ 2366 __I uint32_t RESERVED[2]; 2367 __IO uint32_t IOCR0; /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0 */ 2368 __IO uint32_t IOCR4; /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4 */ 2369 __IO uint32_t IOCR8; /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8 */ 2370 __IO uint32_t IOCR12; /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12 */ 2371 __I uint32_t RESERVED1; 2372 __I uint32_t IN; /*!< (@ 0x48028E24) Port 14 Input Register */ 2373 __I uint32_t RESERVED2[14]; 2374 __IO uint32_t PDISC; /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register */ 2375 __I uint32_t RESERVED3[3]; 2376 __IO uint32_t PPS; /*!< (@ 0x48028E70) Port 14 Pin Power Save Register */ 2377 __IO uint32_t HWSEL; /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register */ 2378 } PORT14_Type; 2379 2380 2381 /* ================================================================================ */ 2382 /* ================ PORT15 ================ */ 2383 /* ================================================================================ */ 2384 2385 2386 /** 2387 * @brief Port 15 (PORT15) 2388 */ 2389 2390 typedef struct { /*!< (@ 0x48028F00) PORT15 Structure */ 2391 __IO uint32_t OUT; /*!< (@ 0x48028F00) Port 15 Output Register */ 2392 __O uint32_t OMR; /*!< (@ 0x48028F04) Port 15 Output Modification Register */ 2393 __I uint32_t RESERVED[2]; 2394 __IO uint32_t IOCR0; /*!< (@ 0x48028F10) Port 15 Input/Output Control Register 0 */ 2395 __IO uint32_t IOCR4; /*!< (@ 0x48028F14) Port 15 Input/Output Control Register 4 */ 2396 __IO uint32_t IOCR8; /*!< (@ 0x48028F18) Port 15 Input/Output Control Register 8 */ 2397 __IO uint32_t IOCR12; /*!< (@ 0x48028F1C) Port 15 Input/Output Control Register 12 */ 2398 __I uint32_t RESERVED1; 2399 __I uint32_t IN; /*!< (@ 0x48028F24) Port 15 Input Register */ 2400 __I uint32_t RESERVED2[14]; 2401 __IO uint32_t PDISC; /*!< (@ 0x48028F60) Port 15 Pin Function Decision Control Register */ 2402 __I uint32_t RESERVED3[3]; 2403 __IO uint32_t PPS; /*!< (@ 0x48028F70) Port 15 Pin Power Save Register */ 2404 __IO uint32_t HWSEL; /*!< (@ 0x48028F74) Port 15 Pin Hardware Select Register */ 2405 } PORT15_Type; 2406 2407 2408 /* -------------------- End of section using anonymous unions ------------------- */ 2409 #if defined(__CC_ARM) 2410 #pragma pop 2411 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 2412 #pragma clang diagnostic pop 2413 #elif defined(__ICCARM__) 2414 /* leave anonymous unions enabled */ 2415 #elif defined(__GNUC__) 2416 /* anonymous unions are enabled by default */ 2417 #elif defined(__TMS470__) 2418 /* anonymous unions are enabled by default */ 2419 #elif defined(__TASKING__) 2420 #pragma warning restore 2421 #else 2422 #warning Not supported compiler type 2423 #endif 2424 2425 2426 2427 /* ================================================================================ */ 2428 /* ================ struct 'PPB' Position & Mask ================ */ 2429 /* ================================================================================ */ 2430 2431 2432 /* ---------------------------------- PPB_ACTLR --------------------------------- */ 2433 #define PPB_ACTLR_DISMCYCINT_Pos (0UL) /*!< PPB ACTLR: DISMCYCINT (Bit 0) */ 2434 #define PPB_ACTLR_DISMCYCINT_Msk (0x1UL) /*!< PPB ACTLR: DISMCYCINT (Bitfield-Mask: 0x01) */ 2435 #define PPB_ACTLR_DISDEFWBUF_Pos (1UL) /*!< PPB ACTLR: DISDEFWBUF (Bit 1) */ 2436 #define PPB_ACTLR_DISDEFWBUF_Msk (0x2UL) /*!< PPB ACTLR: DISDEFWBUF (Bitfield-Mask: 0x01) */ 2437 #define PPB_ACTLR_DISFOLD_Pos (2UL) /*!< PPB ACTLR: DISFOLD (Bit 2) */ 2438 #define PPB_ACTLR_DISFOLD_Msk (0x4UL) /*!< PPB ACTLR: DISFOLD (Bitfield-Mask: 0x01) */ 2439 #define PPB_ACTLR_DISFPCA_Pos (8UL) /*!< PPB ACTLR: DISFPCA (Bit 8) */ 2440 #define PPB_ACTLR_DISFPCA_Msk (0x100UL) /*!< PPB ACTLR: DISFPCA (Bitfield-Mask: 0x01) */ 2441 #define PPB_ACTLR_DISOOFP_Pos (9UL) /*!< PPB ACTLR: DISOOFP (Bit 9) */ 2442 #define PPB_ACTLR_DISOOFP_Msk (0x200UL) /*!< PPB ACTLR: DISOOFP (Bitfield-Mask: 0x01) */ 2443 2444 /* -------------------------------- PPB_SYST_CSR -------------------------------- */ 2445 #define PPB_SYST_CSR_ENABLE_Pos (0UL) /*!< PPB SYST_CSR: ENABLE (Bit 0) */ 2446 #define PPB_SYST_CSR_ENABLE_Msk (0x1UL) /*!< PPB SYST_CSR: ENABLE (Bitfield-Mask: 0x01) */ 2447 #define PPB_SYST_CSR_TICKINT_Pos (1UL) /*!< PPB SYST_CSR: TICKINT (Bit 1) */ 2448 #define PPB_SYST_CSR_TICKINT_Msk (0x2UL) /*!< PPB SYST_CSR: TICKINT (Bitfield-Mask: 0x01) */ 2449 #define PPB_SYST_CSR_CLKSOURCE_Pos (2UL) /*!< PPB SYST_CSR: CLKSOURCE (Bit 2) */ 2450 #define PPB_SYST_CSR_CLKSOURCE_Msk (0x4UL) /*!< PPB SYST_CSR: CLKSOURCE (Bitfield-Mask: 0x01) */ 2451 #define PPB_SYST_CSR_COUNTFLAG_Pos (16UL) /*!< PPB SYST_CSR: COUNTFLAG (Bit 16) */ 2452 #define PPB_SYST_CSR_COUNTFLAG_Msk (0x10000UL) /*!< PPB SYST_CSR: COUNTFLAG (Bitfield-Mask: 0x01) */ 2453 2454 /* -------------------------------- PPB_SYST_RVR -------------------------------- */ 2455 #define PPB_SYST_RVR_RELOAD_Pos (0UL) /*!< PPB SYST_RVR: RELOAD (Bit 0) */ 2456 #define PPB_SYST_RVR_RELOAD_Msk (0xffffffUL) /*!< PPB SYST_RVR: RELOAD (Bitfield-Mask: 0xffffff) */ 2457 2458 /* -------------------------------- PPB_SYST_CVR -------------------------------- */ 2459 #define PPB_SYST_CVR_CURRENT_Pos (0UL) /*!< PPB SYST_CVR: CURRENT (Bit 0) */ 2460 #define PPB_SYST_CVR_CURRENT_Msk (0xffffffUL) /*!< PPB SYST_CVR: CURRENT (Bitfield-Mask: 0xffffff) */ 2461 2462 /* ------------------------------- PPB_SYST_CALIB ------------------------------- */ 2463 #define PPB_SYST_CALIB_TENMS_Pos (0UL) /*!< PPB SYST_CALIB: TENMS (Bit 0) */ 2464 #define PPB_SYST_CALIB_TENMS_Msk (0xffffffUL) /*!< PPB SYST_CALIB: TENMS (Bitfield-Mask: 0xffffff) */ 2465 #define PPB_SYST_CALIB_SKEW_Pos (30UL) /*!< PPB SYST_CALIB: SKEW (Bit 30) */ 2466 #define PPB_SYST_CALIB_SKEW_Msk (0x40000000UL) /*!< PPB SYST_CALIB: SKEW (Bitfield-Mask: 0x01) */ 2467 #define PPB_SYST_CALIB_NOREF_Pos (31UL) /*!< PPB SYST_CALIB: NOREF (Bit 31) */ 2468 #define PPB_SYST_CALIB_NOREF_Msk (0x80000000UL) /*!< PPB SYST_CALIB: NOREF (Bitfield-Mask: 0x01) */ 2469 2470 /* ------------------------------- PPB_NVIC_ISER0 ------------------------------- */ 2471 #define PPB_NVIC_ISER0_SETENA_Pos (0UL) /*!< PPB NVIC_ISER0: SETENA (Bit 0) */ 2472 #define PPB_NVIC_ISER0_SETENA_Msk (0xffffffffUL) /*!< PPB NVIC_ISER0: SETENA (Bitfield-Mask: 0xffffffff) */ 2473 2474 /* ------------------------------- PPB_NVIC_ISER1 ------------------------------- */ 2475 #define PPB_NVIC_ISER1_SETENA_Pos (0UL) /*!< PPB NVIC_ISER1: SETENA (Bit 0) */ 2476 #define PPB_NVIC_ISER1_SETENA_Msk (0xffffffffUL) /*!< PPB NVIC_ISER1: SETENA (Bitfield-Mask: 0xffffffff) */ 2477 2478 /* ------------------------------- PPB_NVIC_ISER2 ------------------------------- */ 2479 #define PPB_NVIC_ISER2_SETENA_Pos (0UL) /*!< PPB NVIC_ISER2: SETENA (Bit 0) */ 2480 #define PPB_NVIC_ISER2_SETENA_Msk (0xffffffffUL) /*!< PPB NVIC_ISER2: SETENA (Bitfield-Mask: 0xffffffff) */ 2481 2482 /* ------------------------------- PPB_NVIC_ISER3 ------------------------------- */ 2483 #define PPB_NVIC_ISER3_SETENA_Pos (0UL) /*!< PPB NVIC_ISER3: SETENA (Bit 0) */ 2484 #define PPB_NVIC_ISER3_SETENA_Msk (0xffffffffUL) /*!< PPB NVIC_ISER3: SETENA (Bitfield-Mask: 0xffffffff) */ 2485 2486 /* ------------------------------- PPB_NVIC_ICER0 ------------------------------- */ 2487 #define PPB_NVIC_ICER0_CLRENA_Pos (0UL) /*!< PPB NVIC_ICER0: CLRENA (Bit 0) */ 2488 #define PPB_NVIC_ICER0_CLRENA_Msk (0xffffffffUL) /*!< PPB NVIC_ICER0: CLRENA (Bitfield-Mask: 0xffffffff) */ 2489 2490 /* ------------------------------- PPB_NVIC_ICER1 ------------------------------- */ 2491 #define PPB_NVIC_ICER1_CLRENA_Pos (0UL) /*!< PPB NVIC_ICER1: CLRENA (Bit 0) */ 2492 #define PPB_NVIC_ICER1_CLRENA_Msk (0xffffffffUL) /*!< PPB NVIC_ICER1: CLRENA (Bitfield-Mask: 0xffffffff) */ 2493 2494 /* ------------------------------- PPB_NVIC_ICER2 ------------------------------- */ 2495 #define PPB_NVIC_ICER2_CLRENA_Pos (0UL) /*!< PPB NVIC_ICER2: CLRENA (Bit 0) */ 2496 #define PPB_NVIC_ICER2_CLRENA_Msk (0xffffffffUL) /*!< PPB NVIC_ICER2: CLRENA (Bitfield-Mask: 0xffffffff) */ 2497 2498 /* ------------------------------- PPB_NVIC_ICER3 ------------------------------- */ 2499 #define PPB_NVIC_ICER3_CLRENA_Pos (0UL) /*!< PPB NVIC_ICER3: CLRENA (Bit 0) */ 2500 #define PPB_NVIC_ICER3_CLRENA_Msk (0xffffffffUL) /*!< PPB NVIC_ICER3: CLRENA (Bitfield-Mask: 0xffffffff) */ 2501 2502 /* ------------------------------- PPB_NVIC_ISPR0 ------------------------------- */ 2503 #define PPB_NVIC_ISPR0_SETPEND_Pos (0UL) /*!< PPB NVIC_ISPR0: SETPEND (Bit 0) */ 2504 #define PPB_NVIC_ISPR0_SETPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ISPR0: SETPEND (Bitfield-Mask: 0xffffffff) */ 2505 2506 /* ------------------------------- PPB_NVIC_ISPR1 ------------------------------- */ 2507 #define PPB_NVIC_ISPR1_SETPEND_Pos (0UL) /*!< PPB NVIC_ISPR1: SETPEND (Bit 0) */ 2508 #define PPB_NVIC_ISPR1_SETPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ISPR1: SETPEND (Bitfield-Mask: 0xffffffff) */ 2509 2510 /* ------------------------------- PPB_NVIC_ISPR2 ------------------------------- */ 2511 #define PPB_NVIC_ISPR2_SETPEND_Pos (0UL) /*!< PPB NVIC_ISPR2: SETPEND (Bit 0) */ 2512 #define PPB_NVIC_ISPR2_SETPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ISPR2: SETPEND (Bitfield-Mask: 0xffffffff) */ 2513 2514 /* ------------------------------- PPB_NVIC_ISPR3 ------------------------------- */ 2515 #define PPB_NVIC_ISPR3_SETPEND_Pos (0UL) /*!< PPB NVIC_ISPR3: SETPEND (Bit 0) */ 2516 #define PPB_NVIC_ISPR3_SETPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ISPR3: SETPEND (Bitfield-Mask: 0xffffffff) */ 2517 2518 /* ------------------------------- PPB_NVIC_ICPR0 ------------------------------- */ 2519 #define PPB_NVIC_ICPR0_CLRPEND_Pos (0UL) /*!< PPB NVIC_ICPR0: CLRPEND (Bit 0) */ 2520 #define PPB_NVIC_ICPR0_CLRPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ICPR0: CLRPEND (Bitfield-Mask: 0xffffffff) */ 2521 2522 /* ------------------------------- PPB_NVIC_ICPR1 ------------------------------- */ 2523 #define PPB_NVIC_ICPR1_CLRPEND_Pos (0UL) /*!< PPB NVIC_ICPR1: CLRPEND (Bit 0) */ 2524 #define PPB_NVIC_ICPR1_CLRPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ICPR1: CLRPEND (Bitfield-Mask: 0xffffffff) */ 2525 2526 /* ------------------------------- PPB_NVIC_ICPR2 ------------------------------- */ 2527 #define PPB_NVIC_ICPR2_CLRPEND_Pos (0UL) /*!< PPB NVIC_ICPR2: CLRPEND (Bit 0) */ 2528 #define PPB_NVIC_ICPR2_CLRPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ICPR2: CLRPEND (Bitfield-Mask: 0xffffffff) */ 2529 2530 /* ------------------------------- PPB_NVIC_ICPR3 ------------------------------- */ 2531 #define PPB_NVIC_ICPR3_CLRPEND_Pos (0UL) /*!< PPB NVIC_ICPR3: CLRPEND (Bit 0) */ 2532 #define PPB_NVIC_ICPR3_CLRPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ICPR3: CLRPEND (Bitfield-Mask: 0xffffffff) */ 2533 2534 /* ------------------------------- PPB_NVIC_IABR0 ------------------------------- */ 2535 #define PPB_NVIC_IABR0_ACTIVE_Pos (0UL) /*!< PPB NVIC_IABR0: ACTIVE (Bit 0) */ 2536 #define PPB_NVIC_IABR0_ACTIVE_Msk (0xffffffffUL) /*!< PPB NVIC_IABR0: ACTIVE (Bitfield-Mask: 0xffffffff) */ 2537 2538 /* ------------------------------- PPB_NVIC_IABR1 ------------------------------- */ 2539 #define PPB_NVIC_IABR1_ACTIVE_Pos (0UL) /*!< PPB NVIC_IABR1: ACTIVE (Bit 0) */ 2540 #define PPB_NVIC_IABR1_ACTIVE_Msk (0xffffffffUL) /*!< PPB NVIC_IABR1: ACTIVE (Bitfield-Mask: 0xffffffff) */ 2541 2542 /* ------------------------------- PPB_NVIC_IABR2 ------------------------------- */ 2543 #define PPB_NVIC_IABR2_ACTIVE_Pos (0UL) /*!< PPB NVIC_IABR2: ACTIVE (Bit 0) */ 2544 #define PPB_NVIC_IABR2_ACTIVE_Msk (0xffffffffUL) /*!< PPB NVIC_IABR2: ACTIVE (Bitfield-Mask: 0xffffffff) */ 2545 2546 /* ------------------------------- PPB_NVIC_IABR3 ------------------------------- */ 2547 #define PPB_NVIC_IABR3_ACTIVE_Pos (0UL) /*!< PPB NVIC_IABR3: ACTIVE (Bit 0) */ 2548 #define PPB_NVIC_IABR3_ACTIVE_Msk (0xffffffffUL) /*!< PPB NVIC_IABR3: ACTIVE (Bitfield-Mask: 0xffffffff) */ 2549 2550 /* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */ 2551 #define PPB_NVIC_IPR0_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR0: PRI_0 (Bit 0) */ 2552 #define PPB_NVIC_IPR0_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR0: PRI_0 (Bitfield-Mask: 0xff) */ 2553 #define PPB_NVIC_IPR0_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR0: PRI_1 (Bit 8) */ 2554 #define PPB_NVIC_IPR0_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR0: PRI_1 (Bitfield-Mask: 0xff) */ 2555 #define PPB_NVIC_IPR0_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR0: PRI_2 (Bit 16) */ 2556 #define PPB_NVIC_IPR0_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR0: PRI_2 (Bitfield-Mask: 0xff) */ 2557 #define PPB_NVIC_IPR0_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR0: PRI_3 (Bit 24) */ 2558 #define PPB_NVIC_IPR0_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR0: PRI_3 (Bitfield-Mask: 0xff) */ 2559 2560 /* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */ 2561 #define PPB_NVIC_IPR1_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR1: PRI_0 (Bit 0) */ 2562 #define PPB_NVIC_IPR1_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR1: PRI_0 (Bitfield-Mask: 0xff) */ 2563 #define PPB_NVIC_IPR1_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR1: PRI_1 (Bit 8) */ 2564 #define PPB_NVIC_IPR1_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR1: PRI_1 (Bitfield-Mask: 0xff) */ 2565 #define PPB_NVIC_IPR1_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR1: PRI_2 (Bit 16) */ 2566 #define PPB_NVIC_IPR1_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR1: PRI_2 (Bitfield-Mask: 0xff) */ 2567 #define PPB_NVIC_IPR1_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR1: PRI_3 (Bit 24) */ 2568 #define PPB_NVIC_IPR1_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR1: PRI_3 (Bitfield-Mask: 0xff) */ 2569 2570 /* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */ 2571 #define PPB_NVIC_IPR2_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR2: PRI_0 (Bit 0) */ 2572 #define PPB_NVIC_IPR2_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR2: PRI_0 (Bitfield-Mask: 0xff) */ 2573 #define PPB_NVIC_IPR2_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR2: PRI_1 (Bit 8) */ 2574 #define PPB_NVIC_IPR2_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR2: PRI_1 (Bitfield-Mask: 0xff) */ 2575 #define PPB_NVIC_IPR2_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR2: PRI_2 (Bit 16) */ 2576 #define PPB_NVIC_IPR2_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR2: PRI_2 (Bitfield-Mask: 0xff) */ 2577 #define PPB_NVIC_IPR2_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR2: PRI_3 (Bit 24) */ 2578 #define PPB_NVIC_IPR2_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR2: PRI_3 (Bitfield-Mask: 0xff) */ 2579 2580 /* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */ 2581 #define PPB_NVIC_IPR3_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR3: PRI_0 (Bit 0) */ 2582 #define PPB_NVIC_IPR3_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR3: PRI_0 (Bitfield-Mask: 0xff) */ 2583 #define PPB_NVIC_IPR3_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR3: PRI_1 (Bit 8) */ 2584 #define PPB_NVIC_IPR3_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR3: PRI_1 (Bitfield-Mask: 0xff) */ 2585 #define PPB_NVIC_IPR3_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR3: PRI_2 (Bit 16) */ 2586 #define PPB_NVIC_IPR3_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR3: PRI_2 (Bitfield-Mask: 0xff) */ 2587 #define PPB_NVIC_IPR3_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR3: PRI_3 (Bit 24) */ 2588 #define PPB_NVIC_IPR3_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR3: PRI_3 (Bitfield-Mask: 0xff) */ 2589 2590 /* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */ 2591 #define PPB_NVIC_IPR4_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR4: PRI_0 (Bit 0) */ 2592 #define PPB_NVIC_IPR4_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR4: PRI_0 (Bitfield-Mask: 0xff) */ 2593 #define PPB_NVIC_IPR4_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR4: PRI_1 (Bit 8) */ 2594 #define PPB_NVIC_IPR4_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR4: PRI_1 (Bitfield-Mask: 0xff) */ 2595 #define PPB_NVIC_IPR4_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR4: PRI_2 (Bit 16) */ 2596 #define PPB_NVIC_IPR4_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR4: PRI_2 (Bitfield-Mask: 0xff) */ 2597 #define PPB_NVIC_IPR4_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR4: PRI_3 (Bit 24) */ 2598 #define PPB_NVIC_IPR4_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR4: PRI_3 (Bitfield-Mask: 0xff) */ 2599 2600 /* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */ 2601 #define PPB_NVIC_IPR5_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR5: PRI_0 (Bit 0) */ 2602 #define PPB_NVIC_IPR5_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR5: PRI_0 (Bitfield-Mask: 0xff) */ 2603 #define PPB_NVIC_IPR5_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR5: PRI_1 (Bit 8) */ 2604 #define PPB_NVIC_IPR5_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR5: PRI_1 (Bitfield-Mask: 0xff) */ 2605 #define PPB_NVIC_IPR5_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR5: PRI_2 (Bit 16) */ 2606 #define PPB_NVIC_IPR5_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR5: PRI_2 (Bitfield-Mask: 0xff) */ 2607 #define PPB_NVIC_IPR5_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR5: PRI_3 (Bit 24) */ 2608 #define PPB_NVIC_IPR5_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR5: PRI_3 (Bitfield-Mask: 0xff) */ 2609 2610 /* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */ 2611 #define PPB_NVIC_IPR6_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR6: PRI_0 (Bit 0) */ 2612 #define PPB_NVIC_IPR6_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR6: PRI_0 (Bitfield-Mask: 0xff) */ 2613 #define PPB_NVIC_IPR6_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR6: PRI_1 (Bit 8) */ 2614 #define PPB_NVIC_IPR6_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR6: PRI_1 (Bitfield-Mask: 0xff) */ 2615 #define PPB_NVIC_IPR6_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR6: PRI_2 (Bit 16) */ 2616 #define PPB_NVIC_IPR6_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR6: PRI_2 (Bitfield-Mask: 0xff) */ 2617 #define PPB_NVIC_IPR6_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR6: PRI_3 (Bit 24) */ 2618 #define PPB_NVIC_IPR6_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR6: PRI_3 (Bitfield-Mask: 0xff) */ 2619 2620 /* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */ 2621 #define PPB_NVIC_IPR7_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR7: PRI_0 (Bit 0) */ 2622 #define PPB_NVIC_IPR7_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR7: PRI_0 (Bitfield-Mask: 0xff) */ 2623 #define PPB_NVIC_IPR7_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR7: PRI_1 (Bit 8) */ 2624 #define PPB_NVIC_IPR7_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR7: PRI_1 (Bitfield-Mask: 0xff) */ 2625 #define PPB_NVIC_IPR7_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR7: PRI_2 (Bit 16) */ 2626 #define PPB_NVIC_IPR7_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR7: PRI_2 (Bitfield-Mask: 0xff) */ 2627 #define PPB_NVIC_IPR7_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR7: PRI_3 (Bit 24) */ 2628 #define PPB_NVIC_IPR7_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR7: PRI_3 (Bitfield-Mask: 0xff) */ 2629 2630 /* -------------------------------- PPB_NVIC_IPR8 ------------------------------- */ 2631 #define PPB_NVIC_IPR8_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR8: PRI_0 (Bit 0) */ 2632 #define PPB_NVIC_IPR8_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR8: PRI_0 (Bitfield-Mask: 0xff) */ 2633 #define PPB_NVIC_IPR8_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR8: PRI_1 (Bit 8) */ 2634 #define PPB_NVIC_IPR8_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR8: PRI_1 (Bitfield-Mask: 0xff) */ 2635 #define PPB_NVIC_IPR8_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR8: PRI_2 (Bit 16) */ 2636 #define PPB_NVIC_IPR8_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR8: PRI_2 (Bitfield-Mask: 0xff) */ 2637 #define PPB_NVIC_IPR8_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR8: PRI_3 (Bit 24) */ 2638 #define PPB_NVIC_IPR8_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR8: PRI_3 (Bitfield-Mask: 0xff) */ 2639 2640 /* -------------------------------- PPB_NVIC_IPR9 ------------------------------- */ 2641 #define PPB_NVIC_IPR9_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR9: PRI_0 (Bit 0) */ 2642 #define PPB_NVIC_IPR9_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR9: PRI_0 (Bitfield-Mask: 0xff) */ 2643 #define PPB_NVIC_IPR9_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR9: PRI_1 (Bit 8) */ 2644 #define PPB_NVIC_IPR9_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR9: PRI_1 (Bitfield-Mask: 0xff) */ 2645 #define PPB_NVIC_IPR9_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR9: PRI_2 (Bit 16) */ 2646 #define PPB_NVIC_IPR9_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR9: PRI_2 (Bitfield-Mask: 0xff) */ 2647 #define PPB_NVIC_IPR9_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR9: PRI_3 (Bit 24) */ 2648 #define PPB_NVIC_IPR9_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR9: PRI_3 (Bitfield-Mask: 0xff) */ 2649 2650 /* ------------------------------- PPB_NVIC_IPR10 ------------------------------- */ 2651 #define PPB_NVIC_IPR10_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR10: PRI_0 (Bit 0) */ 2652 #define PPB_NVIC_IPR10_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR10: PRI_0 (Bitfield-Mask: 0xff) */ 2653 #define PPB_NVIC_IPR10_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR10: PRI_1 (Bit 8) */ 2654 #define PPB_NVIC_IPR10_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR10: PRI_1 (Bitfield-Mask: 0xff) */ 2655 #define PPB_NVIC_IPR10_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR10: PRI_2 (Bit 16) */ 2656 #define PPB_NVIC_IPR10_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR10: PRI_2 (Bitfield-Mask: 0xff) */ 2657 #define PPB_NVIC_IPR10_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR10: PRI_3 (Bit 24) */ 2658 #define PPB_NVIC_IPR10_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR10: PRI_3 (Bitfield-Mask: 0xff) */ 2659 2660 /* ------------------------------- PPB_NVIC_IPR11 ------------------------------- */ 2661 #define PPB_NVIC_IPR11_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR11: PRI_0 (Bit 0) */ 2662 #define PPB_NVIC_IPR11_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR11: PRI_0 (Bitfield-Mask: 0xff) */ 2663 #define PPB_NVIC_IPR11_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR11: PRI_1 (Bit 8) */ 2664 #define PPB_NVIC_IPR11_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR11: PRI_1 (Bitfield-Mask: 0xff) */ 2665 #define PPB_NVIC_IPR11_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR11: PRI_2 (Bit 16) */ 2666 #define PPB_NVIC_IPR11_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR11: PRI_2 (Bitfield-Mask: 0xff) */ 2667 #define PPB_NVIC_IPR11_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR11: PRI_3 (Bit 24) */ 2668 #define PPB_NVIC_IPR11_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR11: PRI_3 (Bitfield-Mask: 0xff) */ 2669 2670 /* ------------------------------- PPB_NVIC_IPR12 ------------------------------- */ 2671 #define PPB_NVIC_IPR12_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR12: PRI_0 (Bit 0) */ 2672 #define PPB_NVIC_IPR12_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR12: PRI_0 (Bitfield-Mask: 0xff) */ 2673 #define PPB_NVIC_IPR12_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR12: PRI_1 (Bit 8) */ 2674 #define PPB_NVIC_IPR12_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR12: PRI_1 (Bitfield-Mask: 0xff) */ 2675 #define PPB_NVIC_IPR12_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR12: PRI_2 (Bit 16) */ 2676 #define PPB_NVIC_IPR12_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR12: PRI_2 (Bitfield-Mask: 0xff) */ 2677 #define PPB_NVIC_IPR12_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR12: PRI_3 (Bit 24) */ 2678 #define PPB_NVIC_IPR12_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR12: PRI_3 (Bitfield-Mask: 0xff) */ 2679 2680 /* ------------------------------- PPB_NVIC_IPR13 ------------------------------- */ 2681 #define PPB_NVIC_IPR13_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR13: PRI_0 (Bit 0) */ 2682 #define PPB_NVIC_IPR13_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR13: PRI_0 (Bitfield-Mask: 0xff) */ 2683 #define PPB_NVIC_IPR13_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR13: PRI_1 (Bit 8) */ 2684 #define PPB_NVIC_IPR13_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR13: PRI_1 (Bitfield-Mask: 0xff) */ 2685 #define PPB_NVIC_IPR13_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR13: PRI_2 (Bit 16) */ 2686 #define PPB_NVIC_IPR13_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR13: PRI_2 (Bitfield-Mask: 0xff) */ 2687 #define PPB_NVIC_IPR13_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR13: PRI_3 (Bit 24) */ 2688 #define PPB_NVIC_IPR13_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR13: PRI_3 (Bitfield-Mask: 0xff) */ 2689 2690 /* ------------------------------- PPB_NVIC_IPR14 ------------------------------- */ 2691 #define PPB_NVIC_IPR14_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR14: PRI_0 (Bit 0) */ 2692 #define PPB_NVIC_IPR14_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR14: PRI_0 (Bitfield-Mask: 0xff) */ 2693 #define PPB_NVIC_IPR14_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR14: PRI_1 (Bit 8) */ 2694 #define PPB_NVIC_IPR14_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR14: PRI_1 (Bitfield-Mask: 0xff) */ 2695 #define PPB_NVIC_IPR14_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR14: PRI_2 (Bit 16) */ 2696 #define PPB_NVIC_IPR14_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR14: PRI_2 (Bitfield-Mask: 0xff) */ 2697 #define PPB_NVIC_IPR14_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR14: PRI_3 (Bit 24) */ 2698 #define PPB_NVIC_IPR14_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR14: PRI_3 (Bitfield-Mask: 0xff) */ 2699 2700 /* ------------------------------- PPB_NVIC_IPR15 ------------------------------- */ 2701 #define PPB_NVIC_IPR15_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR15: PRI_0 (Bit 0) */ 2702 #define PPB_NVIC_IPR15_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR15: PRI_0 (Bitfield-Mask: 0xff) */ 2703 #define PPB_NVIC_IPR15_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR15: PRI_1 (Bit 8) */ 2704 #define PPB_NVIC_IPR15_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR15: PRI_1 (Bitfield-Mask: 0xff) */ 2705 #define PPB_NVIC_IPR15_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR15: PRI_2 (Bit 16) */ 2706 #define PPB_NVIC_IPR15_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR15: PRI_2 (Bitfield-Mask: 0xff) */ 2707 #define PPB_NVIC_IPR15_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR15: PRI_3 (Bit 24) */ 2708 #define PPB_NVIC_IPR15_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR15: PRI_3 (Bitfield-Mask: 0xff) */ 2709 2710 /* ------------------------------- PPB_NVIC_IPR16 ------------------------------- */ 2711 #define PPB_NVIC_IPR16_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR16: PRI_0 (Bit 0) */ 2712 #define PPB_NVIC_IPR16_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR16: PRI_0 (Bitfield-Mask: 0xff) */ 2713 #define PPB_NVIC_IPR16_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR16: PRI_1 (Bit 8) */ 2714 #define PPB_NVIC_IPR16_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR16: PRI_1 (Bitfield-Mask: 0xff) */ 2715 #define PPB_NVIC_IPR16_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR16: PRI_2 (Bit 16) */ 2716 #define PPB_NVIC_IPR16_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR16: PRI_2 (Bitfield-Mask: 0xff) */ 2717 #define PPB_NVIC_IPR16_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR16: PRI_3 (Bit 24) */ 2718 #define PPB_NVIC_IPR16_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR16: PRI_3 (Bitfield-Mask: 0xff) */ 2719 2720 /* ------------------------------- PPB_NVIC_IPR17 ------------------------------- */ 2721 #define PPB_NVIC_IPR17_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR17: PRI_0 (Bit 0) */ 2722 #define PPB_NVIC_IPR17_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR17: PRI_0 (Bitfield-Mask: 0xff) */ 2723 #define PPB_NVIC_IPR17_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR17: PRI_1 (Bit 8) */ 2724 #define PPB_NVIC_IPR17_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR17: PRI_1 (Bitfield-Mask: 0xff) */ 2725 #define PPB_NVIC_IPR17_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR17: PRI_2 (Bit 16) */ 2726 #define PPB_NVIC_IPR17_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR17: PRI_2 (Bitfield-Mask: 0xff) */ 2727 #define PPB_NVIC_IPR17_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR17: PRI_3 (Bit 24) */ 2728 #define PPB_NVIC_IPR17_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR17: PRI_3 (Bitfield-Mask: 0xff) */ 2729 2730 /* ------------------------------- PPB_NVIC_IPR18 ------------------------------- */ 2731 #define PPB_NVIC_IPR18_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR18: PRI_0 (Bit 0) */ 2732 #define PPB_NVIC_IPR18_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR18: PRI_0 (Bitfield-Mask: 0xff) */ 2733 #define PPB_NVIC_IPR18_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR18: PRI_1 (Bit 8) */ 2734 #define PPB_NVIC_IPR18_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR18: PRI_1 (Bitfield-Mask: 0xff) */ 2735 #define PPB_NVIC_IPR18_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR18: PRI_2 (Bit 16) */ 2736 #define PPB_NVIC_IPR18_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR18: PRI_2 (Bitfield-Mask: 0xff) */ 2737 #define PPB_NVIC_IPR18_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR18: PRI_3 (Bit 24) */ 2738 #define PPB_NVIC_IPR18_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR18: PRI_3 (Bitfield-Mask: 0xff) */ 2739 2740 /* ------------------------------- PPB_NVIC_IPR19 ------------------------------- */ 2741 #define PPB_NVIC_IPR19_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR19: PRI_0 (Bit 0) */ 2742 #define PPB_NVIC_IPR19_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR19: PRI_0 (Bitfield-Mask: 0xff) */ 2743 #define PPB_NVIC_IPR19_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR19: PRI_1 (Bit 8) */ 2744 #define PPB_NVIC_IPR19_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR19: PRI_1 (Bitfield-Mask: 0xff) */ 2745 #define PPB_NVIC_IPR19_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR19: PRI_2 (Bit 16) */ 2746 #define PPB_NVIC_IPR19_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR19: PRI_2 (Bitfield-Mask: 0xff) */ 2747 #define PPB_NVIC_IPR19_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR19: PRI_3 (Bit 24) */ 2748 #define PPB_NVIC_IPR19_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR19: PRI_3 (Bitfield-Mask: 0xff) */ 2749 2750 /* ------------------------------- PPB_NVIC_IPR20 ------------------------------- */ 2751 #define PPB_NVIC_IPR20_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR20: PRI_0 (Bit 0) */ 2752 #define PPB_NVIC_IPR20_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR20: PRI_0 (Bitfield-Mask: 0xff) */ 2753 #define PPB_NVIC_IPR20_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR20: PRI_1 (Bit 8) */ 2754 #define PPB_NVIC_IPR20_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR20: PRI_1 (Bitfield-Mask: 0xff) */ 2755 #define PPB_NVIC_IPR20_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR20: PRI_2 (Bit 16) */ 2756 #define PPB_NVIC_IPR20_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR20: PRI_2 (Bitfield-Mask: 0xff) */ 2757 #define PPB_NVIC_IPR20_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR20: PRI_3 (Bit 24) */ 2758 #define PPB_NVIC_IPR20_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR20: PRI_3 (Bitfield-Mask: 0xff) */ 2759 2760 /* ------------------------------- PPB_NVIC_IPR21 ------------------------------- */ 2761 #define PPB_NVIC_IPR21_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR21: PRI_0 (Bit 0) */ 2762 #define PPB_NVIC_IPR21_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR21: PRI_0 (Bitfield-Mask: 0xff) */ 2763 #define PPB_NVIC_IPR21_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR21: PRI_1 (Bit 8) */ 2764 #define PPB_NVIC_IPR21_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR21: PRI_1 (Bitfield-Mask: 0xff) */ 2765 #define PPB_NVIC_IPR21_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR21: PRI_2 (Bit 16) */ 2766 #define PPB_NVIC_IPR21_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR21: PRI_2 (Bitfield-Mask: 0xff) */ 2767 #define PPB_NVIC_IPR21_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR21: PRI_3 (Bit 24) */ 2768 #define PPB_NVIC_IPR21_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR21: PRI_3 (Bitfield-Mask: 0xff) */ 2769 2770 /* ------------------------------- PPB_NVIC_IPR22 ------------------------------- */ 2771 #define PPB_NVIC_IPR22_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR22: PRI_0 (Bit 0) */ 2772 #define PPB_NVIC_IPR22_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR22: PRI_0 (Bitfield-Mask: 0xff) */ 2773 #define PPB_NVIC_IPR22_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR22: PRI_1 (Bit 8) */ 2774 #define PPB_NVIC_IPR22_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR22: PRI_1 (Bitfield-Mask: 0xff) */ 2775 #define PPB_NVIC_IPR22_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR22: PRI_2 (Bit 16) */ 2776 #define PPB_NVIC_IPR22_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR22: PRI_2 (Bitfield-Mask: 0xff) */ 2777 #define PPB_NVIC_IPR22_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR22: PRI_3 (Bit 24) */ 2778 #define PPB_NVIC_IPR22_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR22: PRI_3 (Bitfield-Mask: 0xff) */ 2779 2780 /* ------------------------------- PPB_NVIC_IPR23 ------------------------------- */ 2781 #define PPB_NVIC_IPR23_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR23: PRI_0 (Bit 0) */ 2782 #define PPB_NVIC_IPR23_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR23: PRI_0 (Bitfield-Mask: 0xff) */ 2783 #define PPB_NVIC_IPR23_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR23: PRI_1 (Bit 8) */ 2784 #define PPB_NVIC_IPR23_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR23: PRI_1 (Bitfield-Mask: 0xff) */ 2785 #define PPB_NVIC_IPR23_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR23: PRI_2 (Bit 16) */ 2786 #define PPB_NVIC_IPR23_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR23: PRI_2 (Bitfield-Mask: 0xff) */ 2787 #define PPB_NVIC_IPR23_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR23: PRI_3 (Bit 24) */ 2788 #define PPB_NVIC_IPR23_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR23: PRI_3 (Bitfield-Mask: 0xff) */ 2789 2790 /* ------------------------------- PPB_NVIC_IPR24 ------------------------------- */ 2791 #define PPB_NVIC_IPR24_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR24: PRI_0 (Bit 0) */ 2792 #define PPB_NVIC_IPR24_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR24: PRI_0 (Bitfield-Mask: 0xff) */ 2793 #define PPB_NVIC_IPR24_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR24: PRI_1 (Bit 8) */ 2794 #define PPB_NVIC_IPR24_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR24: PRI_1 (Bitfield-Mask: 0xff) */ 2795 #define PPB_NVIC_IPR24_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR24: PRI_2 (Bit 16) */ 2796 #define PPB_NVIC_IPR24_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR24: PRI_2 (Bitfield-Mask: 0xff) */ 2797 #define PPB_NVIC_IPR24_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR24: PRI_3 (Bit 24) */ 2798 #define PPB_NVIC_IPR24_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR24: PRI_3 (Bitfield-Mask: 0xff) */ 2799 2800 /* ------------------------------- PPB_NVIC_IPR25 ------------------------------- */ 2801 #define PPB_NVIC_IPR25_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR25: PRI_0 (Bit 0) */ 2802 #define PPB_NVIC_IPR25_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR25: PRI_0 (Bitfield-Mask: 0xff) */ 2803 #define PPB_NVIC_IPR25_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR25: PRI_1 (Bit 8) */ 2804 #define PPB_NVIC_IPR25_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR25: PRI_1 (Bitfield-Mask: 0xff) */ 2805 #define PPB_NVIC_IPR25_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR25: PRI_2 (Bit 16) */ 2806 #define PPB_NVIC_IPR25_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR25: PRI_2 (Bitfield-Mask: 0xff) */ 2807 #define PPB_NVIC_IPR25_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR25: PRI_3 (Bit 24) */ 2808 #define PPB_NVIC_IPR25_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR25: PRI_3 (Bitfield-Mask: 0xff) */ 2809 2810 /* ------------------------------- PPB_NVIC_IPR26 ------------------------------- */ 2811 #define PPB_NVIC_IPR26_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR26: PRI_0 (Bit 0) */ 2812 #define PPB_NVIC_IPR26_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR26: PRI_0 (Bitfield-Mask: 0xff) */ 2813 #define PPB_NVIC_IPR26_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR26: PRI_1 (Bit 8) */ 2814 #define PPB_NVIC_IPR26_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR26: PRI_1 (Bitfield-Mask: 0xff) */ 2815 #define PPB_NVIC_IPR26_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR26: PRI_2 (Bit 16) */ 2816 #define PPB_NVIC_IPR26_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR26: PRI_2 (Bitfield-Mask: 0xff) */ 2817 #define PPB_NVIC_IPR26_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR26: PRI_3 (Bit 24) */ 2818 #define PPB_NVIC_IPR26_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR26: PRI_3 (Bitfield-Mask: 0xff) */ 2819 2820 /* ------------------------------- PPB_NVIC_IPR27 ------------------------------- */ 2821 #define PPB_NVIC_IPR27_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR27: PRI_0 (Bit 0) */ 2822 #define PPB_NVIC_IPR27_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR27: PRI_0 (Bitfield-Mask: 0xff) */ 2823 #define PPB_NVIC_IPR27_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR27: PRI_1 (Bit 8) */ 2824 #define PPB_NVIC_IPR27_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR27: PRI_1 (Bitfield-Mask: 0xff) */ 2825 #define PPB_NVIC_IPR27_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR27: PRI_2 (Bit 16) */ 2826 #define PPB_NVIC_IPR27_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR27: PRI_2 (Bitfield-Mask: 0xff) */ 2827 #define PPB_NVIC_IPR27_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR27: PRI_3 (Bit 24) */ 2828 #define PPB_NVIC_IPR27_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR27: PRI_3 (Bitfield-Mask: 0xff) */ 2829 2830 /* ---------------------------------- PPB_CPUID --------------------------------- */ 2831 #define PPB_CPUID_Revision_Pos (0UL) /*!< PPB CPUID: Revision (Bit 0) */ 2832 #define PPB_CPUID_Revision_Msk (0xfUL) /*!< PPB CPUID: Revision (Bitfield-Mask: 0x0f) */ 2833 #define PPB_CPUID_PartNo_Pos (4UL) /*!< PPB CPUID: PartNo (Bit 4) */ 2834 #define PPB_CPUID_PartNo_Msk (0xfff0UL) /*!< PPB CPUID: PartNo (Bitfield-Mask: 0xfff) */ 2835 #define PPB_CPUID_Constant_Pos (16UL) /*!< PPB CPUID: Constant (Bit 16) */ 2836 #define PPB_CPUID_Constant_Msk (0xf0000UL) /*!< PPB CPUID: Constant (Bitfield-Mask: 0x0f) */ 2837 #define PPB_CPUID_Variant_Pos (20UL) /*!< PPB CPUID: Variant (Bit 20) */ 2838 #define PPB_CPUID_Variant_Msk (0xf00000UL) /*!< PPB CPUID: Variant (Bitfield-Mask: 0x0f) */ 2839 #define PPB_CPUID_Implementer_Pos (24UL) /*!< PPB CPUID: Implementer (Bit 24) */ 2840 #define PPB_CPUID_Implementer_Msk (0xff000000UL) /*!< PPB CPUID: Implementer (Bitfield-Mask: 0xff) */ 2841 2842 /* ---------------------------------- PPB_ICSR ---------------------------------- */ 2843 #define PPB_ICSR_VECTACTIVE_Pos (0UL) /*!< PPB ICSR: VECTACTIVE (Bit 0) */ 2844 #define PPB_ICSR_VECTACTIVE_Msk (0x1ffUL) /*!< PPB ICSR: VECTACTIVE (Bitfield-Mask: 0x1ff) */ 2845 #define PPB_ICSR_RETTOBASE_Pos (11UL) /*!< PPB ICSR: RETTOBASE (Bit 11) */ 2846 #define PPB_ICSR_RETTOBASE_Msk (0x800UL) /*!< PPB ICSR: RETTOBASE (Bitfield-Mask: 0x01) */ 2847 #define PPB_ICSR_VECTPENDING_Pos (12UL) /*!< PPB ICSR: VECTPENDING (Bit 12) */ 2848 #define PPB_ICSR_VECTPENDING_Msk (0x3f000UL) /*!< PPB ICSR: VECTPENDING (Bitfield-Mask: 0x3f) */ 2849 #define PPB_ICSR_ISRPENDING_Pos (22UL) /*!< PPB ICSR: ISRPENDING (Bit 22) */ 2850 #define PPB_ICSR_ISRPENDING_Msk (0x400000UL) /*!< PPB ICSR: ISRPENDING (Bitfield-Mask: 0x01) */ 2851 #define PPB_ICSR_PENDSTCLR_Pos (25UL) /*!< PPB ICSR: PENDSTCLR (Bit 25) */ 2852 #define PPB_ICSR_PENDSTCLR_Msk (0x2000000UL) /*!< PPB ICSR: PENDSTCLR (Bitfield-Mask: 0x01) */ 2853 #define PPB_ICSR_PENDSTSET_Pos (26UL) /*!< PPB ICSR: PENDSTSET (Bit 26) */ 2854 #define PPB_ICSR_PENDSTSET_Msk (0x4000000UL) /*!< PPB ICSR: PENDSTSET (Bitfield-Mask: 0x01) */ 2855 #define PPB_ICSR_PENDSVCLR_Pos (27UL) /*!< PPB ICSR: PENDSVCLR (Bit 27) */ 2856 #define PPB_ICSR_PENDSVCLR_Msk (0x8000000UL) /*!< PPB ICSR: PENDSVCLR (Bitfield-Mask: 0x01) */ 2857 #define PPB_ICSR_PENDSVSET_Pos (28UL) /*!< PPB ICSR: PENDSVSET (Bit 28) */ 2858 #define PPB_ICSR_PENDSVSET_Msk (0x10000000UL) /*!< PPB ICSR: PENDSVSET (Bitfield-Mask: 0x01) */ 2859 #define PPB_ICSR_NMIPENDSET_Pos (31UL) /*!< PPB ICSR: NMIPENDSET (Bit 31) */ 2860 #define PPB_ICSR_NMIPENDSET_Msk (0x80000000UL) /*!< PPB ICSR: NMIPENDSET (Bitfield-Mask: 0x01) */ 2861 2862 /* ---------------------------------- PPB_VTOR ---------------------------------- */ 2863 #define PPB_VTOR_TBLOFF_Pos (10UL) /*!< PPB VTOR: TBLOFF (Bit 10) */ 2864 #define PPB_VTOR_TBLOFF_Msk (0xfffffc00UL) /*!< PPB VTOR: TBLOFF (Bitfield-Mask: 0x3fffff) */ 2865 2866 /* ---------------------------------- PPB_AIRCR --------------------------------- */ 2867 #define PPB_AIRCR_VECTRESET_Pos (0UL) /*!< PPB AIRCR: VECTRESET (Bit 0) */ 2868 #define PPB_AIRCR_VECTRESET_Msk (0x1UL) /*!< PPB AIRCR: VECTRESET (Bitfield-Mask: 0x01) */ 2869 #define PPB_AIRCR_VECTCLRACTIVE_Pos (1UL) /*!< PPB AIRCR: VECTCLRACTIVE (Bit 1) */ 2870 #define PPB_AIRCR_VECTCLRACTIVE_Msk (0x2UL) /*!< PPB AIRCR: VECTCLRACTIVE (Bitfield-Mask: 0x01) */ 2871 #define PPB_AIRCR_SYSRESETREQ_Pos (2UL) /*!< PPB AIRCR: SYSRESETREQ (Bit 2) */ 2872 #define PPB_AIRCR_SYSRESETREQ_Msk (0x4UL) /*!< PPB AIRCR: SYSRESETREQ (Bitfield-Mask: 0x01) */ 2873 #define PPB_AIRCR_PRIGROUP_Pos (8UL) /*!< PPB AIRCR: PRIGROUP (Bit 8) */ 2874 #define PPB_AIRCR_PRIGROUP_Msk (0x700UL) /*!< PPB AIRCR: PRIGROUP (Bitfield-Mask: 0x07) */ 2875 #define PPB_AIRCR_ENDIANNESS_Pos (15UL) /*!< PPB AIRCR: ENDIANNESS (Bit 15) */ 2876 #define PPB_AIRCR_ENDIANNESS_Msk (0x8000UL) /*!< PPB AIRCR: ENDIANNESS (Bitfield-Mask: 0x01) */ 2877 #define PPB_AIRCR_VECTKEY_Pos (16UL) /*!< PPB AIRCR: VECTKEY (Bit 16) */ 2878 #define PPB_AIRCR_VECTKEY_Msk (0xffff0000UL) /*!< PPB AIRCR: VECTKEY (Bitfield-Mask: 0xffff) */ 2879 2880 /* ----------------------------------- PPB_SCR ---------------------------------- */ 2881 #define PPB_SCR_SLEEPONEXIT_Pos (1UL) /*!< PPB SCR: SLEEPONEXIT (Bit 1) */ 2882 #define PPB_SCR_SLEEPONEXIT_Msk (0x2UL) /*!< PPB SCR: SLEEPONEXIT (Bitfield-Mask: 0x01) */ 2883 #define PPB_SCR_SLEEPDEEP_Pos (2UL) /*!< PPB SCR: SLEEPDEEP (Bit 2) */ 2884 #define PPB_SCR_SLEEPDEEP_Msk (0x4UL) /*!< PPB SCR: SLEEPDEEP (Bitfield-Mask: 0x01) */ 2885 #define PPB_SCR_SEVONPEND_Pos (4UL) /*!< PPB SCR: SEVONPEND (Bit 4) */ 2886 #define PPB_SCR_SEVONPEND_Msk (0x10UL) /*!< PPB SCR: SEVONPEND (Bitfield-Mask: 0x01) */ 2887 2888 /* ----------------------------------- PPB_CCR ---------------------------------- */ 2889 #define PPB_CCR_NONBASETHRDENA_Pos (0UL) /*!< PPB CCR: NONBASETHRDENA (Bit 0) */ 2890 #define PPB_CCR_NONBASETHRDENA_Msk (0x1UL) /*!< PPB CCR: NONBASETHRDENA (Bitfield-Mask: 0x01) */ 2891 #define PPB_CCR_USERSETMPEND_Pos (1UL) /*!< PPB CCR: USERSETMPEND (Bit 1) */ 2892 #define PPB_CCR_USERSETMPEND_Msk (0x2UL) /*!< PPB CCR: USERSETMPEND (Bitfield-Mask: 0x01) */ 2893 #define PPB_CCR_UNALIGN_TRP_Pos (3UL) /*!< PPB CCR: UNALIGN_TRP (Bit 3) */ 2894 #define PPB_CCR_UNALIGN_TRP_Msk (0x8UL) /*!< PPB CCR: UNALIGN_TRP (Bitfield-Mask: 0x01) */ 2895 #define PPB_CCR_DIV_0_TRP_Pos (4UL) /*!< PPB CCR: DIV_0_TRP (Bit 4) */ 2896 #define PPB_CCR_DIV_0_TRP_Msk (0x10UL) /*!< PPB CCR: DIV_0_TRP (Bitfield-Mask: 0x01) */ 2897 #define PPB_CCR_BFHFNMIGN_Pos (8UL) /*!< PPB CCR: BFHFNMIGN (Bit 8) */ 2898 #define PPB_CCR_BFHFNMIGN_Msk (0x100UL) /*!< PPB CCR: BFHFNMIGN (Bitfield-Mask: 0x01) */ 2899 #define PPB_CCR_STKALIGN_Pos (9UL) /*!< PPB CCR: STKALIGN (Bit 9) */ 2900 #define PPB_CCR_STKALIGN_Msk (0x200UL) /*!< PPB CCR: STKALIGN (Bitfield-Mask: 0x01) */ 2901 2902 /* ---------------------------------- PPB_SHPR1 --------------------------------- */ 2903 #define PPB_SHPR1_PRI_4_Pos (0UL) /*!< PPB SHPR1: PRI_4 (Bit 0) */ 2904 #define PPB_SHPR1_PRI_4_Msk (0xffUL) /*!< PPB SHPR1: PRI_4 (Bitfield-Mask: 0xff) */ 2905 #define PPB_SHPR1_PRI_5_Pos (8UL) /*!< PPB SHPR1: PRI_5 (Bit 8) */ 2906 #define PPB_SHPR1_PRI_5_Msk (0xff00UL) /*!< PPB SHPR1: PRI_5 (Bitfield-Mask: 0xff) */ 2907 #define PPB_SHPR1_PRI_6_Pos (16UL) /*!< PPB SHPR1: PRI_6 (Bit 16) */ 2908 #define PPB_SHPR1_PRI_6_Msk (0xff0000UL) /*!< PPB SHPR1: PRI_6 (Bitfield-Mask: 0xff) */ 2909 2910 /* ---------------------------------- PPB_SHPR2 --------------------------------- */ 2911 #define PPB_SHPR2_PRI_11_Pos (24UL) /*!< PPB SHPR2: PRI_11 (Bit 24) */ 2912 #define PPB_SHPR2_PRI_11_Msk (0xff000000UL) /*!< PPB SHPR2: PRI_11 (Bitfield-Mask: 0xff) */ 2913 2914 /* ---------------------------------- PPB_SHPR3 --------------------------------- */ 2915 #define PPB_SHPR3_PRI_14_Pos (16UL) /*!< PPB SHPR3: PRI_14 (Bit 16) */ 2916 #define PPB_SHPR3_PRI_14_Msk (0xff0000UL) /*!< PPB SHPR3: PRI_14 (Bitfield-Mask: 0xff) */ 2917 #define PPB_SHPR3_PRI_15_Pos (24UL) /*!< PPB SHPR3: PRI_15 (Bit 24) */ 2918 #define PPB_SHPR3_PRI_15_Msk (0xff000000UL) /*!< PPB SHPR3: PRI_15 (Bitfield-Mask: 0xff) */ 2919 2920 /* ---------------------------------- PPB_SHCSR --------------------------------- */ 2921 #define PPB_SHCSR_MEMFAULTACT_Pos (0UL) /*!< PPB SHCSR: MEMFAULTACT (Bit 0) */ 2922 #define PPB_SHCSR_MEMFAULTACT_Msk (0x1UL) /*!< PPB SHCSR: MEMFAULTACT (Bitfield-Mask: 0x01) */ 2923 #define PPB_SHCSR_BUSFAULTACT_Pos (1UL) /*!< PPB SHCSR: BUSFAULTACT (Bit 1) */ 2924 #define PPB_SHCSR_BUSFAULTACT_Msk (0x2UL) /*!< PPB SHCSR: BUSFAULTACT (Bitfield-Mask: 0x01) */ 2925 #define PPB_SHCSR_USGFAULTACT_Pos (3UL) /*!< PPB SHCSR: USGFAULTACT (Bit 3) */ 2926 #define PPB_SHCSR_USGFAULTACT_Msk (0x8UL) /*!< PPB SHCSR: USGFAULTACT (Bitfield-Mask: 0x01) */ 2927 #define PPB_SHCSR_SVCALLACT_Pos (7UL) /*!< PPB SHCSR: SVCALLACT (Bit 7) */ 2928 #define PPB_SHCSR_SVCALLACT_Msk (0x80UL) /*!< PPB SHCSR: SVCALLACT (Bitfield-Mask: 0x01) */ 2929 #define PPB_SHCSR_MONITORACT_Pos (8UL) /*!< PPB SHCSR: MONITORACT (Bit 8) */ 2930 #define PPB_SHCSR_MONITORACT_Msk (0x100UL) /*!< PPB SHCSR: MONITORACT (Bitfield-Mask: 0x01) */ 2931 #define PPB_SHCSR_PENDSVACT_Pos (10UL) /*!< PPB SHCSR: PENDSVACT (Bit 10) */ 2932 #define PPB_SHCSR_PENDSVACT_Msk (0x400UL) /*!< PPB SHCSR: PENDSVACT (Bitfield-Mask: 0x01) */ 2933 #define PPB_SHCSR_SYSTICKACT_Pos (11UL) /*!< PPB SHCSR: SYSTICKACT (Bit 11) */ 2934 #define PPB_SHCSR_SYSTICKACT_Msk (0x800UL) /*!< PPB SHCSR: SYSTICKACT (Bitfield-Mask: 0x01) */ 2935 #define PPB_SHCSR_USGFAULTPENDED_Pos (12UL) /*!< PPB SHCSR: USGFAULTPENDED (Bit 12) */ 2936 #define PPB_SHCSR_USGFAULTPENDED_Msk (0x1000UL) /*!< PPB SHCSR: USGFAULTPENDED (Bitfield-Mask: 0x01) */ 2937 #define PPB_SHCSR_MEMFAULTPENDED_Pos (13UL) /*!< PPB SHCSR: MEMFAULTPENDED (Bit 13) */ 2938 #define PPB_SHCSR_MEMFAULTPENDED_Msk (0x2000UL) /*!< PPB SHCSR: MEMFAULTPENDED (Bitfield-Mask: 0x01) */ 2939 #define PPB_SHCSR_BUSFAULTPENDED_Pos (14UL) /*!< PPB SHCSR: BUSFAULTPENDED (Bit 14) */ 2940 #define PPB_SHCSR_BUSFAULTPENDED_Msk (0x4000UL) /*!< PPB SHCSR: BUSFAULTPENDED (Bitfield-Mask: 0x01) */ 2941 #define PPB_SHCSR_SVCALLPENDED_Pos (15UL) /*!< PPB SHCSR: SVCALLPENDED (Bit 15) */ 2942 #define PPB_SHCSR_SVCALLPENDED_Msk (0x8000UL) /*!< PPB SHCSR: SVCALLPENDED (Bitfield-Mask: 0x01) */ 2943 #define PPB_SHCSR_MEMFAULTENA_Pos (16UL) /*!< PPB SHCSR: MEMFAULTENA (Bit 16) */ 2944 #define PPB_SHCSR_MEMFAULTENA_Msk (0x10000UL) /*!< PPB SHCSR: MEMFAULTENA (Bitfield-Mask: 0x01) */ 2945 #define PPB_SHCSR_BUSFAULTENA_Pos (17UL) /*!< PPB SHCSR: BUSFAULTENA (Bit 17) */ 2946 #define PPB_SHCSR_BUSFAULTENA_Msk (0x20000UL) /*!< PPB SHCSR: BUSFAULTENA (Bitfield-Mask: 0x01) */ 2947 #define PPB_SHCSR_USGFAULTENA_Pos (18UL) /*!< PPB SHCSR: USGFAULTENA (Bit 18) */ 2948 #define PPB_SHCSR_USGFAULTENA_Msk (0x40000UL) /*!< PPB SHCSR: USGFAULTENA (Bitfield-Mask: 0x01) */ 2949 2950 /* ---------------------------------- PPB_CFSR ---------------------------------- */ 2951 #define PPB_CFSR_IACCVIOL_Pos (0UL) /*!< PPB CFSR: IACCVIOL (Bit 0) */ 2952 #define PPB_CFSR_IACCVIOL_Msk (0x1UL) /*!< PPB CFSR: IACCVIOL (Bitfield-Mask: 0x01) */ 2953 #define PPB_CFSR_DACCVIOL_Pos (1UL) /*!< PPB CFSR: DACCVIOL (Bit 1) */ 2954 #define PPB_CFSR_DACCVIOL_Msk (0x2UL) /*!< PPB CFSR: DACCVIOL (Bitfield-Mask: 0x01) */ 2955 #define PPB_CFSR_MUNSTKERR_Pos (3UL) /*!< PPB CFSR: MUNSTKERR (Bit 3) */ 2956 #define PPB_CFSR_MUNSTKERR_Msk (0x8UL) /*!< PPB CFSR: MUNSTKERR (Bitfield-Mask: 0x01) */ 2957 #define PPB_CFSR_MSTKERR_Pos (4UL) /*!< PPB CFSR: MSTKERR (Bit 4) */ 2958 #define PPB_CFSR_MSTKERR_Msk (0x10UL) /*!< PPB CFSR: MSTKERR (Bitfield-Mask: 0x01) */ 2959 #define PPB_CFSR_MLSPERR_Pos (5UL) /*!< PPB CFSR: MLSPERR (Bit 5) */ 2960 #define PPB_CFSR_MLSPERR_Msk (0x20UL) /*!< PPB CFSR: MLSPERR (Bitfield-Mask: 0x01) */ 2961 #define PPB_CFSR_MMARVALID_Pos (7UL) /*!< PPB CFSR: MMARVALID (Bit 7) */ 2962 #define PPB_CFSR_MMARVALID_Msk (0x80UL) /*!< PPB CFSR: MMARVALID (Bitfield-Mask: 0x01) */ 2963 #define PPB_CFSR_IBUSERR_Pos (8UL) /*!< PPB CFSR: IBUSERR (Bit 8) */ 2964 #define PPB_CFSR_IBUSERR_Msk (0x100UL) /*!< PPB CFSR: IBUSERR (Bitfield-Mask: 0x01) */ 2965 #define PPB_CFSR_PRECISERR_Pos (9UL) /*!< PPB CFSR: PRECISERR (Bit 9) */ 2966 #define PPB_CFSR_PRECISERR_Msk (0x200UL) /*!< PPB CFSR: PRECISERR (Bitfield-Mask: 0x01) */ 2967 #define PPB_CFSR_IMPRECISERR_Pos (10UL) /*!< PPB CFSR: IMPRECISERR (Bit 10) */ 2968 #define PPB_CFSR_IMPRECISERR_Msk (0x400UL) /*!< PPB CFSR: IMPRECISERR (Bitfield-Mask: 0x01) */ 2969 #define PPB_CFSR_UNSTKERR_Pos (11UL) /*!< PPB CFSR: UNSTKERR (Bit 11) */ 2970 #define PPB_CFSR_UNSTKERR_Msk (0x800UL) /*!< PPB CFSR: UNSTKERR (Bitfield-Mask: 0x01) */ 2971 #define PPB_CFSR_STKERR_Pos (12UL) /*!< PPB CFSR: STKERR (Bit 12) */ 2972 #define PPB_CFSR_STKERR_Msk (0x1000UL) /*!< PPB CFSR: STKERR (Bitfield-Mask: 0x01) */ 2973 #define PPB_CFSR_LSPERR_Pos (13UL) /*!< PPB CFSR: LSPERR (Bit 13) */ 2974 #define PPB_CFSR_LSPERR_Msk (0x2000UL) /*!< PPB CFSR: LSPERR (Bitfield-Mask: 0x01) */ 2975 #define PPB_CFSR_BFARVALID_Pos (15UL) /*!< PPB CFSR: BFARVALID (Bit 15) */ 2976 #define PPB_CFSR_BFARVALID_Msk (0x8000UL) /*!< PPB CFSR: BFARVALID (Bitfield-Mask: 0x01) */ 2977 #define PPB_CFSR_UNDEFINSTR_Pos (16UL) /*!< PPB CFSR: UNDEFINSTR (Bit 16) */ 2978 #define PPB_CFSR_UNDEFINSTR_Msk (0x10000UL) /*!< PPB CFSR: UNDEFINSTR (Bitfield-Mask: 0x01) */ 2979 #define PPB_CFSR_INVSTATE_Pos (17UL) /*!< PPB CFSR: INVSTATE (Bit 17) */ 2980 #define PPB_CFSR_INVSTATE_Msk (0x20000UL) /*!< PPB CFSR: INVSTATE (Bitfield-Mask: 0x01) */ 2981 #define PPB_CFSR_INVPC_Pos (18UL) /*!< PPB CFSR: INVPC (Bit 18) */ 2982 #define PPB_CFSR_INVPC_Msk (0x40000UL) /*!< PPB CFSR: INVPC (Bitfield-Mask: 0x01) */ 2983 #define PPB_CFSR_NOCP_Pos (19UL) /*!< PPB CFSR: NOCP (Bit 19) */ 2984 #define PPB_CFSR_NOCP_Msk (0x80000UL) /*!< PPB CFSR: NOCP (Bitfield-Mask: 0x01) */ 2985 #define PPB_CFSR_UNALIGNED_Pos (24UL) /*!< PPB CFSR: UNALIGNED (Bit 24) */ 2986 #define PPB_CFSR_UNALIGNED_Msk (0x1000000UL) /*!< PPB CFSR: UNALIGNED (Bitfield-Mask: 0x01) */ 2987 #define PPB_CFSR_DIVBYZERO_Pos (25UL) /*!< PPB CFSR: DIVBYZERO (Bit 25) */ 2988 #define PPB_CFSR_DIVBYZERO_Msk (0x2000000UL) /*!< PPB CFSR: DIVBYZERO (Bitfield-Mask: 0x01) */ 2989 2990 /* ---------------------------------- PPB_HFSR ---------------------------------- */ 2991 #define PPB_HFSR_VECTTBL_Pos (1UL) /*!< PPB HFSR: VECTTBL (Bit 1) */ 2992 #define PPB_HFSR_VECTTBL_Msk (0x2UL) /*!< PPB HFSR: VECTTBL (Bitfield-Mask: 0x01) */ 2993 #define PPB_HFSR_FORCED_Pos (30UL) /*!< PPB HFSR: FORCED (Bit 30) */ 2994 #define PPB_HFSR_FORCED_Msk (0x40000000UL) /*!< PPB HFSR: FORCED (Bitfield-Mask: 0x01) */ 2995 #define PPB_HFSR_DEBUGEVT_Pos (31UL) /*!< PPB HFSR: DEBUGEVT (Bit 31) */ 2996 #define PPB_HFSR_DEBUGEVT_Msk (0x80000000UL) /*!< PPB HFSR: DEBUGEVT (Bitfield-Mask: 0x01) */ 2997 2998 /* ---------------------------------- PPB_MMFAR --------------------------------- */ 2999 #define PPB_MMFAR_ADDRESS_Pos (0UL) /*!< PPB MMFAR: ADDRESS (Bit 0) */ 3000 #define PPB_MMFAR_ADDRESS_Msk (0xffffffffUL) /*!< PPB MMFAR: ADDRESS (Bitfield-Mask: 0xffffffff) */ 3001 3002 /* ---------------------------------- PPB_BFAR ---------------------------------- */ 3003 #define PPB_BFAR_ADDRESS_Pos (0UL) /*!< PPB BFAR: ADDRESS (Bit 0) */ 3004 #define PPB_BFAR_ADDRESS_Msk (0xffffffffUL) /*!< PPB BFAR: ADDRESS (Bitfield-Mask: 0xffffffff) */ 3005 3006 /* ---------------------------------- PPB_AFSR ---------------------------------- */ 3007 #define PPB_AFSR_VALUE_Pos (0UL) /*!< PPB AFSR: VALUE (Bit 0) */ 3008 #define PPB_AFSR_VALUE_Msk (0xffffffffUL) /*!< PPB AFSR: VALUE (Bitfield-Mask: 0xffffffff) */ 3009 3010 /* ---------------------------------- PPB_CPACR --------------------------------- */ 3011 #define PPB_CPACR_CP10_Pos (20UL) /*!< PPB CPACR: CP10 (Bit 20) */ 3012 #define PPB_CPACR_CP10_Msk (0x300000UL) /*!< PPB CPACR: CP10 (Bitfield-Mask: 0x03) */ 3013 #define PPB_CPACR_CP11_Pos (22UL) /*!< PPB CPACR: CP11 (Bit 22) */ 3014 #define PPB_CPACR_CP11_Msk (0xc00000UL) /*!< PPB CPACR: CP11 (Bitfield-Mask: 0x03) */ 3015 3016 /* -------------------------------- PPB_MPU_TYPE -------------------------------- */ 3017 #define PPB_MPU_TYPE_SEPARATE_Pos (0UL) /*!< PPB MPU_TYPE: SEPARATE (Bit 0) */ 3018 #define PPB_MPU_TYPE_SEPARATE_Msk (0x1UL) /*!< PPB MPU_TYPE: SEPARATE (Bitfield-Mask: 0x01) */ 3019 #define PPB_MPU_TYPE_DREGION_Pos (8UL) /*!< PPB MPU_TYPE: DREGION (Bit 8) */ 3020 #define PPB_MPU_TYPE_DREGION_Msk (0xff00UL) /*!< PPB MPU_TYPE: DREGION (Bitfield-Mask: 0xff) */ 3021 #define PPB_MPU_TYPE_IREGION_Pos (16UL) /*!< PPB MPU_TYPE: IREGION (Bit 16) */ 3022 #define PPB_MPU_TYPE_IREGION_Msk (0xff0000UL) /*!< PPB MPU_TYPE: IREGION (Bitfield-Mask: 0xff) */ 3023 3024 /* -------------------------------- PPB_MPU_CTRL -------------------------------- */ 3025 #define PPB_MPU_CTRL_ENABLE_Pos (0UL) /*!< PPB MPU_CTRL: ENABLE (Bit 0) */ 3026 #define PPB_MPU_CTRL_ENABLE_Msk (0x1UL) /*!< PPB MPU_CTRL: ENABLE (Bitfield-Mask: 0x01) */ 3027 #define PPB_MPU_CTRL_HFNMIENA_Pos (1UL) /*!< PPB MPU_CTRL: HFNMIENA (Bit 1) */ 3028 #define PPB_MPU_CTRL_HFNMIENA_Msk (0x2UL) /*!< PPB MPU_CTRL: HFNMIENA (Bitfield-Mask: 0x01) */ 3029 #define PPB_MPU_CTRL_PRIVDEFENA_Pos (2UL) /*!< PPB MPU_CTRL: PRIVDEFENA (Bit 2) */ 3030 #define PPB_MPU_CTRL_PRIVDEFENA_Msk (0x4UL) /*!< PPB MPU_CTRL: PRIVDEFENA (Bitfield-Mask: 0x01) */ 3031 3032 /* --------------------------------- PPB_MPU_RNR -------------------------------- */ 3033 #define PPB_MPU_RNR_REGION_Pos (0UL) /*!< PPB MPU_RNR: REGION (Bit 0) */ 3034 #define PPB_MPU_RNR_REGION_Msk (0xffUL) /*!< PPB MPU_RNR: REGION (Bitfield-Mask: 0xff) */ 3035 3036 /* -------------------------------- PPB_MPU_RBAR -------------------------------- */ 3037 #define PPB_MPU_RBAR_REGION_Pos (0UL) /*!< PPB MPU_RBAR: REGION (Bit 0) */ 3038 #define PPB_MPU_RBAR_REGION_Msk (0xfUL) /*!< PPB MPU_RBAR: REGION (Bitfield-Mask: 0x0f) */ 3039 #define PPB_MPU_RBAR_VALID_Pos (4UL) /*!< PPB MPU_RBAR: VALID (Bit 4) */ 3040 #define PPB_MPU_RBAR_VALID_Msk (0x10UL) /*!< PPB MPU_RBAR: VALID (Bitfield-Mask: 0x01) */ 3041 #define PPB_MPU_RBAR_ADDR_Pos (9UL) /*!< PPB MPU_RBAR: ADDR (Bit 9) */ 3042 #define PPB_MPU_RBAR_ADDR_Msk (0xfffffe00UL) /*!< PPB MPU_RBAR: ADDR (Bitfield-Mask: 0x7fffff) */ 3043 3044 /* -------------------------------- PPB_MPU_RASR -------------------------------- */ 3045 #define PPB_MPU_RASR_ENABLE_Pos (0UL) /*!< PPB MPU_RASR: ENABLE (Bit 0) */ 3046 #define PPB_MPU_RASR_ENABLE_Msk (0x1UL) /*!< PPB MPU_RASR: ENABLE (Bitfield-Mask: 0x01) */ 3047 #define PPB_MPU_RASR_SIZE_Pos (1UL) /*!< PPB MPU_RASR: SIZE (Bit 1) */ 3048 #define PPB_MPU_RASR_SIZE_Msk (0x3eUL) /*!< PPB MPU_RASR: SIZE (Bitfield-Mask: 0x1f) */ 3049 #define PPB_MPU_RASR_SRD_Pos (8UL) /*!< PPB MPU_RASR: SRD (Bit 8) */ 3050 #define PPB_MPU_RASR_SRD_Msk (0xff00UL) /*!< PPB MPU_RASR: SRD (Bitfield-Mask: 0xff) */ 3051 #define PPB_MPU_RASR_B_Pos (16UL) /*!< PPB MPU_RASR: B (Bit 16) */ 3052 #define PPB_MPU_RASR_B_Msk (0x10000UL) /*!< PPB MPU_RASR: B (Bitfield-Mask: 0x01) */ 3053 #define PPB_MPU_RASR_C_Pos (17UL) /*!< PPB MPU_RASR: C (Bit 17) */ 3054 #define PPB_MPU_RASR_C_Msk (0x20000UL) /*!< PPB MPU_RASR: C (Bitfield-Mask: 0x01) */ 3055 #define PPB_MPU_RASR_S_Pos (18UL) /*!< PPB MPU_RASR: S (Bit 18) */ 3056 #define PPB_MPU_RASR_S_Msk (0x40000UL) /*!< PPB MPU_RASR: S (Bitfield-Mask: 0x01) */ 3057 #define PPB_MPU_RASR_TEX_Pos (19UL) /*!< PPB MPU_RASR: TEX (Bit 19) */ 3058 #define PPB_MPU_RASR_TEX_Msk (0x380000UL) /*!< PPB MPU_RASR: TEX (Bitfield-Mask: 0x07) */ 3059 #define PPB_MPU_RASR_AP_Pos (24UL) /*!< PPB MPU_RASR: AP (Bit 24) */ 3060 #define PPB_MPU_RASR_AP_Msk (0x7000000UL) /*!< PPB MPU_RASR: AP (Bitfield-Mask: 0x07) */ 3061 #define PPB_MPU_RASR_XN_Pos (28UL) /*!< PPB MPU_RASR: XN (Bit 28) */ 3062 #define PPB_MPU_RASR_XN_Msk (0x10000000UL) /*!< PPB MPU_RASR: XN (Bitfield-Mask: 0x01) */ 3063 3064 /* ------------------------------- PPB_MPU_RBAR_A1 ------------------------------ */ 3065 #define PPB_MPU_RBAR_A1_REGION_Pos (0UL) /*!< PPB MPU_RBAR_A1: REGION (Bit 0) */ 3066 #define PPB_MPU_RBAR_A1_REGION_Msk (0xfUL) /*!< PPB MPU_RBAR_A1: REGION (Bitfield-Mask: 0x0f) */ 3067 #define PPB_MPU_RBAR_A1_VALID_Pos (4UL) /*!< PPB MPU_RBAR_A1: VALID (Bit 4) */ 3068 #define PPB_MPU_RBAR_A1_VALID_Msk (0x10UL) /*!< PPB MPU_RBAR_A1: VALID (Bitfield-Mask: 0x01) */ 3069 #define PPB_MPU_RBAR_A1_ADDR_Pos (9UL) /*!< PPB MPU_RBAR_A1: ADDR (Bit 9) */ 3070 #define PPB_MPU_RBAR_A1_ADDR_Msk (0xfffffe00UL) /*!< PPB MPU_RBAR_A1: ADDR (Bitfield-Mask: 0x7fffff) */ 3071 3072 /* ------------------------------- PPB_MPU_RASR_A1 ------------------------------ */ 3073 #define PPB_MPU_RASR_A1_ENABLE_Pos (0UL) /*!< PPB MPU_RASR_A1: ENABLE (Bit 0) */ 3074 #define PPB_MPU_RASR_A1_ENABLE_Msk (0x1UL) /*!< PPB MPU_RASR_A1: ENABLE (Bitfield-Mask: 0x01) */ 3075 #define PPB_MPU_RASR_A1_SIZE_Pos (1UL) /*!< PPB MPU_RASR_A1: SIZE (Bit 1) */ 3076 #define PPB_MPU_RASR_A1_SIZE_Msk (0x3eUL) /*!< PPB MPU_RASR_A1: SIZE (Bitfield-Mask: 0x1f) */ 3077 #define PPB_MPU_RASR_A1_SRD_Pos (8UL) /*!< PPB MPU_RASR_A1: SRD (Bit 8) */ 3078 #define PPB_MPU_RASR_A1_SRD_Msk (0xff00UL) /*!< PPB MPU_RASR_A1: SRD (Bitfield-Mask: 0xff) */ 3079 #define PPB_MPU_RASR_A1_B_Pos (16UL) /*!< PPB MPU_RASR_A1: B (Bit 16) */ 3080 #define PPB_MPU_RASR_A1_B_Msk (0x10000UL) /*!< PPB MPU_RASR_A1: B (Bitfield-Mask: 0x01) */ 3081 #define PPB_MPU_RASR_A1_C_Pos (17UL) /*!< PPB MPU_RASR_A1: C (Bit 17) */ 3082 #define PPB_MPU_RASR_A1_C_Msk (0x20000UL) /*!< PPB MPU_RASR_A1: C (Bitfield-Mask: 0x01) */ 3083 #define PPB_MPU_RASR_A1_S_Pos (18UL) /*!< PPB MPU_RASR_A1: S (Bit 18) */ 3084 #define PPB_MPU_RASR_A1_S_Msk (0x40000UL) /*!< PPB MPU_RASR_A1: S (Bitfield-Mask: 0x01) */ 3085 #define PPB_MPU_RASR_A1_TEX_Pos (19UL) /*!< PPB MPU_RASR_A1: TEX (Bit 19) */ 3086 #define PPB_MPU_RASR_A1_TEX_Msk (0x380000UL) /*!< PPB MPU_RASR_A1: TEX (Bitfield-Mask: 0x07) */ 3087 #define PPB_MPU_RASR_A1_AP_Pos (24UL) /*!< PPB MPU_RASR_A1: AP (Bit 24) */ 3088 #define PPB_MPU_RASR_A1_AP_Msk (0x7000000UL) /*!< PPB MPU_RASR_A1: AP (Bitfield-Mask: 0x07) */ 3089 #define PPB_MPU_RASR_A1_XN_Pos (28UL) /*!< PPB MPU_RASR_A1: XN (Bit 28) */ 3090 #define PPB_MPU_RASR_A1_XN_Msk (0x10000000UL) /*!< PPB MPU_RASR_A1: XN (Bitfield-Mask: 0x01) */ 3091 3092 /* ------------------------------- PPB_MPU_RBAR_A2 ------------------------------ */ 3093 #define PPB_MPU_RBAR_A2_REGION_Pos (0UL) /*!< PPB MPU_RBAR_A2: REGION (Bit 0) */ 3094 #define PPB_MPU_RBAR_A2_REGION_Msk (0xfUL) /*!< PPB MPU_RBAR_A2: REGION (Bitfield-Mask: 0x0f) */ 3095 #define PPB_MPU_RBAR_A2_VALID_Pos (4UL) /*!< PPB MPU_RBAR_A2: VALID (Bit 4) */ 3096 #define PPB_MPU_RBAR_A2_VALID_Msk (0x10UL) /*!< PPB MPU_RBAR_A2: VALID (Bitfield-Mask: 0x01) */ 3097 #define PPB_MPU_RBAR_A2_ADDR_Pos (9UL) /*!< PPB MPU_RBAR_A2: ADDR (Bit 9) */ 3098 #define PPB_MPU_RBAR_A2_ADDR_Msk (0xfffffe00UL) /*!< PPB MPU_RBAR_A2: ADDR (Bitfield-Mask: 0x7fffff) */ 3099 3100 /* ------------------------------- PPB_MPU_RASR_A2 ------------------------------ */ 3101 #define PPB_MPU_RASR_A2_ENABLE_Pos (0UL) /*!< PPB MPU_RASR_A2: ENABLE (Bit 0) */ 3102 #define PPB_MPU_RASR_A2_ENABLE_Msk (0x1UL) /*!< PPB MPU_RASR_A2: ENABLE (Bitfield-Mask: 0x01) */ 3103 #define PPB_MPU_RASR_A2_SIZE_Pos (1UL) /*!< PPB MPU_RASR_A2: SIZE (Bit 1) */ 3104 #define PPB_MPU_RASR_A2_SIZE_Msk (0x3eUL) /*!< PPB MPU_RASR_A2: SIZE (Bitfield-Mask: 0x1f) */ 3105 #define PPB_MPU_RASR_A2_SRD_Pos (8UL) /*!< PPB MPU_RASR_A2: SRD (Bit 8) */ 3106 #define PPB_MPU_RASR_A2_SRD_Msk (0xff00UL) /*!< PPB MPU_RASR_A2: SRD (Bitfield-Mask: 0xff) */ 3107 #define PPB_MPU_RASR_A2_B_Pos (16UL) /*!< PPB MPU_RASR_A2: B (Bit 16) */ 3108 #define PPB_MPU_RASR_A2_B_Msk (0x10000UL) /*!< PPB MPU_RASR_A2: B (Bitfield-Mask: 0x01) */ 3109 #define PPB_MPU_RASR_A2_C_Pos (17UL) /*!< PPB MPU_RASR_A2: C (Bit 17) */ 3110 #define PPB_MPU_RASR_A2_C_Msk (0x20000UL) /*!< PPB MPU_RASR_A2: C (Bitfield-Mask: 0x01) */ 3111 #define PPB_MPU_RASR_A2_S_Pos (18UL) /*!< PPB MPU_RASR_A2: S (Bit 18) */ 3112 #define PPB_MPU_RASR_A2_S_Msk (0x40000UL) /*!< PPB MPU_RASR_A2: S (Bitfield-Mask: 0x01) */ 3113 #define PPB_MPU_RASR_A2_TEX_Pos (19UL) /*!< PPB MPU_RASR_A2: TEX (Bit 19) */ 3114 #define PPB_MPU_RASR_A2_TEX_Msk (0x380000UL) /*!< PPB MPU_RASR_A2: TEX (Bitfield-Mask: 0x07) */ 3115 #define PPB_MPU_RASR_A2_AP_Pos (24UL) /*!< PPB MPU_RASR_A2: AP (Bit 24) */ 3116 #define PPB_MPU_RASR_A2_AP_Msk (0x7000000UL) /*!< PPB MPU_RASR_A2: AP (Bitfield-Mask: 0x07) */ 3117 #define PPB_MPU_RASR_A2_XN_Pos (28UL) /*!< PPB MPU_RASR_A2: XN (Bit 28) */ 3118 #define PPB_MPU_RASR_A2_XN_Msk (0x10000000UL) /*!< PPB MPU_RASR_A2: XN (Bitfield-Mask: 0x01) */ 3119 3120 /* ------------------------------- PPB_MPU_RBAR_A3 ------------------------------ */ 3121 #define PPB_MPU_RBAR_A3_REGION_Pos (0UL) /*!< PPB MPU_RBAR_A3: REGION (Bit 0) */ 3122 #define PPB_MPU_RBAR_A3_REGION_Msk (0xfUL) /*!< PPB MPU_RBAR_A3: REGION (Bitfield-Mask: 0x0f) */ 3123 #define PPB_MPU_RBAR_A3_VALID_Pos (4UL) /*!< PPB MPU_RBAR_A3: VALID (Bit 4) */ 3124 #define PPB_MPU_RBAR_A3_VALID_Msk (0x10UL) /*!< PPB MPU_RBAR_A3: VALID (Bitfield-Mask: 0x01) */ 3125 #define PPB_MPU_RBAR_A3_ADDR_Pos (9UL) /*!< PPB MPU_RBAR_A3: ADDR (Bit 9) */ 3126 #define PPB_MPU_RBAR_A3_ADDR_Msk (0xfffffe00UL) /*!< PPB MPU_RBAR_A3: ADDR (Bitfield-Mask: 0x7fffff) */ 3127 3128 /* ------------------------------- PPB_MPU_RASR_A3 ------------------------------ */ 3129 #define PPB_MPU_RASR_A3_ENABLE_Pos (0UL) /*!< PPB MPU_RASR_A3: ENABLE (Bit 0) */ 3130 #define PPB_MPU_RASR_A3_ENABLE_Msk (0x1UL) /*!< PPB MPU_RASR_A3: ENABLE (Bitfield-Mask: 0x01) */ 3131 #define PPB_MPU_RASR_A3_SIZE_Pos (1UL) /*!< PPB MPU_RASR_A3: SIZE (Bit 1) */ 3132 #define PPB_MPU_RASR_A3_SIZE_Msk (0x3eUL) /*!< PPB MPU_RASR_A3: SIZE (Bitfield-Mask: 0x1f) */ 3133 #define PPB_MPU_RASR_A3_SRD_Pos (8UL) /*!< PPB MPU_RASR_A3: SRD (Bit 8) */ 3134 #define PPB_MPU_RASR_A3_SRD_Msk (0xff00UL) /*!< PPB MPU_RASR_A3: SRD (Bitfield-Mask: 0xff) */ 3135 #define PPB_MPU_RASR_A3_B_Pos (16UL) /*!< PPB MPU_RASR_A3: B (Bit 16) */ 3136 #define PPB_MPU_RASR_A3_B_Msk (0x10000UL) /*!< PPB MPU_RASR_A3: B (Bitfield-Mask: 0x01) */ 3137 #define PPB_MPU_RASR_A3_C_Pos (17UL) /*!< PPB MPU_RASR_A3: C (Bit 17) */ 3138 #define PPB_MPU_RASR_A3_C_Msk (0x20000UL) /*!< PPB MPU_RASR_A3: C (Bitfield-Mask: 0x01) */ 3139 #define PPB_MPU_RASR_A3_S_Pos (18UL) /*!< PPB MPU_RASR_A3: S (Bit 18) */ 3140 #define PPB_MPU_RASR_A3_S_Msk (0x40000UL) /*!< PPB MPU_RASR_A3: S (Bitfield-Mask: 0x01) */ 3141 #define PPB_MPU_RASR_A3_TEX_Pos (19UL) /*!< PPB MPU_RASR_A3: TEX (Bit 19) */ 3142 #define PPB_MPU_RASR_A3_TEX_Msk (0x380000UL) /*!< PPB MPU_RASR_A3: TEX (Bitfield-Mask: 0x07) */ 3143 #define PPB_MPU_RASR_A3_AP_Pos (24UL) /*!< PPB MPU_RASR_A3: AP (Bit 24) */ 3144 #define PPB_MPU_RASR_A3_AP_Msk (0x7000000UL) /*!< PPB MPU_RASR_A3: AP (Bitfield-Mask: 0x07) */ 3145 #define PPB_MPU_RASR_A3_XN_Pos (28UL) /*!< PPB MPU_RASR_A3: XN (Bit 28) */ 3146 #define PPB_MPU_RASR_A3_XN_Msk (0x10000000UL) /*!< PPB MPU_RASR_A3: XN (Bitfield-Mask: 0x01) */ 3147 3148 /* ---------------------------------- PPB_STIR ---------------------------------- */ 3149 #define PPB_STIR_INTID_Pos (0UL) /*!< PPB STIR: INTID (Bit 0) */ 3150 #define PPB_STIR_INTID_Msk (0x1ffUL) /*!< PPB STIR: INTID (Bitfield-Mask: 0x1ff) */ 3151 3152 /* ---------------------------------- PPB_FPCCR --------------------------------- */ 3153 #define PPB_FPCCR_LSPACT_Pos (0UL) /*!< PPB FPCCR: LSPACT (Bit 0) */ 3154 #define PPB_FPCCR_LSPACT_Msk (0x1UL) /*!< PPB FPCCR: LSPACT (Bitfield-Mask: 0x01) */ 3155 #define PPB_FPCCR_USER_Pos (1UL) /*!< PPB FPCCR: USER (Bit 1) */ 3156 #define PPB_FPCCR_USER_Msk (0x2UL) /*!< PPB FPCCR: USER (Bitfield-Mask: 0x01) */ 3157 #define PPB_FPCCR_THREAD_Pos (3UL) /*!< PPB FPCCR: THREAD (Bit 3) */ 3158 #define PPB_FPCCR_THREAD_Msk (0x8UL) /*!< PPB FPCCR: THREAD (Bitfield-Mask: 0x01) */ 3159 #define PPB_FPCCR_HFRDY_Pos (4UL) /*!< PPB FPCCR: HFRDY (Bit 4) */ 3160 #define PPB_FPCCR_HFRDY_Msk (0x10UL) /*!< PPB FPCCR: HFRDY (Bitfield-Mask: 0x01) */ 3161 #define PPB_FPCCR_MMRDY_Pos (5UL) /*!< PPB FPCCR: MMRDY (Bit 5) */ 3162 #define PPB_FPCCR_MMRDY_Msk (0x20UL) /*!< PPB FPCCR: MMRDY (Bitfield-Mask: 0x01) */ 3163 #define PPB_FPCCR_BFRDY_Pos (6UL) /*!< PPB FPCCR: BFRDY (Bit 6) */ 3164 #define PPB_FPCCR_BFRDY_Msk (0x40UL) /*!< PPB FPCCR: BFRDY (Bitfield-Mask: 0x01) */ 3165 #define PPB_FPCCR_MONRDY_Pos (8UL) /*!< PPB FPCCR: MONRDY (Bit 8) */ 3166 #define PPB_FPCCR_MONRDY_Msk (0x100UL) /*!< PPB FPCCR: MONRDY (Bitfield-Mask: 0x01) */ 3167 #define PPB_FPCCR_LSPEN_Pos (30UL) /*!< PPB FPCCR: LSPEN (Bit 30) */ 3168 #define PPB_FPCCR_LSPEN_Msk (0x40000000UL) /*!< PPB FPCCR: LSPEN (Bitfield-Mask: 0x01) */ 3169 #define PPB_FPCCR_ASPEN_Pos (31UL) /*!< PPB FPCCR: ASPEN (Bit 31) */ 3170 #define PPB_FPCCR_ASPEN_Msk (0x80000000UL) /*!< PPB FPCCR: ASPEN (Bitfield-Mask: 0x01) */ 3171 3172 /* ---------------------------------- PPB_FPCAR --------------------------------- */ 3173 #define PPB_FPCAR_ADDRESS_Pos (3UL) /*!< PPB FPCAR: ADDRESS (Bit 3) */ 3174 #define PPB_FPCAR_ADDRESS_Msk (0xfffffff8UL) /*!< PPB FPCAR: ADDRESS (Bitfield-Mask: 0x1fffffff) */ 3175 3176 /* --------------------------------- PPB_FPDSCR --------------------------------- */ 3177 #define PPB_FPDSCR_RMode_Pos (22UL) /*!< PPB FPDSCR: RMode (Bit 22) */ 3178 #define PPB_FPDSCR_RMode_Msk (0xc00000UL) /*!< PPB FPDSCR: RMode (Bitfield-Mask: 0x03) */ 3179 #define PPB_FPDSCR_FZ_Pos (24UL) /*!< PPB FPDSCR: FZ (Bit 24) */ 3180 #define PPB_FPDSCR_FZ_Msk (0x1000000UL) /*!< PPB FPDSCR: FZ (Bitfield-Mask: 0x01) */ 3181 #define PPB_FPDSCR_DN_Pos (25UL) /*!< PPB FPDSCR: DN (Bit 25) */ 3182 #define PPB_FPDSCR_DN_Msk (0x2000000UL) /*!< PPB FPDSCR: DN (Bitfield-Mask: 0x01) */ 3183 #define PPB_FPDSCR_AHP_Pos (26UL) /*!< PPB FPDSCR: AHP (Bit 26) */ 3184 #define PPB_FPDSCR_AHP_Msk (0x4000000UL) /*!< PPB FPDSCR: AHP (Bitfield-Mask: 0x01) */ 3185 3186 3187 /* ================================================================================ */ 3188 /* ================ struct 'DLR' Position & Mask ================ */ 3189 /* ================================================================================ */ 3190 3191 3192 /* --------------------------------- DLR_OVRSTAT -------------------------------- */ 3193 #define DLR_OVRSTAT_LN0_Pos (0UL) /*!< DLR OVRSTAT: LN0 (Bit 0) */ 3194 #define DLR_OVRSTAT_LN0_Msk (0x1UL) /*!< DLR OVRSTAT: LN0 (Bitfield-Mask: 0x01) */ 3195 #define DLR_OVRSTAT_LN1_Pos (1UL) /*!< DLR OVRSTAT: LN1 (Bit 1) */ 3196 #define DLR_OVRSTAT_LN1_Msk (0x2UL) /*!< DLR OVRSTAT: LN1 (Bitfield-Mask: 0x01) */ 3197 #define DLR_OVRSTAT_LN2_Pos (2UL) /*!< DLR OVRSTAT: LN2 (Bit 2) */ 3198 #define DLR_OVRSTAT_LN2_Msk (0x4UL) /*!< DLR OVRSTAT: LN2 (Bitfield-Mask: 0x01) */ 3199 #define DLR_OVRSTAT_LN3_Pos (3UL) /*!< DLR OVRSTAT: LN3 (Bit 3) */ 3200 #define DLR_OVRSTAT_LN3_Msk (0x8UL) /*!< DLR OVRSTAT: LN3 (Bitfield-Mask: 0x01) */ 3201 #define DLR_OVRSTAT_LN4_Pos (4UL) /*!< DLR OVRSTAT: LN4 (Bit 4) */ 3202 #define DLR_OVRSTAT_LN4_Msk (0x10UL) /*!< DLR OVRSTAT: LN4 (Bitfield-Mask: 0x01) */ 3203 #define DLR_OVRSTAT_LN5_Pos (5UL) /*!< DLR OVRSTAT: LN5 (Bit 5) */ 3204 #define DLR_OVRSTAT_LN5_Msk (0x20UL) /*!< DLR OVRSTAT: LN5 (Bitfield-Mask: 0x01) */ 3205 #define DLR_OVRSTAT_LN6_Pos (6UL) /*!< DLR OVRSTAT: LN6 (Bit 6) */ 3206 #define DLR_OVRSTAT_LN6_Msk (0x40UL) /*!< DLR OVRSTAT: LN6 (Bitfield-Mask: 0x01) */ 3207 #define DLR_OVRSTAT_LN7_Pos (7UL) /*!< DLR OVRSTAT: LN7 (Bit 7) */ 3208 #define DLR_OVRSTAT_LN7_Msk (0x80UL) /*!< DLR OVRSTAT: LN7 (Bitfield-Mask: 0x01) */ 3209 #define DLR_OVRSTAT_LN8_Pos (8UL) /*!< DLR OVRSTAT: LN8 (Bit 8) */ 3210 #define DLR_OVRSTAT_LN8_Msk (0x100UL) /*!< DLR OVRSTAT: LN8 (Bitfield-Mask: 0x01) */ 3211 #define DLR_OVRSTAT_LN9_Pos (9UL) /*!< DLR OVRSTAT: LN9 (Bit 9) */ 3212 #define DLR_OVRSTAT_LN9_Msk (0x200UL) /*!< DLR OVRSTAT: LN9 (Bitfield-Mask: 0x01) */ 3213 #define DLR_OVRSTAT_LN10_Pos (10UL) /*!< DLR OVRSTAT: LN10 (Bit 10) */ 3214 #define DLR_OVRSTAT_LN10_Msk (0x400UL) /*!< DLR OVRSTAT: LN10 (Bitfield-Mask: 0x01) */ 3215 #define DLR_OVRSTAT_LN11_Pos (11UL) /*!< DLR OVRSTAT: LN11 (Bit 11) */ 3216 #define DLR_OVRSTAT_LN11_Msk (0x800UL) /*!< DLR OVRSTAT: LN11 (Bitfield-Mask: 0x01) */ 3217 3218 /* --------------------------------- DLR_OVRCLR --------------------------------- */ 3219 #define DLR_OVRCLR_LN0_Pos (0UL) /*!< DLR OVRCLR: LN0 (Bit 0) */ 3220 #define DLR_OVRCLR_LN0_Msk (0x1UL) /*!< DLR OVRCLR: LN0 (Bitfield-Mask: 0x01) */ 3221 #define DLR_OVRCLR_LN1_Pos (1UL) /*!< DLR OVRCLR: LN1 (Bit 1) */ 3222 #define DLR_OVRCLR_LN1_Msk (0x2UL) /*!< DLR OVRCLR: LN1 (Bitfield-Mask: 0x01) */ 3223 #define DLR_OVRCLR_LN2_Pos (2UL) /*!< DLR OVRCLR: LN2 (Bit 2) */ 3224 #define DLR_OVRCLR_LN2_Msk (0x4UL) /*!< DLR OVRCLR: LN2 (Bitfield-Mask: 0x01) */ 3225 #define DLR_OVRCLR_LN3_Pos (3UL) /*!< DLR OVRCLR: LN3 (Bit 3) */ 3226 #define DLR_OVRCLR_LN3_Msk (0x8UL) /*!< DLR OVRCLR: LN3 (Bitfield-Mask: 0x01) */ 3227 #define DLR_OVRCLR_LN4_Pos (4UL) /*!< DLR OVRCLR: LN4 (Bit 4) */ 3228 #define DLR_OVRCLR_LN4_Msk (0x10UL) /*!< DLR OVRCLR: LN4 (Bitfield-Mask: 0x01) */ 3229 #define DLR_OVRCLR_LN5_Pos (5UL) /*!< DLR OVRCLR: LN5 (Bit 5) */ 3230 #define DLR_OVRCLR_LN5_Msk (0x20UL) /*!< DLR OVRCLR: LN5 (Bitfield-Mask: 0x01) */ 3231 #define DLR_OVRCLR_LN6_Pos (6UL) /*!< DLR OVRCLR: LN6 (Bit 6) */ 3232 #define DLR_OVRCLR_LN6_Msk (0x40UL) /*!< DLR OVRCLR: LN6 (Bitfield-Mask: 0x01) */ 3233 #define DLR_OVRCLR_LN7_Pos (7UL) /*!< DLR OVRCLR: LN7 (Bit 7) */ 3234 #define DLR_OVRCLR_LN7_Msk (0x80UL) /*!< DLR OVRCLR: LN7 (Bitfield-Mask: 0x01) */ 3235 #define DLR_OVRCLR_LN8_Pos (8UL) /*!< DLR OVRCLR: LN8 (Bit 8) */ 3236 #define DLR_OVRCLR_LN8_Msk (0x100UL) /*!< DLR OVRCLR: LN8 (Bitfield-Mask: 0x01) */ 3237 #define DLR_OVRCLR_LN9_Pos (9UL) /*!< DLR OVRCLR: LN9 (Bit 9) */ 3238 #define DLR_OVRCLR_LN9_Msk (0x200UL) /*!< DLR OVRCLR: LN9 (Bitfield-Mask: 0x01) */ 3239 #define DLR_OVRCLR_LN10_Pos (10UL) /*!< DLR OVRCLR: LN10 (Bit 10) */ 3240 #define DLR_OVRCLR_LN10_Msk (0x400UL) /*!< DLR OVRCLR: LN10 (Bitfield-Mask: 0x01) */ 3241 #define DLR_OVRCLR_LN11_Pos (11UL) /*!< DLR OVRCLR: LN11 (Bit 11) */ 3242 #define DLR_OVRCLR_LN11_Msk (0x800UL) /*!< DLR OVRCLR: LN11 (Bitfield-Mask: 0x01) */ 3243 3244 /* --------------------------------- DLR_SRSEL0 --------------------------------- */ 3245 #define DLR_SRSEL0_RS0_Pos (0UL) /*!< DLR SRSEL0: RS0 (Bit 0) */ 3246 #define DLR_SRSEL0_RS0_Msk (0xfUL) /*!< DLR SRSEL0: RS0 (Bitfield-Mask: 0x0f) */ 3247 #define DLR_SRSEL0_RS1_Pos (4UL) /*!< DLR SRSEL0: RS1 (Bit 4) */ 3248 #define DLR_SRSEL0_RS1_Msk (0xf0UL) /*!< DLR SRSEL0: RS1 (Bitfield-Mask: 0x0f) */ 3249 #define DLR_SRSEL0_RS2_Pos (8UL) /*!< DLR SRSEL0: RS2 (Bit 8) */ 3250 #define DLR_SRSEL0_RS2_Msk (0xf00UL) /*!< DLR SRSEL0: RS2 (Bitfield-Mask: 0x0f) */ 3251 #define DLR_SRSEL0_RS3_Pos (12UL) /*!< DLR SRSEL0: RS3 (Bit 12) */ 3252 #define DLR_SRSEL0_RS3_Msk (0xf000UL) /*!< DLR SRSEL0: RS3 (Bitfield-Mask: 0x0f) */ 3253 #define DLR_SRSEL0_RS4_Pos (16UL) /*!< DLR SRSEL0: RS4 (Bit 16) */ 3254 #define DLR_SRSEL0_RS4_Msk (0xf0000UL) /*!< DLR SRSEL0: RS4 (Bitfield-Mask: 0x0f) */ 3255 #define DLR_SRSEL0_RS5_Pos (20UL) /*!< DLR SRSEL0: RS5 (Bit 20) */ 3256 #define DLR_SRSEL0_RS5_Msk (0xf00000UL) /*!< DLR SRSEL0: RS5 (Bitfield-Mask: 0x0f) */ 3257 #define DLR_SRSEL0_RS6_Pos (24UL) /*!< DLR SRSEL0: RS6 (Bit 24) */ 3258 #define DLR_SRSEL0_RS6_Msk (0xf000000UL) /*!< DLR SRSEL0: RS6 (Bitfield-Mask: 0x0f) */ 3259 #define DLR_SRSEL0_RS7_Pos (28UL) /*!< DLR SRSEL0: RS7 (Bit 28) */ 3260 #define DLR_SRSEL0_RS7_Msk (0xf0000000UL) /*!< DLR SRSEL0: RS7 (Bitfield-Mask: 0x0f) */ 3261 3262 /* --------------------------------- DLR_SRSEL1 --------------------------------- */ 3263 #define DLR_SRSEL1_RS8_Pos (0UL) /*!< DLR SRSEL1: RS8 (Bit 0) */ 3264 #define DLR_SRSEL1_RS8_Msk (0xfUL) /*!< DLR SRSEL1: RS8 (Bitfield-Mask: 0x0f) */ 3265 #define DLR_SRSEL1_RS9_Pos (4UL) /*!< DLR SRSEL1: RS9 (Bit 4) */ 3266 #define DLR_SRSEL1_RS9_Msk (0xf0UL) /*!< DLR SRSEL1: RS9 (Bitfield-Mask: 0x0f) */ 3267 #define DLR_SRSEL1_RS10_Pos (8UL) /*!< DLR SRSEL1: RS10 (Bit 8) */ 3268 #define DLR_SRSEL1_RS10_Msk (0xf00UL) /*!< DLR SRSEL1: RS10 (Bitfield-Mask: 0x0f) */ 3269 #define DLR_SRSEL1_RS11_Pos (12UL) /*!< DLR SRSEL1: RS11 (Bit 12) */ 3270 #define DLR_SRSEL1_RS11_Msk (0xf000UL) /*!< DLR SRSEL1: RS11 (Bitfield-Mask: 0x0f) */ 3271 3272 /* ---------------------------------- DLR_LNEN ---------------------------------- */ 3273 #define DLR_LNEN_LN0_Pos (0UL) /*!< DLR LNEN: LN0 (Bit 0) */ 3274 #define DLR_LNEN_LN0_Msk (0x1UL) /*!< DLR LNEN: LN0 (Bitfield-Mask: 0x01) */ 3275 #define DLR_LNEN_LN1_Pos (1UL) /*!< DLR LNEN: LN1 (Bit 1) */ 3276 #define DLR_LNEN_LN1_Msk (0x2UL) /*!< DLR LNEN: LN1 (Bitfield-Mask: 0x01) */ 3277 #define DLR_LNEN_LN2_Pos (2UL) /*!< DLR LNEN: LN2 (Bit 2) */ 3278 #define DLR_LNEN_LN2_Msk (0x4UL) /*!< DLR LNEN: LN2 (Bitfield-Mask: 0x01) */ 3279 #define DLR_LNEN_LN3_Pos (3UL) /*!< DLR LNEN: LN3 (Bit 3) */ 3280 #define DLR_LNEN_LN3_Msk (0x8UL) /*!< DLR LNEN: LN3 (Bitfield-Mask: 0x01) */ 3281 #define DLR_LNEN_LN4_Pos (4UL) /*!< DLR LNEN: LN4 (Bit 4) */ 3282 #define DLR_LNEN_LN4_Msk (0x10UL) /*!< DLR LNEN: LN4 (Bitfield-Mask: 0x01) */ 3283 #define DLR_LNEN_LN5_Pos (5UL) /*!< DLR LNEN: LN5 (Bit 5) */ 3284 #define DLR_LNEN_LN5_Msk (0x20UL) /*!< DLR LNEN: LN5 (Bitfield-Mask: 0x01) */ 3285 #define DLR_LNEN_LN6_Pos (6UL) /*!< DLR LNEN: LN6 (Bit 6) */ 3286 #define DLR_LNEN_LN6_Msk (0x40UL) /*!< DLR LNEN: LN6 (Bitfield-Mask: 0x01) */ 3287 #define DLR_LNEN_LN7_Pos (7UL) /*!< DLR LNEN: LN7 (Bit 7) */ 3288 #define DLR_LNEN_LN7_Msk (0x80UL) /*!< DLR LNEN: LN7 (Bitfield-Mask: 0x01) */ 3289 #define DLR_LNEN_LN8_Pos (8UL) /*!< DLR LNEN: LN8 (Bit 8) */ 3290 #define DLR_LNEN_LN8_Msk (0x100UL) /*!< DLR LNEN: LN8 (Bitfield-Mask: 0x01) */ 3291 #define DLR_LNEN_LN9_Pos (9UL) /*!< DLR LNEN: LN9 (Bit 9) */ 3292 #define DLR_LNEN_LN9_Msk (0x200UL) /*!< DLR LNEN: LN9 (Bitfield-Mask: 0x01) */ 3293 #define DLR_LNEN_LN10_Pos (10UL) /*!< DLR LNEN: LN10 (Bit 10) */ 3294 #define DLR_LNEN_LN10_Msk (0x400UL) /*!< DLR LNEN: LN10 (Bitfield-Mask: 0x01) */ 3295 #define DLR_LNEN_LN11_Pos (11UL) /*!< DLR LNEN: LN11 (Bit 11) */ 3296 #define DLR_LNEN_LN11_Msk (0x800UL) /*!< DLR LNEN: LN11 (Bitfield-Mask: 0x01) */ 3297 3298 3299 /* ================================================================================ */ 3300 /* ================ Group 'ERU' Position & Mask ================ */ 3301 /* ================================================================================ */ 3302 3303 3304 /* --------------------------------- ERU_EXISEL --------------------------------- */ 3305 #define ERU_EXISEL_EXS0A_Pos (0UL) /*!< ERU EXISEL: EXS0A (Bit 0) */ 3306 #define ERU_EXISEL_EXS0A_Msk (0x3UL) /*!< ERU EXISEL: EXS0A (Bitfield-Mask: 0x03) */ 3307 #define ERU_EXISEL_EXS0B_Pos (2UL) /*!< ERU EXISEL: EXS0B (Bit 2) */ 3308 #define ERU_EXISEL_EXS0B_Msk (0xcUL) /*!< ERU EXISEL: EXS0B (Bitfield-Mask: 0x03) */ 3309 #define ERU_EXISEL_EXS1A_Pos (4UL) /*!< ERU EXISEL: EXS1A (Bit 4) */ 3310 #define ERU_EXISEL_EXS1A_Msk (0x30UL) /*!< ERU EXISEL: EXS1A (Bitfield-Mask: 0x03) */ 3311 #define ERU_EXISEL_EXS1B_Pos (6UL) /*!< ERU EXISEL: EXS1B (Bit 6) */ 3312 #define ERU_EXISEL_EXS1B_Msk (0xc0UL) /*!< ERU EXISEL: EXS1B (Bitfield-Mask: 0x03) */ 3313 #define ERU_EXISEL_EXS2A_Pos (8UL) /*!< ERU EXISEL: EXS2A (Bit 8) */ 3314 #define ERU_EXISEL_EXS2A_Msk (0x300UL) /*!< ERU EXISEL: EXS2A (Bitfield-Mask: 0x03) */ 3315 #define ERU_EXISEL_EXS2B_Pos (10UL) /*!< ERU EXISEL: EXS2B (Bit 10) */ 3316 #define ERU_EXISEL_EXS2B_Msk (0xc00UL) /*!< ERU EXISEL: EXS2B (Bitfield-Mask: 0x03) */ 3317 #define ERU_EXISEL_EXS3A_Pos (12UL) /*!< ERU EXISEL: EXS3A (Bit 12) */ 3318 #define ERU_EXISEL_EXS3A_Msk (0x3000UL) /*!< ERU EXISEL: EXS3A (Bitfield-Mask: 0x03) */ 3319 #define ERU_EXISEL_EXS3B_Pos (14UL) /*!< ERU EXISEL: EXS3B (Bit 14) */ 3320 #define ERU_EXISEL_EXS3B_Msk (0xc000UL) /*!< ERU EXISEL: EXS3B (Bitfield-Mask: 0x03) */ 3321 3322 /* --------------------------------- ERU_EXICON --------------------------------- */ 3323 #define ERU_EXICON_PE_Pos (0UL) /*!< ERU EXICON: PE (Bit 0) */ 3324 #define ERU_EXICON_PE_Msk (0x1UL) /*!< ERU EXICON: PE (Bitfield-Mask: 0x01) */ 3325 #define ERU_EXICON_LD_Pos (1UL) /*!< ERU EXICON: LD (Bit 1) */ 3326 #define ERU_EXICON_LD_Msk (0x2UL) /*!< ERU EXICON: LD (Bitfield-Mask: 0x01) */ 3327 #define ERU_EXICON_RE_Pos (2UL) /*!< ERU EXICON: RE (Bit 2) */ 3328 #define ERU_EXICON_RE_Msk (0x4UL) /*!< ERU EXICON: RE (Bitfield-Mask: 0x01) */ 3329 #define ERU_EXICON_FE_Pos (3UL) /*!< ERU EXICON: FE (Bit 3) */ 3330 #define ERU_EXICON_FE_Msk (0x8UL) /*!< ERU EXICON: FE (Bitfield-Mask: 0x01) */ 3331 #define ERU_EXICON_OCS_Pos (4UL) /*!< ERU EXICON: OCS (Bit 4) */ 3332 #define ERU_EXICON_OCS_Msk (0x70UL) /*!< ERU EXICON: OCS (Bitfield-Mask: 0x07) */ 3333 #define ERU_EXICON_FL_Pos (7UL) /*!< ERU EXICON: FL (Bit 7) */ 3334 #define ERU_EXICON_FL_Msk (0x80UL) /*!< ERU EXICON: FL (Bitfield-Mask: 0x01) */ 3335 #define ERU_EXICON_SS_Pos (8UL) /*!< ERU EXICON: SS (Bit 8) */ 3336 #define ERU_EXICON_SS_Msk (0x300UL) /*!< ERU EXICON: SS (Bitfield-Mask: 0x03) */ 3337 #define ERU_EXICON_NA_Pos (10UL) /*!< ERU EXICON: NA (Bit 10) */ 3338 #define ERU_EXICON_NA_Msk (0x400UL) /*!< ERU EXICON: NA (Bitfield-Mask: 0x01) */ 3339 #define ERU_EXICON_NB_Pos (11UL) /*!< ERU EXICON: NB (Bit 11) */ 3340 #define ERU_EXICON_NB_Msk (0x800UL) /*!< ERU EXICON: NB (Bitfield-Mask: 0x01) */ 3341 3342 /* --------------------------------- ERU_EXOCON --------------------------------- */ 3343 #define ERU_EXOCON_ISS_Pos (0UL) /*!< ERU EXOCON: ISS (Bit 0) */ 3344 #define ERU_EXOCON_ISS_Msk (0x3UL) /*!< ERU EXOCON: ISS (Bitfield-Mask: 0x03) */ 3345 #define ERU_EXOCON_GEEN_Pos (2UL) /*!< ERU EXOCON: GEEN (Bit 2) */ 3346 #define ERU_EXOCON_GEEN_Msk (0x4UL) /*!< ERU EXOCON: GEEN (Bitfield-Mask: 0x01) */ 3347 #define ERU_EXOCON_PDR_Pos (3UL) /*!< ERU EXOCON: PDR (Bit 3) */ 3348 #define ERU_EXOCON_PDR_Msk (0x8UL) /*!< ERU EXOCON: PDR (Bitfield-Mask: 0x01) */ 3349 #define ERU_EXOCON_GP_Pos (4UL) /*!< ERU EXOCON: GP (Bit 4) */ 3350 #define ERU_EXOCON_GP_Msk (0x30UL) /*!< ERU EXOCON: GP (Bitfield-Mask: 0x03) */ 3351 #define ERU_EXOCON_IPEN0_Pos (12UL) /*!< ERU EXOCON: IPEN0 (Bit 12) */ 3352 #define ERU_EXOCON_IPEN0_Msk (0x1000UL) /*!< ERU EXOCON: IPEN0 (Bitfield-Mask: 0x01) */ 3353 #define ERU_EXOCON_IPEN1_Pos (13UL) /*!< ERU EXOCON: IPEN1 (Bit 13) */ 3354 #define ERU_EXOCON_IPEN1_Msk (0x2000UL) /*!< ERU EXOCON: IPEN1 (Bitfield-Mask: 0x01) */ 3355 #define ERU_EXOCON_IPEN2_Pos (14UL) /*!< ERU EXOCON: IPEN2 (Bit 14) */ 3356 #define ERU_EXOCON_IPEN2_Msk (0x4000UL) /*!< ERU EXOCON: IPEN2 (Bitfield-Mask: 0x01) */ 3357 #define ERU_EXOCON_IPEN3_Pos (15UL) /*!< ERU EXOCON: IPEN3 (Bit 15) */ 3358 #define ERU_EXOCON_IPEN3_Msk (0x8000UL) /*!< ERU EXOCON: IPEN3 (Bitfield-Mask: 0x01) */ 3359 3360 3361 /* ================================================================================ */ 3362 /* ================ struct 'GPDMA0' Position & Mask ================ */ 3363 /* ================================================================================ */ 3364 3365 3366 /* -------------------------------- GPDMA0_RAWTFR ------------------------------- */ 3367 #define GPDMA0_RAWTFR_CH0_Pos (0UL) /*!< GPDMA0 RAWTFR: CH0 (Bit 0) */ 3368 #define GPDMA0_RAWTFR_CH0_Msk (0x1UL) /*!< GPDMA0 RAWTFR: CH0 (Bitfield-Mask: 0x01) */ 3369 #define GPDMA0_RAWTFR_CH1_Pos (1UL) /*!< GPDMA0 RAWTFR: CH1 (Bit 1) */ 3370 #define GPDMA0_RAWTFR_CH1_Msk (0x2UL) /*!< GPDMA0 RAWTFR: CH1 (Bitfield-Mask: 0x01) */ 3371 #define GPDMA0_RAWTFR_CH2_Pos (2UL) /*!< GPDMA0 RAWTFR: CH2 (Bit 2) */ 3372 #define GPDMA0_RAWTFR_CH2_Msk (0x4UL) /*!< GPDMA0 RAWTFR: CH2 (Bitfield-Mask: 0x01) */ 3373 #define GPDMA0_RAWTFR_CH3_Pos (3UL) /*!< GPDMA0 RAWTFR: CH3 (Bit 3) */ 3374 #define GPDMA0_RAWTFR_CH3_Msk (0x8UL) /*!< GPDMA0 RAWTFR: CH3 (Bitfield-Mask: 0x01) */ 3375 #define GPDMA0_RAWTFR_CH4_Pos (4UL) /*!< GPDMA0 RAWTFR: CH4 (Bit 4) */ 3376 #define GPDMA0_RAWTFR_CH4_Msk (0x10UL) /*!< GPDMA0 RAWTFR: CH4 (Bitfield-Mask: 0x01) */ 3377 #define GPDMA0_RAWTFR_CH5_Pos (5UL) /*!< GPDMA0 RAWTFR: CH5 (Bit 5) */ 3378 #define GPDMA0_RAWTFR_CH5_Msk (0x20UL) /*!< GPDMA0 RAWTFR: CH5 (Bitfield-Mask: 0x01) */ 3379 #define GPDMA0_RAWTFR_CH6_Pos (6UL) /*!< GPDMA0 RAWTFR: CH6 (Bit 6) */ 3380 #define GPDMA0_RAWTFR_CH6_Msk (0x40UL) /*!< GPDMA0 RAWTFR: CH6 (Bitfield-Mask: 0x01) */ 3381 #define GPDMA0_RAWTFR_CH7_Pos (7UL) /*!< GPDMA0 RAWTFR: CH7 (Bit 7) */ 3382 #define GPDMA0_RAWTFR_CH7_Msk (0x80UL) /*!< GPDMA0 RAWTFR: CH7 (Bitfield-Mask: 0x01) */ 3383 3384 /* ------------------------------- GPDMA0_RAWBLOCK ------------------------------ */ 3385 #define GPDMA0_RAWBLOCK_CH0_Pos (0UL) /*!< GPDMA0 RAWBLOCK: CH0 (Bit 0) */ 3386 #define GPDMA0_RAWBLOCK_CH0_Msk (0x1UL) /*!< GPDMA0 RAWBLOCK: CH0 (Bitfield-Mask: 0x01) */ 3387 #define GPDMA0_RAWBLOCK_CH1_Pos (1UL) /*!< GPDMA0 RAWBLOCK: CH1 (Bit 1) */ 3388 #define GPDMA0_RAWBLOCK_CH1_Msk (0x2UL) /*!< GPDMA0 RAWBLOCK: CH1 (Bitfield-Mask: 0x01) */ 3389 #define GPDMA0_RAWBLOCK_CH2_Pos (2UL) /*!< GPDMA0 RAWBLOCK: CH2 (Bit 2) */ 3390 #define GPDMA0_RAWBLOCK_CH2_Msk (0x4UL) /*!< GPDMA0 RAWBLOCK: CH2 (Bitfield-Mask: 0x01) */ 3391 #define GPDMA0_RAWBLOCK_CH3_Pos (3UL) /*!< GPDMA0 RAWBLOCK: CH3 (Bit 3) */ 3392 #define GPDMA0_RAWBLOCK_CH3_Msk (0x8UL) /*!< GPDMA0 RAWBLOCK: CH3 (Bitfield-Mask: 0x01) */ 3393 #define GPDMA0_RAWBLOCK_CH4_Pos (4UL) /*!< GPDMA0 RAWBLOCK: CH4 (Bit 4) */ 3394 #define GPDMA0_RAWBLOCK_CH4_Msk (0x10UL) /*!< GPDMA0 RAWBLOCK: CH4 (Bitfield-Mask: 0x01) */ 3395 #define GPDMA0_RAWBLOCK_CH5_Pos (5UL) /*!< GPDMA0 RAWBLOCK: CH5 (Bit 5) */ 3396 #define GPDMA0_RAWBLOCK_CH5_Msk (0x20UL) /*!< GPDMA0 RAWBLOCK: CH5 (Bitfield-Mask: 0x01) */ 3397 #define GPDMA0_RAWBLOCK_CH6_Pos (6UL) /*!< GPDMA0 RAWBLOCK: CH6 (Bit 6) */ 3398 #define GPDMA0_RAWBLOCK_CH6_Msk (0x40UL) /*!< GPDMA0 RAWBLOCK: CH6 (Bitfield-Mask: 0x01) */ 3399 #define GPDMA0_RAWBLOCK_CH7_Pos (7UL) /*!< GPDMA0 RAWBLOCK: CH7 (Bit 7) */ 3400 #define GPDMA0_RAWBLOCK_CH7_Msk (0x80UL) /*!< GPDMA0 RAWBLOCK: CH7 (Bitfield-Mask: 0x01) */ 3401 3402 /* ------------------------------ GPDMA0_RAWSRCTRAN ----------------------------- */ 3403 #define GPDMA0_RAWSRCTRAN_CH0_Pos (0UL) /*!< GPDMA0 RAWSRCTRAN: CH0 (Bit 0) */ 3404 #define GPDMA0_RAWSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 RAWSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ 3405 #define GPDMA0_RAWSRCTRAN_CH1_Pos (1UL) /*!< GPDMA0 RAWSRCTRAN: CH1 (Bit 1) */ 3406 #define GPDMA0_RAWSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 RAWSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ 3407 #define GPDMA0_RAWSRCTRAN_CH2_Pos (2UL) /*!< GPDMA0 RAWSRCTRAN: CH2 (Bit 2) */ 3408 #define GPDMA0_RAWSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 RAWSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ 3409 #define GPDMA0_RAWSRCTRAN_CH3_Pos (3UL) /*!< GPDMA0 RAWSRCTRAN: CH3 (Bit 3) */ 3410 #define GPDMA0_RAWSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 RAWSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ 3411 #define GPDMA0_RAWSRCTRAN_CH4_Pos (4UL) /*!< GPDMA0 RAWSRCTRAN: CH4 (Bit 4) */ 3412 #define GPDMA0_RAWSRCTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 RAWSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ 3413 #define GPDMA0_RAWSRCTRAN_CH5_Pos (5UL) /*!< GPDMA0 RAWSRCTRAN: CH5 (Bit 5) */ 3414 #define GPDMA0_RAWSRCTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 RAWSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ 3415 #define GPDMA0_RAWSRCTRAN_CH6_Pos (6UL) /*!< GPDMA0 RAWSRCTRAN: CH6 (Bit 6) */ 3416 #define GPDMA0_RAWSRCTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 RAWSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ 3417 #define GPDMA0_RAWSRCTRAN_CH7_Pos (7UL) /*!< GPDMA0 RAWSRCTRAN: CH7 (Bit 7) */ 3418 #define GPDMA0_RAWSRCTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 RAWSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ 3419 3420 /* ------------------------------ GPDMA0_RAWDSTTRAN ----------------------------- */ 3421 #define GPDMA0_RAWDSTTRAN_CH0_Pos (0UL) /*!< GPDMA0 RAWDSTTRAN: CH0 (Bit 0) */ 3422 #define GPDMA0_RAWDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 RAWDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ 3423 #define GPDMA0_RAWDSTTRAN_CH1_Pos (1UL) /*!< GPDMA0 RAWDSTTRAN: CH1 (Bit 1) */ 3424 #define GPDMA0_RAWDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 RAWDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ 3425 #define GPDMA0_RAWDSTTRAN_CH2_Pos (2UL) /*!< GPDMA0 RAWDSTTRAN: CH2 (Bit 2) */ 3426 #define GPDMA0_RAWDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 RAWDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ 3427 #define GPDMA0_RAWDSTTRAN_CH3_Pos (3UL) /*!< GPDMA0 RAWDSTTRAN: CH3 (Bit 3) */ 3428 #define GPDMA0_RAWDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 RAWDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ 3429 #define GPDMA0_RAWDSTTRAN_CH4_Pos (4UL) /*!< GPDMA0 RAWDSTTRAN: CH4 (Bit 4) */ 3430 #define GPDMA0_RAWDSTTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 RAWDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ 3431 #define GPDMA0_RAWDSTTRAN_CH5_Pos (5UL) /*!< GPDMA0 RAWDSTTRAN: CH5 (Bit 5) */ 3432 #define GPDMA0_RAWDSTTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 RAWDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ 3433 #define GPDMA0_RAWDSTTRAN_CH6_Pos (6UL) /*!< GPDMA0 RAWDSTTRAN: CH6 (Bit 6) */ 3434 #define GPDMA0_RAWDSTTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 RAWDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ 3435 #define GPDMA0_RAWDSTTRAN_CH7_Pos (7UL) /*!< GPDMA0 RAWDSTTRAN: CH7 (Bit 7) */ 3436 #define GPDMA0_RAWDSTTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 RAWDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ 3437 3438 /* -------------------------------- GPDMA0_RAWERR ------------------------------- */ 3439 #define GPDMA0_RAWERR_CH0_Pos (0UL) /*!< GPDMA0 RAWERR: CH0 (Bit 0) */ 3440 #define GPDMA0_RAWERR_CH0_Msk (0x1UL) /*!< GPDMA0 RAWERR: CH0 (Bitfield-Mask: 0x01) */ 3441 #define GPDMA0_RAWERR_CH1_Pos (1UL) /*!< GPDMA0 RAWERR: CH1 (Bit 1) */ 3442 #define GPDMA0_RAWERR_CH1_Msk (0x2UL) /*!< GPDMA0 RAWERR: CH1 (Bitfield-Mask: 0x01) */ 3443 #define GPDMA0_RAWERR_CH2_Pos (2UL) /*!< GPDMA0 RAWERR: CH2 (Bit 2) */ 3444 #define GPDMA0_RAWERR_CH2_Msk (0x4UL) /*!< GPDMA0 RAWERR: CH2 (Bitfield-Mask: 0x01) */ 3445 #define GPDMA0_RAWERR_CH3_Pos (3UL) /*!< GPDMA0 RAWERR: CH3 (Bit 3) */ 3446 #define GPDMA0_RAWERR_CH3_Msk (0x8UL) /*!< GPDMA0 RAWERR: CH3 (Bitfield-Mask: 0x01) */ 3447 #define GPDMA0_RAWERR_CH4_Pos (4UL) /*!< GPDMA0 RAWERR: CH4 (Bit 4) */ 3448 #define GPDMA0_RAWERR_CH4_Msk (0x10UL) /*!< GPDMA0 RAWERR: CH4 (Bitfield-Mask: 0x01) */ 3449 #define GPDMA0_RAWERR_CH5_Pos (5UL) /*!< GPDMA0 RAWERR: CH5 (Bit 5) */ 3450 #define GPDMA0_RAWERR_CH5_Msk (0x20UL) /*!< GPDMA0 RAWERR: CH5 (Bitfield-Mask: 0x01) */ 3451 #define GPDMA0_RAWERR_CH6_Pos (6UL) /*!< GPDMA0 RAWERR: CH6 (Bit 6) */ 3452 #define GPDMA0_RAWERR_CH6_Msk (0x40UL) /*!< GPDMA0 RAWERR: CH6 (Bitfield-Mask: 0x01) */ 3453 #define GPDMA0_RAWERR_CH7_Pos (7UL) /*!< GPDMA0 RAWERR: CH7 (Bit 7) */ 3454 #define GPDMA0_RAWERR_CH7_Msk (0x80UL) /*!< GPDMA0 RAWERR: CH7 (Bitfield-Mask: 0x01) */ 3455 3456 /* ------------------------------ GPDMA0_STATUSTFR ------------------------------ */ 3457 #define GPDMA0_STATUSTFR_CH0_Pos (0UL) /*!< GPDMA0 STATUSTFR: CH0 (Bit 0) */ 3458 #define GPDMA0_STATUSTFR_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSTFR: CH0 (Bitfield-Mask: 0x01) */ 3459 #define GPDMA0_STATUSTFR_CH1_Pos (1UL) /*!< GPDMA0 STATUSTFR: CH1 (Bit 1) */ 3460 #define GPDMA0_STATUSTFR_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSTFR: CH1 (Bitfield-Mask: 0x01) */ 3461 #define GPDMA0_STATUSTFR_CH2_Pos (2UL) /*!< GPDMA0 STATUSTFR: CH2 (Bit 2) */ 3462 #define GPDMA0_STATUSTFR_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSTFR: CH2 (Bitfield-Mask: 0x01) */ 3463 #define GPDMA0_STATUSTFR_CH3_Pos (3UL) /*!< GPDMA0 STATUSTFR: CH3 (Bit 3) */ 3464 #define GPDMA0_STATUSTFR_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSTFR: CH3 (Bitfield-Mask: 0x01) */ 3465 #define GPDMA0_STATUSTFR_CH4_Pos (4UL) /*!< GPDMA0 STATUSTFR: CH4 (Bit 4) */ 3466 #define GPDMA0_STATUSTFR_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSTFR: CH4 (Bitfield-Mask: 0x01) */ 3467 #define GPDMA0_STATUSTFR_CH5_Pos (5UL) /*!< GPDMA0 STATUSTFR: CH5 (Bit 5) */ 3468 #define GPDMA0_STATUSTFR_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSTFR: CH5 (Bitfield-Mask: 0x01) */ 3469 #define GPDMA0_STATUSTFR_CH6_Pos (6UL) /*!< GPDMA0 STATUSTFR: CH6 (Bit 6) */ 3470 #define GPDMA0_STATUSTFR_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSTFR: CH6 (Bitfield-Mask: 0x01) */ 3471 #define GPDMA0_STATUSTFR_CH7_Pos (7UL) /*!< GPDMA0 STATUSTFR: CH7 (Bit 7) */ 3472 #define GPDMA0_STATUSTFR_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSTFR: CH7 (Bitfield-Mask: 0x01) */ 3473 3474 /* ----------------------------- GPDMA0_STATUSBLOCK ----------------------------- */ 3475 #define GPDMA0_STATUSBLOCK_CH0_Pos (0UL) /*!< GPDMA0 STATUSBLOCK: CH0 (Bit 0) */ 3476 #define GPDMA0_STATUSBLOCK_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSBLOCK: CH0 (Bitfield-Mask: 0x01) */ 3477 #define GPDMA0_STATUSBLOCK_CH1_Pos (1UL) /*!< GPDMA0 STATUSBLOCK: CH1 (Bit 1) */ 3478 #define GPDMA0_STATUSBLOCK_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSBLOCK: CH1 (Bitfield-Mask: 0x01) */ 3479 #define GPDMA0_STATUSBLOCK_CH2_Pos (2UL) /*!< GPDMA0 STATUSBLOCK: CH2 (Bit 2) */ 3480 #define GPDMA0_STATUSBLOCK_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSBLOCK: CH2 (Bitfield-Mask: 0x01) */ 3481 #define GPDMA0_STATUSBLOCK_CH3_Pos (3UL) /*!< GPDMA0 STATUSBLOCK: CH3 (Bit 3) */ 3482 #define GPDMA0_STATUSBLOCK_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSBLOCK: CH3 (Bitfield-Mask: 0x01) */ 3483 #define GPDMA0_STATUSBLOCK_CH4_Pos (4UL) /*!< GPDMA0 STATUSBLOCK: CH4 (Bit 4) */ 3484 #define GPDMA0_STATUSBLOCK_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSBLOCK: CH4 (Bitfield-Mask: 0x01) */ 3485 #define GPDMA0_STATUSBLOCK_CH5_Pos (5UL) /*!< GPDMA0 STATUSBLOCK: CH5 (Bit 5) */ 3486 #define GPDMA0_STATUSBLOCK_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSBLOCK: CH5 (Bitfield-Mask: 0x01) */ 3487 #define GPDMA0_STATUSBLOCK_CH6_Pos (6UL) /*!< GPDMA0 STATUSBLOCK: CH6 (Bit 6) */ 3488 #define GPDMA0_STATUSBLOCK_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSBLOCK: CH6 (Bitfield-Mask: 0x01) */ 3489 #define GPDMA0_STATUSBLOCK_CH7_Pos (7UL) /*!< GPDMA0 STATUSBLOCK: CH7 (Bit 7) */ 3490 #define GPDMA0_STATUSBLOCK_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSBLOCK: CH7 (Bitfield-Mask: 0x01) */ 3491 3492 /* ---------------------------- GPDMA0_STATUSSRCTRAN ---------------------------- */ 3493 #define GPDMA0_STATUSSRCTRAN_CH0_Pos (0UL) /*!< GPDMA0 STATUSSRCTRAN: CH0 (Bit 0) */ 3494 #define GPDMA0_STATUSSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ 3495 #define GPDMA0_STATUSSRCTRAN_CH1_Pos (1UL) /*!< GPDMA0 STATUSSRCTRAN: CH1 (Bit 1) */ 3496 #define GPDMA0_STATUSSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ 3497 #define GPDMA0_STATUSSRCTRAN_CH2_Pos (2UL) /*!< GPDMA0 STATUSSRCTRAN: CH2 (Bit 2) */ 3498 #define GPDMA0_STATUSSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ 3499 #define GPDMA0_STATUSSRCTRAN_CH3_Pos (3UL) /*!< GPDMA0 STATUSSRCTRAN: CH3 (Bit 3) */ 3500 #define GPDMA0_STATUSSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ 3501 #define GPDMA0_STATUSSRCTRAN_CH4_Pos (4UL) /*!< GPDMA0 STATUSSRCTRAN: CH4 (Bit 4) */ 3502 #define GPDMA0_STATUSSRCTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ 3503 #define GPDMA0_STATUSSRCTRAN_CH5_Pos (5UL) /*!< GPDMA0 STATUSSRCTRAN: CH5 (Bit 5) */ 3504 #define GPDMA0_STATUSSRCTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ 3505 #define GPDMA0_STATUSSRCTRAN_CH6_Pos (6UL) /*!< GPDMA0 STATUSSRCTRAN: CH6 (Bit 6) */ 3506 #define GPDMA0_STATUSSRCTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ 3507 #define GPDMA0_STATUSSRCTRAN_CH7_Pos (7UL) /*!< GPDMA0 STATUSSRCTRAN: CH7 (Bit 7) */ 3508 #define GPDMA0_STATUSSRCTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ 3509 3510 /* ---------------------------- GPDMA0_STATUSDSTTRAN ---------------------------- */ 3511 #define GPDMA0_STATUSDSTTRAN_CH0_Pos (0UL) /*!< GPDMA0 STATUSDSTTRAN: CH0 (Bit 0) */ 3512 #define GPDMA0_STATUSDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ 3513 #define GPDMA0_STATUSDSTTRAN_CH1_Pos (1UL) /*!< GPDMA0 STATUSDSTTRAN: CH1 (Bit 1) */ 3514 #define GPDMA0_STATUSDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ 3515 #define GPDMA0_STATUSDSTTRAN_CH2_Pos (2UL) /*!< GPDMA0 STATUSDSTTRAN: CH2 (Bit 2) */ 3516 #define GPDMA0_STATUSDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ 3517 #define GPDMA0_STATUSDSTTRAN_CH3_Pos (3UL) /*!< GPDMA0 STATUSDSTTRAN: CH3 (Bit 3) */ 3518 #define GPDMA0_STATUSDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ 3519 #define GPDMA0_STATUSDSTTRAN_CH4_Pos (4UL) /*!< GPDMA0 STATUSDSTTRAN: CH4 (Bit 4) */ 3520 #define GPDMA0_STATUSDSTTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ 3521 #define GPDMA0_STATUSDSTTRAN_CH5_Pos (5UL) /*!< GPDMA0 STATUSDSTTRAN: CH5 (Bit 5) */ 3522 #define GPDMA0_STATUSDSTTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ 3523 #define GPDMA0_STATUSDSTTRAN_CH6_Pos (6UL) /*!< GPDMA0 STATUSDSTTRAN: CH6 (Bit 6) */ 3524 #define GPDMA0_STATUSDSTTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ 3525 #define GPDMA0_STATUSDSTTRAN_CH7_Pos (7UL) /*!< GPDMA0 STATUSDSTTRAN: CH7 (Bit 7) */ 3526 #define GPDMA0_STATUSDSTTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ 3527 3528 /* ------------------------------ GPDMA0_STATUSERR ------------------------------ */ 3529 #define GPDMA0_STATUSERR_CH0_Pos (0UL) /*!< GPDMA0 STATUSERR: CH0 (Bit 0) */ 3530 #define GPDMA0_STATUSERR_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSERR: CH0 (Bitfield-Mask: 0x01) */ 3531 #define GPDMA0_STATUSERR_CH1_Pos (1UL) /*!< GPDMA0 STATUSERR: CH1 (Bit 1) */ 3532 #define GPDMA0_STATUSERR_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSERR: CH1 (Bitfield-Mask: 0x01) */ 3533 #define GPDMA0_STATUSERR_CH2_Pos (2UL) /*!< GPDMA0 STATUSERR: CH2 (Bit 2) */ 3534 #define GPDMA0_STATUSERR_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSERR: CH2 (Bitfield-Mask: 0x01) */ 3535 #define GPDMA0_STATUSERR_CH3_Pos (3UL) /*!< GPDMA0 STATUSERR: CH3 (Bit 3) */ 3536 #define GPDMA0_STATUSERR_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSERR: CH3 (Bitfield-Mask: 0x01) */ 3537 #define GPDMA0_STATUSERR_CH4_Pos (4UL) /*!< GPDMA0 STATUSERR: CH4 (Bit 4) */ 3538 #define GPDMA0_STATUSERR_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSERR: CH4 (Bitfield-Mask: 0x01) */ 3539 #define GPDMA0_STATUSERR_CH5_Pos (5UL) /*!< GPDMA0 STATUSERR: CH5 (Bit 5) */ 3540 #define GPDMA0_STATUSERR_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSERR: CH5 (Bitfield-Mask: 0x01) */ 3541 #define GPDMA0_STATUSERR_CH6_Pos (6UL) /*!< GPDMA0 STATUSERR: CH6 (Bit 6) */ 3542 #define GPDMA0_STATUSERR_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSERR: CH6 (Bitfield-Mask: 0x01) */ 3543 #define GPDMA0_STATUSERR_CH7_Pos (7UL) /*!< GPDMA0 STATUSERR: CH7 (Bit 7) */ 3544 #define GPDMA0_STATUSERR_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSERR: CH7 (Bitfield-Mask: 0x01) */ 3545 3546 /* ------------------------------- GPDMA0_MASKTFR ------------------------------- */ 3547 #define GPDMA0_MASKTFR_CH0_Pos (0UL) /*!< GPDMA0 MASKTFR: CH0 (Bit 0) */ 3548 #define GPDMA0_MASKTFR_CH0_Msk (0x1UL) /*!< GPDMA0 MASKTFR: CH0 (Bitfield-Mask: 0x01) */ 3549 #define GPDMA0_MASKTFR_CH1_Pos (1UL) /*!< GPDMA0 MASKTFR: CH1 (Bit 1) */ 3550 #define GPDMA0_MASKTFR_CH1_Msk (0x2UL) /*!< GPDMA0 MASKTFR: CH1 (Bitfield-Mask: 0x01) */ 3551 #define GPDMA0_MASKTFR_CH2_Pos (2UL) /*!< GPDMA0 MASKTFR: CH2 (Bit 2) */ 3552 #define GPDMA0_MASKTFR_CH2_Msk (0x4UL) /*!< GPDMA0 MASKTFR: CH2 (Bitfield-Mask: 0x01) */ 3553 #define GPDMA0_MASKTFR_CH3_Pos (3UL) /*!< GPDMA0 MASKTFR: CH3 (Bit 3) */ 3554 #define GPDMA0_MASKTFR_CH3_Msk (0x8UL) /*!< GPDMA0 MASKTFR: CH3 (Bitfield-Mask: 0x01) */ 3555 #define GPDMA0_MASKTFR_CH4_Pos (4UL) /*!< GPDMA0 MASKTFR: CH4 (Bit 4) */ 3556 #define GPDMA0_MASKTFR_CH4_Msk (0x10UL) /*!< GPDMA0 MASKTFR: CH4 (Bitfield-Mask: 0x01) */ 3557 #define GPDMA0_MASKTFR_CH5_Pos (5UL) /*!< GPDMA0 MASKTFR: CH5 (Bit 5) */ 3558 #define GPDMA0_MASKTFR_CH5_Msk (0x20UL) /*!< GPDMA0 MASKTFR: CH5 (Bitfield-Mask: 0x01) */ 3559 #define GPDMA0_MASKTFR_CH6_Pos (6UL) /*!< GPDMA0 MASKTFR: CH6 (Bit 6) */ 3560 #define GPDMA0_MASKTFR_CH6_Msk (0x40UL) /*!< GPDMA0 MASKTFR: CH6 (Bitfield-Mask: 0x01) */ 3561 #define GPDMA0_MASKTFR_CH7_Pos (7UL) /*!< GPDMA0 MASKTFR: CH7 (Bit 7) */ 3562 #define GPDMA0_MASKTFR_CH7_Msk (0x80UL) /*!< GPDMA0 MASKTFR: CH7 (Bitfield-Mask: 0x01) */ 3563 #define GPDMA0_MASKTFR_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKTFR: WE_CH0 (Bit 8) */ 3564 #define GPDMA0_MASKTFR_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKTFR: WE_CH0 (Bitfield-Mask: 0x01) */ 3565 #define GPDMA0_MASKTFR_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKTFR: WE_CH1 (Bit 9) */ 3566 #define GPDMA0_MASKTFR_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKTFR: WE_CH1 (Bitfield-Mask: 0x01) */ 3567 #define GPDMA0_MASKTFR_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKTFR: WE_CH2 (Bit 10) */ 3568 #define GPDMA0_MASKTFR_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKTFR: WE_CH2 (Bitfield-Mask: 0x01) */ 3569 #define GPDMA0_MASKTFR_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKTFR: WE_CH3 (Bit 11) */ 3570 #define GPDMA0_MASKTFR_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKTFR: WE_CH3 (Bitfield-Mask: 0x01) */ 3571 #define GPDMA0_MASKTFR_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKTFR: WE_CH4 (Bit 12) */ 3572 #define GPDMA0_MASKTFR_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKTFR: WE_CH4 (Bitfield-Mask: 0x01) */ 3573 #define GPDMA0_MASKTFR_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKTFR: WE_CH5 (Bit 13) */ 3574 #define GPDMA0_MASKTFR_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKTFR: WE_CH5 (Bitfield-Mask: 0x01) */ 3575 #define GPDMA0_MASKTFR_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKTFR: WE_CH6 (Bit 14) */ 3576 #define GPDMA0_MASKTFR_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKTFR: WE_CH6 (Bitfield-Mask: 0x01) */ 3577 #define GPDMA0_MASKTFR_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKTFR: WE_CH7 (Bit 15) */ 3578 #define GPDMA0_MASKTFR_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKTFR: WE_CH7 (Bitfield-Mask: 0x01) */ 3579 3580 /* ------------------------------ GPDMA0_MASKBLOCK ------------------------------ */ 3581 #define GPDMA0_MASKBLOCK_CH0_Pos (0UL) /*!< GPDMA0 MASKBLOCK: CH0 (Bit 0) */ 3582 #define GPDMA0_MASKBLOCK_CH0_Msk (0x1UL) /*!< GPDMA0 MASKBLOCK: CH0 (Bitfield-Mask: 0x01) */ 3583 #define GPDMA0_MASKBLOCK_CH1_Pos (1UL) /*!< GPDMA0 MASKBLOCK: CH1 (Bit 1) */ 3584 #define GPDMA0_MASKBLOCK_CH1_Msk (0x2UL) /*!< GPDMA0 MASKBLOCK: CH1 (Bitfield-Mask: 0x01) */ 3585 #define GPDMA0_MASKBLOCK_CH2_Pos (2UL) /*!< GPDMA0 MASKBLOCK: CH2 (Bit 2) */ 3586 #define GPDMA0_MASKBLOCK_CH2_Msk (0x4UL) /*!< GPDMA0 MASKBLOCK: CH2 (Bitfield-Mask: 0x01) */ 3587 #define GPDMA0_MASKBLOCK_CH3_Pos (3UL) /*!< GPDMA0 MASKBLOCK: CH3 (Bit 3) */ 3588 #define GPDMA0_MASKBLOCK_CH3_Msk (0x8UL) /*!< GPDMA0 MASKBLOCK: CH3 (Bitfield-Mask: 0x01) */ 3589 #define GPDMA0_MASKBLOCK_CH4_Pos (4UL) /*!< GPDMA0 MASKBLOCK: CH4 (Bit 4) */ 3590 #define GPDMA0_MASKBLOCK_CH4_Msk (0x10UL) /*!< GPDMA0 MASKBLOCK: CH4 (Bitfield-Mask: 0x01) */ 3591 #define GPDMA0_MASKBLOCK_CH5_Pos (5UL) /*!< GPDMA0 MASKBLOCK: CH5 (Bit 5) */ 3592 #define GPDMA0_MASKBLOCK_CH5_Msk (0x20UL) /*!< GPDMA0 MASKBLOCK: CH5 (Bitfield-Mask: 0x01) */ 3593 #define GPDMA0_MASKBLOCK_CH6_Pos (6UL) /*!< GPDMA0 MASKBLOCK: CH6 (Bit 6) */ 3594 #define GPDMA0_MASKBLOCK_CH6_Msk (0x40UL) /*!< GPDMA0 MASKBLOCK: CH6 (Bitfield-Mask: 0x01) */ 3595 #define GPDMA0_MASKBLOCK_CH7_Pos (7UL) /*!< GPDMA0 MASKBLOCK: CH7 (Bit 7) */ 3596 #define GPDMA0_MASKBLOCK_CH7_Msk (0x80UL) /*!< GPDMA0 MASKBLOCK: CH7 (Bitfield-Mask: 0x01) */ 3597 #define GPDMA0_MASKBLOCK_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKBLOCK: WE_CH0 (Bit 8) */ 3598 #define GPDMA0_MASKBLOCK_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKBLOCK: WE_CH0 (Bitfield-Mask: 0x01) */ 3599 #define GPDMA0_MASKBLOCK_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKBLOCK: WE_CH1 (Bit 9) */ 3600 #define GPDMA0_MASKBLOCK_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKBLOCK: WE_CH1 (Bitfield-Mask: 0x01) */ 3601 #define GPDMA0_MASKBLOCK_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKBLOCK: WE_CH2 (Bit 10) */ 3602 #define GPDMA0_MASKBLOCK_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKBLOCK: WE_CH2 (Bitfield-Mask: 0x01) */ 3603 #define GPDMA0_MASKBLOCK_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKBLOCK: WE_CH3 (Bit 11) */ 3604 #define GPDMA0_MASKBLOCK_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKBLOCK: WE_CH3 (Bitfield-Mask: 0x01) */ 3605 #define GPDMA0_MASKBLOCK_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKBLOCK: WE_CH4 (Bit 12) */ 3606 #define GPDMA0_MASKBLOCK_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKBLOCK: WE_CH4 (Bitfield-Mask: 0x01) */ 3607 #define GPDMA0_MASKBLOCK_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKBLOCK: WE_CH5 (Bit 13) */ 3608 #define GPDMA0_MASKBLOCK_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKBLOCK: WE_CH5 (Bitfield-Mask: 0x01) */ 3609 #define GPDMA0_MASKBLOCK_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKBLOCK: WE_CH6 (Bit 14) */ 3610 #define GPDMA0_MASKBLOCK_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKBLOCK: WE_CH6 (Bitfield-Mask: 0x01) */ 3611 #define GPDMA0_MASKBLOCK_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKBLOCK: WE_CH7 (Bit 15) */ 3612 #define GPDMA0_MASKBLOCK_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKBLOCK: WE_CH7 (Bitfield-Mask: 0x01) */ 3613 3614 /* ----------------------------- GPDMA0_MASKSRCTRAN ----------------------------- */ 3615 #define GPDMA0_MASKSRCTRAN_CH0_Pos (0UL) /*!< GPDMA0 MASKSRCTRAN: CH0 (Bit 0) */ 3616 #define GPDMA0_MASKSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 MASKSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ 3617 #define GPDMA0_MASKSRCTRAN_CH1_Pos (1UL) /*!< GPDMA0 MASKSRCTRAN: CH1 (Bit 1) */ 3618 #define GPDMA0_MASKSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 MASKSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ 3619 #define GPDMA0_MASKSRCTRAN_CH2_Pos (2UL) /*!< GPDMA0 MASKSRCTRAN: CH2 (Bit 2) */ 3620 #define GPDMA0_MASKSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 MASKSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ 3621 #define GPDMA0_MASKSRCTRAN_CH3_Pos (3UL) /*!< GPDMA0 MASKSRCTRAN: CH3 (Bit 3) */ 3622 #define GPDMA0_MASKSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 MASKSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ 3623 #define GPDMA0_MASKSRCTRAN_CH4_Pos (4UL) /*!< GPDMA0 MASKSRCTRAN: CH4 (Bit 4) */ 3624 #define GPDMA0_MASKSRCTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 MASKSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ 3625 #define GPDMA0_MASKSRCTRAN_CH5_Pos (5UL) /*!< GPDMA0 MASKSRCTRAN: CH5 (Bit 5) */ 3626 #define GPDMA0_MASKSRCTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 MASKSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ 3627 #define GPDMA0_MASKSRCTRAN_CH6_Pos (6UL) /*!< GPDMA0 MASKSRCTRAN: CH6 (Bit 6) */ 3628 #define GPDMA0_MASKSRCTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 MASKSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ 3629 #define GPDMA0_MASKSRCTRAN_CH7_Pos (7UL) /*!< GPDMA0 MASKSRCTRAN: CH7 (Bit 7) */ 3630 #define GPDMA0_MASKSRCTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 MASKSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ 3631 #define GPDMA0_MASKSRCTRAN_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 (Bit 8) */ 3632 #define GPDMA0_MASKSRCTRAN_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ 3633 #define GPDMA0_MASKSRCTRAN_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 (Bit 9) */ 3634 #define GPDMA0_MASKSRCTRAN_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ 3635 #define GPDMA0_MASKSRCTRAN_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 (Bit 10) */ 3636 #define GPDMA0_MASKSRCTRAN_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ 3637 #define GPDMA0_MASKSRCTRAN_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 (Bit 11) */ 3638 #define GPDMA0_MASKSRCTRAN_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ 3639 #define GPDMA0_MASKSRCTRAN_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 (Bit 12) */ 3640 #define GPDMA0_MASKSRCTRAN_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 (Bitfield-Mask: 0x01) */ 3641 #define GPDMA0_MASKSRCTRAN_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 (Bit 13) */ 3642 #define GPDMA0_MASKSRCTRAN_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 (Bitfield-Mask: 0x01) */ 3643 #define GPDMA0_MASKSRCTRAN_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 (Bit 14) */ 3644 #define GPDMA0_MASKSRCTRAN_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 (Bitfield-Mask: 0x01) */ 3645 #define GPDMA0_MASKSRCTRAN_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 (Bit 15) */ 3646 #define GPDMA0_MASKSRCTRAN_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 (Bitfield-Mask: 0x01) */ 3647 3648 /* ----------------------------- GPDMA0_MASKDSTTRAN ----------------------------- */ 3649 #define GPDMA0_MASKDSTTRAN_CH0_Pos (0UL) /*!< GPDMA0 MASKDSTTRAN: CH0 (Bit 0) */ 3650 #define GPDMA0_MASKDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 MASKDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ 3651 #define GPDMA0_MASKDSTTRAN_CH1_Pos (1UL) /*!< GPDMA0 MASKDSTTRAN: CH1 (Bit 1) */ 3652 #define GPDMA0_MASKDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 MASKDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ 3653 #define GPDMA0_MASKDSTTRAN_CH2_Pos (2UL) /*!< GPDMA0 MASKDSTTRAN: CH2 (Bit 2) */ 3654 #define GPDMA0_MASKDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 MASKDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ 3655 #define GPDMA0_MASKDSTTRAN_CH3_Pos (3UL) /*!< GPDMA0 MASKDSTTRAN: CH3 (Bit 3) */ 3656 #define GPDMA0_MASKDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 MASKDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ 3657 #define GPDMA0_MASKDSTTRAN_CH4_Pos (4UL) /*!< GPDMA0 MASKDSTTRAN: CH4 (Bit 4) */ 3658 #define GPDMA0_MASKDSTTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 MASKDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ 3659 #define GPDMA0_MASKDSTTRAN_CH5_Pos (5UL) /*!< GPDMA0 MASKDSTTRAN: CH5 (Bit 5) */ 3660 #define GPDMA0_MASKDSTTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 MASKDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ 3661 #define GPDMA0_MASKDSTTRAN_CH6_Pos (6UL) /*!< GPDMA0 MASKDSTTRAN: CH6 (Bit 6) */ 3662 #define GPDMA0_MASKDSTTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 MASKDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ 3663 #define GPDMA0_MASKDSTTRAN_CH7_Pos (7UL) /*!< GPDMA0 MASKDSTTRAN: CH7 (Bit 7) */ 3664 #define GPDMA0_MASKDSTTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 MASKDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ 3665 #define GPDMA0_MASKDSTTRAN_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 (Bit 8) */ 3666 #define GPDMA0_MASKDSTTRAN_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ 3667 #define GPDMA0_MASKDSTTRAN_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 (Bit 9) */ 3668 #define GPDMA0_MASKDSTTRAN_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ 3669 #define GPDMA0_MASKDSTTRAN_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 (Bit 10) */ 3670 #define GPDMA0_MASKDSTTRAN_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ 3671 #define GPDMA0_MASKDSTTRAN_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 (Bit 11) */ 3672 #define GPDMA0_MASKDSTTRAN_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ 3673 #define GPDMA0_MASKDSTTRAN_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 (Bit 12) */ 3674 #define GPDMA0_MASKDSTTRAN_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 (Bitfield-Mask: 0x01) */ 3675 #define GPDMA0_MASKDSTTRAN_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 (Bit 13) */ 3676 #define GPDMA0_MASKDSTTRAN_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 (Bitfield-Mask: 0x01) */ 3677 #define GPDMA0_MASKDSTTRAN_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 (Bit 14) */ 3678 #define GPDMA0_MASKDSTTRAN_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 (Bitfield-Mask: 0x01) */ 3679 #define GPDMA0_MASKDSTTRAN_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 (Bit 15) */ 3680 #define GPDMA0_MASKDSTTRAN_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 (Bitfield-Mask: 0x01) */ 3681 3682 /* ------------------------------- GPDMA0_MASKERR ------------------------------- */ 3683 #define GPDMA0_MASKERR_CH0_Pos (0UL) /*!< GPDMA0 MASKERR: CH0 (Bit 0) */ 3684 #define GPDMA0_MASKERR_CH0_Msk (0x1UL) /*!< GPDMA0 MASKERR: CH0 (Bitfield-Mask: 0x01) */ 3685 #define GPDMA0_MASKERR_CH1_Pos (1UL) /*!< GPDMA0 MASKERR: CH1 (Bit 1) */ 3686 #define GPDMA0_MASKERR_CH1_Msk (0x2UL) /*!< GPDMA0 MASKERR: CH1 (Bitfield-Mask: 0x01) */ 3687 #define GPDMA0_MASKERR_CH2_Pos (2UL) /*!< GPDMA0 MASKERR: CH2 (Bit 2) */ 3688 #define GPDMA0_MASKERR_CH2_Msk (0x4UL) /*!< GPDMA0 MASKERR: CH2 (Bitfield-Mask: 0x01) */ 3689 #define GPDMA0_MASKERR_CH3_Pos (3UL) /*!< GPDMA0 MASKERR: CH3 (Bit 3) */ 3690 #define GPDMA0_MASKERR_CH3_Msk (0x8UL) /*!< GPDMA0 MASKERR: CH3 (Bitfield-Mask: 0x01) */ 3691 #define GPDMA0_MASKERR_CH4_Pos (4UL) /*!< GPDMA0 MASKERR: CH4 (Bit 4) */ 3692 #define GPDMA0_MASKERR_CH4_Msk (0x10UL) /*!< GPDMA0 MASKERR: CH4 (Bitfield-Mask: 0x01) */ 3693 #define GPDMA0_MASKERR_CH5_Pos (5UL) /*!< GPDMA0 MASKERR: CH5 (Bit 5) */ 3694 #define GPDMA0_MASKERR_CH5_Msk (0x20UL) /*!< GPDMA0 MASKERR: CH5 (Bitfield-Mask: 0x01) */ 3695 #define GPDMA0_MASKERR_CH6_Pos (6UL) /*!< GPDMA0 MASKERR: CH6 (Bit 6) */ 3696 #define GPDMA0_MASKERR_CH6_Msk (0x40UL) /*!< GPDMA0 MASKERR: CH6 (Bitfield-Mask: 0x01) */ 3697 #define GPDMA0_MASKERR_CH7_Pos (7UL) /*!< GPDMA0 MASKERR: CH7 (Bit 7) */ 3698 #define GPDMA0_MASKERR_CH7_Msk (0x80UL) /*!< GPDMA0 MASKERR: CH7 (Bitfield-Mask: 0x01) */ 3699 #define GPDMA0_MASKERR_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKERR: WE_CH0 (Bit 8) */ 3700 #define GPDMA0_MASKERR_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKERR: WE_CH0 (Bitfield-Mask: 0x01) */ 3701 #define GPDMA0_MASKERR_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKERR: WE_CH1 (Bit 9) */ 3702 #define GPDMA0_MASKERR_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKERR: WE_CH1 (Bitfield-Mask: 0x01) */ 3703 #define GPDMA0_MASKERR_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKERR: WE_CH2 (Bit 10) */ 3704 #define GPDMA0_MASKERR_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKERR: WE_CH2 (Bitfield-Mask: 0x01) */ 3705 #define GPDMA0_MASKERR_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKERR: WE_CH3 (Bit 11) */ 3706 #define GPDMA0_MASKERR_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKERR: WE_CH3 (Bitfield-Mask: 0x01) */ 3707 #define GPDMA0_MASKERR_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKERR: WE_CH4 (Bit 12) */ 3708 #define GPDMA0_MASKERR_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKERR: WE_CH4 (Bitfield-Mask: 0x01) */ 3709 #define GPDMA0_MASKERR_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKERR: WE_CH5 (Bit 13) */ 3710 #define GPDMA0_MASKERR_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKERR: WE_CH5 (Bitfield-Mask: 0x01) */ 3711 #define GPDMA0_MASKERR_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKERR: WE_CH6 (Bit 14) */ 3712 #define GPDMA0_MASKERR_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKERR: WE_CH6 (Bitfield-Mask: 0x01) */ 3713 #define GPDMA0_MASKERR_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKERR: WE_CH7 (Bit 15) */ 3714 #define GPDMA0_MASKERR_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKERR: WE_CH7 (Bitfield-Mask: 0x01) */ 3715 3716 /* ------------------------------- GPDMA0_CLEARTFR ------------------------------ */ 3717 #define GPDMA0_CLEARTFR_CH0_Pos (0UL) /*!< GPDMA0 CLEARTFR: CH0 (Bit 0) */ 3718 #define GPDMA0_CLEARTFR_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARTFR: CH0 (Bitfield-Mask: 0x01) */ 3719 #define GPDMA0_CLEARTFR_CH1_Pos (1UL) /*!< GPDMA0 CLEARTFR: CH1 (Bit 1) */ 3720 #define GPDMA0_CLEARTFR_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARTFR: CH1 (Bitfield-Mask: 0x01) */ 3721 #define GPDMA0_CLEARTFR_CH2_Pos (2UL) /*!< GPDMA0 CLEARTFR: CH2 (Bit 2) */ 3722 #define GPDMA0_CLEARTFR_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARTFR: CH2 (Bitfield-Mask: 0x01) */ 3723 #define GPDMA0_CLEARTFR_CH3_Pos (3UL) /*!< GPDMA0 CLEARTFR: CH3 (Bit 3) */ 3724 #define GPDMA0_CLEARTFR_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARTFR: CH3 (Bitfield-Mask: 0x01) */ 3725 #define GPDMA0_CLEARTFR_CH4_Pos (4UL) /*!< GPDMA0 CLEARTFR: CH4 (Bit 4) */ 3726 #define GPDMA0_CLEARTFR_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARTFR: CH4 (Bitfield-Mask: 0x01) */ 3727 #define GPDMA0_CLEARTFR_CH5_Pos (5UL) /*!< GPDMA0 CLEARTFR: CH5 (Bit 5) */ 3728 #define GPDMA0_CLEARTFR_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARTFR: CH5 (Bitfield-Mask: 0x01) */ 3729 #define GPDMA0_CLEARTFR_CH6_Pos (6UL) /*!< GPDMA0 CLEARTFR: CH6 (Bit 6) */ 3730 #define GPDMA0_CLEARTFR_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARTFR: CH6 (Bitfield-Mask: 0x01) */ 3731 #define GPDMA0_CLEARTFR_CH7_Pos (7UL) /*!< GPDMA0 CLEARTFR: CH7 (Bit 7) */ 3732 #define GPDMA0_CLEARTFR_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARTFR: CH7 (Bitfield-Mask: 0x01) */ 3733 3734 /* ------------------------------ GPDMA0_CLEARBLOCK ----------------------------- */ 3735 #define GPDMA0_CLEARBLOCK_CH0_Pos (0UL) /*!< GPDMA0 CLEARBLOCK: CH0 (Bit 0) */ 3736 #define GPDMA0_CLEARBLOCK_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARBLOCK: CH0 (Bitfield-Mask: 0x01) */ 3737 #define GPDMA0_CLEARBLOCK_CH1_Pos (1UL) /*!< GPDMA0 CLEARBLOCK: CH1 (Bit 1) */ 3738 #define GPDMA0_CLEARBLOCK_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARBLOCK: CH1 (Bitfield-Mask: 0x01) */ 3739 #define GPDMA0_CLEARBLOCK_CH2_Pos (2UL) /*!< GPDMA0 CLEARBLOCK: CH2 (Bit 2) */ 3740 #define GPDMA0_CLEARBLOCK_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARBLOCK: CH2 (Bitfield-Mask: 0x01) */ 3741 #define GPDMA0_CLEARBLOCK_CH3_Pos (3UL) /*!< GPDMA0 CLEARBLOCK: CH3 (Bit 3) */ 3742 #define GPDMA0_CLEARBLOCK_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARBLOCK: CH3 (Bitfield-Mask: 0x01) */ 3743 #define GPDMA0_CLEARBLOCK_CH4_Pos (4UL) /*!< GPDMA0 CLEARBLOCK: CH4 (Bit 4) */ 3744 #define GPDMA0_CLEARBLOCK_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARBLOCK: CH4 (Bitfield-Mask: 0x01) */ 3745 #define GPDMA0_CLEARBLOCK_CH5_Pos (5UL) /*!< GPDMA0 CLEARBLOCK: CH5 (Bit 5) */ 3746 #define GPDMA0_CLEARBLOCK_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARBLOCK: CH5 (Bitfield-Mask: 0x01) */ 3747 #define GPDMA0_CLEARBLOCK_CH6_Pos (6UL) /*!< GPDMA0 CLEARBLOCK: CH6 (Bit 6) */ 3748 #define GPDMA0_CLEARBLOCK_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARBLOCK: CH6 (Bitfield-Mask: 0x01) */ 3749 #define GPDMA0_CLEARBLOCK_CH7_Pos (7UL) /*!< GPDMA0 CLEARBLOCK: CH7 (Bit 7) */ 3750 #define GPDMA0_CLEARBLOCK_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARBLOCK: CH7 (Bitfield-Mask: 0x01) */ 3751 3752 /* ----------------------------- GPDMA0_CLEARSRCTRAN ---------------------------- */ 3753 #define GPDMA0_CLEARSRCTRAN_CH0_Pos (0UL) /*!< GPDMA0 CLEARSRCTRAN: CH0 (Bit 0) */ 3754 #define GPDMA0_CLEARSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ 3755 #define GPDMA0_CLEARSRCTRAN_CH1_Pos (1UL) /*!< GPDMA0 CLEARSRCTRAN: CH1 (Bit 1) */ 3756 #define GPDMA0_CLEARSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ 3757 #define GPDMA0_CLEARSRCTRAN_CH2_Pos (2UL) /*!< GPDMA0 CLEARSRCTRAN: CH2 (Bit 2) */ 3758 #define GPDMA0_CLEARSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ 3759 #define GPDMA0_CLEARSRCTRAN_CH3_Pos (3UL) /*!< GPDMA0 CLEARSRCTRAN: CH3 (Bit 3) */ 3760 #define GPDMA0_CLEARSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ 3761 #define GPDMA0_CLEARSRCTRAN_CH4_Pos (4UL) /*!< GPDMA0 CLEARSRCTRAN: CH4 (Bit 4) */ 3762 #define GPDMA0_CLEARSRCTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ 3763 #define GPDMA0_CLEARSRCTRAN_CH5_Pos (5UL) /*!< GPDMA0 CLEARSRCTRAN: CH5 (Bit 5) */ 3764 #define GPDMA0_CLEARSRCTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ 3765 #define GPDMA0_CLEARSRCTRAN_CH6_Pos (6UL) /*!< GPDMA0 CLEARSRCTRAN: CH6 (Bit 6) */ 3766 #define GPDMA0_CLEARSRCTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ 3767 #define GPDMA0_CLEARSRCTRAN_CH7_Pos (7UL) /*!< GPDMA0 CLEARSRCTRAN: CH7 (Bit 7) */ 3768 #define GPDMA0_CLEARSRCTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ 3769 3770 /* ----------------------------- GPDMA0_CLEARDSTTRAN ---------------------------- */ 3771 #define GPDMA0_CLEARDSTTRAN_CH0_Pos (0UL) /*!< GPDMA0 CLEARDSTTRAN: CH0 (Bit 0) */ 3772 #define GPDMA0_CLEARDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ 3773 #define GPDMA0_CLEARDSTTRAN_CH1_Pos (1UL) /*!< GPDMA0 CLEARDSTTRAN: CH1 (Bit 1) */ 3774 #define GPDMA0_CLEARDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ 3775 #define GPDMA0_CLEARDSTTRAN_CH2_Pos (2UL) /*!< GPDMA0 CLEARDSTTRAN: CH2 (Bit 2) */ 3776 #define GPDMA0_CLEARDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ 3777 #define GPDMA0_CLEARDSTTRAN_CH3_Pos (3UL) /*!< GPDMA0 CLEARDSTTRAN: CH3 (Bit 3) */ 3778 #define GPDMA0_CLEARDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ 3779 #define GPDMA0_CLEARDSTTRAN_CH4_Pos (4UL) /*!< GPDMA0 CLEARDSTTRAN: CH4 (Bit 4) */ 3780 #define GPDMA0_CLEARDSTTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ 3781 #define GPDMA0_CLEARDSTTRAN_CH5_Pos (5UL) /*!< GPDMA0 CLEARDSTTRAN: CH5 (Bit 5) */ 3782 #define GPDMA0_CLEARDSTTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ 3783 #define GPDMA0_CLEARDSTTRAN_CH6_Pos (6UL) /*!< GPDMA0 CLEARDSTTRAN: CH6 (Bit 6) */ 3784 #define GPDMA0_CLEARDSTTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ 3785 #define GPDMA0_CLEARDSTTRAN_CH7_Pos (7UL) /*!< GPDMA0 CLEARDSTTRAN: CH7 (Bit 7) */ 3786 #define GPDMA0_CLEARDSTTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ 3787 3788 /* ------------------------------- GPDMA0_CLEARERR ------------------------------ */ 3789 #define GPDMA0_CLEARERR_CH0_Pos (0UL) /*!< GPDMA0 CLEARERR: CH0 (Bit 0) */ 3790 #define GPDMA0_CLEARERR_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARERR: CH0 (Bitfield-Mask: 0x01) */ 3791 #define GPDMA0_CLEARERR_CH1_Pos (1UL) /*!< GPDMA0 CLEARERR: CH1 (Bit 1) */ 3792 #define GPDMA0_CLEARERR_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARERR: CH1 (Bitfield-Mask: 0x01) */ 3793 #define GPDMA0_CLEARERR_CH2_Pos (2UL) /*!< GPDMA0 CLEARERR: CH2 (Bit 2) */ 3794 #define GPDMA0_CLEARERR_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARERR: CH2 (Bitfield-Mask: 0x01) */ 3795 #define GPDMA0_CLEARERR_CH3_Pos (3UL) /*!< GPDMA0 CLEARERR: CH3 (Bit 3) */ 3796 #define GPDMA0_CLEARERR_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARERR: CH3 (Bitfield-Mask: 0x01) */ 3797 #define GPDMA0_CLEARERR_CH4_Pos (4UL) /*!< GPDMA0 CLEARERR: CH4 (Bit 4) */ 3798 #define GPDMA0_CLEARERR_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARERR: CH4 (Bitfield-Mask: 0x01) */ 3799 #define GPDMA0_CLEARERR_CH5_Pos (5UL) /*!< GPDMA0 CLEARERR: CH5 (Bit 5) */ 3800 #define GPDMA0_CLEARERR_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARERR: CH5 (Bitfield-Mask: 0x01) */ 3801 #define GPDMA0_CLEARERR_CH6_Pos (6UL) /*!< GPDMA0 CLEARERR: CH6 (Bit 6) */ 3802 #define GPDMA0_CLEARERR_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARERR: CH6 (Bitfield-Mask: 0x01) */ 3803 #define GPDMA0_CLEARERR_CH7_Pos (7UL) /*!< GPDMA0 CLEARERR: CH7 (Bit 7) */ 3804 #define GPDMA0_CLEARERR_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARERR: CH7 (Bitfield-Mask: 0x01) */ 3805 3806 /* ------------------------------ GPDMA0_STATUSINT ------------------------------ */ 3807 #define GPDMA0_STATUSINT_TFR_Pos (0UL) /*!< GPDMA0 STATUSINT: TFR (Bit 0) */ 3808 #define GPDMA0_STATUSINT_TFR_Msk (0x1UL) /*!< GPDMA0 STATUSINT: TFR (Bitfield-Mask: 0x01) */ 3809 #define GPDMA0_STATUSINT_BLOCK_Pos (1UL) /*!< GPDMA0 STATUSINT: BLOCK (Bit 1) */ 3810 #define GPDMA0_STATUSINT_BLOCK_Msk (0x2UL) /*!< GPDMA0 STATUSINT: BLOCK (Bitfield-Mask: 0x01) */ 3811 #define GPDMA0_STATUSINT_SRCT_Pos (2UL) /*!< GPDMA0 STATUSINT: SRCT (Bit 2) */ 3812 #define GPDMA0_STATUSINT_SRCT_Msk (0x4UL) /*!< GPDMA0 STATUSINT: SRCT (Bitfield-Mask: 0x01) */ 3813 #define GPDMA0_STATUSINT_DSTT_Pos (3UL) /*!< GPDMA0 STATUSINT: DSTT (Bit 3) */ 3814 #define GPDMA0_STATUSINT_DSTT_Msk (0x8UL) /*!< GPDMA0 STATUSINT: DSTT (Bitfield-Mask: 0x01) */ 3815 #define GPDMA0_STATUSINT_ERR_Pos (4UL) /*!< GPDMA0 STATUSINT: ERR (Bit 4) */ 3816 #define GPDMA0_STATUSINT_ERR_Msk (0x10UL) /*!< GPDMA0 STATUSINT: ERR (Bitfield-Mask: 0x01) */ 3817 3818 /* ------------------------------ GPDMA0_REQSRCREG ------------------------------ */ 3819 #define GPDMA0_REQSRCREG_CH0_Pos (0UL) /*!< GPDMA0 REQSRCREG: CH0 (Bit 0) */ 3820 #define GPDMA0_REQSRCREG_CH0_Msk (0x1UL) /*!< GPDMA0 REQSRCREG: CH0 (Bitfield-Mask: 0x01) */ 3821 #define GPDMA0_REQSRCREG_CH1_Pos (1UL) /*!< GPDMA0 REQSRCREG: CH1 (Bit 1) */ 3822 #define GPDMA0_REQSRCREG_CH1_Msk (0x2UL) /*!< GPDMA0 REQSRCREG: CH1 (Bitfield-Mask: 0x01) */ 3823 #define GPDMA0_REQSRCREG_CH2_Pos (2UL) /*!< GPDMA0 REQSRCREG: CH2 (Bit 2) */ 3824 #define GPDMA0_REQSRCREG_CH2_Msk (0x4UL) /*!< GPDMA0 REQSRCREG: CH2 (Bitfield-Mask: 0x01) */ 3825 #define GPDMA0_REQSRCREG_CH3_Pos (3UL) /*!< GPDMA0 REQSRCREG: CH3 (Bit 3) */ 3826 #define GPDMA0_REQSRCREG_CH3_Msk (0x8UL) /*!< GPDMA0 REQSRCREG: CH3 (Bitfield-Mask: 0x01) */ 3827 #define GPDMA0_REQSRCREG_CH4_Pos (4UL) /*!< GPDMA0 REQSRCREG: CH4 (Bit 4) */ 3828 #define GPDMA0_REQSRCREG_CH4_Msk (0x10UL) /*!< GPDMA0 REQSRCREG: CH4 (Bitfield-Mask: 0x01) */ 3829 #define GPDMA0_REQSRCREG_CH5_Pos (5UL) /*!< GPDMA0 REQSRCREG: CH5 (Bit 5) */ 3830 #define GPDMA0_REQSRCREG_CH5_Msk (0x20UL) /*!< GPDMA0 REQSRCREG: CH5 (Bitfield-Mask: 0x01) */ 3831 #define GPDMA0_REQSRCREG_CH6_Pos (6UL) /*!< GPDMA0 REQSRCREG: CH6 (Bit 6) */ 3832 #define GPDMA0_REQSRCREG_CH6_Msk (0x40UL) /*!< GPDMA0 REQSRCREG: CH6 (Bitfield-Mask: 0x01) */ 3833 #define GPDMA0_REQSRCREG_CH7_Pos (7UL) /*!< GPDMA0 REQSRCREG: CH7 (Bit 7) */ 3834 #define GPDMA0_REQSRCREG_CH7_Msk (0x80UL) /*!< GPDMA0 REQSRCREG: CH7 (Bitfield-Mask: 0x01) */ 3835 #define GPDMA0_REQSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA0 REQSRCREG: WE_CH0 (Bit 8) */ 3836 #define GPDMA0_REQSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 REQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ 3837 #define GPDMA0_REQSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA0 REQSRCREG: WE_CH1 (Bit 9) */ 3838 #define GPDMA0_REQSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 REQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ 3839 #define GPDMA0_REQSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA0 REQSRCREG: WE_CH2 (Bit 10) */ 3840 #define GPDMA0_REQSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 REQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ 3841 #define GPDMA0_REQSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA0 REQSRCREG: WE_CH3 (Bit 11) */ 3842 #define GPDMA0_REQSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 REQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ 3843 #define GPDMA0_REQSRCREG_WE_CH4_Pos (12UL) /*!< GPDMA0 REQSRCREG: WE_CH4 (Bit 12) */ 3844 #define GPDMA0_REQSRCREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 REQSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ 3845 #define GPDMA0_REQSRCREG_WE_CH5_Pos (13UL) /*!< GPDMA0 REQSRCREG: WE_CH5 (Bit 13) */ 3846 #define GPDMA0_REQSRCREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 REQSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ 3847 #define GPDMA0_REQSRCREG_WE_CH6_Pos (14UL) /*!< GPDMA0 REQSRCREG: WE_CH6 (Bit 14) */ 3848 #define GPDMA0_REQSRCREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 REQSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ 3849 #define GPDMA0_REQSRCREG_WE_CH7_Pos (15UL) /*!< GPDMA0 REQSRCREG: WE_CH7 (Bit 15) */ 3850 #define GPDMA0_REQSRCREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 REQSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ 3851 3852 /* ------------------------------ GPDMA0_REQDSTREG ------------------------------ */ 3853 #define GPDMA0_REQDSTREG_CH0_Pos (0UL) /*!< GPDMA0 REQDSTREG: CH0 (Bit 0) */ 3854 #define GPDMA0_REQDSTREG_CH0_Msk (0x1UL) /*!< GPDMA0 REQDSTREG: CH0 (Bitfield-Mask: 0x01) */ 3855 #define GPDMA0_REQDSTREG_CH1_Pos (1UL) /*!< GPDMA0 REQDSTREG: CH1 (Bit 1) */ 3856 #define GPDMA0_REQDSTREG_CH1_Msk (0x2UL) /*!< GPDMA0 REQDSTREG: CH1 (Bitfield-Mask: 0x01) */ 3857 #define GPDMA0_REQDSTREG_CH2_Pos (2UL) /*!< GPDMA0 REQDSTREG: CH2 (Bit 2) */ 3858 #define GPDMA0_REQDSTREG_CH2_Msk (0x4UL) /*!< GPDMA0 REQDSTREG: CH2 (Bitfield-Mask: 0x01) */ 3859 #define GPDMA0_REQDSTREG_CH3_Pos (3UL) /*!< GPDMA0 REQDSTREG: CH3 (Bit 3) */ 3860 #define GPDMA0_REQDSTREG_CH3_Msk (0x8UL) /*!< GPDMA0 REQDSTREG: CH3 (Bitfield-Mask: 0x01) */ 3861 #define GPDMA0_REQDSTREG_CH4_Pos (4UL) /*!< GPDMA0 REQDSTREG: CH4 (Bit 4) */ 3862 #define GPDMA0_REQDSTREG_CH4_Msk (0x10UL) /*!< GPDMA0 REQDSTREG: CH4 (Bitfield-Mask: 0x01) */ 3863 #define GPDMA0_REQDSTREG_CH5_Pos (5UL) /*!< GPDMA0 REQDSTREG: CH5 (Bit 5) */ 3864 #define GPDMA0_REQDSTREG_CH5_Msk (0x20UL) /*!< GPDMA0 REQDSTREG: CH5 (Bitfield-Mask: 0x01) */ 3865 #define GPDMA0_REQDSTREG_CH6_Pos (6UL) /*!< GPDMA0 REQDSTREG: CH6 (Bit 6) */ 3866 #define GPDMA0_REQDSTREG_CH6_Msk (0x40UL) /*!< GPDMA0 REQDSTREG: CH6 (Bitfield-Mask: 0x01) */ 3867 #define GPDMA0_REQDSTREG_CH7_Pos (7UL) /*!< GPDMA0 REQDSTREG: CH7 (Bit 7) */ 3868 #define GPDMA0_REQDSTREG_CH7_Msk (0x80UL) /*!< GPDMA0 REQDSTREG: CH7 (Bitfield-Mask: 0x01) */ 3869 #define GPDMA0_REQDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA0 REQDSTREG: WE_CH0 (Bit 8) */ 3870 #define GPDMA0_REQDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 REQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ 3871 #define GPDMA0_REQDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA0 REQDSTREG: WE_CH1 (Bit 9) */ 3872 #define GPDMA0_REQDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 REQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ 3873 #define GPDMA0_REQDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA0 REQDSTREG: WE_CH2 (Bit 10) */ 3874 #define GPDMA0_REQDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 REQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ 3875 #define GPDMA0_REQDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA0 REQDSTREG: WE_CH3 (Bit 11) */ 3876 #define GPDMA0_REQDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 REQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ 3877 #define GPDMA0_REQDSTREG_WE_CH4_Pos (12UL) /*!< GPDMA0 REQDSTREG: WE_CH4 (Bit 12) */ 3878 #define GPDMA0_REQDSTREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 REQDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ 3879 #define GPDMA0_REQDSTREG_WE_CH5_Pos (13UL) /*!< GPDMA0 REQDSTREG: WE_CH5 (Bit 13) */ 3880 #define GPDMA0_REQDSTREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 REQDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ 3881 #define GPDMA0_REQDSTREG_WE_CH6_Pos (14UL) /*!< GPDMA0 REQDSTREG: WE_CH6 (Bit 14) */ 3882 #define GPDMA0_REQDSTREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 REQDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ 3883 #define GPDMA0_REQDSTREG_WE_CH7_Pos (15UL) /*!< GPDMA0 REQDSTREG: WE_CH7 (Bit 15) */ 3884 #define GPDMA0_REQDSTREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 REQDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ 3885 3886 /* ----------------------------- GPDMA0_SGLREQSRCREG ---------------------------- */ 3887 #define GPDMA0_SGLREQSRCREG_CH0_Pos (0UL) /*!< GPDMA0 SGLREQSRCREG: CH0 (Bit 0) */ 3888 #define GPDMA0_SGLREQSRCREG_CH0_Msk (0x1UL) /*!< GPDMA0 SGLREQSRCREG: CH0 (Bitfield-Mask: 0x01) */ 3889 #define GPDMA0_SGLREQSRCREG_CH1_Pos (1UL) /*!< GPDMA0 SGLREQSRCREG: CH1 (Bit 1) */ 3890 #define GPDMA0_SGLREQSRCREG_CH1_Msk (0x2UL) /*!< GPDMA0 SGLREQSRCREG: CH1 (Bitfield-Mask: 0x01) */ 3891 #define GPDMA0_SGLREQSRCREG_CH2_Pos (2UL) /*!< GPDMA0 SGLREQSRCREG: CH2 (Bit 2) */ 3892 #define GPDMA0_SGLREQSRCREG_CH2_Msk (0x4UL) /*!< GPDMA0 SGLREQSRCREG: CH2 (Bitfield-Mask: 0x01) */ 3893 #define GPDMA0_SGLREQSRCREG_CH3_Pos (3UL) /*!< GPDMA0 SGLREQSRCREG: CH3 (Bit 3) */ 3894 #define GPDMA0_SGLREQSRCREG_CH3_Msk (0x8UL) /*!< GPDMA0 SGLREQSRCREG: CH3 (Bitfield-Mask: 0x01) */ 3895 #define GPDMA0_SGLREQSRCREG_CH4_Pos (4UL) /*!< GPDMA0 SGLREQSRCREG: CH4 (Bit 4) */ 3896 #define GPDMA0_SGLREQSRCREG_CH4_Msk (0x10UL) /*!< GPDMA0 SGLREQSRCREG: CH4 (Bitfield-Mask: 0x01) */ 3897 #define GPDMA0_SGLREQSRCREG_CH5_Pos (5UL) /*!< GPDMA0 SGLREQSRCREG: CH5 (Bit 5) */ 3898 #define GPDMA0_SGLREQSRCREG_CH5_Msk (0x20UL) /*!< GPDMA0 SGLREQSRCREG: CH5 (Bitfield-Mask: 0x01) */ 3899 #define GPDMA0_SGLREQSRCREG_CH6_Pos (6UL) /*!< GPDMA0 SGLREQSRCREG: CH6 (Bit 6) */ 3900 #define GPDMA0_SGLREQSRCREG_CH6_Msk (0x40UL) /*!< GPDMA0 SGLREQSRCREG: CH6 (Bitfield-Mask: 0x01) */ 3901 #define GPDMA0_SGLREQSRCREG_CH7_Pos (7UL) /*!< GPDMA0 SGLREQSRCREG: CH7 (Bit 7) */ 3902 #define GPDMA0_SGLREQSRCREG_CH7_Msk (0x80UL) /*!< GPDMA0 SGLREQSRCREG: CH7 (Bitfield-Mask: 0x01) */ 3903 #define GPDMA0_SGLREQSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 (Bit 8) */ 3904 #define GPDMA0_SGLREQSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ 3905 #define GPDMA0_SGLREQSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 (Bit 9) */ 3906 #define GPDMA0_SGLREQSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ 3907 #define GPDMA0_SGLREQSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 (Bit 10) */ 3908 #define GPDMA0_SGLREQSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ 3909 #define GPDMA0_SGLREQSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 (Bit 11) */ 3910 #define GPDMA0_SGLREQSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ 3911 #define GPDMA0_SGLREQSRCREG_WE_CH4_Pos (12UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 (Bit 12) */ 3912 #define GPDMA0_SGLREQSRCREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ 3913 #define GPDMA0_SGLREQSRCREG_WE_CH5_Pos (13UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 (Bit 13) */ 3914 #define GPDMA0_SGLREQSRCREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ 3915 #define GPDMA0_SGLREQSRCREG_WE_CH6_Pos (14UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 (Bit 14) */ 3916 #define GPDMA0_SGLREQSRCREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ 3917 #define GPDMA0_SGLREQSRCREG_WE_CH7_Pos (15UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 (Bit 15) */ 3918 #define GPDMA0_SGLREQSRCREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ 3919 3920 /* ----------------------------- GPDMA0_SGLREQDSTREG ---------------------------- */ 3921 #define GPDMA0_SGLREQDSTREG_CH0_Pos (0UL) /*!< GPDMA0 SGLREQDSTREG: CH0 (Bit 0) */ 3922 #define GPDMA0_SGLREQDSTREG_CH0_Msk (0x1UL) /*!< GPDMA0 SGLREQDSTREG: CH0 (Bitfield-Mask: 0x01) */ 3923 #define GPDMA0_SGLREQDSTREG_CH1_Pos (1UL) /*!< GPDMA0 SGLREQDSTREG: CH1 (Bit 1) */ 3924 #define GPDMA0_SGLREQDSTREG_CH1_Msk (0x2UL) /*!< GPDMA0 SGLREQDSTREG: CH1 (Bitfield-Mask: 0x01) */ 3925 #define GPDMA0_SGLREQDSTREG_CH2_Pos (2UL) /*!< GPDMA0 SGLREQDSTREG: CH2 (Bit 2) */ 3926 #define GPDMA0_SGLREQDSTREG_CH2_Msk (0x4UL) /*!< GPDMA0 SGLREQDSTREG: CH2 (Bitfield-Mask: 0x01) */ 3927 #define GPDMA0_SGLREQDSTREG_CH3_Pos (3UL) /*!< GPDMA0 SGLREQDSTREG: CH3 (Bit 3) */ 3928 #define GPDMA0_SGLREQDSTREG_CH3_Msk (0x8UL) /*!< GPDMA0 SGLREQDSTREG: CH3 (Bitfield-Mask: 0x01) */ 3929 #define GPDMA0_SGLREQDSTREG_CH4_Pos (4UL) /*!< GPDMA0 SGLREQDSTREG: CH4 (Bit 4) */ 3930 #define GPDMA0_SGLREQDSTREG_CH4_Msk (0x10UL) /*!< GPDMA0 SGLREQDSTREG: CH4 (Bitfield-Mask: 0x01) */ 3931 #define GPDMA0_SGLREQDSTREG_CH5_Pos (5UL) /*!< GPDMA0 SGLREQDSTREG: CH5 (Bit 5) */ 3932 #define GPDMA0_SGLREQDSTREG_CH5_Msk (0x20UL) /*!< GPDMA0 SGLREQDSTREG: CH5 (Bitfield-Mask: 0x01) */ 3933 #define GPDMA0_SGLREQDSTREG_CH6_Pos (6UL) /*!< GPDMA0 SGLREQDSTREG: CH6 (Bit 6) */ 3934 #define GPDMA0_SGLREQDSTREG_CH6_Msk (0x40UL) /*!< GPDMA0 SGLREQDSTREG: CH6 (Bitfield-Mask: 0x01) */ 3935 #define GPDMA0_SGLREQDSTREG_CH7_Pos (7UL) /*!< GPDMA0 SGLREQDSTREG: CH7 (Bit 7) */ 3936 #define GPDMA0_SGLREQDSTREG_CH7_Msk (0x80UL) /*!< GPDMA0 SGLREQDSTREG: CH7 (Bitfield-Mask: 0x01) */ 3937 #define GPDMA0_SGLREQDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 (Bit 8) */ 3938 #define GPDMA0_SGLREQDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ 3939 #define GPDMA0_SGLREQDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 (Bit 9) */ 3940 #define GPDMA0_SGLREQDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ 3941 #define GPDMA0_SGLREQDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 (Bit 10) */ 3942 #define GPDMA0_SGLREQDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ 3943 #define GPDMA0_SGLREQDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 (Bit 11) */ 3944 #define GPDMA0_SGLREQDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ 3945 #define GPDMA0_SGLREQDSTREG_WE_CH4_Pos (12UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 (Bit 12) */ 3946 #define GPDMA0_SGLREQDSTREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ 3947 #define GPDMA0_SGLREQDSTREG_WE_CH5_Pos (13UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 (Bit 13) */ 3948 #define GPDMA0_SGLREQDSTREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ 3949 #define GPDMA0_SGLREQDSTREG_WE_CH6_Pos (14UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 (Bit 14) */ 3950 #define GPDMA0_SGLREQDSTREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ 3951 #define GPDMA0_SGLREQDSTREG_WE_CH7_Pos (15UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 (Bit 15) */ 3952 #define GPDMA0_SGLREQDSTREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ 3953 3954 /* ------------------------------ GPDMA0_LSTSRCREG ------------------------------ */ 3955 #define GPDMA0_LSTSRCREG_CH0_Pos (0UL) /*!< GPDMA0 LSTSRCREG: CH0 (Bit 0) */ 3956 #define GPDMA0_LSTSRCREG_CH0_Msk (0x1UL) /*!< GPDMA0 LSTSRCREG: CH0 (Bitfield-Mask: 0x01) */ 3957 #define GPDMA0_LSTSRCREG_CH1_Pos (1UL) /*!< GPDMA0 LSTSRCREG: CH1 (Bit 1) */ 3958 #define GPDMA0_LSTSRCREG_CH1_Msk (0x2UL) /*!< GPDMA0 LSTSRCREG: CH1 (Bitfield-Mask: 0x01) */ 3959 #define GPDMA0_LSTSRCREG_CH2_Pos (2UL) /*!< GPDMA0 LSTSRCREG: CH2 (Bit 2) */ 3960 #define GPDMA0_LSTSRCREG_CH2_Msk (0x4UL) /*!< GPDMA0 LSTSRCREG: CH2 (Bitfield-Mask: 0x01) */ 3961 #define GPDMA0_LSTSRCREG_CH3_Pos (3UL) /*!< GPDMA0 LSTSRCREG: CH3 (Bit 3) */ 3962 #define GPDMA0_LSTSRCREG_CH3_Msk (0x8UL) /*!< GPDMA0 LSTSRCREG: CH3 (Bitfield-Mask: 0x01) */ 3963 #define GPDMA0_LSTSRCREG_CH4_Pos (4UL) /*!< GPDMA0 LSTSRCREG: CH4 (Bit 4) */ 3964 #define GPDMA0_LSTSRCREG_CH4_Msk (0x10UL) /*!< GPDMA0 LSTSRCREG: CH4 (Bitfield-Mask: 0x01) */ 3965 #define GPDMA0_LSTSRCREG_CH5_Pos (5UL) /*!< GPDMA0 LSTSRCREG: CH5 (Bit 5) */ 3966 #define GPDMA0_LSTSRCREG_CH5_Msk (0x20UL) /*!< GPDMA0 LSTSRCREG: CH5 (Bitfield-Mask: 0x01) */ 3967 #define GPDMA0_LSTSRCREG_CH6_Pos (6UL) /*!< GPDMA0 LSTSRCREG: CH6 (Bit 6) */ 3968 #define GPDMA0_LSTSRCREG_CH6_Msk (0x40UL) /*!< GPDMA0 LSTSRCREG: CH6 (Bitfield-Mask: 0x01) */ 3969 #define GPDMA0_LSTSRCREG_CH7_Pos (7UL) /*!< GPDMA0 LSTSRCREG: CH7 (Bit 7) */ 3970 #define GPDMA0_LSTSRCREG_CH7_Msk (0x80UL) /*!< GPDMA0 LSTSRCREG: CH7 (Bitfield-Mask: 0x01) */ 3971 #define GPDMA0_LSTSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA0 LSTSRCREG: WE_CH0 (Bit 8) */ 3972 #define GPDMA0_LSTSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 LSTSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ 3973 #define GPDMA0_LSTSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA0 LSTSRCREG: WE_CH1 (Bit 9) */ 3974 #define GPDMA0_LSTSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 LSTSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ 3975 #define GPDMA0_LSTSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA0 LSTSRCREG: WE_CH2 (Bit 10) */ 3976 #define GPDMA0_LSTSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 LSTSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ 3977 #define GPDMA0_LSTSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA0 LSTSRCREG: WE_CH3 (Bit 11) */ 3978 #define GPDMA0_LSTSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 LSTSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ 3979 #define GPDMA0_LSTSRCREG_WE_CH4_Pos (12UL) /*!< GPDMA0 LSTSRCREG: WE_CH4 (Bit 12) */ 3980 #define GPDMA0_LSTSRCREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 LSTSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ 3981 #define GPDMA0_LSTSRCREG_WE_CH5_Pos (13UL) /*!< GPDMA0 LSTSRCREG: WE_CH5 (Bit 13) */ 3982 #define GPDMA0_LSTSRCREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 LSTSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ 3983 #define GPDMA0_LSTSRCREG_WE_CH6_Pos (14UL) /*!< GPDMA0 LSTSRCREG: WE_CH6 (Bit 14) */ 3984 #define GPDMA0_LSTSRCREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 LSTSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ 3985 #define GPDMA0_LSTSRCREG_WE_CH7_Pos (15UL) /*!< GPDMA0 LSTSRCREG: WE_CH7 (Bit 15) */ 3986 #define GPDMA0_LSTSRCREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 LSTSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ 3987 3988 /* ------------------------------ GPDMA0_LSTDSTREG ------------------------------ */ 3989 #define GPDMA0_LSTDSTREG_CH0_Pos (0UL) /*!< GPDMA0 LSTDSTREG: CH0 (Bit 0) */ 3990 #define GPDMA0_LSTDSTREG_CH0_Msk (0x1UL) /*!< GPDMA0 LSTDSTREG: CH0 (Bitfield-Mask: 0x01) */ 3991 #define GPDMA0_LSTDSTREG_CH1_Pos (1UL) /*!< GPDMA0 LSTDSTREG: CH1 (Bit 1) */ 3992 #define GPDMA0_LSTDSTREG_CH1_Msk (0x2UL) /*!< GPDMA0 LSTDSTREG: CH1 (Bitfield-Mask: 0x01) */ 3993 #define GPDMA0_LSTDSTREG_CH2_Pos (2UL) /*!< GPDMA0 LSTDSTREG: CH2 (Bit 2) */ 3994 #define GPDMA0_LSTDSTREG_CH2_Msk (0x4UL) /*!< GPDMA0 LSTDSTREG: CH2 (Bitfield-Mask: 0x01) */ 3995 #define GPDMA0_LSTDSTREG_CH3_Pos (3UL) /*!< GPDMA0 LSTDSTREG: CH3 (Bit 3) */ 3996 #define GPDMA0_LSTDSTREG_CH3_Msk (0x8UL) /*!< GPDMA0 LSTDSTREG: CH3 (Bitfield-Mask: 0x01) */ 3997 #define GPDMA0_LSTDSTREG_CH4_Pos (4UL) /*!< GPDMA0 LSTDSTREG: CH4 (Bit 4) */ 3998 #define GPDMA0_LSTDSTREG_CH4_Msk (0x10UL) /*!< GPDMA0 LSTDSTREG: CH4 (Bitfield-Mask: 0x01) */ 3999 #define GPDMA0_LSTDSTREG_CH5_Pos (5UL) /*!< GPDMA0 LSTDSTREG: CH5 (Bit 5) */ 4000 #define GPDMA0_LSTDSTREG_CH5_Msk (0x20UL) /*!< GPDMA0 LSTDSTREG: CH5 (Bitfield-Mask: 0x01) */ 4001 #define GPDMA0_LSTDSTREG_CH6_Pos (6UL) /*!< GPDMA0 LSTDSTREG: CH6 (Bit 6) */ 4002 #define GPDMA0_LSTDSTREG_CH6_Msk (0x40UL) /*!< GPDMA0 LSTDSTREG: CH6 (Bitfield-Mask: 0x01) */ 4003 #define GPDMA0_LSTDSTREG_CH7_Pos (7UL) /*!< GPDMA0 LSTDSTREG: CH7 (Bit 7) */ 4004 #define GPDMA0_LSTDSTREG_CH7_Msk (0x80UL) /*!< GPDMA0 LSTDSTREG: CH7 (Bitfield-Mask: 0x01) */ 4005 #define GPDMA0_LSTDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA0 LSTDSTREG: WE_CH0 (Bit 8) */ 4006 #define GPDMA0_LSTDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 LSTDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ 4007 #define GPDMA0_LSTDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA0 LSTDSTREG: WE_CH1 (Bit 9) */ 4008 #define GPDMA0_LSTDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 LSTDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ 4009 #define GPDMA0_LSTDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA0 LSTDSTREG: WE_CH2 (Bit 10) */ 4010 #define GPDMA0_LSTDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 LSTDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ 4011 #define GPDMA0_LSTDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA0 LSTDSTREG: WE_CH3 (Bit 11) */ 4012 #define GPDMA0_LSTDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 LSTDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ 4013 #define GPDMA0_LSTDSTREG_WE_CH4_Pos (12UL) /*!< GPDMA0 LSTDSTREG: WE_CH4 (Bit 12) */ 4014 #define GPDMA0_LSTDSTREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 LSTDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ 4015 #define GPDMA0_LSTDSTREG_WE_CH5_Pos (13UL) /*!< GPDMA0 LSTDSTREG: WE_CH5 (Bit 13) */ 4016 #define GPDMA0_LSTDSTREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 LSTDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ 4017 #define GPDMA0_LSTDSTREG_WE_CH6_Pos (14UL) /*!< GPDMA0 LSTDSTREG: WE_CH6 (Bit 14) */ 4018 #define GPDMA0_LSTDSTREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 LSTDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ 4019 #define GPDMA0_LSTDSTREG_WE_CH7_Pos (15UL) /*!< GPDMA0 LSTDSTREG: WE_CH7 (Bit 15) */ 4020 #define GPDMA0_LSTDSTREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 LSTDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ 4021 4022 /* ------------------------------ GPDMA0_DMACFGREG ------------------------------ */ 4023 #define GPDMA0_DMACFGREG_DMA_EN_Pos (0UL) /*!< GPDMA0 DMACFGREG: DMA_EN (Bit 0) */ 4024 #define GPDMA0_DMACFGREG_DMA_EN_Msk (0x1UL) /*!< GPDMA0 DMACFGREG: DMA_EN (Bitfield-Mask: 0x01) */ 4025 4026 /* ------------------------------- GPDMA0_CHENREG ------------------------------- */ 4027 #define GPDMA0_CHENREG_CH_Pos (0UL) /*!< GPDMA0 CHENREG: CH (Bit 0) */ 4028 #define GPDMA0_CHENREG_CH_Msk (0xffUL) /*!< GPDMA0 CHENREG: CH (Bitfield-Mask: 0xff) */ 4029 #define GPDMA0_CHENREG_WE_CH_Pos (8UL) /*!< GPDMA0 CHENREG: WE_CH (Bit 8) */ 4030 #define GPDMA0_CHENREG_WE_CH_Msk (0xff00UL) /*!< GPDMA0 CHENREG: WE_CH (Bitfield-Mask: 0xff) */ 4031 4032 /* ---------------------------------- GPDMA0_ID --------------------------------- */ 4033 #define GPDMA0_ID_VALUE_Pos (0UL) /*!< GPDMA0 ID: VALUE (Bit 0) */ 4034 #define GPDMA0_ID_VALUE_Msk (0xffffffffUL) /*!< GPDMA0 ID: VALUE (Bitfield-Mask: 0xffffffff) */ 4035 4036 /* --------------------------------- GPDMA0_TYPE -------------------------------- */ 4037 #define GPDMA0_TYPE_VALUE_Pos (0UL) /*!< GPDMA0 TYPE: VALUE (Bit 0) */ 4038 #define GPDMA0_TYPE_VALUE_Msk (0xffffffffUL) /*!< GPDMA0 TYPE: VALUE (Bitfield-Mask: 0xffffffff) */ 4039 4040 /* ------------------------------- GPDMA0_VERSION ------------------------------- */ 4041 #define GPDMA0_VERSION_VALUE_Pos (0UL) /*!< GPDMA0 VERSION: VALUE (Bit 0) */ 4042 #define GPDMA0_VERSION_VALUE_Msk (0xffffffffUL) /*!< GPDMA0 VERSION: VALUE (Bitfield-Mask: 0xffffffff) */ 4043 4044 4045 /* ================================================================================ */ 4046 /* ================ Group 'GPDMA0_CH0_1' Position & Mask ================ */ 4047 /* ================================================================================ */ 4048 4049 4050 /* ------------------------------ GPDMA0_CH_SAR ------------------------------ */ 4051 #define GPDMA0_CH_SAR_SAR_Pos (0UL) /*!< GPDMA0_CH0_1 SAR: SAR (Bit 0) */ 4052 #define GPDMA0_CH_SAR_SAR_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 SAR: SAR (Bitfield-Mask: 0xffffffff) */ 4053 4054 /* ------------------------------ GPDMA0_CH_DAR ------------------------------ */ 4055 #define GPDMA0_CH_DAR_DAR_Pos (0UL) /*!< GPDMA0_CH0_1 DAR: DAR (Bit 0) */ 4056 #define GPDMA0_CH_DAR_DAR_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 DAR: DAR (Bitfield-Mask: 0xffffffff) */ 4057 4058 /* ------------------------------ GPDMA0_CH_LLP ------------------------------ */ 4059 #define GPDMA0_CH_LLP_LOC_Pos (2UL) /*!< GPDMA0_CH0_1 LLP: LOC (Bit 2) */ 4060 #define GPDMA0_CH_LLP_LOC_Msk (0xfffffffcUL) /*!< GPDMA0_CH0_1 LLP: LOC (Bitfield-Mask: 0x3fffffff) */ 4061 4062 /* ------------------------------ GPDMA0_CH_CTLL ----------------------------- */ 4063 #define GPDMA0_CH_CTLL_INT_EN_Pos (0UL) /*!< GPDMA0_CH0_1 CTLL: INT_EN (Bit 0) */ 4064 #define GPDMA0_CH_CTLL_INT_EN_Msk (0x1UL) /*!< GPDMA0_CH0_1 CTLL: INT_EN (Bitfield-Mask: 0x01) */ 4065 #define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos (1UL) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH (Bit 1) */ 4066 #define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk (0xeUL) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH (Bitfield-Mask: 0x07) */ 4067 #define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos (4UL) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH (Bit 4) */ 4068 #define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk (0x70UL) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH (Bitfield-Mask: 0x07) */ 4069 #define GPDMA0_CH_CTLL_DINC_Pos (7UL) /*!< GPDMA0_CH0_1 CTLL: DINC (Bit 7) */ 4070 #define GPDMA0_CH_CTLL_DINC_Msk (0x180UL) /*!< GPDMA0_CH0_1 CTLL: DINC (Bitfield-Mask: 0x03) */ 4071 #define GPDMA0_CH_CTLL_SINC_Pos (9UL) /*!< GPDMA0_CH0_1 CTLL: SINC (Bit 9) */ 4072 #define GPDMA0_CH_CTLL_SINC_Msk (0x600UL) /*!< GPDMA0_CH0_1 CTLL: SINC (Bitfield-Mask: 0x03) */ 4073 #define GPDMA0_CH_CTLL_DEST_MSIZE_Pos (11UL) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE (Bit 11) */ 4074 #define GPDMA0_CH_CTLL_DEST_MSIZE_Msk (0x3800UL) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE (Bitfield-Mask: 0x07) */ 4075 #define GPDMA0_CH_CTLL_SRC_MSIZE_Pos (14UL) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE (Bit 14) */ 4076 #define GPDMA0_CH_CTLL_SRC_MSIZE_Msk (0x1c000UL) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE (Bitfield-Mask: 0x07) */ 4077 #define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos (17UL) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN (Bit 17) */ 4078 #define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk (0x20000UL) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN (Bitfield-Mask: 0x01) */ 4079 #define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos (18UL) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN (Bit 18) */ 4080 #define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk (0x40000UL) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN (Bitfield-Mask: 0x01) */ 4081 #define GPDMA0_CH_CTLL_TT_FC_Pos (20UL) /*!< GPDMA0_CH0_1 CTLL: TT_FC (Bit 20) */ 4082 #define GPDMA0_CH_CTLL_TT_FC_Msk (0x700000UL) /*!< GPDMA0_CH0_1 CTLL: TT_FC (Bitfield-Mask: 0x07) */ 4083 #define GPDMA0_CH_CTLL_LLP_DST_EN_Pos (27UL) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN (Bit 27) */ 4084 #define GPDMA0_CH_CTLL_LLP_DST_EN_Msk (0x8000000UL) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN (Bitfield-Mask: 0x01) */ 4085 #define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos (28UL) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN (Bit 28) */ 4086 #define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk (0x10000000UL) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN (Bitfield-Mask: 0x01) */ 4087 4088 /* ------------------------------ GPDMA0_CH_CTLH ----------------------------- */ 4089 #define GPDMA0_CH_CTLH_BLOCK_TS_Pos (0UL) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS (Bit 0) */ 4090 #define GPDMA0_CH_CTLH_BLOCK_TS_Msk (0xfffUL) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS (Bitfield-Mask: 0xfff) */ 4091 #define GPDMA0_CH_CTLH_DONE_Pos (12UL) /*!< GPDMA0_CH0_1 CTLH: DONE (Bit 12) */ 4092 #define GPDMA0_CH_CTLH_DONE_Msk (0x1000UL) /*!< GPDMA0_CH0_1 CTLH: DONE (Bitfield-Mask: 0x01) */ 4093 4094 /* ----------------------------- GPDMA0_CH_SSTAT ----------------------------- */ 4095 #define GPDMA0_CH_SSTAT_SSTAT_Pos (0UL) /*!< GPDMA0_CH0_1 SSTAT: SSTAT (Bit 0) */ 4096 #define GPDMA0_CH_SSTAT_SSTAT_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 SSTAT: SSTAT (Bitfield-Mask: 0xffffffff) */ 4097 4098 /* ----------------------------- GPDMA0_CH_DSTAT ----------------------------- */ 4099 #define GPDMA0_CH_DSTAT_DSTAT_Pos (0UL) /*!< GPDMA0_CH0_1 DSTAT: DSTAT (Bit 0) */ 4100 #define GPDMA0_CH_DSTAT_DSTAT_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 DSTAT: DSTAT (Bitfield-Mask: 0xffffffff) */ 4101 4102 /* ---------------------------- GPDMA0_CH_SSTATAR ---------------------------- */ 4103 #define GPDMA0_CH_SSTATAR_SSTATAR_Pos (0UL) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR (Bit 0) */ 4104 #define GPDMA0_CH_SSTATAR_SSTATAR_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR (Bitfield-Mask: 0xffffffff) */ 4105 4106 /* ---------------------------- GPDMA0_CH_DSTATAR ---------------------------- */ 4107 #define GPDMA0_CH_DSTATAR_DSTATAR_Pos (0UL) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR (Bit 0) */ 4108 #define GPDMA0_CH_DSTATAR_DSTATAR_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR (Bitfield-Mask: 0xffffffff) */ 4109 4110 /* ------------------------------ GPDMA0_CH_CFGL ----------------------------- */ 4111 #define GPDMA0_CH_CFGL_CH_PRIOR_Pos (5UL) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR (Bit 5) */ 4112 #define GPDMA0_CH_CFGL_CH_PRIOR_Msk (0xe0UL) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR (Bitfield-Mask: 0x07) */ 4113 #define GPDMA0_CH_CFGL_CH_SUSP_Pos (8UL) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP (Bit 8) */ 4114 #define GPDMA0_CH_CFGL_CH_SUSP_Msk (0x100UL) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP (Bitfield-Mask: 0x01) */ 4115 #define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos (9UL) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY (Bit 9) */ 4116 #define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk (0x200UL) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY (Bitfield-Mask: 0x01) */ 4117 #define GPDMA0_CH_CFGL_HS_SEL_DST_Pos (10UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST (Bit 10) */ 4118 #define GPDMA0_CH_CFGL_HS_SEL_DST_Msk (0x400UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST (Bitfield-Mask: 0x01) */ 4119 #define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos (11UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC (Bit 11) */ 4120 #define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk (0x800UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC (Bitfield-Mask: 0x01) */ 4121 #define GPDMA0_CH_CFGL_LOCK_CH_L_Pos (12UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L (Bit 12) */ 4122 #define GPDMA0_CH_CFGL_LOCK_CH_L_Msk (0x3000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L (Bitfield-Mask: 0x03) */ 4123 #define GPDMA0_CH_CFGL_LOCK_B_L_Pos (14UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L (Bit 14) */ 4124 #define GPDMA0_CH_CFGL_LOCK_B_L_Msk (0xc000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L (Bitfield-Mask: 0x03) */ 4125 #define GPDMA0_CH_CFGL_LOCK_CH_Pos (16UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH (Bit 16) */ 4126 #define GPDMA0_CH_CFGL_LOCK_CH_Msk (0x10000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH (Bitfield-Mask: 0x01) */ 4127 #define GPDMA0_CH_CFGL_LOCK_B_Pos (17UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B (Bit 17) */ 4128 #define GPDMA0_CH_CFGL_LOCK_B_Msk (0x20000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B (Bitfield-Mask: 0x01) */ 4129 #define GPDMA0_CH_CFGL_DST_HS_POL_Pos (18UL) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL (Bit 18) */ 4130 #define GPDMA0_CH_CFGL_DST_HS_POL_Msk (0x40000UL) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL (Bitfield-Mask: 0x01) */ 4131 #define GPDMA0_CH_CFGL_SRC_HS_POL_Pos (19UL) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL (Bit 19) */ 4132 #define GPDMA0_CH_CFGL_SRC_HS_POL_Msk (0x80000UL) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL (Bitfield-Mask: 0x01) */ 4133 #define GPDMA0_CH_CFGL_MAX_ABRST_Pos (20UL) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST (Bit 20) */ 4134 #define GPDMA0_CH_CFGL_MAX_ABRST_Msk (0x3ff00000UL) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST (Bitfield-Mask: 0x3ff) */ 4135 #define GPDMA0_CH_CFGL_RELOAD_SRC_Pos (30UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC (Bit 30) */ 4136 #define GPDMA0_CH_CFGL_RELOAD_SRC_Msk (0x40000000UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC (Bitfield-Mask: 0x01) */ 4137 #define GPDMA0_CH_CFGL_RELOAD_DST_Pos (31UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST (Bit 31) */ 4138 #define GPDMA0_CH_CFGL_RELOAD_DST_Msk (0x80000000UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST (Bitfield-Mask: 0x01) */ 4139 4140 /* ------------------------------ GPDMA0_CH_CFGH ----------------------------- */ 4141 #define GPDMA0_CH_CFGH_FCMODE_Pos (0UL) /*!< GPDMA0_CH0_1 CFGH: FCMODE (Bit 0) */ 4142 #define GPDMA0_CH_CFGH_FCMODE_Msk (0x1UL) /*!< GPDMA0_CH0_1 CFGH: FCMODE (Bitfield-Mask: 0x01) */ 4143 #define GPDMA0_CH_CFGH_FIFO_MODE_Pos (1UL) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE (Bit 1) */ 4144 #define GPDMA0_CH_CFGH_FIFO_MODE_Msk (0x2UL) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE (Bitfield-Mask: 0x01) */ 4145 #define GPDMA0_CH_CFGH_PROTCTL_Pos (2UL) /*!< GPDMA0_CH0_1 CFGH: PROTCTL (Bit 2) */ 4146 #define GPDMA0_CH_CFGH_PROTCTL_Msk (0x1cUL) /*!< GPDMA0_CH0_1 CFGH: PROTCTL (Bitfield-Mask: 0x07) */ 4147 #define GPDMA0_CH_CFGH_DS_UPD_EN_Pos (5UL) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN (Bit 5) */ 4148 #define GPDMA0_CH_CFGH_DS_UPD_EN_Msk (0x20UL) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN (Bitfield-Mask: 0x01) */ 4149 #define GPDMA0_CH_CFGH_SS_UPD_EN_Pos (6UL) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN (Bit 6) */ 4150 #define GPDMA0_CH_CFGH_SS_UPD_EN_Msk (0x40UL) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN (Bitfield-Mask: 0x01) */ 4151 #define GPDMA0_CH_CFGH_SRC_PER_Pos (7UL) /*!< GPDMA0_CH0_1 CFGH: SRC_PER (Bit 7) */ 4152 #define GPDMA0_CH_CFGH_SRC_PER_Msk (0x780UL) /*!< GPDMA0_CH0_1 CFGH: SRC_PER (Bitfield-Mask: 0x0f) */ 4153 #define GPDMA0_CH_CFGH_DEST_PER_Pos (11UL) /*!< GPDMA0_CH0_1 CFGH: DEST_PER (Bit 11) */ 4154 #define GPDMA0_CH_CFGH_DEST_PER_Msk (0x7800UL) /*!< GPDMA0_CH0_1 CFGH: DEST_PER (Bitfield-Mask: 0x0f) */ 4155 4156 /* ------------------------------ GPDMA0_CH_SGR ------------------------------ */ 4157 #define GPDMA0_CH_SGR_SGI_Pos (0UL) /*!< GPDMA0_CH0_1 SGR: SGI (Bit 0) */ 4158 #define GPDMA0_CH_SGR_SGI_Msk (0xfffffUL) /*!< GPDMA0_CH0_1 SGR: SGI (Bitfield-Mask: 0xfffff) */ 4159 #define GPDMA0_CH_SGR_SGC_Pos (20UL) /*!< GPDMA0_CH0_1 SGR: SGC (Bit 20) */ 4160 #define GPDMA0_CH_SGR_SGC_Msk (0xfff00000UL) /*!< GPDMA0_CH0_1 SGR: SGC (Bitfield-Mask: 0xfff) */ 4161 4162 /* ------------------------------ GPDMA0_CH_DSR ------------------------------ */ 4163 #define GPDMA0_CH_DSR_DSI_Pos (0UL) /*!< GPDMA0_CH0_1 DSR: DSI (Bit 0) */ 4164 #define GPDMA0_CH_DSR_DSI_Msk (0xfffffUL) /*!< GPDMA0_CH0_1 DSR: DSI (Bitfield-Mask: 0xfffff) */ 4165 #define GPDMA0_CH_DSR_DSC_Pos (20UL) /*!< GPDMA0_CH0_1 DSR: DSC (Bit 20) */ 4166 #define GPDMA0_CH_DSR_DSC_Msk (0xfff00000UL) /*!< GPDMA0_CH0_1 DSR: DSC (Bitfield-Mask: 0xfff) */ 4167 4168 4169 /* ================================================================================ */ 4170 /* ================ struct 'GPDMA1' Position & Mask ================ */ 4171 /* ================================================================================ */ 4172 4173 4174 /* -------------------------------- GPDMA1_RAWTFR ------------------------------- */ 4175 #define GPDMA1_RAWTFR_CH0_Pos (0UL) /*!< GPDMA1 RAWTFR: CH0 (Bit 0) */ 4176 #define GPDMA1_RAWTFR_CH0_Msk (0x1UL) /*!< GPDMA1 RAWTFR: CH0 (Bitfield-Mask: 0x01) */ 4177 #define GPDMA1_RAWTFR_CH1_Pos (1UL) /*!< GPDMA1 RAWTFR: CH1 (Bit 1) */ 4178 #define GPDMA1_RAWTFR_CH1_Msk (0x2UL) /*!< GPDMA1 RAWTFR: CH1 (Bitfield-Mask: 0x01) */ 4179 #define GPDMA1_RAWTFR_CH2_Pos (2UL) /*!< GPDMA1 RAWTFR: CH2 (Bit 2) */ 4180 #define GPDMA1_RAWTFR_CH2_Msk (0x4UL) /*!< GPDMA1 RAWTFR: CH2 (Bitfield-Mask: 0x01) */ 4181 #define GPDMA1_RAWTFR_CH3_Pos (3UL) /*!< GPDMA1 RAWTFR: CH3 (Bit 3) */ 4182 #define GPDMA1_RAWTFR_CH3_Msk (0x8UL) /*!< GPDMA1 RAWTFR: CH3 (Bitfield-Mask: 0x01) */ 4183 4184 /* ------------------------------- GPDMA1_RAWBLOCK ------------------------------ */ 4185 #define GPDMA1_RAWBLOCK_CH0_Pos (0UL) /*!< GPDMA1 RAWBLOCK: CH0 (Bit 0) */ 4186 #define GPDMA1_RAWBLOCK_CH0_Msk (0x1UL) /*!< GPDMA1 RAWBLOCK: CH0 (Bitfield-Mask: 0x01) */ 4187 #define GPDMA1_RAWBLOCK_CH1_Pos (1UL) /*!< GPDMA1 RAWBLOCK: CH1 (Bit 1) */ 4188 #define GPDMA1_RAWBLOCK_CH1_Msk (0x2UL) /*!< GPDMA1 RAWBLOCK: CH1 (Bitfield-Mask: 0x01) */ 4189 #define GPDMA1_RAWBLOCK_CH2_Pos (2UL) /*!< GPDMA1 RAWBLOCK: CH2 (Bit 2) */ 4190 #define GPDMA1_RAWBLOCK_CH2_Msk (0x4UL) /*!< GPDMA1 RAWBLOCK: CH2 (Bitfield-Mask: 0x01) */ 4191 #define GPDMA1_RAWBLOCK_CH3_Pos (3UL) /*!< GPDMA1 RAWBLOCK: CH3 (Bit 3) */ 4192 #define GPDMA1_RAWBLOCK_CH3_Msk (0x8UL) /*!< GPDMA1 RAWBLOCK: CH3 (Bitfield-Mask: 0x01) */ 4193 4194 /* ------------------------------ GPDMA1_RAWSRCTRAN ----------------------------- */ 4195 #define GPDMA1_RAWSRCTRAN_CH0_Pos (0UL) /*!< GPDMA1 RAWSRCTRAN: CH0 (Bit 0) */ 4196 #define GPDMA1_RAWSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA1 RAWSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ 4197 #define GPDMA1_RAWSRCTRAN_CH1_Pos (1UL) /*!< GPDMA1 RAWSRCTRAN: CH1 (Bit 1) */ 4198 #define GPDMA1_RAWSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA1 RAWSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ 4199 #define GPDMA1_RAWSRCTRAN_CH2_Pos (2UL) /*!< GPDMA1 RAWSRCTRAN: CH2 (Bit 2) */ 4200 #define GPDMA1_RAWSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA1 RAWSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ 4201 #define GPDMA1_RAWSRCTRAN_CH3_Pos (3UL) /*!< GPDMA1 RAWSRCTRAN: CH3 (Bit 3) */ 4202 #define GPDMA1_RAWSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA1 RAWSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ 4203 4204 /* ------------------------------ GPDMA1_RAWDSTTRAN ----------------------------- */ 4205 #define GPDMA1_RAWDSTTRAN_CH0_Pos (0UL) /*!< GPDMA1 RAWDSTTRAN: CH0 (Bit 0) */ 4206 #define GPDMA1_RAWDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA1 RAWDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ 4207 #define GPDMA1_RAWDSTTRAN_CH1_Pos (1UL) /*!< GPDMA1 RAWDSTTRAN: CH1 (Bit 1) */ 4208 #define GPDMA1_RAWDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA1 RAWDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ 4209 #define GPDMA1_RAWDSTTRAN_CH2_Pos (2UL) /*!< GPDMA1 RAWDSTTRAN: CH2 (Bit 2) */ 4210 #define GPDMA1_RAWDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA1 RAWDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ 4211 #define GPDMA1_RAWDSTTRAN_CH3_Pos (3UL) /*!< GPDMA1 RAWDSTTRAN: CH3 (Bit 3) */ 4212 #define GPDMA1_RAWDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA1 RAWDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ 4213 4214 /* -------------------------------- GPDMA1_RAWERR ------------------------------- */ 4215 #define GPDMA1_RAWERR_CH0_Pos (0UL) /*!< GPDMA1 RAWERR: CH0 (Bit 0) */ 4216 #define GPDMA1_RAWERR_CH0_Msk (0x1UL) /*!< GPDMA1 RAWERR: CH0 (Bitfield-Mask: 0x01) */ 4217 #define GPDMA1_RAWERR_CH1_Pos (1UL) /*!< GPDMA1 RAWERR: CH1 (Bit 1) */ 4218 #define GPDMA1_RAWERR_CH1_Msk (0x2UL) /*!< GPDMA1 RAWERR: CH1 (Bitfield-Mask: 0x01) */ 4219 #define GPDMA1_RAWERR_CH2_Pos (2UL) /*!< GPDMA1 RAWERR: CH2 (Bit 2) */ 4220 #define GPDMA1_RAWERR_CH2_Msk (0x4UL) /*!< GPDMA1 RAWERR: CH2 (Bitfield-Mask: 0x01) */ 4221 #define GPDMA1_RAWERR_CH3_Pos (3UL) /*!< GPDMA1 RAWERR: CH3 (Bit 3) */ 4222 #define GPDMA1_RAWERR_CH3_Msk (0x8UL) /*!< GPDMA1 RAWERR: CH3 (Bitfield-Mask: 0x01) */ 4223 4224 /* ------------------------------ GPDMA1_STATUSTFR ------------------------------ */ 4225 #define GPDMA1_STATUSTFR_CH0_Pos (0UL) /*!< GPDMA1 STATUSTFR: CH0 (Bit 0) */ 4226 #define GPDMA1_STATUSTFR_CH0_Msk (0x1UL) /*!< GPDMA1 STATUSTFR: CH0 (Bitfield-Mask: 0x01) */ 4227 #define GPDMA1_STATUSTFR_CH1_Pos (1UL) /*!< GPDMA1 STATUSTFR: CH1 (Bit 1) */ 4228 #define GPDMA1_STATUSTFR_CH1_Msk (0x2UL) /*!< GPDMA1 STATUSTFR: CH1 (Bitfield-Mask: 0x01) */ 4229 #define GPDMA1_STATUSTFR_CH2_Pos (2UL) /*!< GPDMA1 STATUSTFR: CH2 (Bit 2) */ 4230 #define GPDMA1_STATUSTFR_CH2_Msk (0x4UL) /*!< GPDMA1 STATUSTFR: CH2 (Bitfield-Mask: 0x01) */ 4231 #define GPDMA1_STATUSTFR_CH3_Pos (3UL) /*!< GPDMA1 STATUSTFR: CH3 (Bit 3) */ 4232 #define GPDMA1_STATUSTFR_CH3_Msk (0x8UL) /*!< GPDMA1 STATUSTFR: CH3 (Bitfield-Mask: 0x01) */ 4233 4234 /* ----------------------------- GPDMA1_STATUSBLOCK ----------------------------- */ 4235 #define GPDMA1_STATUSBLOCK_CH0_Pos (0UL) /*!< GPDMA1 STATUSBLOCK: CH0 (Bit 0) */ 4236 #define GPDMA1_STATUSBLOCK_CH0_Msk (0x1UL) /*!< GPDMA1 STATUSBLOCK: CH0 (Bitfield-Mask: 0x01) */ 4237 #define GPDMA1_STATUSBLOCK_CH1_Pos (1UL) /*!< GPDMA1 STATUSBLOCK: CH1 (Bit 1) */ 4238 #define GPDMA1_STATUSBLOCK_CH1_Msk (0x2UL) /*!< GPDMA1 STATUSBLOCK: CH1 (Bitfield-Mask: 0x01) */ 4239 #define GPDMA1_STATUSBLOCK_CH2_Pos (2UL) /*!< GPDMA1 STATUSBLOCK: CH2 (Bit 2) */ 4240 #define GPDMA1_STATUSBLOCK_CH2_Msk (0x4UL) /*!< GPDMA1 STATUSBLOCK: CH2 (Bitfield-Mask: 0x01) */ 4241 #define GPDMA1_STATUSBLOCK_CH3_Pos (3UL) /*!< GPDMA1 STATUSBLOCK: CH3 (Bit 3) */ 4242 #define GPDMA1_STATUSBLOCK_CH3_Msk (0x8UL) /*!< GPDMA1 STATUSBLOCK: CH3 (Bitfield-Mask: 0x01) */ 4243 4244 /* ---------------------------- GPDMA1_STATUSSRCTRAN ---------------------------- */ 4245 #define GPDMA1_STATUSSRCTRAN_CH0_Pos (0UL) /*!< GPDMA1 STATUSSRCTRAN: CH0 (Bit 0) */ 4246 #define GPDMA1_STATUSSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA1 STATUSSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ 4247 #define GPDMA1_STATUSSRCTRAN_CH1_Pos (1UL) /*!< GPDMA1 STATUSSRCTRAN: CH1 (Bit 1) */ 4248 #define GPDMA1_STATUSSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA1 STATUSSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ 4249 #define GPDMA1_STATUSSRCTRAN_CH2_Pos (2UL) /*!< GPDMA1 STATUSSRCTRAN: CH2 (Bit 2) */ 4250 #define GPDMA1_STATUSSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA1 STATUSSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ 4251 #define GPDMA1_STATUSSRCTRAN_CH3_Pos (3UL) /*!< GPDMA1 STATUSSRCTRAN: CH3 (Bit 3) */ 4252 #define GPDMA1_STATUSSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA1 STATUSSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ 4253 4254 /* ---------------------------- GPDMA1_STATUSDSTTRAN ---------------------------- */ 4255 #define GPDMA1_STATUSDSTTRAN_CH0_Pos (0UL) /*!< GPDMA1 STATUSDSTTRAN: CH0 (Bit 0) */ 4256 #define GPDMA1_STATUSDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA1 STATUSDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ 4257 #define GPDMA1_STATUSDSTTRAN_CH1_Pos (1UL) /*!< GPDMA1 STATUSDSTTRAN: CH1 (Bit 1) */ 4258 #define GPDMA1_STATUSDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA1 STATUSDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ 4259 #define GPDMA1_STATUSDSTTRAN_CH2_Pos (2UL) /*!< GPDMA1 STATUSDSTTRAN: CH2 (Bit 2) */ 4260 #define GPDMA1_STATUSDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA1 STATUSDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ 4261 #define GPDMA1_STATUSDSTTRAN_CH3_Pos (3UL) /*!< GPDMA1 STATUSDSTTRAN: CH3 (Bit 3) */ 4262 #define GPDMA1_STATUSDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA1 STATUSDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ 4263 4264 /* ------------------------------ GPDMA1_STATUSERR ------------------------------ */ 4265 #define GPDMA1_STATUSERR_CH0_Pos (0UL) /*!< GPDMA1 STATUSERR: CH0 (Bit 0) */ 4266 #define GPDMA1_STATUSERR_CH0_Msk (0x1UL) /*!< GPDMA1 STATUSERR: CH0 (Bitfield-Mask: 0x01) */ 4267 #define GPDMA1_STATUSERR_CH1_Pos (1UL) /*!< GPDMA1 STATUSERR: CH1 (Bit 1) */ 4268 #define GPDMA1_STATUSERR_CH1_Msk (0x2UL) /*!< GPDMA1 STATUSERR: CH1 (Bitfield-Mask: 0x01) */ 4269 #define GPDMA1_STATUSERR_CH2_Pos (2UL) /*!< GPDMA1 STATUSERR: CH2 (Bit 2) */ 4270 #define GPDMA1_STATUSERR_CH2_Msk (0x4UL) /*!< GPDMA1 STATUSERR: CH2 (Bitfield-Mask: 0x01) */ 4271 #define GPDMA1_STATUSERR_CH3_Pos (3UL) /*!< GPDMA1 STATUSERR: CH3 (Bit 3) */ 4272 #define GPDMA1_STATUSERR_CH3_Msk (0x8UL) /*!< GPDMA1 STATUSERR: CH3 (Bitfield-Mask: 0x01) */ 4273 4274 /* ------------------------------- GPDMA1_MASKTFR ------------------------------- */ 4275 #define GPDMA1_MASKTFR_CH0_Pos (0UL) /*!< GPDMA1 MASKTFR: CH0 (Bit 0) */ 4276 #define GPDMA1_MASKTFR_CH0_Msk (0x1UL) /*!< GPDMA1 MASKTFR: CH0 (Bitfield-Mask: 0x01) */ 4277 #define GPDMA1_MASKTFR_CH1_Pos (1UL) /*!< GPDMA1 MASKTFR: CH1 (Bit 1) */ 4278 #define GPDMA1_MASKTFR_CH1_Msk (0x2UL) /*!< GPDMA1 MASKTFR: CH1 (Bitfield-Mask: 0x01) */ 4279 #define GPDMA1_MASKTFR_CH2_Pos (2UL) /*!< GPDMA1 MASKTFR: CH2 (Bit 2) */ 4280 #define GPDMA1_MASKTFR_CH2_Msk (0x4UL) /*!< GPDMA1 MASKTFR: CH2 (Bitfield-Mask: 0x01) */ 4281 #define GPDMA1_MASKTFR_CH3_Pos (3UL) /*!< GPDMA1 MASKTFR: CH3 (Bit 3) */ 4282 #define GPDMA1_MASKTFR_CH3_Msk (0x8UL) /*!< GPDMA1 MASKTFR: CH3 (Bitfield-Mask: 0x01) */ 4283 #define GPDMA1_MASKTFR_WE_CH0_Pos (8UL) /*!< GPDMA1 MASKTFR: WE_CH0 (Bit 8) */ 4284 #define GPDMA1_MASKTFR_WE_CH0_Msk (0x100UL) /*!< GPDMA1 MASKTFR: WE_CH0 (Bitfield-Mask: 0x01) */ 4285 #define GPDMA1_MASKTFR_WE_CH1_Pos (9UL) /*!< GPDMA1 MASKTFR: WE_CH1 (Bit 9) */ 4286 #define GPDMA1_MASKTFR_WE_CH1_Msk (0x200UL) /*!< GPDMA1 MASKTFR: WE_CH1 (Bitfield-Mask: 0x01) */ 4287 #define GPDMA1_MASKTFR_WE_CH2_Pos (10UL) /*!< GPDMA1 MASKTFR: WE_CH2 (Bit 10) */ 4288 #define GPDMA1_MASKTFR_WE_CH2_Msk (0x400UL) /*!< GPDMA1 MASKTFR: WE_CH2 (Bitfield-Mask: 0x01) */ 4289 #define GPDMA1_MASKTFR_WE_CH3_Pos (11UL) /*!< GPDMA1 MASKTFR: WE_CH3 (Bit 11) */ 4290 #define GPDMA1_MASKTFR_WE_CH3_Msk (0x800UL) /*!< GPDMA1 MASKTFR: WE_CH3 (Bitfield-Mask: 0x01) */ 4291 4292 /* ------------------------------ GPDMA1_MASKBLOCK ------------------------------ */ 4293 #define GPDMA1_MASKBLOCK_CH0_Pos (0UL) /*!< GPDMA1 MASKBLOCK: CH0 (Bit 0) */ 4294 #define GPDMA1_MASKBLOCK_CH0_Msk (0x1UL) /*!< GPDMA1 MASKBLOCK: CH0 (Bitfield-Mask: 0x01) */ 4295 #define GPDMA1_MASKBLOCK_CH1_Pos (1UL) /*!< GPDMA1 MASKBLOCK: CH1 (Bit 1) */ 4296 #define GPDMA1_MASKBLOCK_CH1_Msk (0x2UL) /*!< GPDMA1 MASKBLOCK: CH1 (Bitfield-Mask: 0x01) */ 4297 #define GPDMA1_MASKBLOCK_CH2_Pos (2UL) /*!< GPDMA1 MASKBLOCK: CH2 (Bit 2) */ 4298 #define GPDMA1_MASKBLOCK_CH2_Msk (0x4UL) /*!< GPDMA1 MASKBLOCK: CH2 (Bitfield-Mask: 0x01) */ 4299 #define GPDMA1_MASKBLOCK_CH3_Pos (3UL) /*!< GPDMA1 MASKBLOCK: CH3 (Bit 3) */ 4300 #define GPDMA1_MASKBLOCK_CH3_Msk (0x8UL) /*!< GPDMA1 MASKBLOCK: CH3 (Bitfield-Mask: 0x01) */ 4301 #define GPDMA1_MASKBLOCK_WE_CH0_Pos (8UL) /*!< GPDMA1 MASKBLOCK: WE_CH0 (Bit 8) */ 4302 #define GPDMA1_MASKBLOCK_WE_CH0_Msk (0x100UL) /*!< GPDMA1 MASKBLOCK: WE_CH0 (Bitfield-Mask: 0x01) */ 4303 #define GPDMA1_MASKBLOCK_WE_CH1_Pos (9UL) /*!< GPDMA1 MASKBLOCK: WE_CH1 (Bit 9) */ 4304 #define GPDMA1_MASKBLOCK_WE_CH1_Msk (0x200UL) /*!< GPDMA1 MASKBLOCK: WE_CH1 (Bitfield-Mask: 0x01) */ 4305 #define GPDMA1_MASKBLOCK_WE_CH2_Pos (10UL) /*!< GPDMA1 MASKBLOCK: WE_CH2 (Bit 10) */ 4306 #define GPDMA1_MASKBLOCK_WE_CH2_Msk (0x400UL) /*!< GPDMA1 MASKBLOCK: WE_CH2 (Bitfield-Mask: 0x01) */ 4307 #define GPDMA1_MASKBLOCK_WE_CH3_Pos (11UL) /*!< GPDMA1 MASKBLOCK: WE_CH3 (Bit 11) */ 4308 #define GPDMA1_MASKBLOCK_WE_CH3_Msk (0x800UL) /*!< GPDMA1 MASKBLOCK: WE_CH3 (Bitfield-Mask: 0x01) */ 4309 4310 /* ----------------------------- GPDMA1_MASKSRCTRAN ----------------------------- */ 4311 #define GPDMA1_MASKSRCTRAN_CH0_Pos (0UL) /*!< GPDMA1 MASKSRCTRAN: CH0 (Bit 0) */ 4312 #define GPDMA1_MASKSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA1 MASKSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ 4313 #define GPDMA1_MASKSRCTRAN_CH1_Pos (1UL) /*!< GPDMA1 MASKSRCTRAN: CH1 (Bit 1) */ 4314 #define GPDMA1_MASKSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA1 MASKSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ 4315 #define GPDMA1_MASKSRCTRAN_CH2_Pos (2UL) /*!< GPDMA1 MASKSRCTRAN: CH2 (Bit 2) */ 4316 #define GPDMA1_MASKSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA1 MASKSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ 4317 #define GPDMA1_MASKSRCTRAN_CH3_Pos (3UL) /*!< GPDMA1 MASKSRCTRAN: CH3 (Bit 3) */ 4318 #define GPDMA1_MASKSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA1 MASKSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ 4319 #define GPDMA1_MASKSRCTRAN_WE_CH0_Pos (8UL) /*!< GPDMA1 MASKSRCTRAN: WE_CH0 (Bit 8) */ 4320 #define GPDMA1_MASKSRCTRAN_WE_CH0_Msk (0x100UL) /*!< GPDMA1 MASKSRCTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ 4321 #define GPDMA1_MASKSRCTRAN_WE_CH1_Pos (9UL) /*!< GPDMA1 MASKSRCTRAN: WE_CH1 (Bit 9) */ 4322 #define GPDMA1_MASKSRCTRAN_WE_CH1_Msk (0x200UL) /*!< GPDMA1 MASKSRCTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ 4323 #define GPDMA1_MASKSRCTRAN_WE_CH2_Pos (10UL) /*!< GPDMA1 MASKSRCTRAN: WE_CH2 (Bit 10) */ 4324 #define GPDMA1_MASKSRCTRAN_WE_CH2_Msk (0x400UL) /*!< GPDMA1 MASKSRCTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ 4325 #define GPDMA1_MASKSRCTRAN_WE_CH3_Pos (11UL) /*!< GPDMA1 MASKSRCTRAN: WE_CH3 (Bit 11) */ 4326 #define GPDMA1_MASKSRCTRAN_WE_CH3_Msk (0x800UL) /*!< GPDMA1 MASKSRCTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ 4327 4328 /* ----------------------------- GPDMA1_MASKDSTTRAN ----------------------------- */ 4329 #define GPDMA1_MASKDSTTRAN_CH0_Pos (0UL) /*!< GPDMA1 MASKDSTTRAN: CH0 (Bit 0) */ 4330 #define GPDMA1_MASKDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA1 MASKDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ 4331 #define GPDMA1_MASKDSTTRAN_CH1_Pos (1UL) /*!< GPDMA1 MASKDSTTRAN: CH1 (Bit 1) */ 4332 #define GPDMA1_MASKDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA1 MASKDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ 4333 #define GPDMA1_MASKDSTTRAN_CH2_Pos (2UL) /*!< GPDMA1 MASKDSTTRAN: CH2 (Bit 2) */ 4334 #define GPDMA1_MASKDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA1 MASKDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ 4335 #define GPDMA1_MASKDSTTRAN_CH3_Pos (3UL) /*!< GPDMA1 MASKDSTTRAN: CH3 (Bit 3) */ 4336 #define GPDMA1_MASKDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA1 MASKDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ 4337 #define GPDMA1_MASKDSTTRAN_WE_CH0_Pos (8UL) /*!< GPDMA1 MASKDSTTRAN: WE_CH0 (Bit 8) */ 4338 #define GPDMA1_MASKDSTTRAN_WE_CH0_Msk (0x100UL) /*!< GPDMA1 MASKDSTTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ 4339 #define GPDMA1_MASKDSTTRAN_WE_CH1_Pos (9UL) /*!< GPDMA1 MASKDSTTRAN: WE_CH1 (Bit 9) */ 4340 #define GPDMA1_MASKDSTTRAN_WE_CH1_Msk (0x200UL) /*!< GPDMA1 MASKDSTTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ 4341 #define GPDMA1_MASKDSTTRAN_WE_CH2_Pos (10UL) /*!< GPDMA1 MASKDSTTRAN: WE_CH2 (Bit 10) */ 4342 #define GPDMA1_MASKDSTTRAN_WE_CH2_Msk (0x400UL) /*!< GPDMA1 MASKDSTTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ 4343 #define GPDMA1_MASKDSTTRAN_WE_CH3_Pos (11UL) /*!< GPDMA1 MASKDSTTRAN: WE_CH3 (Bit 11) */ 4344 #define GPDMA1_MASKDSTTRAN_WE_CH3_Msk (0x800UL) /*!< GPDMA1 MASKDSTTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ 4345 4346 /* ------------------------------- GPDMA1_MASKERR ------------------------------- */ 4347 #define GPDMA1_MASKERR_CH0_Pos (0UL) /*!< GPDMA1 MASKERR: CH0 (Bit 0) */ 4348 #define GPDMA1_MASKERR_CH0_Msk (0x1UL) /*!< GPDMA1 MASKERR: CH0 (Bitfield-Mask: 0x01) */ 4349 #define GPDMA1_MASKERR_CH1_Pos (1UL) /*!< GPDMA1 MASKERR: CH1 (Bit 1) */ 4350 #define GPDMA1_MASKERR_CH1_Msk (0x2UL) /*!< GPDMA1 MASKERR: CH1 (Bitfield-Mask: 0x01) */ 4351 #define GPDMA1_MASKERR_CH2_Pos (2UL) /*!< GPDMA1 MASKERR: CH2 (Bit 2) */ 4352 #define GPDMA1_MASKERR_CH2_Msk (0x4UL) /*!< GPDMA1 MASKERR: CH2 (Bitfield-Mask: 0x01) */ 4353 #define GPDMA1_MASKERR_CH3_Pos (3UL) /*!< GPDMA1 MASKERR: CH3 (Bit 3) */ 4354 #define GPDMA1_MASKERR_CH3_Msk (0x8UL) /*!< GPDMA1 MASKERR: CH3 (Bitfield-Mask: 0x01) */ 4355 #define GPDMA1_MASKERR_WE_CH0_Pos (8UL) /*!< GPDMA1 MASKERR: WE_CH0 (Bit 8) */ 4356 #define GPDMA1_MASKERR_WE_CH0_Msk (0x100UL) /*!< GPDMA1 MASKERR: WE_CH0 (Bitfield-Mask: 0x01) */ 4357 #define GPDMA1_MASKERR_WE_CH1_Pos (9UL) /*!< GPDMA1 MASKERR: WE_CH1 (Bit 9) */ 4358 #define GPDMA1_MASKERR_WE_CH1_Msk (0x200UL) /*!< GPDMA1 MASKERR: WE_CH1 (Bitfield-Mask: 0x01) */ 4359 #define GPDMA1_MASKERR_WE_CH2_Pos (10UL) /*!< GPDMA1 MASKERR: WE_CH2 (Bit 10) */ 4360 #define GPDMA1_MASKERR_WE_CH2_Msk (0x400UL) /*!< GPDMA1 MASKERR: WE_CH2 (Bitfield-Mask: 0x01) */ 4361 #define GPDMA1_MASKERR_WE_CH3_Pos (11UL) /*!< GPDMA1 MASKERR: WE_CH3 (Bit 11) */ 4362 #define GPDMA1_MASKERR_WE_CH3_Msk (0x800UL) /*!< GPDMA1 MASKERR: WE_CH3 (Bitfield-Mask: 0x01) */ 4363 4364 /* ------------------------------- GPDMA1_CLEARTFR ------------------------------ */ 4365 #define GPDMA1_CLEARTFR_CH0_Pos (0UL) /*!< GPDMA1 CLEARTFR: CH0 (Bit 0) */ 4366 #define GPDMA1_CLEARTFR_CH0_Msk (0x1UL) /*!< GPDMA1 CLEARTFR: CH0 (Bitfield-Mask: 0x01) */ 4367 #define GPDMA1_CLEARTFR_CH1_Pos (1UL) /*!< GPDMA1 CLEARTFR: CH1 (Bit 1) */ 4368 #define GPDMA1_CLEARTFR_CH1_Msk (0x2UL) /*!< GPDMA1 CLEARTFR: CH1 (Bitfield-Mask: 0x01) */ 4369 #define GPDMA1_CLEARTFR_CH2_Pos (2UL) /*!< GPDMA1 CLEARTFR: CH2 (Bit 2) */ 4370 #define GPDMA1_CLEARTFR_CH2_Msk (0x4UL) /*!< GPDMA1 CLEARTFR: CH2 (Bitfield-Mask: 0x01) */ 4371 #define GPDMA1_CLEARTFR_CH3_Pos (3UL) /*!< GPDMA1 CLEARTFR: CH3 (Bit 3) */ 4372 #define GPDMA1_CLEARTFR_CH3_Msk (0x8UL) /*!< GPDMA1 CLEARTFR: CH3 (Bitfield-Mask: 0x01) */ 4373 4374 /* ------------------------------ GPDMA1_CLEARBLOCK ----------------------------- */ 4375 #define GPDMA1_CLEARBLOCK_CH0_Pos (0UL) /*!< GPDMA1 CLEARBLOCK: CH0 (Bit 0) */ 4376 #define GPDMA1_CLEARBLOCK_CH0_Msk (0x1UL) /*!< GPDMA1 CLEARBLOCK: CH0 (Bitfield-Mask: 0x01) */ 4377 #define GPDMA1_CLEARBLOCK_CH1_Pos (1UL) /*!< GPDMA1 CLEARBLOCK: CH1 (Bit 1) */ 4378 #define GPDMA1_CLEARBLOCK_CH1_Msk (0x2UL) /*!< GPDMA1 CLEARBLOCK: CH1 (Bitfield-Mask: 0x01) */ 4379 #define GPDMA1_CLEARBLOCK_CH2_Pos (2UL) /*!< GPDMA1 CLEARBLOCK: CH2 (Bit 2) */ 4380 #define GPDMA1_CLEARBLOCK_CH2_Msk (0x4UL) /*!< GPDMA1 CLEARBLOCK: CH2 (Bitfield-Mask: 0x01) */ 4381 #define GPDMA1_CLEARBLOCK_CH3_Pos (3UL) /*!< GPDMA1 CLEARBLOCK: CH3 (Bit 3) */ 4382 #define GPDMA1_CLEARBLOCK_CH3_Msk (0x8UL) /*!< GPDMA1 CLEARBLOCK: CH3 (Bitfield-Mask: 0x01) */ 4383 4384 /* ----------------------------- GPDMA1_CLEARSRCTRAN ---------------------------- */ 4385 #define GPDMA1_CLEARSRCTRAN_CH0_Pos (0UL) /*!< GPDMA1 CLEARSRCTRAN: CH0 (Bit 0) */ 4386 #define GPDMA1_CLEARSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA1 CLEARSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ 4387 #define GPDMA1_CLEARSRCTRAN_CH1_Pos (1UL) /*!< GPDMA1 CLEARSRCTRAN: CH1 (Bit 1) */ 4388 #define GPDMA1_CLEARSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA1 CLEARSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ 4389 #define GPDMA1_CLEARSRCTRAN_CH2_Pos (2UL) /*!< GPDMA1 CLEARSRCTRAN: CH2 (Bit 2) */ 4390 #define GPDMA1_CLEARSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA1 CLEARSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ 4391 #define GPDMA1_CLEARSRCTRAN_CH3_Pos (3UL) /*!< GPDMA1 CLEARSRCTRAN: CH3 (Bit 3) */ 4392 #define GPDMA1_CLEARSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA1 CLEARSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ 4393 4394 /* ----------------------------- GPDMA1_CLEARDSTTRAN ---------------------------- */ 4395 #define GPDMA1_CLEARDSTTRAN_CH0_Pos (0UL) /*!< GPDMA1 CLEARDSTTRAN: CH0 (Bit 0) */ 4396 #define GPDMA1_CLEARDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA1 CLEARDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ 4397 #define GPDMA1_CLEARDSTTRAN_CH1_Pos (1UL) /*!< GPDMA1 CLEARDSTTRAN: CH1 (Bit 1) */ 4398 #define GPDMA1_CLEARDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA1 CLEARDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ 4399 #define GPDMA1_CLEARDSTTRAN_CH2_Pos (2UL) /*!< GPDMA1 CLEARDSTTRAN: CH2 (Bit 2) */ 4400 #define GPDMA1_CLEARDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA1 CLEARDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ 4401 #define GPDMA1_CLEARDSTTRAN_CH3_Pos (3UL) /*!< GPDMA1 CLEARDSTTRAN: CH3 (Bit 3) */ 4402 #define GPDMA1_CLEARDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA1 CLEARDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ 4403 4404 /* ------------------------------- GPDMA1_CLEARERR ------------------------------ */ 4405 #define GPDMA1_CLEARERR_CH0_Pos (0UL) /*!< GPDMA1 CLEARERR: CH0 (Bit 0) */ 4406 #define GPDMA1_CLEARERR_CH0_Msk (0x1UL) /*!< GPDMA1 CLEARERR: CH0 (Bitfield-Mask: 0x01) */ 4407 #define GPDMA1_CLEARERR_CH1_Pos (1UL) /*!< GPDMA1 CLEARERR: CH1 (Bit 1) */ 4408 #define GPDMA1_CLEARERR_CH1_Msk (0x2UL) /*!< GPDMA1 CLEARERR: CH1 (Bitfield-Mask: 0x01) */ 4409 #define GPDMA1_CLEARERR_CH2_Pos (2UL) /*!< GPDMA1 CLEARERR: CH2 (Bit 2) */ 4410 #define GPDMA1_CLEARERR_CH2_Msk (0x4UL) /*!< GPDMA1 CLEARERR: CH2 (Bitfield-Mask: 0x01) */ 4411 #define GPDMA1_CLEARERR_CH3_Pos (3UL) /*!< GPDMA1 CLEARERR: CH3 (Bit 3) */ 4412 #define GPDMA1_CLEARERR_CH3_Msk (0x8UL) /*!< GPDMA1 CLEARERR: CH3 (Bitfield-Mask: 0x01) */ 4413 4414 /* ------------------------------ GPDMA1_STATUSINT ------------------------------ */ 4415 #define GPDMA1_STATUSINT_TFR_Pos (0UL) /*!< GPDMA1 STATUSINT: TFR (Bit 0) */ 4416 #define GPDMA1_STATUSINT_TFR_Msk (0x1UL) /*!< GPDMA1 STATUSINT: TFR (Bitfield-Mask: 0x01) */ 4417 #define GPDMA1_STATUSINT_BLOCK_Pos (1UL) /*!< GPDMA1 STATUSINT: BLOCK (Bit 1) */ 4418 #define GPDMA1_STATUSINT_BLOCK_Msk (0x2UL) /*!< GPDMA1 STATUSINT: BLOCK (Bitfield-Mask: 0x01) */ 4419 #define GPDMA1_STATUSINT_SRCT_Pos (2UL) /*!< GPDMA1 STATUSINT: SRCT (Bit 2) */ 4420 #define GPDMA1_STATUSINT_SRCT_Msk (0x4UL) /*!< GPDMA1 STATUSINT: SRCT (Bitfield-Mask: 0x01) */ 4421 #define GPDMA1_STATUSINT_DSTT_Pos (3UL) /*!< GPDMA1 STATUSINT: DSTT (Bit 3) */ 4422 #define GPDMA1_STATUSINT_DSTT_Msk (0x8UL) /*!< GPDMA1 STATUSINT: DSTT (Bitfield-Mask: 0x01) */ 4423 #define GPDMA1_STATUSINT_ERR_Pos (4UL) /*!< GPDMA1 STATUSINT: ERR (Bit 4) */ 4424 #define GPDMA1_STATUSINT_ERR_Msk (0x10UL) /*!< GPDMA1 STATUSINT: ERR (Bitfield-Mask: 0x01) */ 4425 4426 /* ------------------------------ GPDMA1_REQSRCREG ------------------------------ */ 4427 #define GPDMA1_REQSRCREG_CH0_Pos (0UL) /*!< GPDMA1 REQSRCREG: CH0 (Bit 0) */ 4428 #define GPDMA1_REQSRCREG_CH0_Msk (0x1UL) /*!< GPDMA1 REQSRCREG: CH0 (Bitfield-Mask: 0x01) */ 4429 #define GPDMA1_REQSRCREG_CH1_Pos (1UL) /*!< GPDMA1 REQSRCREG: CH1 (Bit 1) */ 4430 #define GPDMA1_REQSRCREG_CH1_Msk (0x2UL) /*!< GPDMA1 REQSRCREG: CH1 (Bitfield-Mask: 0x01) */ 4431 #define GPDMA1_REQSRCREG_CH2_Pos (2UL) /*!< GPDMA1 REQSRCREG: CH2 (Bit 2) */ 4432 #define GPDMA1_REQSRCREG_CH2_Msk (0x4UL) /*!< GPDMA1 REQSRCREG: CH2 (Bitfield-Mask: 0x01) */ 4433 #define GPDMA1_REQSRCREG_CH3_Pos (3UL) /*!< GPDMA1 REQSRCREG: CH3 (Bit 3) */ 4434 #define GPDMA1_REQSRCREG_CH3_Msk (0x8UL) /*!< GPDMA1 REQSRCREG: CH3 (Bitfield-Mask: 0x01) */ 4435 #define GPDMA1_REQSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA1 REQSRCREG: WE_CH0 (Bit 8) */ 4436 #define GPDMA1_REQSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA1 REQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ 4437 #define GPDMA1_REQSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA1 REQSRCREG: WE_CH1 (Bit 9) */ 4438 #define GPDMA1_REQSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA1 REQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ 4439 #define GPDMA1_REQSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA1 REQSRCREG: WE_CH2 (Bit 10) */ 4440 #define GPDMA1_REQSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA1 REQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ 4441 #define GPDMA1_REQSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA1 REQSRCREG: WE_CH3 (Bit 11) */ 4442 #define GPDMA1_REQSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA1 REQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ 4443 4444 /* ------------------------------ GPDMA1_REQDSTREG ------------------------------ */ 4445 #define GPDMA1_REQDSTREG_CH0_Pos (0UL) /*!< GPDMA1 REQDSTREG: CH0 (Bit 0) */ 4446 #define GPDMA1_REQDSTREG_CH0_Msk (0x1UL) /*!< GPDMA1 REQDSTREG: CH0 (Bitfield-Mask: 0x01) */ 4447 #define GPDMA1_REQDSTREG_CH1_Pos (1UL) /*!< GPDMA1 REQDSTREG: CH1 (Bit 1) */ 4448 #define GPDMA1_REQDSTREG_CH1_Msk (0x2UL) /*!< GPDMA1 REQDSTREG: CH1 (Bitfield-Mask: 0x01) */ 4449 #define GPDMA1_REQDSTREG_CH2_Pos (2UL) /*!< GPDMA1 REQDSTREG: CH2 (Bit 2) */ 4450 #define GPDMA1_REQDSTREG_CH2_Msk (0x4UL) /*!< GPDMA1 REQDSTREG: CH2 (Bitfield-Mask: 0x01) */ 4451 #define GPDMA1_REQDSTREG_CH3_Pos (3UL) /*!< GPDMA1 REQDSTREG: CH3 (Bit 3) */ 4452 #define GPDMA1_REQDSTREG_CH3_Msk (0x8UL) /*!< GPDMA1 REQDSTREG: CH3 (Bitfield-Mask: 0x01) */ 4453 #define GPDMA1_REQDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA1 REQDSTREG: WE_CH0 (Bit 8) */ 4454 #define GPDMA1_REQDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA1 REQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ 4455 #define GPDMA1_REQDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA1 REQDSTREG: WE_CH1 (Bit 9) */ 4456 #define GPDMA1_REQDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA1 REQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ 4457 #define GPDMA1_REQDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA1 REQDSTREG: WE_CH2 (Bit 10) */ 4458 #define GPDMA1_REQDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA1 REQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ 4459 #define GPDMA1_REQDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA1 REQDSTREG: WE_CH3 (Bit 11) */ 4460 #define GPDMA1_REQDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA1 REQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ 4461 4462 /* ----------------------------- GPDMA1_SGLREQSRCREG ---------------------------- */ 4463 #define GPDMA1_SGLREQSRCREG_CH0_Pos (0UL) /*!< GPDMA1 SGLREQSRCREG: CH0 (Bit 0) */ 4464 #define GPDMA1_SGLREQSRCREG_CH0_Msk (0x1UL) /*!< GPDMA1 SGLREQSRCREG: CH0 (Bitfield-Mask: 0x01) */ 4465 #define GPDMA1_SGLREQSRCREG_CH1_Pos (1UL) /*!< GPDMA1 SGLREQSRCREG: CH1 (Bit 1) */ 4466 #define GPDMA1_SGLREQSRCREG_CH1_Msk (0x2UL) /*!< GPDMA1 SGLREQSRCREG: CH1 (Bitfield-Mask: 0x01) */ 4467 #define GPDMA1_SGLREQSRCREG_CH2_Pos (2UL) /*!< GPDMA1 SGLREQSRCREG: CH2 (Bit 2) */ 4468 #define GPDMA1_SGLREQSRCREG_CH2_Msk (0x4UL) /*!< GPDMA1 SGLREQSRCREG: CH2 (Bitfield-Mask: 0x01) */ 4469 #define GPDMA1_SGLREQSRCREG_CH3_Pos (3UL) /*!< GPDMA1 SGLREQSRCREG: CH3 (Bit 3) */ 4470 #define GPDMA1_SGLREQSRCREG_CH3_Msk (0x8UL) /*!< GPDMA1 SGLREQSRCREG: CH3 (Bitfield-Mask: 0x01) */ 4471 #define GPDMA1_SGLREQSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA1 SGLREQSRCREG: WE_CH0 (Bit 8) */ 4472 #define GPDMA1_SGLREQSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA1 SGLREQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ 4473 #define GPDMA1_SGLREQSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA1 SGLREQSRCREG: WE_CH1 (Bit 9) */ 4474 #define GPDMA1_SGLREQSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA1 SGLREQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ 4475 #define GPDMA1_SGLREQSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA1 SGLREQSRCREG: WE_CH2 (Bit 10) */ 4476 #define GPDMA1_SGLREQSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA1 SGLREQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ 4477 #define GPDMA1_SGLREQSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA1 SGLREQSRCREG: WE_CH3 (Bit 11) */ 4478 #define GPDMA1_SGLREQSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA1 SGLREQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ 4479 4480 /* ----------------------------- GPDMA1_SGLREQDSTREG ---------------------------- */ 4481 #define GPDMA1_SGLREQDSTREG_CH0_Pos (0UL) /*!< GPDMA1 SGLREQDSTREG: CH0 (Bit 0) */ 4482 #define GPDMA1_SGLREQDSTREG_CH0_Msk (0x1UL) /*!< GPDMA1 SGLREQDSTREG: CH0 (Bitfield-Mask: 0x01) */ 4483 #define GPDMA1_SGLREQDSTREG_CH1_Pos (1UL) /*!< GPDMA1 SGLREQDSTREG: CH1 (Bit 1) */ 4484 #define GPDMA1_SGLREQDSTREG_CH1_Msk (0x2UL) /*!< GPDMA1 SGLREQDSTREG: CH1 (Bitfield-Mask: 0x01) */ 4485 #define GPDMA1_SGLREQDSTREG_CH2_Pos (2UL) /*!< GPDMA1 SGLREQDSTREG: CH2 (Bit 2) */ 4486 #define GPDMA1_SGLREQDSTREG_CH2_Msk (0x4UL) /*!< GPDMA1 SGLREQDSTREG: CH2 (Bitfield-Mask: 0x01) */ 4487 #define GPDMA1_SGLREQDSTREG_CH3_Pos (3UL) /*!< GPDMA1 SGLREQDSTREG: CH3 (Bit 3) */ 4488 #define GPDMA1_SGLREQDSTREG_CH3_Msk (0x8UL) /*!< GPDMA1 SGLREQDSTREG: CH3 (Bitfield-Mask: 0x01) */ 4489 #define GPDMA1_SGLREQDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA1 SGLREQDSTREG: WE_CH0 (Bit 8) */ 4490 #define GPDMA1_SGLREQDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA1 SGLREQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ 4491 #define GPDMA1_SGLREQDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA1 SGLREQDSTREG: WE_CH1 (Bit 9) */ 4492 #define GPDMA1_SGLREQDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA1 SGLREQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ 4493 #define GPDMA1_SGLREQDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA1 SGLREQDSTREG: WE_CH2 (Bit 10) */ 4494 #define GPDMA1_SGLREQDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA1 SGLREQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ 4495 #define GPDMA1_SGLREQDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA1 SGLREQDSTREG: WE_CH3 (Bit 11) */ 4496 #define GPDMA1_SGLREQDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA1 SGLREQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ 4497 4498 /* ------------------------------ GPDMA1_LSTSRCREG ------------------------------ */ 4499 #define GPDMA1_LSTSRCREG_CH0_Pos (0UL) /*!< GPDMA1 LSTSRCREG: CH0 (Bit 0) */ 4500 #define GPDMA1_LSTSRCREG_CH0_Msk (0x1UL) /*!< GPDMA1 LSTSRCREG: CH0 (Bitfield-Mask: 0x01) */ 4501 #define GPDMA1_LSTSRCREG_CH1_Pos (1UL) /*!< GPDMA1 LSTSRCREG: CH1 (Bit 1) */ 4502 #define GPDMA1_LSTSRCREG_CH1_Msk (0x2UL) /*!< GPDMA1 LSTSRCREG: CH1 (Bitfield-Mask: 0x01) */ 4503 #define GPDMA1_LSTSRCREG_CH2_Pos (2UL) /*!< GPDMA1 LSTSRCREG: CH2 (Bit 2) */ 4504 #define GPDMA1_LSTSRCREG_CH2_Msk (0x4UL) /*!< GPDMA1 LSTSRCREG: CH2 (Bitfield-Mask: 0x01) */ 4505 #define GPDMA1_LSTSRCREG_CH3_Pos (3UL) /*!< GPDMA1 LSTSRCREG: CH3 (Bit 3) */ 4506 #define GPDMA1_LSTSRCREG_CH3_Msk (0x8UL) /*!< GPDMA1 LSTSRCREG: CH3 (Bitfield-Mask: 0x01) */ 4507 #define GPDMA1_LSTSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA1 LSTSRCREG: WE_CH0 (Bit 8) */ 4508 #define GPDMA1_LSTSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA1 LSTSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ 4509 #define GPDMA1_LSTSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA1 LSTSRCREG: WE_CH1 (Bit 9) */ 4510 #define GPDMA1_LSTSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA1 LSTSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ 4511 #define GPDMA1_LSTSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA1 LSTSRCREG: WE_CH2 (Bit 10) */ 4512 #define GPDMA1_LSTSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA1 LSTSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ 4513 #define GPDMA1_LSTSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA1 LSTSRCREG: WE_CH3 (Bit 11) */ 4514 #define GPDMA1_LSTSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA1 LSTSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ 4515 4516 /* ------------------------------ GPDMA1_LSTDSTREG ------------------------------ */ 4517 #define GPDMA1_LSTDSTREG_CH0_Pos (0UL) /*!< GPDMA1 LSTDSTREG: CH0 (Bit 0) */ 4518 #define GPDMA1_LSTDSTREG_CH0_Msk (0x1UL) /*!< GPDMA1 LSTDSTREG: CH0 (Bitfield-Mask: 0x01) */ 4519 #define GPDMA1_LSTDSTREG_CH1_Pos (1UL) /*!< GPDMA1 LSTDSTREG: CH1 (Bit 1) */ 4520 #define GPDMA1_LSTDSTREG_CH1_Msk (0x2UL) /*!< GPDMA1 LSTDSTREG: CH1 (Bitfield-Mask: 0x01) */ 4521 #define GPDMA1_LSTDSTREG_CH2_Pos (2UL) /*!< GPDMA1 LSTDSTREG: CH2 (Bit 2) */ 4522 #define GPDMA1_LSTDSTREG_CH2_Msk (0x4UL) /*!< GPDMA1 LSTDSTREG: CH2 (Bitfield-Mask: 0x01) */ 4523 #define GPDMA1_LSTDSTREG_CH3_Pos (3UL) /*!< GPDMA1 LSTDSTREG: CH3 (Bit 3) */ 4524 #define GPDMA1_LSTDSTREG_CH3_Msk (0x8UL) /*!< GPDMA1 LSTDSTREG: CH3 (Bitfield-Mask: 0x01) */ 4525 #define GPDMA1_LSTDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA1 LSTDSTREG: WE_CH0 (Bit 8) */ 4526 #define GPDMA1_LSTDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA1 LSTDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ 4527 #define GPDMA1_LSTDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA1 LSTDSTREG: WE_CH1 (Bit 9) */ 4528 #define GPDMA1_LSTDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA1 LSTDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ 4529 #define GPDMA1_LSTDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA1 LSTDSTREG: WE_CH2 (Bit 10) */ 4530 #define GPDMA1_LSTDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA1 LSTDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ 4531 #define GPDMA1_LSTDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA1 LSTDSTREG: WE_CH3 (Bit 11) */ 4532 #define GPDMA1_LSTDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA1 LSTDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ 4533 4534 /* ------------------------------ GPDMA1_DMACFGREG ------------------------------ */ 4535 #define GPDMA1_DMACFGREG_DMA_EN_Pos (0UL) /*!< GPDMA1 DMACFGREG: DMA_EN (Bit 0) */ 4536 #define GPDMA1_DMACFGREG_DMA_EN_Msk (0x1UL) /*!< GPDMA1 DMACFGREG: DMA_EN (Bitfield-Mask: 0x01) */ 4537 4538 /* ------------------------------- GPDMA1_CHENREG ------------------------------- */ 4539 #define GPDMA1_CHENREG_CH_Pos (0UL) /*!< GPDMA1 CHENREG: CH (Bit 0) */ 4540 #define GPDMA1_CHENREG_CH_Msk (0xfUL) /*!< GPDMA1 CHENREG: CH (Bitfield-Mask: 0x0f) */ 4541 #define GPDMA1_CHENREG_WE_CH_Pos (8UL) /*!< GPDMA1 CHENREG: WE_CH (Bit 8) */ 4542 #define GPDMA1_CHENREG_WE_CH_Msk (0xf00UL) /*!< GPDMA1 CHENREG: WE_CH (Bitfield-Mask: 0x0f) */ 4543 4544 /* ---------------------------------- GPDMA1_ID --------------------------------- */ 4545 #define GPDMA1_ID_VALUE_Pos (0UL) /*!< GPDMA1 ID: VALUE (Bit 0) */ 4546 #define GPDMA1_ID_VALUE_Msk (0xffffffffUL) /*!< GPDMA1 ID: VALUE (Bitfield-Mask: 0xffffffff) */ 4547 4548 /* --------------------------------- GPDMA1_TYPE -------------------------------- */ 4549 #define GPDMA1_TYPE_VALUE_Pos (0UL) /*!< GPDMA1 TYPE: VALUE (Bit 0) */ 4550 #define GPDMA1_TYPE_VALUE_Msk (0xffffffffUL) /*!< GPDMA1 TYPE: VALUE (Bitfield-Mask: 0xffffffff) */ 4551 4552 /* ------------------------------- GPDMA1_VERSION ------------------------------- */ 4553 #define GPDMA1_VERSION_VALUE_Pos (0UL) /*!< GPDMA1 VERSION: VALUE (Bit 0) */ 4554 #define GPDMA1_VERSION_VALUE_Msk (0xffffffffUL) /*!< GPDMA1 VERSION: VALUE (Bitfield-Mask: 0xffffffff) */ 4555 4556 4557 /* ================================================================================ */ 4558 /* ================ Group 'GPDMA1_CH' Position & Mask ================ */ 4559 /* ================================================================================ */ 4560 4561 4562 /* -------------------------------- GPDMA1_CH_SAR ------------------------------- */ 4563 #define GPDMA1_CH_SAR_SAR_Pos (0UL) /*!< GPDMA1_CH SAR: SAR (Bit 0) */ 4564 #define GPDMA1_CH_SAR_SAR_Msk (0xffffffffUL) /*!< GPDMA1_CH SAR: SAR (Bitfield-Mask: 0xffffffff) */ 4565 4566 /* -------------------------------- GPDMA1_CH_DAR ------------------------------- */ 4567 #define GPDMA1_CH_DAR_DAR_Pos (0UL) /*!< GPDMA1_CH DAR: DAR (Bit 0) */ 4568 #define GPDMA1_CH_DAR_DAR_Msk (0xffffffffUL) /*!< GPDMA1_CH DAR: DAR (Bitfield-Mask: 0xffffffff) */ 4569 4570 /* ------------------------------- GPDMA1_CH_CTLL ------------------------------- */ 4571 #define GPDMA1_CH_CTLL_INT_EN_Pos (0UL) /*!< GPDMA1_CH CTLL: INT_EN (Bit 0) */ 4572 #define GPDMA1_CH_CTLL_INT_EN_Msk (0x1UL) /*!< GPDMA1_CH CTLL: INT_EN (Bitfield-Mask: 0x01) */ 4573 #define GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos (1UL) /*!< GPDMA1_CH CTLL: DST_TR_WIDTH (Bit 1) */ 4574 #define GPDMA1_CH_CTLL_DST_TR_WIDTH_Msk (0xeUL) /*!< GPDMA1_CH CTLL: DST_TR_WIDTH (Bitfield-Mask: 0x07) */ 4575 #define GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos (4UL) /*!< GPDMA1_CH CTLL: SRC_TR_WIDTH (Bit 4) */ 4576 #define GPDMA1_CH_CTLL_SRC_TR_WIDTH_Msk (0x70UL) /*!< GPDMA1_CH CTLL: SRC_TR_WIDTH (Bitfield-Mask: 0x07) */ 4577 #define GPDMA1_CH_CTLL_DINC_Pos (7UL) /*!< GPDMA1_CH CTLL: DINC (Bit 7) */ 4578 #define GPDMA1_CH_CTLL_DINC_Msk (0x180UL) /*!< GPDMA1_CH CTLL: DINC (Bitfield-Mask: 0x03) */ 4579 #define GPDMA1_CH_CTLL_SINC_Pos (9UL) /*!< GPDMA1_CH CTLL: SINC (Bit 9) */ 4580 #define GPDMA1_CH_CTLL_SINC_Msk (0x600UL) /*!< GPDMA1_CH CTLL: SINC (Bitfield-Mask: 0x03) */ 4581 #define GPDMA1_CH_CTLL_DEST_MSIZE_Pos (11UL) /*!< GPDMA1_CH CTLL: DEST_MSIZE (Bit 11) */ 4582 #define GPDMA1_CH_CTLL_DEST_MSIZE_Msk (0x3800UL) /*!< GPDMA1_CH CTLL: DEST_MSIZE (Bitfield-Mask: 0x07) */ 4583 #define GPDMA1_CH_CTLL_SRC_MSIZE_Pos (14UL) /*!< GPDMA1_CH CTLL: SRC_MSIZE (Bit 14) */ 4584 #define GPDMA1_CH_CTLL_SRC_MSIZE_Msk (0x1c000UL) /*!< GPDMA1_CH CTLL: SRC_MSIZE (Bitfield-Mask: 0x07) */ 4585 #define GPDMA1_CH_CTLL_TT_FC_Pos (20UL) /*!< GPDMA1_CH CTLL: TT_FC (Bit 20) */ 4586 #define GPDMA1_CH_CTLL_TT_FC_Msk (0x700000UL) /*!< GPDMA1_CH CTLL: TT_FC (Bitfield-Mask: 0x07) */ 4587 4588 /* ------------------------------- GPDMA1_CH_CTLH ------------------------------- */ 4589 #define GPDMA1_CH_CTLH_BLOCK_TS_Pos (0UL) /*!< GPDMA1_CH CTLH: BLOCK_TS (Bit 0) */ 4590 #define GPDMA1_CH_CTLH_BLOCK_TS_Msk (0xfffUL) /*!< GPDMA1_CH CTLH: BLOCK_TS (Bitfield-Mask: 0xfff) */ 4591 #define GPDMA1_CH_CTLH_DONE_Pos (12UL) /*!< GPDMA1_CH CTLH: DONE (Bit 12) */ 4592 #define GPDMA1_CH_CTLH_DONE_Msk (0x1000UL) /*!< GPDMA1_CH CTLH: DONE (Bitfield-Mask: 0x01) */ 4593 4594 /* ------------------------------- GPDMA1_CH_CFGL ------------------------------- */ 4595 #define GPDMA1_CH_CFGL_CH_PRIOR_Pos (5UL) /*!< GPDMA1_CH CFGL: CH_PRIOR (Bit 5) */ 4596 #define GPDMA1_CH_CFGL_CH_PRIOR_Msk (0xe0UL) /*!< GPDMA1_CH CFGL: CH_PRIOR (Bitfield-Mask: 0x07) */ 4597 #define GPDMA1_CH_CFGL_CH_SUSP_Pos (8UL) /*!< GPDMA1_CH CFGL: CH_SUSP (Bit 8) */ 4598 #define GPDMA1_CH_CFGL_CH_SUSP_Msk (0x100UL) /*!< GPDMA1_CH CFGL: CH_SUSP (Bitfield-Mask: 0x01) */ 4599 #define GPDMA1_CH_CFGL_FIFO_EMPTY_Pos (9UL) /*!< GPDMA1_CH CFGL: FIFO_EMPTY (Bit 9) */ 4600 #define GPDMA1_CH_CFGL_FIFO_EMPTY_Msk (0x200UL) /*!< GPDMA1_CH CFGL: FIFO_EMPTY (Bitfield-Mask: 0x01) */ 4601 #define GPDMA1_CH_CFGL_HS_SEL_DST_Pos (10UL) /*!< GPDMA1_CH CFGL: HS_SEL_DST (Bit 10) */ 4602 #define GPDMA1_CH_CFGL_HS_SEL_DST_Msk (0x400UL) /*!< GPDMA1_CH CFGL: HS_SEL_DST (Bitfield-Mask: 0x01) */ 4603 #define GPDMA1_CH_CFGL_HS_SEL_SRC_Pos (11UL) /*!< GPDMA1_CH CFGL: HS_SEL_SRC (Bit 11) */ 4604 #define GPDMA1_CH_CFGL_HS_SEL_SRC_Msk (0x800UL) /*!< GPDMA1_CH CFGL: HS_SEL_SRC (Bitfield-Mask: 0x01) */ 4605 #define GPDMA1_CH_CFGL_LOCK_CH_L_Pos (12UL) /*!< GPDMA1_CH CFGL: LOCK_CH_L (Bit 12) */ 4606 #define GPDMA1_CH_CFGL_LOCK_CH_L_Msk (0x3000UL) /*!< GPDMA1_CH CFGL: LOCK_CH_L (Bitfield-Mask: 0x03) */ 4607 #define GPDMA1_CH_CFGL_LOCK_B_L_Pos (14UL) /*!< GPDMA1_CH CFGL: LOCK_B_L (Bit 14) */ 4608 #define GPDMA1_CH_CFGL_LOCK_B_L_Msk (0xc000UL) /*!< GPDMA1_CH CFGL: LOCK_B_L (Bitfield-Mask: 0x03) */ 4609 #define GPDMA1_CH_CFGL_LOCK_CH_Pos (16UL) /*!< GPDMA1_CH CFGL: LOCK_CH (Bit 16) */ 4610 #define GPDMA1_CH_CFGL_LOCK_CH_Msk (0x10000UL) /*!< GPDMA1_CH CFGL: LOCK_CH (Bitfield-Mask: 0x01) */ 4611 #define GPDMA1_CH_CFGL_LOCK_B_Pos (17UL) /*!< GPDMA1_CH CFGL: LOCK_B (Bit 17) */ 4612 #define GPDMA1_CH_CFGL_LOCK_B_Msk (0x20000UL) /*!< GPDMA1_CH CFGL: LOCK_B (Bitfield-Mask: 0x01) */ 4613 #define GPDMA1_CH_CFGL_DST_HS_POL_Pos (18UL) /*!< GPDMA1_CH CFGL: DST_HS_POL (Bit 18) */ 4614 #define GPDMA1_CH_CFGL_DST_HS_POL_Msk (0x40000UL) /*!< GPDMA1_CH CFGL: DST_HS_POL (Bitfield-Mask: 0x01) */ 4615 #define GPDMA1_CH_CFGL_SRC_HS_POL_Pos (19UL) /*!< GPDMA1_CH CFGL: SRC_HS_POL (Bit 19) */ 4616 #define GPDMA1_CH_CFGL_SRC_HS_POL_Msk (0x80000UL) /*!< GPDMA1_CH CFGL: SRC_HS_POL (Bitfield-Mask: 0x01) */ 4617 #define GPDMA1_CH_CFGL_MAX_ABRST_Pos (20UL) /*!< GPDMA1_CH CFGL: MAX_ABRST (Bit 20) */ 4618 #define GPDMA1_CH_CFGL_MAX_ABRST_Msk (0x3ff00000UL) /*!< GPDMA1_CH CFGL: MAX_ABRST (Bitfield-Mask: 0x3ff) */ 4619 4620 /* ------------------------------- GPDMA1_CH_CFGH ------------------------------- */ 4621 #define GPDMA1_CH_CFGH_FCMODE_Pos (0UL) /*!< GPDMA1_CH CFGH: FCMODE (Bit 0) */ 4622 #define GPDMA1_CH_CFGH_FCMODE_Msk (0x1UL) /*!< GPDMA1_CH CFGH: FCMODE (Bitfield-Mask: 0x01) */ 4623 #define GPDMA1_CH_CFGH_FIFO_MODE_Pos (1UL) /*!< GPDMA1_CH CFGH: FIFO_MODE (Bit 1) */ 4624 #define GPDMA1_CH_CFGH_FIFO_MODE_Msk (0x2UL) /*!< GPDMA1_CH CFGH: FIFO_MODE (Bitfield-Mask: 0x01) */ 4625 #define GPDMA1_CH_CFGH_PROTCTL_Pos (2UL) /*!< GPDMA1_CH CFGH: PROTCTL (Bit 2) */ 4626 #define GPDMA1_CH_CFGH_PROTCTL_Msk (0x1cUL) /*!< GPDMA1_CH CFGH: PROTCTL (Bitfield-Mask: 0x07) */ 4627 #define GPDMA1_CH_CFGH_SRC_PER_Pos (7UL) /*!< GPDMA1_CH CFGH: SRC_PER (Bit 7) */ 4628 #define GPDMA1_CH_CFGH_SRC_PER_Msk (0x780UL) /*!< GPDMA1_CH CFGH: SRC_PER (Bitfield-Mask: 0x0f) */ 4629 #define GPDMA1_CH_CFGH_DEST_PER_Pos (11UL) /*!< GPDMA1_CH CFGH: DEST_PER (Bit 11) */ 4630 #define GPDMA1_CH_CFGH_DEST_PER_Msk (0x7800UL) /*!< GPDMA1_CH CFGH: DEST_PER (Bitfield-Mask: 0x0f) */ 4631 4632 4633 /* ================================================================================ */ 4634 /* ================ struct 'FCE' Position & Mask ================ */ 4635 /* ================================================================================ */ 4636 4637 4638 /* ----------------------------------- FCE_CLC ---------------------------------- */ 4639 #define FCE_CLC_DISR_Pos (0UL) /*!< FCE CLC: DISR (Bit 0) */ 4640 #define FCE_CLC_DISR_Msk (0x1UL) /*!< FCE CLC: DISR (Bitfield-Mask: 0x01) */ 4641 #define FCE_CLC_DISS_Pos (1UL) /*!< FCE CLC: DISS (Bit 1) */ 4642 #define FCE_CLC_DISS_Msk (0x2UL) /*!< FCE CLC: DISS (Bitfield-Mask: 0x01) */ 4643 4644 /* ----------------------------------- FCE_ID ----------------------------------- */ 4645 #define FCE_ID_MOD_REV_Pos (0UL) /*!< FCE ID: MOD_REV (Bit 0) */ 4646 #define FCE_ID_MOD_REV_Msk (0xffUL) /*!< FCE ID: MOD_REV (Bitfield-Mask: 0xff) */ 4647 #define FCE_ID_MOD_TYPE_Pos (8UL) /*!< FCE ID: MOD_TYPE (Bit 8) */ 4648 #define FCE_ID_MOD_TYPE_Msk (0xff00UL) /*!< FCE ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 4649 #define FCE_ID_MOD_NUMBER_Pos (16UL) /*!< FCE ID: MOD_NUMBER (Bit 16) */ 4650 #define FCE_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< FCE ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 4651 4652 4653 /* ================================================================================ */ 4654 /* ================ Group 'FCE_KE' Position & Mask ================ */ 4655 /* ================================================================================ */ 4656 4657 4658 /* ---------------------------------- FCE_KE_IR --------------------------------- */ 4659 #define FCE_KE_IR_IR_Pos (0UL) /*!< FCE_KE IR: IR (Bit 0) */ 4660 #define FCE_KE_IR_IR_Msk (0xffffffffUL) /*!< FCE_KE IR: IR (Bitfield-Mask: 0xffffffff) */ 4661 4662 /* --------------------------------- FCE_KE_RES --------------------------------- */ 4663 #define FCE_KE_RES_RES_Pos (0UL) /*!< FCE_KE RES: RES (Bit 0) */ 4664 #define FCE_KE_RES_RES_Msk (0xffffffffUL) /*!< FCE_KE RES: RES (Bitfield-Mask: 0xffffffff) */ 4665 4666 /* --------------------------------- FCE_KE_CFG --------------------------------- */ 4667 #define FCE_KE_CFG_CMI_Pos (0UL) /*!< FCE_KE CFG: CMI (Bit 0) */ 4668 #define FCE_KE_CFG_CMI_Msk (0x1UL) /*!< FCE_KE CFG: CMI (Bitfield-Mask: 0x01) */ 4669 #define FCE_KE_CFG_CEI_Pos (1UL) /*!< FCE_KE CFG: CEI (Bit 1) */ 4670 #define FCE_KE_CFG_CEI_Msk (0x2UL) /*!< FCE_KE CFG: CEI (Bitfield-Mask: 0x01) */ 4671 #define FCE_KE_CFG_LEI_Pos (2UL) /*!< FCE_KE CFG: LEI (Bit 2) */ 4672 #define FCE_KE_CFG_LEI_Msk (0x4UL) /*!< FCE_KE CFG: LEI (Bitfield-Mask: 0x01) */ 4673 #define FCE_KE_CFG_BEI_Pos (3UL) /*!< FCE_KE CFG: BEI (Bit 3) */ 4674 #define FCE_KE_CFG_BEI_Msk (0x8UL) /*!< FCE_KE CFG: BEI (Bitfield-Mask: 0x01) */ 4675 #define FCE_KE_CFG_CCE_Pos (4UL) /*!< FCE_KE CFG: CCE (Bit 4) */ 4676 #define FCE_KE_CFG_CCE_Msk (0x10UL) /*!< FCE_KE CFG: CCE (Bitfield-Mask: 0x01) */ 4677 #define FCE_KE_CFG_ALR_Pos (5UL) /*!< FCE_KE CFG: ALR (Bit 5) */ 4678 #define FCE_KE_CFG_ALR_Msk (0x20UL) /*!< FCE_KE CFG: ALR (Bitfield-Mask: 0x01) */ 4679 #define FCE_KE_CFG_REFIN_Pos (8UL) /*!< FCE_KE CFG: REFIN (Bit 8) */ 4680 #define FCE_KE_CFG_REFIN_Msk (0x100UL) /*!< FCE_KE CFG: REFIN (Bitfield-Mask: 0x01) */ 4681 #define FCE_KE_CFG_REFOUT_Pos (9UL) /*!< FCE_KE CFG: REFOUT (Bit 9) */ 4682 #define FCE_KE_CFG_REFOUT_Msk (0x200UL) /*!< FCE_KE CFG: REFOUT (Bitfield-Mask: 0x01) */ 4683 #define FCE_KE_CFG_XSEL_Pos (10UL) /*!< FCE_KE CFG: XSEL (Bit 10) */ 4684 #define FCE_KE_CFG_XSEL_Msk (0x400UL) /*!< FCE_KE CFG: XSEL (Bitfield-Mask: 0x01) */ 4685 4686 /* --------------------------------- FCE_KE_STS --------------------------------- */ 4687 #define FCE_KE_STS_CMF_Pos (0UL) /*!< FCE_KE STS: CMF (Bit 0) */ 4688 #define FCE_KE_STS_CMF_Msk (0x1UL) /*!< FCE_KE STS: CMF (Bitfield-Mask: 0x01) */ 4689 #define FCE_KE_STS_CEF_Pos (1UL) /*!< FCE_KE STS: CEF (Bit 1) */ 4690 #define FCE_KE_STS_CEF_Msk (0x2UL) /*!< FCE_KE STS: CEF (Bitfield-Mask: 0x01) */ 4691 #define FCE_KE_STS_LEF_Pos (2UL) /*!< FCE_KE STS: LEF (Bit 2) */ 4692 #define FCE_KE_STS_LEF_Msk (0x4UL) /*!< FCE_KE STS: LEF (Bitfield-Mask: 0x01) */ 4693 #define FCE_KE_STS_BEF_Pos (3UL) /*!< FCE_KE STS: BEF (Bit 3) */ 4694 #define FCE_KE_STS_BEF_Msk (0x8UL) /*!< FCE_KE STS: BEF (Bitfield-Mask: 0x01) */ 4695 4696 /* -------------------------------- FCE_KE_LENGTH ------------------------------- */ 4697 #define FCE_KE_LENGTH_LENGTH_Pos (0UL) /*!< FCE_KE LENGTH: LENGTH (Bit 0) */ 4698 #define FCE_KE_LENGTH_LENGTH_Msk (0xffffUL) /*!< FCE_KE LENGTH: LENGTH (Bitfield-Mask: 0xffff) */ 4699 4700 /* -------------------------------- FCE_KE_CHECK -------------------------------- */ 4701 #define FCE_KE_CHECK_CHECK_Pos (0UL) /*!< FCE_KE CHECK: CHECK (Bit 0) */ 4702 #define FCE_KE_CHECK_CHECK_Msk (0xffffffffUL) /*!< FCE_KE CHECK: CHECK (Bitfield-Mask: 0xffffffff) */ 4703 4704 /* --------------------------------- FCE_KE_CRC --------------------------------- */ 4705 #define FCE_KE_CRC_CRC_Pos (0UL) /*!< FCE_KE CRC: CRC (Bit 0) */ 4706 #define FCE_KE_CRC_CRC_Msk (0xffffffffUL) /*!< FCE_KE CRC: CRC (Bitfield-Mask: 0xffffffff) */ 4707 4708 /* --------------------------------- FCE_KE_CTR --------------------------------- */ 4709 #define FCE_KE_CTR_FCM_Pos (0UL) /*!< FCE_KE CTR: FCM (Bit 0) */ 4710 #define FCE_KE_CTR_FCM_Msk (0x1UL) /*!< FCE_KE CTR: FCM (Bitfield-Mask: 0x01) */ 4711 #define FCE_KE_CTR_FRM_CFG_Pos (1UL) /*!< FCE_KE CTR: FRM_CFG (Bit 1) */ 4712 #define FCE_KE_CTR_FRM_CFG_Msk (0x2UL) /*!< FCE_KE CTR: FRM_CFG (Bitfield-Mask: 0x01) */ 4713 #define FCE_KE_CTR_FRM_CHECK_Pos (2UL) /*!< FCE_KE CTR: FRM_CHECK (Bit 2) */ 4714 #define FCE_KE_CTR_FRM_CHECK_Msk (0x4UL) /*!< FCE_KE CTR: FRM_CHECK (Bitfield-Mask: 0x01) */ 4715 4716 4717 /* ================================================================================ */ 4718 /* ================ Group 'PBA' Position & Mask ================ */ 4719 /* ================================================================================ */ 4720 4721 4722 /* ----------------------------------- PBA_STS ---------------------------------- */ 4723 #define PBA_STS_WERR_Pos (0UL) /*!< PBA STS: WERR (Bit 0) */ 4724 #define PBA_STS_WERR_Msk (0x1UL) /*!< PBA STS: WERR (Bitfield-Mask: 0x01) */ 4725 4726 /* ---------------------------------- PBA_WADDR --------------------------------- */ 4727 #define PBA_WADDR_WADDR_Pos (0UL) /*!< PBA WADDR: WADDR (Bit 0) */ 4728 #define PBA_WADDR_WADDR_Msk (0xffffffffUL) /*!< PBA WADDR: WADDR (Bitfield-Mask: 0xffffffff) */ 4729 4730 4731 /* ================================================================================ */ 4732 /* ================ Group 'FLASH' Position & Mask ================ */ 4733 /* ================================================================================ */ 4734 4735 4736 /* ---------------------------------- FLASH_ID ---------------------------------- */ 4737 #define FLASH_ID_MOD_REV_Pos (0UL) /*!< FLASH ID: MOD_REV (Bit 0) */ 4738 #define FLASH_ID_MOD_REV_Msk (0xffUL) /*!< FLASH ID: MOD_REV (Bitfield-Mask: 0xff) */ 4739 #define FLASH_ID_MOD_TYPE_Pos (8UL) /*!< FLASH ID: MOD_TYPE (Bit 8) */ 4740 #define FLASH_ID_MOD_TYPE_Msk (0xff00UL) /*!< FLASH ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 4741 #define FLASH_ID_MOD_NUMBER_Pos (16UL) /*!< FLASH ID: MOD_NUMBER (Bit 16) */ 4742 #define FLASH_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< FLASH ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 4743 4744 /* ---------------------------------- FLASH_FSR --------------------------------- */ 4745 #define FLASH_FSR_PBUSY_Pos (0UL) /*!< FLASH FSR: PBUSY (Bit 0) */ 4746 #define FLASH_FSR_PBUSY_Msk (0x1UL) /*!< FLASH FSR: PBUSY (Bitfield-Mask: 0x01) */ 4747 #define FLASH_FSR_FABUSY_Pos (1UL) /*!< FLASH FSR: FABUSY (Bit 1) */ 4748 #define FLASH_FSR_FABUSY_Msk (0x2UL) /*!< FLASH FSR: FABUSY (Bitfield-Mask: 0x01) */ 4749 #define FLASH_FSR_PROG_Pos (4UL) /*!< FLASH FSR: PROG (Bit 4) */ 4750 #define FLASH_FSR_PROG_Msk (0x10UL) /*!< FLASH FSR: PROG (Bitfield-Mask: 0x01) */ 4751 #define FLASH_FSR_ERASE_Pos (5UL) /*!< FLASH FSR: ERASE (Bit 5) */ 4752 #define FLASH_FSR_ERASE_Msk (0x20UL) /*!< FLASH FSR: ERASE (Bitfield-Mask: 0x01) */ 4753 #define FLASH_FSR_PFPAGE_Pos (6UL) /*!< FLASH FSR: PFPAGE (Bit 6) */ 4754 #define FLASH_FSR_PFPAGE_Msk (0x40UL) /*!< FLASH FSR: PFPAGE (Bitfield-Mask: 0x01) */ 4755 #define FLASH_FSR_PFOPER_Pos (8UL) /*!< FLASH FSR: PFOPER (Bit 8) */ 4756 #define FLASH_FSR_PFOPER_Msk (0x100UL) /*!< FLASH FSR: PFOPER (Bitfield-Mask: 0x01) */ 4757 #define FLASH_FSR_SQER_Pos (10UL) /*!< FLASH FSR: SQER (Bit 10) */ 4758 #define FLASH_FSR_SQER_Msk (0x400UL) /*!< FLASH FSR: SQER (Bitfield-Mask: 0x01) */ 4759 #define FLASH_FSR_PROER_Pos (11UL) /*!< FLASH FSR: PROER (Bit 11) */ 4760 #define FLASH_FSR_PROER_Msk (0x800UL) /*!< FLASH FSR: PROER (Bitfield-Mask: 0x01) */ 4761 #define FLASH_FSR_PFSBER_Pos (12UL) /*!< FLASH FSR: PFSBER (Bit 12) */ 4762 #define FLASH_FSR_PFSBER_Msk (0x1000UL) /*!< FLASH FSR: PFSBER (Bitfield-Mask: 0x01) */ 4763 #define FLASH_FSR_PFDBER_Pos (14UL) /*!< FLASH FSR: PFDBER (Bit 14) */ 4764 #define FLASH_FSR_PFDBER_Msk (0x4000UL) /*!< FLASH FSR: PFDBER (Bitfield-Mask: 0x01) */ 4765 #define FLASH_FSR_PROIN_Pos (16UL) /*!< FLASH FSR: PROIN (Bit 16) */ 4766 #define FLASH_FSR_PROIN_Msk (0x10000UL) /*!< FLASH FSR: PROIN (Bitfield-Mask: 0x01) */ 4767 #define FLASH_FSR_RPROIN_Pos (18UL) /*!< FLASH FSR: RPROIN (Bit 18) */ 4768 #define FLASH_FSR_RPROIN_Msk (0x40000UL) /*!< FLASH FSR: RPROIN (Bitfield-Mask: 0x01) */ 4769 #define FLASH_FSR_RPRODIS_Pos (19UL) /*!< FLASH FSR: RPRODIS (Bit 19) */ 4770 #define FLASH_FSR_RPRODIS_Msk (0x80000UL) /*!< FLASH FSR: RPRODIS (Bitfield-Mask: 0x01) */ 4771 #define FLASH_FSR_WPROIN0_Pos (21UL) /*!< FLASH FSR: WPROIN0 (Bit 21) */ 4772 #define FLASH_FSR_WPROIN0_Msk (0x200000UL) /*!< FLASH FSR: WPROIN0 (Bitfield-Mask: 0x01) */ 4773 #define FLASH_FSR_WPROIN1_Pos (22UL) /*!< FLASH FSR: WPROIN1 (Bit 22) */ 4774 #define FLASH_FSR_WPROIN1_Msk (0x400000UL) /*!< FLASH FSR: WPROIN1 (Bitfield-Mask: 0x01) */ 4775 #define FLASH_FSR_WPROIN2_Pos (23UL) /*!< FLASH FSR: WPROIN2 (Bit 23) */ 4776 #define FLASH_FSR_WPROIN2_Msk (0x800000UL) /*!< FLASH FSR: WPROIN2 (Bitfield-Mask: 0x01) */ 4777 #define FLASH_FSR_WPRODIS0_Pos (25UL) /*!< FLASH FSR: WPRODIS0 (Bit 25) */ 4778 #define FLASH_FSR_WPRODIS0_Msk (0x2000000UL) /*!< FLASH FSR: WPRODIS0 (Bitfield-Mask: 0x01) */ 4779 #define FLASH_FSR_WPRODIS1_Pos (26UL) /*!< FLASH FSR: WPRODIS1 (Bit 26) */ 4780 #define FLASH_FSR_WPRODIS1_Msk (0x4000000UL) /*!< FLASH FSR: WPRODIS1 (Bitfield-Mask: 0x01) */ 4781 #define FLASH_FSR_SLM_Pos (28UL) /*!< FLASH FSR: SLM (Bit 28) */ 4782 #define FLASH_FSR_SLM_Msk (0x10000000UL) /*!< FLASH FSR: SLM (Bitfield-Mask: 0x01) */ 4783 #define FLASH_FSR_VER_Pos (31UL) /*!< FLASH FSR: VER (Bit 31) */ 4784 #define FLASH_FSR_VER_Msk (0x80000000UL) /*!< FLASH FSR: VER (Bitfield-Mask: 0x01) */ 4785 4786 /* --------------------------------- FLASH_FCON --------------------------------- */ 4787 #define FLASH_FCON_WSPFLASH_Pos (0UL) /*!< FLASH FCON: WSPFLASH (Bit 0) */ 4788 #define FLASH_FCON_WSPFLASH_Msk (0xfUL) /*!< FLASH FCON: WSPFLASH (Bitfield-Mask: 0x0f) */ 4789 #define FLASH_FCON_WSECPF_Pos (4UL) /*!< FLASH FCON: WSECPF (Bit 4) */ 4790 #define FLASH_FCON_WSECPF_Msk (0x10UL) /*!< FLASH FCON: WSECPF (Bitfield-Mask: 0x01) */ 4791 #define FLASH_FCON_IDLE_Pos (13UL) /*!< FLASH FCON: IDLE (Bit 13) */ 4792 #define FLASH_FCON_IDLE_Msk (0x2000UL) /*!< FLASH FCON: IDLE (Bitfield-Mask: 0x01) */ 4793 #define FLASH_FCON_ESLDIS_Pos (14UL) /*!< FLASH FCON: ESLDIS (Bit 14) */ 4794 #define FLASH_FCON_ESLDIS_Msk (0x4000UL) /*!< FLASH FCON: ESLDIS (Bitfield-Mask: 0x01) */ 4795 #define FLASH_FCON_SLEEP_Pos (15UL) /*!< FLASH FCON: SLEEP (Bit 15) */ 4796 #define FLASH_FCON_SLEEP_Msk (0x8000UL) /*!< FLASH FCON: SLEEP (Bitfield-Mask: 0x01) */ 4797 #define FLASH_FCON_RPA_Pos (16UL) /*!< FLASH FCON: RPA (Bit 16) */ 4798 #define FLASH_FCON_RPA_Msk (0x10000UL) /*!< FLASH FCON: RPA (Bitfield-Mask: 0x01) */ 4799 #define FLASH_FCON_DCF_Pos (17UL) /*!< FLASH FCON: DCF (Bit 17) */ 4800 #define FLASH_FCON_DCF_Msk (0x20000UL) /*!< FLASH FCON: DCF (Bitfield-Mask: 0x01) */ 4801 #define FLASH_FCON_DDF_Pos (18UL) /*!< FLASH FCON: DDF (Bit 18) */ 4802 #define FLASH_FCON_DDF_Msk (0x40000UL) /*!< FLASH FCON: DDF (Bitfield-Mask: 0x01) */ 4803 #define FLASH_FCON_VOPERM_Pos (24UL) /*!< FLASH FCON: VOPERM (Bit 24) */ 4804 #define FLASH_FCON_VOPERM_Msk (0x1000000UL) /*!< FLASH FCON: VOPERM (Bitfield-Mask: 0x01) */ 4805 #define FLASH_FCON_SQERM_Pos (25UL) /*!< FLASH FCON: SQERM (Bit 25) */ 4806 #define FLASH_FCON_SQERM_Msk (0x2000000UL) /*!< FLASH FCON: SQERM (Bitfield-Mask: 0x01) */ 4807 #define FLASH_FCON_PROERM_Pos (26UL) /*!< FLASH FCON: PROERM (Bit 26) */ 4808 #define FLASH_FCON_PROERM_Msk (0x4000000UL) /*!< FLASH FCON: PROERM (Bitfield-Mask: 0x01) */ 4809 #define FLASH_FCON_PFSBERM_Pos (27UL) /*!< FLASH FCON: PFSBERM (Bit 27) */ 4810 #define FLASH_FCON_PFSBERM_Msk (0x8000000UL) /*!< FLASH FCON: PFSBERM (Bitfield-Mask: 0x01) */ 4811 #define FLASH_FCON_PFDBERM_Pos (29UL) /*!< FLASH FCON: PFDBERM (Bit 29) */ 4812 #define FLASH_FCON_PFDBERM_Msk (0x20000000UL) /*!< FLASH FCON: PFDBERM (Bitfield-Mask: 0x01) */ 4813 #define FLASH_FCON_EOBM_Pos (31UL) /*!< FLASH FCON: EOBM (Bit 31) */ 4814 #define FLASH_FCON_EOBM_Msk (0x80000000UL) /*!< FLASH FCON: EOBM (Bitfield-Mask: 0x01) */ 4815 4816 /* --------------------------------- FLASH_MARP --------------------------------- */ 4817 #define FLASH_MARP_MARGIN_Pos (0UL) /*!< FLASH MARP: MARGIN (Bit 0) */ 4818 #define FLASH_MARP_MARGIN_Msk (0xfUL) /*!< FLASH MARP: MARGIN (Bitfield-Mask: 0x0f) */ 4819 #define FLASH_MARP_TRAPDIS_Pos (15UL) /*!< FLASH MARP: TRAPDIS (Bit 15) */ 4820 #define FLASH_MARP_TRAPDIS_Msk (0x8000UL) /*!< FLASH MARP: TRAPDIS (Bitfield-Mask: 0x01) */ 4821 4822 /* -------------------------------- FLASH_PROCON0 ------------------------------- */ 4823 #define FLASH_PROCON0_S0L_Pos (0UL) /*!< FLASH PROCON0: S0L (Bit 0) */ 4824 #define FLASH_PROCON0_S0L_Msk (0x1UL) /*!< FLASH PROCON0: S0L (Bitfield-Mask: 0x01) */ 4825 #define FLASH_PROCON0_S1L_Pos (1UL) /*!< FLASH PROCON0: S1L (Bit 1) */ 4826 #define FLASH_PROCON0_S1L_Msk (0x2UL) /*!< FLASH PROCON0: S1L (Bitfield-Mask: 0x01) */ 4827 #define FLASH_PROCON0_S2L_Pos (2UL) /*!< FLASH PROCON0: S2L (Bit 2) */ 4828 #define FLASH_PROCON0_S2L_Msk (0x4UL) /*!< FLASH PROCON0: S2L (Bitfield-Mask: 0x01) */ 4829 #define FLASH_PROCON0_S3L_Pos (3UL) /*!< FLASH PROCON0: S3L (Bit 3) */ 4830 #define FLASH_PROCON0_S3L_Msk (0x8UL) /*!< FLASH PROCON0: S3L (Bitfield-Mask: 0x01) */ 4831 #define FLASH_PROCON0_S4L_Pos (4UL) /*!< FLASH PROCON0: S4L (Bit 4) */ 4832 #define FLASH_PROCON0_S4L_Msk (0x10UL) /*!< FLASH PROCON0: S4L (Bitfield-Mask: 0x01) */ 4833 #define FLASH_PROCON0_S5L_Pos (5UL) /*!< FLASH PROCON0: S5L (Bit 5) */ 4834 #define FLASH_PROCON0_S5L_Msk (0x20UL) /*!< FLASH PROCON0: S5L (Bitfield-Mask: 0x01) */ 4835 #define FLASH_PROCON0_S6L_Pos (6UL) /*!< FLASH PROCON0: S6L (Bit 6) */ 4836 #define FLASH_PROCON0_S6L_Msk (0x40UL) /*!< FLASH PROCON0: S6L (Bitfield-Mask: 0x01) */ 4837 #define FLASH_PROCON0_S7L_Pos (7UL) /*!< FLASH PROCON0: S7L (Bit 7) */ 4838 #define FLASH_PROCON0_S7L_Msk (0x80UL) /*!< FLASH PROCON0: S7L (Bitfield-Mask: 0x01) */ 4839 #define FLASH_PROCON0_S8L_Pos (8UL) /*!< FLASH PROCON0: S8L (Bit 8) */ 4840 #define FLASH_PROCON0_S8L_Msk (0x100UL) /*!< FLASH PROCON0: S8L (Bitfield-Mask: 0x01) */ 4841 #define FLASH_PROCON0_S9L_Pos (9UL) /*!< FLASH PROCON0: S9L (Bit 9) */ 4842 #define FLASH_PROCON0_S9L_Msk (0x200UL) /*!< FLASH PROCON0: S9L (Bitfield-Mask: 0x01) */ 4843 #define FLASH_PROCON0_S10_S11L_Pos (10UL) /*!< FLASH PROCON0: S10_S11L (Bit 10) */ 4844 #define FLASH_PROCON0_S10_S11L_Msk (0x400UL) /*!< FLASH PROCON0: S10_S11L (Bitfield-Mask: 0x01) */ 4845 #define FLASH_PROCON0_RPRO_Pos (15UL) /*!< FLASH PROCON0: RPRO (Bit 15) */ 4846 #define FLASH_PROCON0_RPRO_Msk (0x8000UL) /*!< FLASH PROCON0: RPRO (Bitfield-Mask: 0x01) */ 4847 4848 /* -------------------------------- FLASH_PROCON1 ------------------------------- */ 4849 #define FLASH_PROCON1_S0L_Pos (0UL) /*!< FLASH PROCON1: S0L (Bit 0) */ 4850 #define FLASH_PROCON1_S0L_Msk (0x1UL) /*!< FLASH PROCON1: S0L (Bitfield-Mask: 0x01) */ 4851 #define FLASH_PROCON1_S1L_Pos (1UL) /*!< FLASH PROCON1: S1L (Bit 1) */ 4852 #define FLASH_PROCON1_S1L_Msk (0x2UL) /*!< FLASH PROCON1: S1L (Bitfield-Mask: 0x01) */ 4853 #define FLASH_PROCON1_S2L_Pos (2UL) /*!< FLASH PROCON1: S2L (Bit 2) */ 4854 #define FLASH_PROCON1_S2L_Msk (0x4UL) /*!< FLASH PROCON1: S2L (Bitfield-Mask: 0x01) */ 4855 #define FLASH_PROCON1_S3L_Pos (3UL) /*!< FLASH PROCON1: S3L (Bit 3) */ 4856 #define FLASH_PROCON1_S3L_Msk (0x8UL) /*!< FLASH PROCON1: S3L (Bitfield-Mask: 0x01) */ 4857 #define FLASH_PROCON1_S4L_Pos (4UL) /*!< FLASH PROCON1: S4L (Bit 4) */ 4858 #define FLASH_PROCON1_S4L_Msk (0x10UL) /*!< FLASH PROCON1: S4L (Bitfield-Mask: 0x01) */ 4859 #define FLASH_PROCON1_S5L_Pos (5UL) /*!< FLASH PROCON1: S5L (Bit 5) */ 4860 #define FLASH_PROCON1_S5L_Msk (0x20UL) /*!< FLASH PROCON1: S5L (Bitfield-Mask: 0x01) */ 4861 #define FLASH_PROCON1_S6L_Pos (6UL) /*!< FLASH PROCON1: S6L (Bit 6) */ 4862 #define FLASH_PROCON1_S6L_Msk (0x40UL) /*!< FLASH PROCON1: S6L (Bitfield-Mask: 0x01) */ 4863 #define FLASH_PROCON1_S7L_Pos (7UL) /*!< FLASH PROCON1: S7L (Bit 7) */ 4864 #define FLASH_PROCON1_S7L_Msk (0x80UL) /*!< FLASH PROCON1: S7L (Bitfield-Mask: 0x01) */ 4865 #define FLASH_PROCON1_S8L_Pos (8UL) /*!< FLASH PROCON1: S8L (Bit 8) */ 4866 #define FLASH_PROCON1_S8L_Msk (0x100UL) /*!< FLASH PROCON1: S8L (Bitfield-Mask: 0x01) */ 4867 #define FLASH_PROCON1_S9L_Pos (9UL) /*!< FLASH PROCON1: S9L (Bit 9) */ 4868 #define FLASH_PROCON1_S9L_Msk (0x200UL) /*!< FLASH PROCON1: S9L (Bitfield-Mask: 0x01) */ 4869 #define FLASH_PROCON1_S10_S11L_Pos (10UL) /*!< FLASH PROCON1: S10_S11L (Bit 10) */ 4870 #define FLASH_PROCON1_S10_S11L_Msk (0x400UL) /*!< FLASH PROCON1: S10_S11L (Bitfield-Mask: 0x01) */ 4871 4872 /* -------------------------------- FLASH_PROCON2 ------------------------------- */ 4873 #define FLASH_PROCON2_S0ROM_Pos (0UL) /*!< FLASH PROCON2: S0ROM (Bit 0) */ 4874 #define FLASH_PROCON2_S0ROM_Msk (0x1UL) /*!< FLASH PROCON2: S0ROM (Bitfield-Mask: 0x01) */ 4875 #define FLASH_PROCON2_S1ROM_Pos (1UL) /*!< FLASH PROCON2: S1ROM (Bit 1) */ 4876 #define FLASH_PROCON2_S1ROM_Msk (0x2UL) /*!< FLASH PROCON2: S1ROM (Bitfield-Mask: 0x01) */ 4877 #define FLASH_PROCON2_S2ROM_Pos (2UL) /*!< FLASH PROCON2: S2ROM (Bit 2) */ 4878 #define FLASH_PROCON2_S2ROM_Msk (0x4UL) /*!< FLASH PROCON2: S2ROM (Bitfield-Mask: 0x01) */ 4879 #define FLASH_PROCON2_S3ROM_Pos (3UL) /*!< FLASH PROCON2: S3ROM (Bit 3) */ 4880 #define FLASH_PROCON2_S3ROM_Msk (0x8UL) /*!< FLASH PROCON2: S3ROM (Bitfield-Mask: 0x01) */ 4881 #define FLASH_PROCON2_S4ROM_Pos (4UL) /*!< FLASH PROCON2: S4ROM (Bit 4) */ 4882 #define FLASH_PROCON2_S4ROM_Msk (0x10UL) /*!< FLASH PROCON2: S4ROM (Bitfield-Mask: 0x01) */ 4883 #define FLASH_PROCON2_S5ROM_Pos (5UL) /*!< FLASH PROCON2: S5ROM (Bit 5) */ 4884 #define FLASH_PROCON2_S5ROM_Msk (0x20UL) /*!< FLASH PROCON2: S5ROM (Bitfield-Mask: 0x01) */ 4885 #define FLASH_PROCON2_S6ROM_Pos (6UL) /*!< FLASH PROCON2: S6ROM (Bit 6) */ 4886 #define FLASH_PROCON2_S6ROM_Msk (0x40UL) /*!< FLASH PROCON2: S6ROM (Bitfield-Mask: 0x01) */ 4887 #define FLASH_PROCON2_S7ROM_Pos (7UL) /*!< FLASH PROCON2: S7ROM (Bit 7) */ 4888 #define FLASH_PROCON2_S7ROM_Msk (0x80UL) /*!< FLASH PROCON2: S7ROM (Bitfield-Mask: 0x01) */ 4889 #define FLASH_PROCON2_S8ROM_Pos (8UL) /*!< FLASH PROCON2: S8ROM (Bit 8) */ 4890 #define FLASH_PROCON2_S8ROM_Msk (0x100UL) /*!< FLASH PROCON2: S8ROM (Bitfield-Mask: 0x01) */ 4891 #define FLASH_PROCON2_S9ROM_Pos (9UL) /*!< FLASH PROCON2: S9ROM (Bit 9) */ 4892 #define FLASH_PROCON2_S9ROM_Msk (0x200UL) /*!< FLASH PROCON2: S9ROM (Bitfield-Mask: 0x01) */ 4893 #define FLASH_PROCON2_S10_S11ROM_Pos (10UL) /*!< FLASH PROCON2: S10_S11ROM (Bit 10) */ 4894 #define FLASH_PROCON2_S10_S11ROM_Msk (0x400UL) /*!< FLASH PROCON2: S10_S11ROM (Bitfield-Mask: 0x01) */ 4895 4896 4897 /* ================================================================================ */ 4898 /* ================ struct 'PREF' Position & Mask ================ */ 4899 /* ================================================================================ */ 4900 4901 4902 /* ---------------------------------- PREF_PCON --------------------------------- */ 4903 #define PREF_PCON_IBYP_Pos (0UL) /*!< PREF PCON: IBYP (Bit 0) */ 4904 #define PREF_PCON_IBYP_Msk (0x1UL) /*!< PREF PCON: IBYP (Bitfield-Mask: 0x01) */ 4905 #define PREF_PCON_IINV_Pos (1UL) /*!< PREF PCON: IINV (Bit 1) */ 4906 #define PREF_PCON_IINV_Msk (0x2UL) /*!< PREF PCON: IINV (Bitfield-Mask: 0x01) */ 4907 4908 4909 /* ================================================================================ */ 4910 /* ================ Group 'PMU' Position & Mask ================ */ 4911 /* ================================================================================ */ 4912 4913 4914 /* ----------------------------------- PMU_ID ----------------------------------- */ 4915 #define PMU_ID_MOD_REV_Pos (0UL) /*!< PMU ID: MOD_REV (Bit 0) */ 4916 #define PMU_ID_MOD_REV_Msk (0xffUL) /*!< PMU ID: MOD_REV (Bitfield-Mask: 0xff) */ 4917 #define PMU_ID_MOD_TYPE_Pos (8UL) /*!< PMU ID: MOD_TYPE (Bit 8) */ 4918 #define PMU_ID_MOD_TYPE_Msk (0xff00UL) /*!< PMU ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 4919 #define PMU_ID_MOD_NUMBER_Pos (16UL) /*!< PMU ID: MOD_NUMBER (Bit 16) */ 4920 #define PMU_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< PMU ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 4921 4922 4923 /* ================================================================================ */ 4924 /* ================ struct 'WDT' Position & Mask ================ */ 4925 /* ================================================================================ */ 4926 4927 4928 /* ----------------------------------- WDT_ID ----------------------------------- */ 4929 #define WDT_ID_MOD_REV_Pos (0UL) /*!< WDT ID: MOD_REV (Bit 0) */ 4930 #define WDT_ID_MOD_REV_Msk (0xffUL) /*!< WDT ID: MOD_REV (Bitfield-Mask: 0xff) */ 4931 #define WDT_ID_MOD_TYPE_Pos (8UL) /*!< WDT ID: MOD_TYPE (Bit 8) */ 4932 #define WDT_ID_MOD_TYPE_Msk (0xff00UL) /*!< WDT ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 4933 #define WDT_ID_MOD_NUMBER_Pos (16UL) /*!< WDT ID: MOD_NUMBER (Bit 16) */ 4934 #define WDT_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< WDT ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 4935 4936 /* ----------------------------------- WDT_CTR ---------------------------------- */ 4937 #define WDT_CTR_ENB_Pos (0UL) /*!< WDT CTR: ENB (Bit 0) */ 4938 #define WDT_CTR_ENB_Msk (0x1UL) /*!< WDT CTR: ENB (Bitfield-Mask: 0x01) */ 4939 #define WDT_CTR_PRE_Pos (1UL) /*!< WDT CTR: PRE (Bit 1) */ 4940 #define WDT_CTR_PRE_Msk (0x2UL) /*!< WDT CTR: PRE (Bitfield-Mask: 0x01) */ 4941 #define WDT_CTR_DSP_Pos (4UL) /*!< WDT CTR: DSP (Bit 4) */ 4942 #define WDT_CTR_DSP_Msk (0x10UL) /*!< WDT CTR: DSP (Bitfield-Mask: 0x01) */ 4943 #define WDT_CTR_SPW_Pos (8UL) /*!< WDT CTR: SPW (Bit 8) */ 4944 #define WDT_CTR_SPW_Msk (0xff00UL) /*!< WDT CTR: SPW (Bitfield-Mask: 0xff) */ 4945 4946 /* ----------------------------------- WDT_SRV ---------------------------------- */ 4947 #define WDT_SRV_SRV_Pos (0UL) /*!< WDT SRV: SRV (Bit 0) */ 4948 #define WDT_SRV_SRV_Msk (0xffffffffUL) /*!< WDT SRV: SRV (Bitfield-Mask: 0xffffffff) */ 4949 4950 /* ----------------------------------- WDT_TIM ---------------------------------- */ 4951 #define WDT_TIM_TIM_Pos (0UL) /*!< WDT TIM: TIM (Bit 0) */ 4952 #define WDT_TIM_TIM_Msk (0xffffffffUL) /*!< WDT TIM: TIM (Bitfield-Mask: 0xffffffff) */ 4953 4954 /* ----------------------------------- WDT_WLB ---------------------------------- */ 4955 #define WDT_WLB_WLB_Pos (0UL) /*!< WDT WLB: WLB (Bit 0) */ 4956 #define WDT_WLB_WLB_Msk (0xffffffffUL) /*!< WDT WLB: WLB (Bitfield-Mask: 0xffffffff) */ 4957 4958 /* ----------------------------------- WDT_WUB ---------------------------------- */ 4959 #define WDT_WUB_WUB_Pos (0UL) /*!< WDT WUB: WUB (Bit 0) */ 4960 #define WDT_WUB_WUB_Msk (0xffffffffUL) /*!< WDT WUB: WUB (Bitfield-Mask: 0xffffffff) */ 4961 4962 /* --------------------------------- WDT_WDTSTS --------------------------------- */ 4963 #define WDT_WDTSTS_ALMS_Pos (0UL) /*!< WDT WDTSTS: ALMS (Bit 0) */ 4964 #define WDT_WDTSTS_ALMS_Msk (0x1UL) /*!< WDT WDTSTS: ALMS (Bitfield-Mask: 0x01) */ 4965 4966 /* --------------------------------- WDT_WDTCLR --------------------------------- */ 4967 #define WDT_WDTCLR_ALMC_Pos (0UL) /*!< WDT WDTCLR: ALMC (Bit 0) */ 4968 #define WDT_WDTCLR_ALMC_Msk (0x1UL) /*!< WDT WDTCLR: ALMC (Bitfield-Mask: 0x01) */ 4969 4970 4971 /* ================================================================================ */ 4972 /* ================ struct 'RTC' Position & Mask ================ */ 4973 /* ================================================================================ */ 4974 4975 4976 /* ----------------------------------- RTC_ID ----------------------------------- */ 4977 #define RTC_ID_MOD_REV_Pos (0UL) /*!< RTC ID: MOD_REV (Bit 0) */ 4978 #define RTC_ID_MOD_REV_Msk (0xffUL) /*!< RTC ID: MOD_REV (Bitfield-Mask: 0xff) */ 4979 #define RTC_ID_MOD_TYPE_Pos (8UL) /*!< RTC ID: MOD_TYPE (Bit 8) */ 4980 #define RTC_ID_MOD_TYPE_Msk (0xff00UL) /*!< RTC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 4981 #define RTC_ID_MOD_NUMBER_Pos (16UL) /*!< RTC ID: MOD_NUMBER (Bit 16) */ 4982 #define RTC_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< RTC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 4983 4984 /* ----------------------------------- RTC_CTR ---------------------------------- */ 4985 #define RTC_CTR_ENB_Pos (0UL) /*!< RTC CTR: ENB (Bit 0) */ 4986 #define RTC_CTR_ENB_Msk (0x1UL) /*!< RTC CTR: ENB (Bitfield-Mask: 0x01) */ 4987 #define RTC_CTR_TAE_Pos (2UL) /*!< RTC CTR: TAE (Bit 2) */ 4988 #define RTC_CTR_TAE_Msk (0x4UL) /*!< RTC CTR: TAE (Bitfield-Mask: 0x01) */ 4989 #define RTC_CTR_ESEC_Pos (8UL) /*!< RTC CTR: ESEC (Bit 8) */ 4990 #define RTC_CTR_ESEC_Msk (0x100UL) /*!< RTC CTR: ESEC (Bitfield-Mask: 0x01) */ 4991 #define RTC_CTR_EMIC_Pos (9UL) /*!< RTC CTR: EMIC (Bit 9) */ 4992 #define RTC_CTR_EMIC_Msk (0x200UL) /*!< RTC CTR: EMIC (Bitfield-Mask: 0x01) */ 4993 #define RTC_CTR_EHOC_Pos (10UL) /*!< RTC CTR: EHOC (Bit 10) */ 4994 #define RTC_CTR_EHOC_Msk (0x400UL) /*!< RTC CTR: EHOC (Bitfield-Mask: 0x01) */ 4995 #define RTC_CTR_EDAC_Pos (11UL) /*!< RTC CTR: EDAC (Bit 11) */ 4996 #define RTC_CTR_EDAC_Msk (0x800UL) /*!< RTC CTR: EDAC (Bitfield-Mask: 0x01) */ 4997 #define RTC_CTR_EMOC_Pos (13UL) /*!< RTC CTR: EMOC (Bit 13) */ 4998 #define RTC_CTR_EMOC_Msk (0x2000UL) /*!< RTC CTR: EMOC (Bitfield-Mask: 0x01) */ 4999 #define RTC_CTR_EYEC_Pos (14UL) /*!< RTC CTR: EYEC (Bit 14) */ 5000 #define RTC_CTR_EYEC_Msk (0x4000UL) /*!< RTC CTR: EYEC (Bitfield-Mask: 0x01) */ 5001 #define RTC_CTR_DIV_Pos (16UL) /*!< RTC CTR: DIV (Bit 16) */ 5002 #define RTC_CTR_DIV_Msk (0xffff0000UL) /*!< RTC CTR: DIV (Bitfield-Mask: 0xffff) */ 5003 5004 /* --------------------------------- RTC_RAWSTAT -------------------------------- */ 5005 #define RTC_RAWSTAT_RPSE_Pos (0UL) /*!< RTC RAWSTAT: RPSE (Bit 0) */ 5006 #define RTC_RAWSTAT_RPSE_Msk (0x1UL) /*!< RTC RAWSTAT: RPSE (Bitfield-Mask: 0x01) */ 5007 #define RTC_RAWSTAT_RPMI_Pos (1UL) /*!< RTC RAWSTAT: RPMI (Bit 1) */ 5008 #define RTC_RAWSTAT_RPMI_Msk (0x2UL) /*!< RTC RAWSTAT: RPMI (Bitfield-Mask: 0x01) */ 5009 #define RTC_RAWSTAT_RPHO_Pos (2UL) /*!< RTC RAWSTAT: RPHO (Bit 2) */ 5010 #define RTC_RAWSTAT_RPHO_Msk (0x4UL) /*!< RTC RAWSTAT: RPHO (Bitfield-Mask: 0x01) */ 5011 #define RTC_RAWSTAT_RPDA_Pos (3UL) /*!< RTC RAWSTAT: RPDA (Bit 3) */ 5012 #define RTC_RAWSTAT_RPDA_Msk (0x8UL) /*!< RTC RAWSTAT: RPDA (Bitfield-Mask: 0x01) */ 5013 #define RTC_RAWSTAT_RPMO_Pos (5UL) /*!< RTC RAWSTAT: RPMO (Bit 5) */ 5014 #define RTC_RAWSTAT_RPMO_Msk (0x20UL) /*!< RTC RAWSTAT: RPMO (Bitfield-Mask: 0x01) */ 5015 #define RTC_RAWSTAT_RPYE_Pos (6UL) /*!< RTC RAWSTAT: RPYE (Bit 6) */ 5016 #define RTC_RAWSTAT_RPYE_Msk (0x40UL) /*!< RTC RAWSTAT: RPYE (Bitfield-Mask: 0x01) */ 5017 #define RTC_RAWSTAT_RAI_Pos (8UL) /*!< RTC RAWSTAT: RAI (Bit 8) */ 5018 #define RTC_RAWSTAT_RAI_Msk (0x100UL) /*!< RTC RAWSTAT: RAI (Bitfield-Mask: 0x01) */ 5019 5020 /* ---------------------------------- RTC_STSSR --------------------------------- */ 5021 #define RTC_STSSR_SPSE_Pos (0UL) /*!< RTC STSSR: SPSE (Bit 0) */ 5022 #define RTC_STSSR_SPSE_Msk (0x1UL) /*!< RTC STSSR: SPSE (Bitfield-Mask: 0x01) */ 5023 #define RTC_STSSR_SPMI_Pos (1UL) /*!< RTC STSSR: SPMI (Bit 1) */ 5024 #define RTC_STSSR_SPMI_Msk (0x2UL) /*!< RTC STSSR: SPMI (Bitfield-Mask: 0x01) */ 5025 #define RTC_STSSR_SPHO_Pos (2UL) /*!< RTC STSSR: SPHO (Bit 2) */ 5026 #define RTC_STSSR_SPHO_Msk (0x4UL) /*!< RTC STSSR: SPHO (Bitfield-Mask: 0x01) */ 5027 #define RTC_STSSR_SPDA_Pos (3UL) /*!< RTC STSSR: SPDA (Bit 3) */ 5028 #define RTC_STSSR_SPDA_Msk (0x8UL) /*!< RTC STSSR: SPDA (Bitfield-Mask: 0x01) */ 5029 #define RTC_STSSR_SPMO_Pos (5UL) /*!< RTC STSSR: SPMO (Bit 5) */ 5030 #define RTC_STSSR_SPMO_Msk (0x20UL) /*!< RTC STSSR: SPMO (Bitfield-Mask: 0x01) */ 5031 #define RTC_STSSR_SPYE_Pos (6UL) /*!< RTC STSSR: SPYE (Bit 6) */ 5032 #define RTC_STSSR_SPYE_Msk (0x40UL) /*!< RTC STSSR: SPYE (Bitfield-Mask: 0x01) */ 5033 #define RTC_STSSR_SAI_Pos (8UL) /*!< RTC STSSR: SAI (Bit 8) */ 5034 #define RTC_STSSR_SAI_Msk (0x100UL) /*!< RTC STSSR: SAI (Bitfield-Mask: 0x01) */ 5035 5036 /* ---------------------------------- RTC_MSKSR --------------------------------- */ 5037 #define RTC_MSKSR_MPSE_Pos (0UL) /*!< RTC MSKSR: MPSE (Bit 0) */ 5038 #define RTC_MSKSR_MPSE_Msk (0x1UL) /*!< RTC MSKSR: MPSE (Bitfield-Mask: 0x01) */ 5039 #define RTC_MSKSR_MPMI_Pos (1UL) /*!< RTC MSKSR: MPMI (Bit 1) */ 5040 #define RTC_MSKSR_MPMI_Msk (0x2UL) /*!< RTC MSKSR: MPMI (Bitfield-Mask: 0x01) */ 5041 #define RTC_MSKSR_MPHO_Pos (2UL) /*!< RTC MSKSR: MPHO (Bit 2) */ 5042 #define RTC_MSKSR_MPHO_Msk (0x4UL) /*!< RTC MSKSR: MPHO (Bitfield-Mask: 0x01) */ 5043 #define RTC_MSKSR_MPDA_Pos (3UL) /*!< RTC MSKSR: MPDA (Bit 3) */ 5044 #define RTC_MSKSR_MPDA_Msk (0x8UL) /*!< RTC MSKSR: MPDA (Bitfield-Mask: 0x01) */ 5045 #define RTC_MSKSR_MPMO_Pos (5UL) /*!< RTC MSKSR: MPMO (Bit 5) */ 5046 #define RTC_MSKSR_MPMO_Msk (0x20UL) /*!< RTC MSKSR: MPMO (Bitfield-Mask: 0x01) */ 5047 #define RTC_MSKSR_MPYE_Pos (6UL) /*!< RTC MSKSR: MPYE (Bit 6) */ 5048 #define RTC_MSKSR_MPYE_Msk (0x40UL) /*!< RTC MSKSR: MPYE (Bitfield-Mask: 0x01) */ 5049 #define RTC_MSKSR_MAI_Pos (8UL) /*!< RTC MSKSR: MAI (Bit 8) */ 5050 #define RTC_MSKSR_MAI_Msk (0x100UL) /*!< RTC MSKSR: MAI (Bitfield-Mask: 0x01) */ 5051 5052 /* ---------------------------------- RTC_CLRSR --------------------------------- */ 5053 #define RTC_CLRSR_RPSE_Pos (0UL) /*!< RTC CLRSR: RPSE (Bit 0) */ 5054 #define RTC_CLRSR_RPSE_Msk (0x1UL) /*!< RTC CLRSR: RPSE (Bitfield-Mask: 0x01) */ 5055 #define RTC_CLRSR_RPMI_Pos (1UL) /*!< RTC CLRSR: RPMI (Bit 1) */ 5056 #define RTC_CLRSR_RPMI_Msk (0x2UL) /*!< RTC CLRSR: RPMI (Bitfield-Mask: 0x01) */ 5057 #define RTC_CLRSR_RPHO_Pos (2UL) /*!< RTC CLRSR: RPHO (Bit 2) */ 5058 #define RTC_CLRSR_RPHO_Msk (0x4UL) /*!< RTC CLRSR: RPHO (Bitfield-Mask: 0x01) */ 5059 #define RTC_CLRSR_RPDA_Pos (3UL) /*!< RTC CLRSR: RPDA (Bit 3) */ 5060 #define RTC_CLRSR_RPDA_Msk (0x8UL) /*!< RTC CLRSR: RPDA (Bitfield-Mask: 0x01) */ 5061 #define RTC_CLRSR_RPMO_Pos (5UL) /*!< RTC CLRSR: RPMO (Bit 5) */ 5062 #define RTC_CLRSR_RPMO_Msk (0x20UL) /*!< RTC CLRSR: RPMO (Bitfield-Mask: 0x01) */ 5063 #define RTC_CLRSR_RPYE_Pos (6UL) /*!< RTC CLRSR: RPYE (Bit 6) */ 5064 #define RTC_CLRSR_RPYE_Msk (0x40UL) /*!< RTC CLRSR: RPYE (Bitfield-Mask: 0x01) */ 5065 #define RTC_CLRSR_RAI_Pos (8UL) /*!< RTC CLRSR: RAI (Bit 8) */ 5066 #define RTC_CLRSR_RAI_Msk (0x100UL) /*!< RTC CLRSR: RAI (Bitfield-Mask: 0x01) */ 5067 5068 /* ---------------------------------- RTC_ATIM0 --------------------------------- */ 5069 #define RTC_ATIM0_ASE_Pos (0UL) /*!< RTC ATIM0: ASE (Bit 0) */ 5070 #define RTC_ATIM0_ASE_Msk (0x3fUL) /*!< RTC ATIM0: ASE (Bitfield-Mask: 0x3f) */ 5071 #define RTC_ATIM0_AMI_Pos (8UL) /*!< RTC ATIM0: AMI (Bit 8) */ 5072 #define RTC_ATIM0_AMI_Msk (0x3f00UL) /*!< RTC ATIM0: AMI (Bitfield-Mask: 0x3f) */ 5073 #define RTC_ATIM0_AHO_Pos (16UL) /*!< RTC ATIM0: AHO (Bit 16) */ 5074 #define RTC_ATIM0_AHO_Msk (0x1f0000UL) /*!< RTC ATIM0: AHO (Bitfield-Mask: 0x1f) */ 5075 #define RTC_ATIM0_ADA_Pos (24UL) /*!< RTC ATIM0: ADA (Bit 24) */ 5076 #define RTC_ATIM0_ADA_Msk (0x1f000000UL) /*!< RTC ATIM0: ADA (Bitfield-Mask: 0x1f) */ 5077 5078 /* ---------------------------------- RTC_ATIM1 --------------------------------- */ 5079 #define RTC_ATIM1_AMO_Pos (8UL) /*!< RTC ATIM1: AMO (Bit 8) */ 5080 #define RTC_ATIM1_AMO_Msk (0xf00UL) /*!< RTC ATIM1: AMO (Bitfield-Mask: 0x0f) */ 5081 #define RTC_ATIM1_AYE_Pos (16UL) /*!< RTC ATIM1: AYE (Bit 16) */ 5082 #define RTC_ATIM1_AYE_Msk (0xffff0000UL) /*!< RTC ATIM1: AYE (Bitfield-Mask: 0xffff) */ 5083 5084 /* ---------------------------------- RTC_TIM0 ---------------------------------- */ 5085 #define RTC_TIM0_SE_Pos (0UL) /*!< RTC TIM0: SE (Bit 0) */ 5086 #define RTC_TIM0_SE_Msk (0x3fUL) /*!< RTC TIM0: SE (Bitfield-Mask: 0x3f) */ 5087 #define RTC_TIM0_MI_Pos (8UL) /*!< RTC TIM0: MI (Bit 8) */ 5088 #define RTC_TIM0_MI_Msk (0x3f00UL) /*!< RTC TIM0: MI (Bitfield-Mask: 0x3f) */ 5089 #define RTC_TIM0_HO_Pos (16UL) /*!< RTC TIM0: HO (Bit 16) */ 5090 #define RTC_TIM0_HO_Msk (0x1f0000UL) /*!< RTC TIM0: HO (Bitfield-Mask: 0x1f) */ 5091 #define RTC_TIM0_DA_Pos (24UL) /*!< RTC TIM0: DA (Bit 24) */ 5092 #define RTC_TIM0_DA_Msk (0x1f000000UL) /*!< RTC TIM0: DA (Bitfield-Mask: 0x1f) */ 5093 5094 /* ---------------------------------- RTC_TIM1 ---------------------------------- */ 5095 #define RTC_TIM1_DAWE_Pos (0UL) /*!< RTC TIM1: DAWE (Bit 0) */ 5096 #define RTC_TIM1_DAWE_Msk (0x7UL) /*!< RTC TIM1: DAWE (Bitfield-Mask: 0x07) */ 5097 #define RTC_TIM1_MO_Pos (8UL) /*!< RTC TIM1: MO (Bit 8) */ 5098 #define RTC_TIM1_MO_Msk (0xf00UL) /*!< RTC TIM1: MO (Bitfield-Mask: 0x0f) */ 5099 #define RTC_TIM1_YE_Pos (16UL) /*!< RTC TIM1: YE (Bit 16) */ 5100 #define RTC_TIM1_YE_Msk (0xffff0000UL) /*!< RTC TIM1: YE (Bitfield-Mask: 0xffff) */ 5101 5102 5103 /* ================================================================================ */ 5104 /* ================ struct 'SCU_CLK' Position & Mask ================ */ 5105 /* ================================================================================ */ 5106 5107 5108 /* ------------------------------- SCU_CLK_CLKSTAT ------------------------------ */ 5109 #define SCU_CLK_CLKSTAT_USBCST_Pos (0UL) /*!< SCU_CLK CLKSTAT: USBCST (Bit 0) */ 5110 #define SCU_CLK_CLKSTAT_USBCST_Msk (0x1UL) /*!< SCU_CLK CLKSTAT: USBCST (Bitfield-Mask: 0x01) */ 5111 #define SCU_CLK_CLKSTAT_MMCCST_Pos (1UL) /*!< SCU_CLK CLKSTAT: MMCCST (Bit 1) */ 5112 #define SCU_CLK_CLKSTAT_MMCCST_Msk (0x2UL) /*!< SCU_CLK CLKSTAT: MMCCST (Bitfield-Mask: 0x01) */ 5113 #define SCU_CLK_CLKSTAT_ETH0CST_Pos (2UL) /*!< SCU_CLK CLKSTAT: ETH0CST (Bit 2) */ 5114 #define SCU_CLK_CLKSTAT_ETH0CST_Msk (0x4UL) /*!< SCU_CLK CLKSTAT: ETH0CST (Bitfield-Mask: 0x01) */ 5115 #define SCU_CLK_CLKSTAT_EBUCST_Pos (3UL) /*!< SCU_CLK CLKSTAT: EBUCST (Bit 3) */ 5116 #define SCU_CLK_CLKSTAT_EBUCST_Msk (0x8UL) /*!< SCU_CLK CLKSTAT: EBUCST (Bitfield-Mask: 0x01) */ 5117 #define SCU_CLK_CLKSTAT_CCUCST_Pos (4UL) /*!< SCU_CLK CLKSTAT: CCUCST (Bit 4) */ 5118 #define SCU_CLK_CLKSTAT_CCUCST_Msk (0x10UL) /*!< SCU_CLK CLKSTAT: CCUCST (Bitfield-Mask: 0x01) */ 5119 #define SCU_CLK_CLKSTAT_WDTCST_Pos (5UL) /*!< SCU_CLK CLKSTAT: WDTCST (Bit 5) */ 5120 #define SCU_CLK_CLKSTAT_WDTCST_Msk (0x20UL) /*!< SCU_CLK CLKSTAT: WDTCST (Bitfield-Mask: 0x01) */ 5121 5122 /* ------------------------------- SCU_CLK_CLKSET ------------------------------- */ 5123 #define SCU_CLK_CLKSET_USBCEN_Pos (0UL) /*!< SCU_CLK CLKSET: USBCEN (Bit 0) */ 5124 #define SCU_CLK_CLKSET_USBCEN_Msk (0x1UL) /*!< SCU_CLK CLKSET: USBCEN (Bitfield-Mask: 0x01) */ 5125 #define SCU_CLK_CLKSET_MMCCEN_Pos (1UL) /*!< SCU_CLK CLKSET: MMCCEN (Bit 1) */ 5126 #define SCU_CLK_CLKSET_MMCCEN_Msk (0x2UL) /*!< SCU_CLK CLKSET: MMCCEN (Bitfield-Mask: 0x01) */ 5127 #define SCU_CLK_CLKSET_ETH0CEN_Pos (2UL) /*!< SCU_CLK CLKSET: ETH0CEN (Bit 2) */ 5128 #define SCU_CLK_CLKSET_ETH0CEN_Msk (0x4UL) /*!< SCU_CLK CLKSET: ETH0CEN (Bitfield-Mask: 0x01) */ 5129 #define SCU_CLK_CLKSET_EBUCEN_Pos (3UL) /*!< SCU_CLK CLKSET: EBUCEN (Bit 3) */ 5130 #define SCU_CLK_CLKSET_EBUCEN_Msk (0x8UL) /*!< SCU_CLK CLKSET: EBUCEN (Bitfield-Mask: 0x01) */ 5131 #define SCU_CLK_CLKSET_CCUCEN_Pos (4UL) /*!< SCU_CLK CLKSET: CCUCEN (Bit 4) */ 5132 #define SCU_CLK_CLKSET_CCUCEN_Msk (0x10UL) /*!< SCU_CLK CLKSET: CCUCEN (Bitfield-Mask: 0x01) */ 5133 #define SCU_CLK_CLKSET_WDTCEN_Pos (5UL) /*!< SCU_CLK CLKSET: WDTCEN (Bit 5) */ 5134 #define SCU_CLK_CLKSET_WDTCEN_Msk (0x20UL) /*!< SCU_CLK CLKSET: WDTCEN (Bitfield-Mask: 0x01) */ 5135 5136 /* ------------------------------- SCU_CLK_CLKCLR ------------------------------- */ 5137 #define SCU_CLK_CLKCLR_USBCDI_Pos (0UL) /*!< SCU_CLK CLKCLR: USBCDI (Bit 0) */ 5138 #define SCU_CLK_CLKCLR_USBCDI_Msk (0x1UL) /*!< SCU_CLK CLKCLR: USBCDI (Bitfield-Mask: 0x01) */ 5139 #define SCU_CLK_CLKCLR_MMCCDI_Pos (1UL) /*!< SCU_CLK CLKCLR: MMCCDI (Bit 1) */ 5140 #define SCU_CLK_CLKCLR_MMCCDI_Msk (0x2UL) /*!< SCU_CLK CLKCLR: MMCCDI (Bitfield-Mask: 0x01) */ 5141 #define SCU_CLK_CLKCLR_ETH0CDI_Pos (2UL) /*!< SCU_CLK CLKCLR: ETH0CDI (Bit 2) */ 5142 #define SCU_CLK_CLKCLR_ETH0CDI_Msk (0x4UL) /*!< SCU_CLK CLKCLR: ETH0CDI (Bitfield-Mask: 0x01) */ 5143 #define SCU_CLK_CLKCLR_EBUCDI_Pos (3UL) /*!< SCU_CLK CLKCLR: EBUCDI (Bit 3) */ 5144 #define SCU_CLK_CLKCLR_EBUCDI_Msk (0x8UL) /*!< SCU_CLK CLKCLR: EBUCDI (Bitfield-Mask: 0x01) */ 5145 #define SCU_CLK_CLKCLR_CCUCDI_Pos (4UL) /*!< SCU_CLK CLKCLR: CCUCDI (Bit 4) */ 5146 #define SCU_CLK_CLKCLR_CCUCDI_Msk (0x10UL) /*!< SCU_CLK CLKCLR: CCUCDI (Bitfield-Mask: 0x01) */ 5147 #define SCU_CLK_CLKCLR_WDTCDI_Pos (5UL) /*!< SCU_CLK CLKCLR: WDTCDI (Bit 5) */ 5148 #define SCU_CLK_CLKCLR_WDTCDI_Msk (0x20UL) /*!< SCU_CLK CLKCLR: WDTCDI (Bitfield-Mask: 0x01) */ 5149 5150 /* ------------------------------ SCU_CLK_SYSCLKCR ------------------------------ */ 5151 #define SCU_CLK_SYSCLKCR_SYSDIV_Pos (0UL) /*!< SCU_CLK SYSCLKCR: SYSDIV (Bit 0) */ 5152 #define SCU_CLK_SYSCLKCR_SYSDIV_Msk (0xffUL) /*!< SCU_CLK SYSCLKCR: SYSDIV (Bitfield-Mask: 0xff) */ 5153 #define SCU_CLK_SYSCLKCR_SYSSEL_Pos (16UL) /*!< SCU_CLK SYSCLKCR: SYSSEL (Bit 16) */ 5154 #define SCU_CLK_SYSCLKCR_SYSSEL_Msk (0x10000UL) /*!< SCU_CLK SYSCLKCR: SYSSEL (Bitfield-Mask: 0x01) */ 5155 5156 /* ------------------------------ SCU_CLK_CPUCLKCR ------------------------------ */ 5157 #define SCU_CLK_CPUCLKCR_CPUDIV_Pos (0UL) /*!< SCU_CLK CPUCLKCR: CPUDIV (Bit 0) */ 5158 #define SCU_CLK_CPUCLKCR_CPUDIV_Msk (0x1UL) /*!< SCU_CLK CPUCLKCR: CPUDIV (Bitfield-Mask: 0x01) */ 5159 5160 /* ------------------------------- SCU_CLK_PBCLKCR ------------------------------ */ 5161 #define SCU_CLK_PBCLKCR_PBDIV_Pos (0UL) /*!< SCU_CLK PBCLKCR: PBDIV (Bit 0) */ 5162 #define SCU_CLK_PBCLKCR_PBDIV_Msk (0x1UL) /*!< SCU_CLK PBCLKCR: PBDIV (Bitfield-Mask: 0x01) */ 5163 5164 /* ------------------------------ SCU_CLK_USBCLKCR ------------------------------ */ 5165 #define SCU_CLK_USBCLKCR_USBDIV_Pos (0UL) /*!< SCU_CLK USBCLKCR: USBDIV (Bit 0) */ 5166 #define SCU_CLK_USBCLKCR_USBDIV_Msk (0x7UL) /*!< SCU_CLK USBCLKCR: USBDIV (Bitfield-Mask: 0x07) */ 5167 #define SCU_CLK_USBCLKCR_USBSEL_Pos (16UL) /*!< SCU_CLK USBCLKCR: USBSEL (Bit 16) */ 5168 #define SCU_CLK_USBCLKCR_USBSEL_Msk (0x10000UL) /*!< SCU_CLK USBCLKCR: USBSEL (Bitfield-Mask: 0x01) */ 5169 5170 /* ------------------------------ SCU_CLK_EBUCLKCR ------------------------------ */ 5171 #define SCU_CLK_EBUCLKCR_EBUDIV_Pos (0UL) /*!< SCU_CLK EBUCLKCR: EBUDIV (Bit 0) */ 5172 #define SCU_CLK_EBUCLKCR_EBUDIV_Msk (0x3fUL) /*!< SCU_CLK EBUCLKCR: EBUDIV (Bitfield-Mask: 0x3f) */ 5173 5174 /* ------------------------------ SCU_CLK_CCUCLKCR ------------------------------ */ 5175 #define SCU_CLK_CCUCLKCR_CCUDIV_Pos (0UL) /*!< SCU_CLK CCUCLKCR: CCUDIV (Bit 0) */ 5176 #define SCU_CLK_CCUCLKCR_CCUDIV_Msk (0x1UL) /*!< SCU_CLK CCUCLKCR: CCUDIV (Bitfield-Mask: 0x01) */ 5177 5178 /* ------------------------------ SCU_CLK_WDTCLKCR ------------------------------ */ 5179 #define SCU_CLK_WDTCLKCR_WDTDIV_Pos (0UL) /*!< SCU_CLK WDTCLKCR: WDTDIV (Bit 0) */ 5180 #define SCU_CLK_WDTCLKCR_WDTDIV_Msk (0xffUL) /*!< SCU_CLK WDTCLKCR: WDTDIV (Bitfield-Mask: 0xff) */ 5181 #define SCU_CLK_WDTCLKCR_WDTSEL_Pos (16UL) /*!< SCU_CLK WDTCLKCR: WDTSEL (Bit 16) */ 5182 #define SCU_CLK_WDTCLKCR_WDTSEL_Msk (0x30000UL) /*!< SCU_CLK WDTCLKCR: WDTSEL (Bitfield-Mask: 0x03) */ 5183 5184 /* ------------------------------ SCU_CLK_EXTCLKCR ------------------------------ */ 5185 #define SCU_CLK_EXTCLKCR_ECKSEL_Pos (0UL) /*!< SCU_CLK EXTCLKCR: ECKSEL (Bit 0) */ 5186 #define SCU_CLK_EXTCLKCR_ECKSEL_Msk (0x3UL) /*!< SCU_CLK EXTCLKCR: ECKSEL (Bitfield-Mask: 0x03) */ 5187 #define SCU_CLK_EXTCLKCR_ECKDIV_Pos (16UL) /*!< SCU_CLK EXTCLKCR: ECKDIV (Bit 16) */ 5188 #define SCU_CLK_EXTCLKCR_ECKDIV_Msk (0x1ff0000UL) /*!< SCU_CLK EXTCLKCR: ECKDIV (Bitfield-Mask: 0x1ff) */ 5189 5190 /* ------------------------------- SCU_CLK_SLEEPCR ------------------------------ */ 5191 #define SCU_CLK_SLEEPCR_SYSSEL_Pos (0UL) /*!< SCU_CLK SLEEPCR: SYSSEL (Bit 0) */ 5192 #define SCU_CLK_SLEEPCR_SYSSEL_Msk (0x1UL) /*!< SCU_CLK SLEEPCR: SYSSEL (Bitfield-Mask: 0x01) */ 5193 #define SCU_CLK_SLEEPCR_USBCR_Pos (16UL) /*!< SCU_CLK SLEEPCR: USBCR (Bit 16) */ 5194 #define SCU_CLK_SLEEPCR_USBCR_Msk (0x10000UL) /*!< SCU_CLK SLEEPCR: USBCR (Bitfield-Mask: 0x01) */ 5195 #define SCU_CLK_SLEEPCR_MMCCR_Pos (17UL) /*!< SCU_CLK SLEEPCR: MMCCR (Bit 17) */ 5196 #define SCU_CLK_SLEEPCR_MMCCR_Msk (0x20000UL) /*!< SCU_CLK SLEEPCR: MMCCR (Bitfield-Mask: 0x01) */ 5197 #define SCU_CLK_SLEEPCR_ETH0CR_Pos (18UL) /*!< SCU_CLK SLEEPCR: ETH0CR (Bit 18) */ 5198 #define SCU_CLK_SLEEPCR_ETH0CR_Msk (0x40000UL) /*!< SCU_CLK SLEEPCR: ETH0CR (Bitfield-Mask: 0x01) */ 5199 #define SCU_CLK_SLEEPCR_EBUCR_Pos (19UL) /*!< SCU_CLK SLEEPCR: EBUCR (Bit 19) */ 5200 #define SCU_CLK_SLEEPCR_EBUCR_Msk (0x80000UL) /*!< SCU_CLK SLEEPCR: EBUCR (Bitfield-Mask: 0x01) */ 5201 #define SCU_CLK_SLEEPCR_CCUCR_Pos (20UL) /*!< SCU_CLK SLEEPCR: CCUCR (Bit 20) */ 5202 #define SCU_CLK_SLEEPCR_CCUCR_Msk (0x100000UL) /*!< SCU_CLK SLEEPCR: CCUCR (Bitfield-Mask: 0x01) */ 5203 #define SCU_CLK_SLEEPCR_WDTCR_Pos (21UL) /*!< SCU_CLK SLEEPCR: WDTCR (Bit 21) */ 5204 #define SCU_CLK_SLEEPCR_WDTCR_Msk (0x200000UL) /*!< SCU_CLK SLEEPCR: WDTCR (Bitfield-Mask: 0x01) */ 5205 5206 /* ------------------------------ SCU_CLK_DSLEEPCR ------------------------------ */ 5207 #define SCU_CLK_DSLEEPCR_SYSSEL_Pos (0UL) /*!< SCU_CLK DSLEEPCR: SYSSEL (Bit 0) */ 5208 #define SCU_CLK_DSLEEPCR_SYSSEL_Msk (0x3UL) /*!< SCU_CLK DSLEEPCR: SYSSEL (Bitfield-Mask: 0x03) */ 5209 #define SCU_CLK_DSLEEPCR_FPDN_Pos (11UL) /*!< SCU_CLK DSLEEPCR: FPDN (Bit 11) */ 5210 #define SCU_CLK_DSLEEPCR_FPDN_Msk (0x800UL) /*!< SCU_CLK DSLEEPCR: FPDN (Bitfield-Mask: 0x01) */ 5211 #define SCU_CLK_DSLEEPCR_PLLPDN_Pos (12UL) /*!< SCU_CLK DSLEEPCR: PLLPDN (Bit 12) */ 5212 #define SCU_CLK_DSLEEPCR_PLLPDN_Msk (0x1000UL) /*!< SCU_CLK DSLEEPCR: PLLPDN (Bitfield-Mask: 0x01) */ 5213 #define SCU_CLK_DSLEEPCR_VCOPDN_Pos (13UL) /*!< SCU_CLK DSLEEPCR: VCOPDN (Bit 13) */ 5214 #define SCU_CLK_DSLEEPCR_VCOPDN_Msk (0x2000UL) /*!< SCU_CLK DSLEEPCR: VCOPDN (Bitfield-Mask: 0x01) */ 5215 #define SCU_CLK_DSLEEPCR_USBCR_Pos (16UL) /*!< SCU_CLK DSLEEPCR: USBCR (Bit 16) */ 5216 #define SCU_CLK_DSLEEPCR_USBCR_Msk (0x10000UL) /*!< SCU_CLK DSLEEPCR: USBCR (Bitfield-Mask: 0x01) */ 5217 #define SCU_CLK_DSLEEPCR_MMCCR_Pos (17UL) /*!< SCU_CLK DSLEEPCR: MMCCR (Bit 17) */ 5218 #define SCU_CLK_DSLEEPCR_MMCCR_Msk (0x20000UL) /*!< SCU_CLK DSLEEPCR: MMCCR (Bitfield-Mask: 0x01) */ 5219 #define SCU_CLK_DSLEEPCR_ETH0CR_Pos (18UL) /*!< SCU_CLK DSLEEPCR: ETH0CR (Bit 18) */ 5220 #define SCU_CLK_DSLEEPCR_ETH0CR_Msk (0x40000UL) /*!< SCU_CLK DSLEEPCR: ETH0CR (Bitfield-Mask: 0x01) */ 5221 #define SCU_CLK_DSLEEPCR_EBUCR_Pos (19UL) /*!< SCU_CLK DSLEEPCR: EBUCR (Bit 19) */ 5222 #define SCU_CLK_DSLEEPCR_EBUCR_Msk (0x80000UL) /*!< SCU_CLK DSLEEPCR: EBUCR (Bitfield-Mask: 0x01) */ 5223 #define SCU_CLK_DSLEEPCR_CCUCR_Pos (20UL) /*!< SCU_CLK DSLEEPCR: CCUCR (Bit 20) */ 5224 #define SCU_CLK_DSLEEPCR_CCUCR_Msk (0x100000UL) /*!< SCU_CLK DSLEEPCR: CCUCR (Bitfield-Mask: 0x01) */ 5225 #define SCU_CLK_DSLEEPCR_WDTCR_Pos (21UL) /*!< SCU_CLK DSLEEPCR: WDTCR (Bit 21) */ 5226 #define SCU_CLK_DSLEEPCR_WDTCR_Msk (0x200000UL) /*!< SCU_CLK DSLEEPCR: WDTCR (Bitfield-Mask: 0x01) */ 5227 5228 5229 /* ================================================================================ */ 5230 /* ================ struct 'SCU_OSC' Position & Mask ================ */ 5231 /* ================================================================================ */ 5232 5233 5234 /* ------------------------------ SCU_OSC_OSCHPSTAT ----------------------------- */ 5235 #define SCU_OSC_OSCHPSTAT_X1D_Pos (0UL) /*!< SCU_OSC OSCHPSTAT: X1D (Bit 0) */ 5236 #define SCU_OSC_OSCHPSTAT_X1D_Msk (0x1UL) /*!< SCU_OSC OSCHPSTAT: X1D (Bitfield-Mask: 0x01) */ 5237 5238 /* ------------------------------ SCU_OSC_OSCHPCTRL ----------------------------- */ 5239 #define SCU_OSC_OSCHPCTRL_X1DEN_Pos (0UL) /*!< SCU_OSC OSCHPCTRL: X1DEN (Bit 0) */ 5240 #define SCU_OSC_OSCHPCTRL_X1DEN_Msk (0x1UL) /*!< SCU_OSC OSCHPCTRL: X1DEN (Bitfield-Mask: 0x01) */ 5241 #define SCU_OSC_OSCHPCTRL_SHBY_Pos (1UL) /*!< SCU_OSC OSCHPCTRL: SHBY (Bit 1) */ 5242 #define SCU_OSC_OSCHPCTRL_SHBY_Msk (0x2UL) /*!< SCU_OSC OSCHPCTRL: SHBY (Bitfield-Mask: 0x01) */ 5243 #define SCU_OSC_OSCHPCTRL_MODE_Pos (4UL) /*!< SCU_OSC OSCHPCTRL: MODE (Bit 4) */ 5244 #define SCU_OSC_OSCHPCTRL_MODE_Msk (0x30UL) /*!< SCU_OSC OSCHPCTRL: MODE (Bitfield-Mask: 0x03) */ 5245 #define SCU_OSC_OSCHPCTRL_OSCVAL_Pos (16UL) /*!< SCU_OSC OSCHPCTRL: OSCVAL (Bit 16) */ 5246 #define SCU_OSC_OSCHPCTRL_OSCVAL_Msk (0xf0000UL) /*!< SCU_OSC OSCHPCTRL: OSCVAL (Bitfield-Mask: 0x0f) */ 5247 5248 /* ----------------------------- SCU_OSC_CLKCALCONST ---------------------------- */ 5249 #define SCU_OSC_CLKCALCONST_CALIBCONST_Pos (0UL) /*!< SCU_OSC CLKCALCONST: CALIBCONST (Bit 0) */ 5250 #define SCU_OSC_CLKCALCONST_CALIBCONST_Msk (0xfUL) /*!< SCU_OSC CLKCALCONST: CALIBCONST (Bitfield-Mask: 0x0f) */ 5251 5252 5253 /* ================================================================================ */ 5254 /* ================ struct 'SCU_PLL' Position & Mask ================ */ 5255 /* ================================================================================ */ 5256 5257 5258 /* ------------------------------- SCU_PLL_PLLSTAT ------------------------------ */ 5259 #define SCU_PLL_PLLSTAT_VCOBYST_Pos (0UL) /*!< SCU_PLL PLLSTAT: VCOBYST (Bit 0) */ 5260 #define SCU_PLL_PLLSTAT_VCOBYST_Msk (0x1UL) /*!< SCU_PLL PLLSTAT: VCOBYST (Bitfield-Mask: 0x01) */ 5261 #define SCU_PLL_PLLSTAT_PWDSTAT_Pos (1UL) /*!< SCU_PLL PLLSTAT: PWDSTAT (Bit 1) */ 5262 #define SCU_PLL_PLLSTAT_PWDSTAT_Msk (0x2UL) /*!< SCU_PLL PLLSTAT: PWDSTAT (Bitfield-Mask: 0x01) */ 5263 #define SCU_PLL_PLLSTAT_VCOLOCK_Pos (2UL) /*!< SCU_PLL PLLSTAT: VCOLOCK (Bit 2) */ 5264 #define SCU_PLL_PLLSTAT_VCOLOCK_Msk (0x4UL) /*!< SCU_PLL PLLSTAT: VCOLOCK (Bitfield-Mask: 0x01) */ 5265 #define SCU_PLL_PLLSTAT_K1RDY_Pos (4UL) /*!< SCU_PLL PLLSTAT: K1RDY (Bit 4) */ 5266 #define SCU_PLL_PLLSTAT_K1RDY_Msk (0x10UL) /*!< SCU_PLL PLLSTAT: K1RDY (Bitfield-Mask: 0x01) */ 5267 #define SCU_PLL_PLLSTAT_K2RDY_Pos (5UL) /*!< SCU_PLL PLLSTAT: K2RDY (Bit 5) */ 5268 #define SCU_PLL_PLLSTAT_K2RDY_Msk (0x20UL) /*!< SCU_PLL PLLSTAT: K2RDY (Bitfield-Mask: 0x01) */ 5269 #define SCU_PLL_PLLSTAT_BY_Pos (6UL) /*!< SCU_PLL PLLSTAT: BY (Bit 6) */ 5270 #define SCU_PLL_PLLSTAT_BY_Msk (0x40UL) /*!< SCU_PLL PLLSTAT: BY (Bitfield-Mask: 0x01) */ 5271 #define SCU_PLL_PLLSTAT_PLLLV_Pos (7UL) /*!< SCU_PLL PLLSTAT: PLLLV (Bit 7) */ 5272 #define SCU_PLL_PLLSTAT_PLLLV_Msk (0x80UL) /*!< SCU_PLL PLLSTAT: PLLLV (Bitfield-Mask: 0x01) */ 5273 #define SCU_PLL_PLLSTAT_PLLHV_Pos (8UL) /*!< SCU_PLL PLLSTAT: PLLHV (Bit 8) */ 5274 #define SCU_PLL_PLLSTAT_PLLHV_Msk (0x100UL) /*!< SCU_PLL PLLSTAT: PLLHV (Bitfield-Mask: 0x01) */ 5275 #define SCU_PLL_PLLSTAT_PLLSP_Pos (9UL) /*!< SCU_PLL PLLSTAT: PLLSP (Bit 9) */ 5276 #define SCU_PLL_PLLSTAT_PLLSP_Msk (0x200UL) /*!< SCU_PLL PLLSTAT: PLLSP (Bitfield-Mask: 0x01) */ 5277 5278 /* ------------------------------- SCU_PLL_PLLCON0 ------------------------------ */ 5279 #define SCU_PLL_PLLCON0_VCOBYP_Pos (0UL) /*!< SCU_PLL PLLCON0: VCOBYP (Bit 0) */ 5280 #define SCU_PLL_PLLCON0_VCOBYP_Msk (0x1UL) /*!< SCU_PLL PLLCON0: VCOBYP (Bitfield-Mask: 0x01) */ 5281 #define SCU_PLL_PLLCON0_VCOPWD_Pos (1UL) /*!< SCU_PLL PLLCON0: VCOPWD (Bit 1) */ 5282 #define SCU_PLL_PLLCON0_VCOPWD_Msk (0x2UL) /*!< SCU_PLL PLLCON0: VCOPWD (Bitfield-Mask: 0x01) */ 5283 #define SCU_PLL_PLLCON0_VCOTR_Pos (2UL) /*!< SCU_PLL PLLCON0: VCOTR (Bit 2) */ 5284 #define SCU_PLL_PLLCON0_VCOTR_Msk (0x4UL) /*!< SCU_PLL PLLCON0: VCOTR (Bitfield-Mask: 0x01) */ 5285 #define SCU_PLL_PLLCON0_FINDIS_Pos (4UL) /*!< SCU_PLL PLLCON0: FINDIS (Bit 4) */ 5286 #define SCU_PLL_PLLCON0_FINDIS_Msk (0x10UL) /*!< SCU_PLL PLLCON0: FINDIS (Bitfield-Mask: 0x01) */ 5287 #define SCU_PLL_PLLCON0_OSCDISCDIS_Pos (6UL) /*!< SCU_PLL PLLCON0: OSCDISCDIS (Bit 6) */ 5288 #define SCU_PLL_PLLCON0_OSCDISCDIS_Msk (0x40UL) /*!< SCU_PLL PLLCON0: OSCDISCDIS (Bitfield-Mask: 0x01) */ 5289 #define SCU_PLL_PLLCON0_PLLPWD_Pos (16UL) /*!< SCU_PLL PLLCON0: PLLPWD (Bit 16) */ 5290 #define SCU_PLL_PLLCON0_PLLPWD_Msk (0x10000UL) /*!< SCU_PLL PLLCON0: PLLPWD (Bitfield-Mask: 0x01) */ 5291 #define SCU_PLL_PLLCON0_OSCRES_Pos (17UL) /*!< SCU_PLL PLLCON0: OSCRES (Bit 17) */ 5292 #define SCU_PLL_PLLCON0_OSCRES_Msk (0x20000UL) /*!< SCU_PLL PLLCON0: OSCRES (Bitfield-Mask: 0x01) */ 5293 #define SCU_PLL_PLLCON0_RESLD_Pos (18UL) /*!< SCU_PLL PLLCON0: RESLD (Bit 18) */ 5294 #define SCU_PLL_PLLCON0_RESLD_Msk (0x40000UL) /*!< SCU_PLL PLLCON0: RESLD (Bitfield-Mask: 0x01) */ 5295 #define SCU_PLL_PLLCON0_AOTREN_Pos (19UL) /*!< SCU_PLL PLLCON0: AOTREN (Bit 19) */ 5296 #define SCU_PLL_PLLCON0_AOTREN_Msk (0x80000UL) /*!< SCU_PLL PLLCON0: AOTREN (Bitfield-Mask: 0x01) */ 5297 #define SCU_PLL_PLLCON0_FOTR_Pos (20UL) /*!< SCU_PLL PLLCON0: FOTR (Bit 20) */ 5298 #define SCU_PLL_PLLCON0_FOTR_Msk (0x100000UL) /*!< SCU_PLL PLLCON0: FOTR (Bitfield-Mask: 0x01) */ 5299 5300 /* ------------------------------- SCU_PLL_PLLCON1 ------------------------------ */ 5301 #define SCU_PLL_PLLCON1_K1DIV_Pos (0UL) /*!< SCU_PLL PLLCON1: K1DIV (Bit 0) */ 5302 #define SCU_PLL_PLLCON1_K1DIV_Msk (0x7fUL) /*!< SCU_PLL PLLCON1: K1DIV (Bitfield-Mask: 0x7f) */ 5303 #define SCU_PLL_PLLCON1_NDIV_Pos (8UL) /*!< SCU_PLL PLLCON1: NDIV (Bit 8) */ 5304 #define SCU_PLL_PLLCON1_NDIV_Msk (0x7f00UL) /*!< SCU_PLL PLLCON1: NDIV (Bitfield-Mask: 0x7f) */ 5305 #define SCU_PLL_PLLCON1_K2DIV_Pos (16UL) /*!< SCU_PLL PLLCON1: K2DIV (Bit 16) */ 5306 #define SCU_PLL_PLLCON1_K2DIV_Msk (0x7f0000UL) /*!< SCU_PLL PLLCON1: K2DIV (Bitfield-Mask: 0x7f) */ 5307 #define SCU_PLL_PLLCON1_PDIV_Pos (24UL) /*!< SCU_PLL PLLCON1: PDIV (Bit 24) */ 5308 #define SCU_PLL_PLLCON1_PDIV_Msk (0xf000000UL) /*!< SCU_PLL PLLCON1: PDIV (Bitfield-Mask: 0x0f) */ 5309 5310 /* ------------------------------- SCU_PLL_PLLCON2 ------------------------------ */ 5311 #define SCU_PLL_PLLCON2_PINSEL_Pos (0UL) /*!< SCU_PLL PLLCON2: PINSEL (Bit 0) */ 5312 #define SCU_PLL_PLLCON2_PINSEL_Msk (0x1UL) /*!< SCU_PLL PLLCON2: PINSEL (Bitfield-Mask: 0x01) */ 5313 #define SCU_PLL_PLLCON2_K1INSEL_Pos (8UL) /*!< SCU_PLL PLLCON2: K1INSEL (Bit 8) */ 5314 #define SCU_PLL_PLLCON2_K1INSEL_Msk (0x100UL) /*!< SCU_PLL PLLCON2: K1INSEL (Bitfield-Mask: 0x01) */ 5315 5316 /* ----------------------------- SCU_PLL_USBPLLSTAT ----------------------------- */ 5317 #define SCU_PLL_USBPLLSTAT_VCOBYST_Pos (0UL) /*!< SCU_PLL USBPLLSTAT: VCOBYST (Bit 0) */ 5318 #define SCU_PLL_USBPLLSTAT_VCOBYST_Msk (0x1UL) /*!< SCU_PLL USBPLLSTAT: VCOBYST (Bitfield-Mask: 0x01) */ 5319 #define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos (1UL) /*!< SCU_PLL USBPLLSTAT: PWDSTAT (Bit 1) */ 5320 #define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk (0x2UL) /*!< SCU_PLL USBPLLSTAT: PWDSTAT (Bitfield-Mask: 0x01) */ 5321 #define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos (2UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCK (Bit 2) */ 5322 #define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk (0x4UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCK (Bitfield-Mask: 0x01) */ 5323 #define SCU_PLL_USBPLLSTAT_BY_Pos (6UL) /*!< SCU_PLL USBPLLSTAT: BY (Bit 6) */ 5324 #define SCU_PLL_USBPLLSTAT_BY_Msk (0x40UL) /*!< SCU_PLL USBPLLSTAT: BY (Bitfield-Mask: 0x01) */ 5325 #define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos (7UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED (Bit 7) */ 5326 #define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk (0x80UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED (Bitfield-Mask: 0x01) */ 5327 5328 /* ------------------------------ SCU_PLL_USBPLLCON ----------------------------- */ 5329 #define SCU_PLL_USBPLLCON_VCOBYP_Pos (0UL) /*!< SCU_PLL USBPLLCON: VCOBYP (Bit 0) */ 5330 #define SCU_PLL_USBPLLCON_VCOBYP_Msk (0x1UL) /*!< SCU_PLL USBPLLCON: VCOBYP (Bitfield-Mask: 0x01) */ 5331 #define SCU_PLL_USBPLLCON_VCOPWD_Pos (1UL) /*!< SCU_PLL USBPLLCON: VCOPWD (Bit 1) */ 5332 #define SCU_PLL_USBPLLCON_VCOPWD_Msk (0x2UL) /*!< SCU_PLL USBPLLCON: VCOPWD (Bitfield-Mask: 0x01) */ 5333 #define SCU_PLL_USBPLLCON_VCOTR_Pos (2UL) /*!< SCU_PLL USBPLLCON: VCOTR (Bit 2) */ 5334 #define SCU_PLL_USBPLLCON_VCOTR_Msk (0x4UL) /*!< SCU_PLL USBPLLCON: VCOTR (Bitfield-Mask: 0x01) */ 5335 #define SCU_PLL_USBPLLCON_FINDIS_Pos (4UL) /*!< SCU_PLL USBPLLCON: FINDIS (Bit 4) */ 5336 #define SCU_PLL_USBPLLCON_FINDIS_Msk (0x10UL) /*!< SCU_PLL USBPLLCON: FINDIS (Bitfield-Mask: 0x01) */ 5337 #define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos (6UL) /*!< SCU_PLL USBPLLCON: OSCDISCDIS (Bit 6) */ 5338 #define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk (0x40UL) /*!< SCU_PLL USBPLLCON: OSCDISCDIS (Bitfield-Mask: 0x01) */ 5339 #define SCU_PLL_USBPLLCON_NDIV_Pos (8UL) /*!< SCU_PLL USBPLLCON: NDIV (Bit 8) */ 5340 #define SCU_PLL_USBPLLCON_NDIV_Msk (0x7f00UL) /*!< SCU_PLL USBPLLCON: NDIV (Bitfield-Mask: 0x7f) */ 5341 #define SCU_PLL_USBPLLCON_PLLPWD_Pos (16UL) /*!< SCU_PLL USBPLLCON: PLLPWD (Bit 16) */ 5342 #define SCU_PLL_USBPLLCON_PLLPWD_Msk (0x10000UL) /*!< SCU_PLL USBPLLCON: PLLPWD (Bitfield-Mask: 0x01) */ 5343 #define SCU_PLL_USBPLLCON_RESLD_Pos (18UL) /*!< SCU_PLL USBPLLCON: RESLD (Bit 18) */ 5344 #define SCU_PLL_USBPLLCON_RESLD_Msk (0x40000UL) /*!< SCU_PLL USBPLLCON: RESLD (Bitfield-Mask: 0x01) */ 5345 #define SCU_PLL_USBPLLCON_PDIV_Pos (24UL) /*!< SCU_PLL USBPLLCON: PDIV (Bit 24) */ 5346 #define SCU_PLL_USBPLLCON_PDIV_Msk (0xf000000UL) /*!< SCU_PLL USBPLLCON: PDIV (Bitfield-Mask: 0x0f) */ 5347 5348 /* ------------------------------ SCU_PLL_CLKMXSTAT ----------------------------- */ 5349 #define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos (0UL) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX (Bit 0) */ 5350 #define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk (0x3UL) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX (Bitfield-Mask: 0x03) */ 5351 5352 5353 /* ================================================================================ */ 5354 /* ================ struct 'SCU_GENERAL' Position & Mask ================ */ 5355 /* ================================================================================ */ 5356 5357 5358 /* ------------------------------- SCU_GENERAL_ID ------------------------------- */ 5359 #define SCU_GENERAL_ID_MOD_REV_Pos (0UL) /*!< SCU_GENERAL ID: MOD_REV (Bit 0) */ 5360 #define SCU_GENERAL_ID_MOD_REV_Msk (0xffUL) /*!< SCU_GENERAL ID: MOD_REV (Bitfield-Mask: 0xff) */ 5361 #define SCU_GENERAL_ID_MOD_TYPE_Pos (8UL) /*!< SCU_GENERAL ID: MOD_TYPE (Bit 8) */ 5362 #define SCU_GENERAL_ID_MOD_TYPE_Msk (0xff00UL) /*!< SCU_GENERAL ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 5363 #define SCU_GENERAL_ID_MOD_NUMBER_Pos (16UL) /*!< SCU_GENERAL ID: MOD_NUMBER (Bit 16) */ 5364 #define SCU_GENERAL_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< SCU_GENERAL ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 5365 5366 /* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */ 5367 #define SCU_GENERAL_IDCHIP_IDCHIP_Pos (0UL) /*!< SCU_GENERAL IDCHIP: IDCHIP (Bit 0) */ 5368 #define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL) /*!< SCU_GENERAL IDCHIP: IDCHIP (Bitfield-Mask: 0xffffffff) */ 5369 5370 /* ----------------------------- SCU_GENERAL_IDMANUF ---------------------------- */ 5371 #define SCU_GENERAL_IDMANUF_DEPT_Pos (0UL) /*!< SCU_GENERAL IDMANUF: DEPT (Bit 0) */ 5372 #define SCU_GENERAL_IDMANUF_DEPT_Msk (0x1fUL) /*!< SCU_GENERAL IDMANUF: DEPT (Bitfield-Mask: 0x1f) */ 5373 #define SCU_GENERAL_IDMANUF_MANUF_Pos (5UL) /*!< SCU_GENERAL IDMANUF: MANUF (Bit 5) */ 5374 #define SCU_GENERAL_IDMANUF_MANUF_Msk (0xffe0UL) /*!< SCU_GENERAL IDMANUF: MANUF (Bitfield-Mask: 0x7ff) */ 5375 5376 /* ------------------------------ SCU_GENERAL_STCON ----------------------------- */ 5377 #define SCU_GENERAL_STCON_HWCON_Pos (0UL) /*!< SCU_GENERAL STCON: HWCON (Bit 0) */ 5378 #define SCU_GENERAL_STCON_HWCON_Msk (0x3UL) /*!< SCU_GENERAL STCON: HWCON (Bitfield-Mask: 0x03) */ 5379 #define SCU_GENERAL_STCON_SWCON_Pos (8UL) /*!< SCU_GENERAL STCON: SWCON (Bit 8) */ 5380 #define SCU_GENERAL_STCON_SWCON_Msk (0xf00UL) /*!< SCU_GENERAL STCON: SWCON (Bitfield-Mask: 0x0f) */ 5381 5382 /* ------------------------------- SCU_GENERAL_GPR ------------------------------ */ 5383 #define SCU_GENERAL_GPR_DAT_Pos (0UL) /*!< SCU_GENERAL GPR: DAT (Bit 0) */ 5384 #define SCU_GENERAL_GPR_DAT_Msk (0xffffffffUL) /*!< SCU_GENERAL GPR: DAT (Bitfield-Mask: 0xffffffff) */ 5385 5386 /* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */ 5387 #define SCU_GENERAL_CCUCON_GSC40_Pos (0UL) /*!< SCU_GENERAL CCUCON: GSC40 (Bit 0) */ 5388 #define SCU_GENERAL_CCUCON_GSC40_Msk (0x1UL) /*!< SCU_GENERAL CCUCON: GSC40 (Bitfield-Mask: 0x01) */ 5389 #define SCU_GENERAL_CCUCON_GSC41_Pos (1UL) /*!< SCU_GENERAL CCUCON: GSC41 (Bit 1) */ 5390 #define SCU_GENERAL_CCUCON_GSC41_Msk (0x2UL) /*!< SCU_GENERAL CCUCON: GSC41 (Bitfield-Mask: 0x01) */ 5391 #define SCU_GENERAL_CCUCON_GSC42_Pos (2UL) /*!< SCU_GENERAL CCUCON: GSC42 (Bit 2) */ 5392 #define SCU_GENERAL_CCUCON_GSC42_Msk (0x4UL) /*!< SCU_GENERAL CCUCON: GSC42 (Bitfield-Mask: 0x01) */ 5393 #define SCU_GENERAL_CCUCON_GSC43_Pos (3UL) /*!< SCU_GENERAL CCUCON: GSC43 (Bit 3) */ 5394 #define SCU_GENERAL_CCUCON_GSC43_Msk (0x8UL) /*!< SCU_GENERAL CCUCON: GSC43 (Bitfield-Mask: 0x01) */ 5395 #define SCU_GENERAL_CCUCON_GSC80_Pos (8UL) /*!< SCU_GENERAL CCUCON: GSC80 (Bit 8) */ 5396 #define SCU_GENERAL_CCUCON_GSC80_Msk (0x100UL) /*!< SCU_GENERAL CCUCON: GSC80 (Bitfield-Mask: 0x01) */ 5397 #define SCU_GENERAL_CCUCON_GSC81_Pos (9UL) /*!< SCU_GENERAL CCUCON: GSC81 (Bit 9) */ 5398 #define SCU_GENERAL_CCUCON_GSC81_Msk (0x200UL) /*!< SCU_GENERAL CCUCON: GSC81 (Bitfield-Mask: 0x01) */ 5399 5400 /* ----------------------------- SCU_GENERAL_DTSCON ----------------------------- */ 5401 #define SCU_GENERAL_DTSCON_PWD_Pos (0UL) /*!< SCU_GENERAL DTSCON: PWD (Bit 0) */ 5402 #define SCU_GENERAL_DTSCON_PWD_Msk (0x1UL) /*!< SCU_GENERAL DTSCON: PWD (Bitfield-Mask: 0x01) */ 5403 #define SCU_GENERAL_DTSCON_START_Pos (1UL) /*!< SCU_GENERAL DTSCON: START (Bit 1) */ 5404 #define SCU_GENERAL_DTSCON_START_Msk (0x2UL) /*!< SCU_GENERAL DTSCON: START (Bitfield-Mask: 0x01) */ 5405 #define SCU_GENERAL_DTSCON_OFFSET_Pos (4UL) /*!< SCU_GENERAL DTSCON: OFFSET (Bit 4) */ 5406 #define SCU_GENERAL_DTSCON_OFFSET_Msk (0x7f0UL) /*!< SCU_GENERAL DTSCON: OFFSET (Bitfield-Mask: 0x7f) */ 5407 #define SCU_GENERAL_DTSCON_GAIN_Pos (11UL) /*!< SCU_GENERAL DTSCON: GAIN (Bit 11) */ 5408 #define SCU_GENERAL_DTSCON_GAIN_Msk (0x1f800UL) /*!< SCU_GENERAL DTSCON: GAIN (Bitfield-Mask: 0x3f) */ 5409 #define SCU_GENERAL_DTSCON_REFTRIM_Pos (17UL) /*!< SCU_GENERAL DTSCON: REFTRIM (Bit 17) */ 5410 #define SCU_GENERAL_DTSCON_REFTRIM_Msk (0xe0000UL) /*!< SCU_GENERAL DTSCON: REFTRIM (Bitfield-Mask: 0x07) */ 5411 #define SCU_GENERAL_DTSCON_BGTRIM_Pos (20UL) /*!< SCU_GENERAL DTSCON: BGTRIM (Bit 20) */ 5412 #define SCU_GENERAL_DTSCON_BGTRIM_Msk (0xf00000UL) /*!< SCU_GENERAL DTSCON: BGTRIM (Bitfield-Mask: 0x0f) */ 5413 5414 /* ----------------------------- SCU_GENERAL_DTSSTAT ---------------------------- */ 5415 #define SCU_GENERAL_DTSSTAT_RESULT_Pos (0UL) /*!< SCU_GENERAL DTSSTAT: RESULT (Bit 0) */ 5416 #define SCU_GENERAL_DTSSTAT_RESULT_Msk (0x3ffUL) /*!< SCU_GENERAL DTSSTAT: RESULT (Bitfield-Mask: 0x3ff) */ 5417 #define SCU_GENERAL_DTSSTAT_RDY_Pos (14UL) /*!< SCU_GENERAL DTSSTAT: RDY (Bit 14) */ 5418 #define SCU_GENERAL_DTSSTAT_RDY_Msk (0x4000UL) /*!< SCU_GENERAL DTSSTAT: RDY (Bitfield-Mask: 0x01) */ 5419 #define SCU_GENERAL_DTSSTAT_BUSY_Pos (15UL) /*!< SCU_GENERAL DTSSTAT: BUSY (Bit 15) */ 5420 #define SCU_GENERAL_DTSSTAT_BUSY_Msk (0x8000UL) /*!< SCU_GENERAL DTSSTAT: BUSY (Bitfield-Mask: 0x01) */ 5421 5422 /* ---------------------------- SCU_GENERAL_SDMMCDEL ---------------------------- */ 5423 #define SCU_GENERAL_SDMMCDEL_TAPEN_Pos (0UL) /*!< SCU_GENERAL SDMMCDEL: TAPEN (Bit 0) */ 5424 #define SCU_GENERAL_SDMMCDEL_TAPEN_Msk (0x1UL) /*!< SCU_GENERAL SDMMCDEL: TAPEN (Bitfield-Mask: 0x01) */ 5425 #define SCU_GENERAL_SDMMCDEL_TAPDEL_Pos (4UL) /*!< SCU_GENERAL SDMMCDEL: TAPDEL (Bit 4) */ 5426 #define SCU_GENERAL_SDMMCDEL_TAPDEL_Msk (0xf0UL) /*!< SCU_GENERAL SDMMCDEL: TAPDEL (Bitfield-Mask: 0x0f) */ 5427 5428 /* ----------------------------- SCU_GENERAL_GORCEN ----------------------------- */ 5429 #define SCU_GENERAL_GORCEN_ENORC6_Pos (6UL) /*!< SCU_GENERAL GORCEN: ENORC6 (Bit 6) */ 5430 #define SCU_GENERAL_GORCEN_ENORC6_Msk (0x40UL) /*!< SCU_GENERAL GORCEN: ENORC6 (Bitfield-Mask: 0x01) */ 5431 #define SCU_GENERAL_GORCEN_ENORC7_Pos (7UL) /*!< SCU_GENERAL GORCEN: ENORC7 (Bit 7) */ 5432 #define SCU_GENERAL_GORCEN_ENORC7_Msk (0x80UL) /*!< SCU_GENERAL GORCEN: ENORC7 (Bitfield-Mask: 0x01) */ 5433 5434 /* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */ 5435 #define SCU_GENERAL_MIRRSTS_HDCLR_Pos (1UL) /*!< SCU_GENERAL MIRRSTS: HDCLR (Bit 1) */ 5436 #define SCU_GENERAL_MIRRSTS_HDCLR_Msk (0x2UL) /*!< SCU_GENERAL MIRRSTS: HDCLR (Bitfield-Mask: 0x01) */ 5437 #define SCU_GENERAL_MIRRSTS_HDSET_Pos (2UL) /*!< SCU_GENERAL MIRRSTS: HDSET (Bit 2) */ 5438 #define SCU_GENERAL_MIRRSTS_HDSET_Msk (0x4UL) /*!< SCU_GENERAL MIRRSTS: HDSET (Bitfield-Mask: 0x01) */ 5439 #define SCU_GENERAL_MIRRSTS_HDCR_Pos (3UL) /*!< SCU_GENERAL MIRRSTS: HDCR (Bit 3) */ 5440 #define SCU_GENERAL_MIRRSTS_HDCR_Msk (0x8UL) /*!< SCU_GENERAL MIRRSTS: HDCR (Bitfield-Mask: 0x01) */ 5441 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos (5UL) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bit 5) */ 5442 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk (0x20UL) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bitfield-Mask: 0x01) */ 5443 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos (7UL) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bit 7) */ 5444 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk (0x80UL) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bitfield-Mask: 0x01) */ 5445 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos (8UL) /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bit 8) */ 5446 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x100UL) /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bitfield-Mask: 0x01) */ 5447 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos (9UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 (Bit 9) */ 5448 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x200UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 (Bitfield-Mask: 0x01) */ 5449 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos (10UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 (Bit 10) */ 5450 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x400UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 (Bitfield-Mask: 0x01) */ 5451 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos (11UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 (Bit 11) */ 5452 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x800UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 (Bitfield-Mask: 0x01) */ 5453 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos (12UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 (Bit 12) */ 5454 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x1000UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 (Bitfield-Mask: 0x01) */ 5455 #define SCU_GENERAL_MIRRSTS_RMX_Pos (13UL) /*!< SCU_GENERAL MIRRSTS: RMX (Bit 13) */ 5456 #define SCU_GENERAL_MIRRSTS_RMX_Msk (0x2000UL) /*!< SCU_GENERAL MIRRSTS: RMX (Bitfield-Mask: 0x01) */ 5457 #define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos (14UL) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR (Bit 14) */ 5458 #define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk (0x4000UL) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR (Bitfield-Mask: 0x01) */ 5459 #define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos (15UL) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR (Bit 15) */ 5460 #define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk (0x8000UL) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR (Bitfield-Mask: 0x01) */ 5461 5462 /* ------------------------------ SCU_GENERAL_RMACR ----------------------------- */ 5463 #define SCU_GENERAL_RMACR_RDWR_Pos (0UL) /*!< SCU_GENERAL RMACR: RDWR (Bit 0) */ 5464 #define SCU_GENERAL_RMACR_RDWR_Msk (0x1UL) /*!< SCU_GENERAL RMACR: RDWR (Bitfield-Mask: 0x01) */ 5465 #define SCU_GENERAL_RMACR_ADDR_Pos (16UL) /*!< SCU_GENERAL RMACR: ADDR (Bit 16) */ 5466 #define SCU_GENERAL_RMACR_ADDR_Msk (0xf0000UL) /*!< SCU_GENERAL RMACR: ADDR (Bitfield-Mask: 0x0f) */ 5467 5468 /* ----------------------------- SCU_GENERAL_RMDATA ----------------------------- */ 5469 #define SCU_GENERAL_RMDATA_DATA_Pos (0UL) /*!< SCU_GENERAL RMDATA: DATA (Bit 0) */ 5470 #define SCU_GENERAL_RMDATA_DATA_Msk (0xffffffffUL) /*!< SCU_GENERAL RMDATA: DATA (Bitfield-Mask: 0xffffffff) */ 5471 5472 5473 /* ================================================================================ */ 5474 /* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */ 5475 /* ================================================================================ */ 5476 5477 5478 /* ---------------------------- SCU_INTERRUPT_SRSTAT ---------------------------- */ 5479 #define SCU_INTERRUPT_SRSTAT_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRSTAT: PRWARN (Bit 0) */ 5480 #define SCU_INTERRUPT_SRSTAT_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRSTAT: PRWARN (Bitfield-Mask: 0x01) */ 5481 #define SCU_INTERRUPT_SRSTAT_PI_Pos (1UL) /*!< SCU_INTERRUPT SRSTAT: PI (Bit 1) */ 5482 #define SCU_INTERRUPT_SRSTAT_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRSTAT: PI (Bitfield-Mask: 0x01) */ 5483 #define SCU_INTERRUPT_SRSTAT_AI_Pos (2UL) /*!< SCU_INTERRUPT SRSTAT: AI (Bit 2) */ 5484 #define SCU_INTERRUPT_SRSTAT_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRSTAT: AI (Bitfield-Mask: 0x01) */ 5485 #define SCU_INTERRUPT_SRSTAT_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bit 3) */ 5486 #define SCU_INTERRUPT_SRSTAT_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bitfield-Mask: 0x01) */ 5487 #define SCU_INTERRUPT_SRSTAT_HDCLR_Pos (17UL) /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bit 17) */ 5488 #define SCU_INTERRUPT_SRSTAT_HDCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bitfield-Mask: 0x01) */ 5489 #define SCU_INTERRUPT_SRSTAT_HDSET_Pos (18UL) /*!< SCU_INTERRUPT SRSTAT: HDSET (Bit 18) */ 5490 #define SCU_INTERRUPT_SRSTAT_HDSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRSTAT: HDSET (Bitfield-Mask: 0x01) */ 5491 #define SCU_INTERRUPT_SRSTAT_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRSTAT: HDCR (Bit 19) */ 5492 #define SCU_INTERRUPT_SRSTAT_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRSTAT: HDCR (Bitfield-Mask: 0x01) */ 5493 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bit 21) */ 5494 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bitfield-Mask: 0x01) */ 5495 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bit 23) */ 5496 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bitfield-Mask: 0x01) */ 5497 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bit 24) */ 5498 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bitfield-Mask: 0x01) */ 5499 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 (Bit 25) */ 5500 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 (Bitfield-Mask: 0x01) */ 5501 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 (Bit 26) */ 5502 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 (Bitfield-Mask: 0x01) */ 5503 #define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 (Bit 27) */ 5504 #define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 (Bitfield-Mask: 0x01) */ 5505 #define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 (Bit 28) */ 5506 #define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 (Bitfield-Mask: 0x01) */ 5507 #define SCU_INTERRUPT_SRSTAT_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRSTAT: RMX (Bit 29) */ 5508 #define SCU_INTERRUPT_SRSTAT_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRSTAT: RMX (Bitfield-Mask: 0x01) */ 5509 5510 /* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */ 5511 #define SCU_INTERRUPT_SRRAW_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRRAW: PRWARN (Bit 0) */ 5512 #define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRRAW: PRWARN (Bitfield-Mask: 0x01) */ 5513 #define SCU_INTERRUPT_SRRAW_PI_Pos (1UL) /*!< SCU_INTERRUPT SRRAW: PI (Bit 1) */ 5514 #define SCU_INTERRUPT_SRRAW_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRRAW: PI (Bitfield-Mask: 0x01) */ 5515 #define SCU_INTERRUPT_SRRAW_AI_Pos (2UL) /*!< SCU_INTERRUPT SRRAW: AI (Bit 2) */ 5516 #define SCU_INTERRUPT_SRRAW_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRRAW: AI (Bitfield-Mask: 0x01) */ 5517 #define SCU_INTERRUPT_SRRAW_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRRAW: DLROVR (Bit 3) */ 5518 #define SCU_INTERRUPT_SRRAW_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRRAW: DLROVR (Bitfield-Mask: 0x01) */ 5519 #define SCU_INTERRUPT_SRRAW_HDCLR_Pos (17UL) /*!< SCU_INTERRUPT SRRAW: HDCLR (Bit 17) */ 5520 #define SCU_INTERRUPT_SRRAW_HDCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRRAW: HDCLR (Bitfield-Mask: 0x01) */ 5521 #define SCU_INTERRUPT_SRRAW_HDSET_Pos (18UL) /*!< SCU_INTERRUPT SRRAW: HDSET (Bit 18) */ 5522 #define SCU_INTERRUPT_SRRAW_HDSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRRAW: HDSET (Bitfield-Mask: 0x01) */ 5523 #define SCU_INTERRUPT_SRRAW_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRRAW: HDCR (Bit 19) */ 5524 #define SCU_INTERRUPT_SRRAW_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRRAW: HDCR (Bitfield-Mask: 0x01) */ 5525 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bit 21) */ 5526 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bitfield-Mask: 0x01) */ 5527 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bit 23) */ 5528 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bitfield-Mask: 0x01) */ 5529 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bit 24) */ 5530 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bitfield-Mask: 0x01) */ 5531 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 (Bit 25) */ 5532 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 (Bitfield-Mask: 0x01) */ 5533 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 (Bit 26) */ 5534 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 (Bitfield-Mask: 0x01) */ 5535 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 (Bit 27) */ 5536 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 (Bitfield-Mask: 0x01) */ 5537 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 (Bit 28) */ 5538 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 (Bitfield-Mask: 0x01) */ 5539 #define SCU_INTERRUPT_SRRAW_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRRAW: RMX (Bit 29) */ 5540 #define SCU_INTERRUPT_SRRAW_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRRAW: RMX (Bitfield-Mask: 0x01) */ 5541 5542 /* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */ 5543 #define SCU_INTERRUPT_SRMSK_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRMSK: PRWARN (Bit 0) */ 5544 #define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRMSK: PRWARN (Bitfield-Mask: 0x01) */ 5545 #define SCU_INTERRUPT_SRMSK_PI_Pos (1UL) /*!< SCU_INTERRUPT SRMSK: PI (Bit 1) */ 5546 #define SCU_INTERRUPT_SRMSK_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRMSK: PI (Bitfield-Mask: 0x01) */ 5547 #define SCU_INTERRUPT_SRMSK_AI_Pos (2UL) /*!< SCU_INTERRUPT SRMSK: AI (Bit 2) */ 5548 #define SCU_INTERRUPT_SRMSK_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRMSK: AI (Bitfield-Mask: 0x01) */ 5549 #define SCU_INTERRUPT_SRMSK_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRMSK: DLROVR (Bit 3) */ 5550 #define SCU_INTERRUPT_SRMSK_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRMSK: DLROVR (Bitfield-Mask: 0x01) */ 5551 #define SCU_INTERRUPT_SRMSK_HDCLR_Pos (17UL) /*!< SCU_INTERRUPT SRMSK: HDCLR (Bit 17) */ 5552 #define SCU_INTERRUPT_SRMSK_HDCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRMSK: HDCLR (Bitfield-Mask: 0x01) */ 5553 #define SCU_INTERRUPT_SRMSK_HDSET_Pos (18UL) /*!< SCU_INTERRUPT SRMSK: HDSET (Bit 18) */ 5554 #define SCU_INTERRUPT_SRMSK_HDSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRMSK: HDSET (Bitfield-Mask: 0x01) */ 5555 #define SCU_INTERRUPT_SRMSK_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRMSK: HDCR (Bit 19) */ 5556 #define SCU_INTERRUPT_SRMSK_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRMSK: HDCR (Bitfield-Mask: 0x01) */ 5557 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bit 21) */ 5558 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bitfield-Mask: 0x01) */ 5559 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bit 23) */ 5560 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bitfield-Mask: 0x01) */ 5561 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bit 24) */ 5562 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bitfield-Mask: 0x01) */ 5563 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 (Bit 25) */ 5564 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 (Bitfield-Mask: 0x01) */ 5565 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 (Bit 26) */ 5566 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 (Bitfield-Mask: 0x01) */ 5567 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 (Bit 27) */ 5568 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 (Bitfield-Mask: 0x01) */ 5569 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 (Bit 28) */ 5570 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 (Bitfield-Mask: 0x01) */ 5571 #define SCU_INTERRUPT_SRMSK_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRMSK: RMX (Bit 29) */ 5572 #define SCU_INTERRUPT_SRMSK_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRMSK: RMX (Bitfield-Mask: 0x01) */ 5573 5574 /* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */ 5575 #define SCU_INTERRUPT_SRCLR_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRCLR: PRWARN (Bit 0) */ 5576 #define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRCLR: PRWARN (Bitfield-Mask: 0x01) */ 5577 #define SCU_INTERRUPT_SRCLR_PI_Pos (1UL) /*!< SCU_INTERRUPT SRCLR: PI (Bit 1) */ 5578 #define SCU_INTERRUPT_SRCLR_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRCLR: PI (Bitfield-Mask: 0x01) */ 5579 #define SCU_INTERRUPT_SRCLR_AI_Pos (2UL) /*!< SCU_INTERRUPT SRCLR: AI (Bit 2) */ 5580 #define SCU_INTERRUPT_SRCLR_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRCLR: AI (Bitfield-Mask: 0x01) */ 5581 #define SCU_INTERRUPT_SRCLR_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRCLR: DLROVR (Bit 3) */ 5582 #define SCU_INTERRUPT_SRCLR_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRCLR: DLROVR (Bitfield-Mask: 0x01) */ 5583 #define SCU_INTERRUPT_SRCLR_HDCLR_Pos (17UL) /*!< SCU_INTERRUPT SRCLR: HDCLR (Bit 17) */ 5584 #define SCU_INTERRUPT_SRCLR_HDCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRCLR: HDCLR (Bitfield-Mask: 0x01) */ 5585 #define SCU_INTERRUPT_SRCLR_HDSET_Pos (18UL) /*!< SCU_INTERRUPT SRCLR: HDSET (Bit 18) */ 5586 #define SCU_INTERRUPT_SRCLR_HDSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRCLR: HDSET (Bitfield-Mask: 0x01) */ 5587 #define SCU_INTERRUPT_SRCLR_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRCLR: HDCR (Bit 19) */ 5588 #define SCU_INTERRUPT_SRCLR_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRCLR: HDCR (Bitfield-Mask: 0x01) */ 5589 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bit 21) */ 5590 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bitfield-Mask: 0x01) */ 5591 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bit 23) */ 5592 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bitfield-Mask: 0x01) */ 5593 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bit 24) */ 5594 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bitfield-Mask: 0x01) */ 5595 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 (Bit 25) */ 5596 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 (Bitfield-Mask: 0x01) */ 5597 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 (Bit 26) */ 5598 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 (Bitfield-Mask: 0x01) */ 5599 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 (Bit 27) */ 5600 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 (Bitfield-Mask: 0x01) */ 5601 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 (Bit 28) */ 5602 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 (Bitfield-Mask: 0x01) */ 5603 #define SCU_INTERRUPT_SRCLR_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRCLR: RMX (Bit 29) */ 5604 #define SCU_INTERRUPT_SRCLR_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRCLR: RMX (Bitfield-Mask: 0x01) */ 5605 5606 /* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */ 5607 #define SCU_INTERRUPT_SRSET_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRSET: PRWARN (Bit 0) */ 5608 #define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRSET: PRWARN (Bitfield-Mask: 0x01) */ 5609 #define SCU_INTERRUPT_SRSET_PI_Pos (1UL) /*!< SCU_INTERRUPT SRSET: PI (Bit 1) */ 5610 #define SCU_INTERRUPT_SRSET_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRSET: PI (Bitfield-Mask: 0x01) */ 5611 #define SCU_INTERRUPT_SRSET_AI_Pos (2UL) /*!< SCU_INTERRUPT SRSET: AI (Bit 2) */ 5612 #define SCU_INTERRUPT_SRSET_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRSET: AI (Bitfield-Mask: 0x01) */ 5613 #define SCU_INTERRUPT_SRSET_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRSET: DLROVR (Bit 3) */ 5614 #define SCU_INTERRUPT_SRSET_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRSET: DLROVR (Bitfield-Mask: 0x01) */ 5615 #define SCU_INTERRUPT_SRSET_HDCRCLR_Pos (17UL) /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bit 17) */ 5616 #define SCU_INTERRUPT_SRSET_HDCRCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bitfield-Mask: 0x01) */ 5617 #define SCU_INTERRUPT_SRSET_HDCRSET_Pos (18UL) /*!< SCU_INTERRUPT SRSET: HDCRSET (Bit 18) */ 5618 #define SCU_INTERRUPT_SRSET_HDCRSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRSET: HDCRSET (Bitfield-Mask: 0x01) */ 5619 #define SCU_INTERRUPT_SRSET_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRSET: HDCR (Bit 19) */ 5620 #define SCU_INTERRUPT_SRSET_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRSET: HDCR (Bitfield-Mask: 0x01) */ 5621 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bit 21) */ 5622 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bitfield-Mask: 0x01) */ 5623 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bit 23) */ 5624 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bitfield-Mask: 0x01) */ 5625 #define SCU_INTERRUPT_SRSET_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bit 24) */ 5626 #define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bitfield-Mask: 0x01) */ 5627 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 (Bit 25) */ 5628 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 (Bitfield-Mask: 0x01) */ 5629 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 (Bit 26) */ 5630 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 (Bitfield-Mask: 0x01) */ 5631 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 (Bit 27) */ 5632 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 (Bitfield-Mask: 0x01) */ 5633 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 (Bit 28) */ 5634 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 (Bitfield-Mask: 0x01) */ 5635 #define SCU_INTERRUPT_SRSET_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRSET: RMX (Bit 29) */ 5636 #define SCU_INTERRUPT_SRSET_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRSET: RMX (Bitfield-Mask: 0x01) */ 5637 5638 /* --------------------------- SCU_INTERRUPT_NMIREQEN --------------------------- */ 5639 #define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT NMIREQEN: PRWARN (Bit 0) */ 5640 #define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT NMIREQEN: PRWARN (Bitfield-Mask: 0x01) */ 5641 #define SCU_INTERRUPT_NMIREQEN_PI_Pos (1UL) /*!< SCU_INTERRUPT NMIREQEN: PI (Bit 1) */ 5642 #define SCU_INTERRUPT_NMIREQEN_PI_Msk (0x2UL) /*!< SCU_INTERRUPT NMIREQEN: PI (Bitfield-Mask: 0x01) */ 5643 #define SCU_INTERRUPT_NMIREQEN_AI_Pos (2UL) /*!< SCU_INTERRUPT NMIREQEN: AI (Bit 2) */ 5644 #define SCU_INTERRUPT_NMIREQEN_AI_Msk (0x4UL) /*!< SCU_INTERRUPT NMIREQEN: AI (Bitfield-Mask: 0x01) */ 5645 #define SCU_INTERRUPT_NMIREQEN_ERU00_Pos (16UL) /*!< SCU_INTERRUPT NMIREQEN: ERU00 (Bit 16) */ 5646 #define SCU_INTERRUPT_NMIREQEN_ERU00_Msk (0x10000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU00 (Bitfield-Mask: 0x01) */ 5647 #define SCU_INTERRUPT_NMIREQEN_ERU01_Pos (17UL) /*!< SCU_INTERRUPT NMIREQEN: ERU01 (Bit 17) */ 5648 #define SCU_INTERRUPT_NMIREQEN_ERU01_Msk (0x20000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU01 (Bitfield-Mask: 0x01) */ 5649 #define SCU_INTERRUPT_NMIREQEN_ERU02_Pos (18UL) /*!< SCU_INTERRUPT NMIREQEN: ERU02 (Bit 18) */ 5650 #define SCU_INTERRUPT_NMIREQEN_ERU02_Msk (0x40000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU02 (Bitfield-Mask: 0x01) */ 5651 #define SCU_INTERRUPT_NMIREQEN_ERU03_Pos (19UL) /*!< SCU_INTERRUPT NMIREQEN: ERU03 (Bit 19) */ 5652 #define SCU_INTERRUPT_NMIREQEN_ERU03_Msk (0x80000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU03 (Bitfield-Mask: 0x01) */ 5653 5654 5655 /* ================================================================================ */ 5656 /* ================ struct 'SCU_PARITY' Position & Mask ================ */ 5657 /* ================================================================================ */ 5658 5659 5660 /* ------------------------------- SCU_PARITY_PEEN ------------------------------ */ 5661 #define SCU_PARITY_PEEN_PEENPS_Pos (0UL) /*!< SCU_PARITY PEEN: PEENPS (Bit 0) */ 5662 #define SCU_PARITY_PEEN_PEENPS_Msk (0x1UL) /*!< SCU_PARITY PEEN: PEENPS (Bitfield-Mask: 0x01) */ 5663 #define SCU_PARITY_PEEN_PEENDS1_Pos (1UL) /*!< SCU_PARITY PEEN: PEENDS1 (Bit 1) */ 5664 #define SCU_PARITY_PEEN_PEENDS1_Msk (0x2UL) /*!< SCU_PARITY PEEN: PEENDS1 (Bitfield-Mask: 0x01) */ 5665 #define SCU_PARITY_PEEN_PEENDS2_Pos (2UL) /*!< SCU_PARITY PEEN: PEENDS2 (Bit 2) */ 5666 #define SCU_PARITY_PEEN_PEENDS2_Msk (0x4UL) /*!< SCU_PARITY PEEN: PEENDS2 (Bitfield-Mask: 0x01) */ 5667 #define SCU_PARITY_PEEN_PEENU0_Pos (8UL) /*!< SCU_PARITY PEEN: PEENU0 (Bit 8) */ 5668 #define SCU_PARITY_PEEN_PEENU0_Msk (0x100UL) /*!< SCU_PARITY PEEN: PEENU0 (Bitfield-Mask: 0x01) */ 5669 #define SCU_PARITY_PEEN_PEENU1_Pos (9UL) /*!< SCU_PARITY PEEN: PEENU1 (Bit 9) */ 5670 #define SCU_PARITY_PEEN_PEENU1_Msk (0x200UL) /*!< SCU_PARITY PEEN: PEENU1 (Bitfield-Mask: 0x01) */ 5671 #define SCU_PARITY_PEEN_PEENU2_Pos (10UL) /*!< SCU_PARITY PEEN: PEENU2 (Bit 10) */ 5672 #define SCU_PARITY_PEEN_PEENU2_Msk (0x400UL) /*!< SCU_PARITY PEEN: PEENU2 (Bitfield-Mask: 0x01) */ 5673 #define SCU_PARITY_PEEN_PEENMC_Pos (12UL) /*!< SCU_PARITY PEEN: PEENMC (Bit 12) */ 5674 #define SCU_PARITY_PEEN_PEENMC_Msk (0x1000UL) /*!< SCU_PARITY PEEN: PEENMC (Bitfield-Mask: 0x01) */ 5675 #define SCU_PARITY_PEEN_PEENPPRF_Pos (13UL) /*!< SCU_PARITY PEEN: PEENPPRF (Bit 13) */ 5676 #define SCU_PARITY_PEEN_PEENPPRF_Msk (0x2000UL) /*!< SCU_PARITY PEEN: PEENPPRF (Bitfield-Mask: 0x01) */ 5677 #define SCU_PARITY_PEEN_PEENUSB_Pos (16UL) /*!< SCU_PARITY PEEN: PEENUSB (Bit 16) */ 5678 #define SCU_PARITY_PEEN_PEENUSB_Msk (0x10000UL) /*!< SCU_PARITY PEEN: PEENUSB (Bitfield-Mask: 0x01) */ 5679 #define SCU_PARITY_PEEN_PEENETH0TX_Pos (17UL) /*!< SCU_PARITY PEEN: PEENETH0TX (Bit 17) */ 5680 #define SCU_PARITY_PEEN_PEENETH0TX_Msk (0x20000UL) /*!< SCU_PARITY PEEN: PEENETH0TX (Bitfield-Mask: 0x01) */ 5681 #define SCU_PARITY_PEEN_PEENETH0RX_Pos (18UL) /*!< SCU_PARITY PEEN: PEENETH0RX (Bit 18) */ 5682 #define SCU_PARITY_PEEN_PEENETH0RX_Msk (0x40000UL) /*!< SCU_PARITY PEEN: PEENETH0RX (Bitfield-Mask: 0x01) */ 5683 #define SCU_PARITY_PEEN_PEENSD0_Pos (19UL) /*!< SCU_PARITY PEEN: PEENSD0 (Bit 19) */ 5684 #define SCU_PARITY_PEEN_PEENSD0_Msk (0x80000UL) /*!< SCU_PARITY PEEN: PEENSD0 (Bitfield-Mask: 0x01) */ 5685 #define SCU_PARITY_PEEN_PEENSD1_Pos (20UL) /*!< SCU_PARITY PEEN: PEENSD1 (Bit 20) */ 5686 #define SCU_PARITY_PEEN_PEENSD1_Msk (0x100000UL) /*!< SCU_PARITY PEEN: PEENSD1 (Bitfield-Mask: 0x01) */ 5687 5688 /* ----------------------------- SCU_PARITY_MCHKCON ----------------------------- */ 5689 #define SCU_PARITY_MCHKCON_SELPS_Pos (0UL) /*!< SCU_PARITY MCHKCON: SELPS (Bit 0) */ 5690 #define SCU_PARITY_MCHKCON_SELPS_Msk (0x1UL) /*!< SCU_PARITY MCHKCON: SELPS (Bitfield-Mask: 0x01) */ 5691 #define SCU_PARITY_MCHKCON_SELDS1_Pos (1UL) /*!< SCU_PARITY MCHKCON: SELDS1 (Bit 1) */ 5692 #define SCU_PARITY_MCHKCON_SELDS1_Msk (0x2UL) /*!< SCU_PARITY MCHKCON: SELDS1 (Bitfield-Mask: 0x01) */ 5693 #define SCU_PARITY_MCHKCON_SELDS2_Pos (2UL) /*!< SCU_PARITY MCHKCON: SELDS2 (Bit 2) */ 5694 #define SCU_PARITY_MCHKCON_SELDS2_Msk (0x4UL) /*!< SCU_PARITY MCHKCON: SELDS2 (Bitfield-Mask: 0x01) */ 5695 #define SCU_PARITY_MCHKCON_USIC0DRA_Pos (8UL) /*!< SCU_PARITY MCHKCON: USIC0DRA (Bit 8) */ 5696 #define SCU_PARITY_MCHKCON_USIC0DRA_Msk (0x100UL) /*!< SCU_PARITY MCHKCON: USIC0DRA (Bitfield-Mask: 0x01) */ 5697 #define SCU_PARITY_MCHKCON_USIC1DRA_Pos (9UL) /*!< SCU_PARITY MCHKCON: USIC1DRA (Bit 9) */ 5698 #define SCU_PARITY_MCHKCON_USIC1DRA_Msk (0x200UL) /*!< SCU_PARITY MCHKCON: USIC1DRA (Bitfield-Mask: 0x01) */ 5699 #define SCU_PARITY_MCHKCON_USIC2DRA_Pos (10UL) /*!< SCU_PARITY MCHKCON: USIC2DRA (Bit 10) */ 5700 #define SCU_PARITY_MCHKCON_USIC2DRA_Msk (0x400UL) /*!< SCU_PARITY MCHKCON: USIC2DRA (Bitfield-Mask: 0x01) */ 5701 #define SCU_PARITY_MCHKCON_MCANDRA_Pos (12UL) /*!< SCU_PARITY MCHKCON: MCANDRA (Bit 12) */ 5702 #define SCU_PARITY_MCHKCON_MCANDRA_Msk (0x1000UL) /*!< SCU_PARITY MCHKCON: MCANDRA (Bitfield-Mask: 0x01) */ 5703 #define SCU_PARITY_MCHKCON_PPRFDRA_Pos (13UL) /*!< SCU_PARITY MCHKCON: PPRFDRA (Bit 13) */ 5704 #define SCU_PARITY_MCHKCON_PPRFDRA_Msk (0x2000UL) /*!< SCU_PARITY MCHKCON: PPRFDRA (Bitfield-Mask: 0x01) */ 5705 #define SCU_PARITY_MCHKCON_SELUSB_Pos (16UL) /*!< SCU_PARITY MCHKCON: SELUSB (Bit 16) */ 5706 #define SCU_PARITY_MCHKCON_SELUSB_Msk (0x10000UL) /*!< SCU_PARITY MCHKCON: SELUSB (Bitfield-Mask: 0x01) */ 5707 #define SCU_PARITY_MCHKCON_SELETH0TX_Pos (17UL) /*!< SCU_PARITY MCHKCON: SELETH0TX (Bit 17) */ 5708 #define SCU_PARITY_MCHKCON_SELETH0TX_Msk (0x20000UL) /*!< SCU_PARITY MCHKCON: SELETH0TX (Bitfield-Mask: 0x01) */ 5709 #define SCU_PARITY_MCHKCON_SELETH0RX_Pos (18UL) /*!< SCU_PARITY MCHKCON: SELETH0RX (Bit 18) */ 5710 #define SCU_PARITY_MCHKCON_SELETH0RX_Msk (0x40000UL) /*!< SCU_PARITY MCHKCON: SELETH0RX (Bitfield-Mask: 0x01) */ 5711 #define SCU_PARITY_MCHKCON_SELSD0_Pos (19UL) /*!< SCU_PARITY MCHKCON: SELSD0 (Bit 19) */ 5712 #define SCU_PARITY_MCHKCON_SELSD0_Msk (0x80000UL) /*!< SCU_PARITY MCHKCON: SELSD0 (Bitfield-Mask: 0x01) */ 5713 #define SCU_PARITY_MCHKCON_SELSD1_Pos (20UL) /*!< SCU_PARITY MCHKCON: SELSD1 (Bit 20) */ 5714 #define SCU_PARITY_MCHKCON_SELSD1_Msk (0x100000UL) /*!< SCU_PARITY MCHKCON: SELSD1 (Bitfield-Mask: 0x01) */ 5715 5716 /* ------------------------------- SCU_PARITY_PETE ------------------------------ */ 5717 #define SCU_PARITY_PETE_PETEPS_Pos (0UL) /*!< SCU_PARITY PETE: PETEPS (Bit 0) */ 5718 #define SCU_PARITY_PETE_PETEPS_Msk (0x1UL) /*!< SCU_PARITY PETE: PETEPS (Bitfield-Mask: 0x01) */ 5719 #define SCU_PARITY_PETE_PETEDS1_Pos (1UL) /*!< SCU_PARITY PETE: PETEDS1 (Bit 1) */ 5720 #define SCU_PARITY_PETE_PETEDS1_Msk (0x2UL) /*!< SCU_PARITY PETE: PETEDS1 (Bitfield-Mask: 0x01) */ 5721 #define SCU_PARITY_PETE_PETEDS2_Pos (2UL) /*!< SCU_PARITY PETE: PETEDS2 (Bit 2) */ 5722 #define SCU_PARITY_PETE_PETEDS2_Msk (0x4UL) /*!< SCU_PARITY PETE: PETEDS2 (Bitfield-Mask: 0x01) */ 5723 #define SCU_PARITY_PETE_PETEU0_Pos (8UL) /*!< SCU_PARITY PETE: PETEU0 (Bit 8) */ 5724 #define SCU_PARITY_PETE_PETEU0_Msk (0x100UL) /*!< SCU_PARITY PETE: PETEU0 (Bitfield-Mask: 0x01) */ 5725 #define SCU_PARITY_PETE_PETEU1_Pos (9UL) /*!< SCU_PARITY PETE: PETEU1 (Bit 9) */ 5726 #define SCU_PARITY_PETE_PETEU1_Msk (0x200UL) /*!< SCU_PARITY PETE: PETEU1 (Bitfield-Mask: 0x01) */ 5727 #define SCU_PARITY_PETE_PETEU2_Pos (10UL) /*!< SCU_PARITY PETE: PETEU2 (Bit 10) */ 5728 #define SCU_PARITY_PETE_PETEU2_Msk (0x400UL) /*!< SCU_PARITY PETE: PETEU2 (Bitfield-Mask: 0x01) */ 5729 #define SCU_PARITY_PETE_PETEMC_Pos (12UL) /*!< SCU_PARITY PETE: PETEMC (Bit 12) */ 5730 #define SCU_PARITY_PETE_PETEMC_Msk (0x1000UL) /*!< SCU_PARITY PETE: PETEMC (Bitfield-Mask: 0x01) */ 5731 #define SCU_PARITY_PETE_PETEPPRF_Pos (13UL) /*!< SCU_PARITY PETE: PETEPPRF (Bit 13) */ 5732 #define SCU_PARITY_PETE_PETEPPRF_Msk (0x2000UL) /*!< SCU_PARITY PETE: PETEPPRF (Bitfield-Mask: 0x01) */ 5733 #define SCU_PARITY_PETE_PETEUSB_Pos (16UL) /*!< SCU_PARITY PETE: PETEUSB (Bit 16) */ 5734 #define SCU_PARITY_PETE_PETEUSB_Msk (0x10000UL) /*!< SCU_PARITY PETE: PETEUSB (Bitfield-Mask: 0x01) */ 5735 #define SCU_PARITY_PETE_PETEETH0TX_Pos (17UL) /*!< SCU_PARITY PETE: PETEETH0TX (Bit 17) */ 5736 #define SCU_PARITY_PETE_PETEETH0TX_Msk (0x20000UL) /*!< SCU_PARITY PETE: PETEETH0TX (Bitfield-Mask: 0x01) */ 5737 #define SCU_PARITY_PETE_PETEETH0RX_Pos (18UL) /*!< SCU_PARITY PETE: PETEETH0RX (Bit 18) */ 5738 #define SCU_PARITY_PETE_PETEETH0RX_Msk (0x40000UL) /*!< SCU_PARITY PETE: PETEETH0RX (Bitfield-Mask: 0x01) */ 5739 #define SCU_PARITY_PETE_PETESD0_Pos (19UL) /*!< SCU_PARITY PETE: PETESD0 (Bit 19) */ 5740 #define SCU_PARITY_PETE_PETESD0_Msk (0x80000UL) /*!< SCU_PARITY PETE: PETESD0 (Bitfield-Mask: 0x01) */ 5741 #define SCU_PARITY_PETE_PETESD1_Pos (20UL) /*!< SCU_PARITY PETE: PETESD1 (Bit 20) */ 5742 #define SCU_PARITY_PETE_PETESD1_Msk (0x100000UL) /*!< SCU_PARITY PETE: PETESD1 (Bitfield-Mask: 0x01) */ 5743 5744 /* ----------------------------- SCU_PARITY_PERSTEN ----------------------------- */ 5745 #define SCU_PARITY_PERSTEN_RSEN_Pos (0UL) /*!< SCU_PARITY PERSTEN: RSEN (Bit 0) */ 5746 #define SCU_PARITY_PERSTEN_RSEN_Msk (0x1UL) /*!< SCU_PARITY PERSTEN: RSEN (Bitfield-Mask: 0x01) */ 5747 5748 /* ------------------------------ SCU_PARITY_PEFLAG ----------------------------- */ 5749 #define SCU_PARITY_PEFLAG_PEFPS_Pos (0UL) /*!< SCU_PARITY PEFLAG: PEFPS (Bit 0) */ 5750 #define SCU_PARITY_PEFLAG_PEFPS_Msk (0x1UL) /*!< SCU_PARITY PEFLAG: PEFPS (Bitfield-Mask: 0x01) */ 5751 #define SCU_PARITY_PEFLAG_PEFDS1_Pos (1UL) /*!< SCU_PARITY PEFLAG: PEFDS1 (Bit 1) */ 5752 #define SCU_PARITY_PEFLAG_PEFDS1_Msk (0x2UL) /*!< SCU_PARITY PEFLAG: PEFDS1 (Bitfield-Mask: 0x01) */ 5753 #define SCU_PARITY_PEFLAG_PEFDS2_Pos (2UL) /*!< SCU_PARITY PEFLAG: PEFDS2 (Bit 2) */ 5754 #define SCU_PARITY_PEFLAG_PEFDS2_Msk (0x4UL) /*!< SCU_PARITY PEFLAG: PEFDS2 (Bitfield-Mask: 0x01) */ 5755 #define SCU_PARITY_PEFLAG_PEFU0_Pos (8UL) /*!< SCU_PARITY PEFLAG: PEFU0 (Bit 8) */ 5756 #define SCU_PARITY_PEFLAG_PEFU0_Msk (0x100UL) /*!< SCU_PARITY PEFLAG: PEFU0 (Bitfield-Mask: 0x01) */ 5757 #define SCU_PARITY_PEFLAG_PEFU1_Pos (9UL) /*!< SCU_PARITY PEFLAG: PEFU1 (Bit 9) */ 5758 #define SCU_PARITY_PEFLAG_PEFU1_Msk (0x200UL) /*!< SCU_PARITY PEFLAG: PEFU1 (Bitfield-Mask: 0x01) */ 5759 #define SCU_PARITY_PEFLAG_PEFU2_Pos (10UL) /*!< SCU_PARITY PEFLAG: PEFU2 (Bit 10) */ 5760 #define SCU_PARITY_PEFLAG_PEFU2_Msk (0x400UL) /*!< SCU_PARITY PEFLAG: PEFU2 (Bitfield-Mask: 0x01) */ 5761 #define SCU_PARITY_PEFLAG_PEFMC_Pos (12UL) /*!< SCU_PARITY PEFLAG: PEFMC (Bit 12) */ 5762 #define SCU_PARITY_PEFLAG_PEFMC_Msk (0x1000UL) /*!< SCU_PARITY PEFLAG: PEFMC (Bitfield-Mask: 0x01) */ 5763 #define SCU_PARITY_PEFLAG_PEFPPRF_Pos (13UL) /*!< SCU_PARITY PEFLAG: PEFPPRF (Bit 13) */ 5764 #define SCU_PARITY_PEFLAG_PEFPPRF_Msk (0x2000UL) /*!< SCU_PARITY PEFLAG: PEFPPRF (Bitfield-Mask: 0x01) */ 5765 #define SCU_PARITY_PEFLAG_PEUSB_Pos (16UL) /*!< SCU_PARITY PEFLAG: PEUSB (Bit 16) */ 5766 #define SCU_PARITY_PEFLAG_PEUSB_Msk (0x10000UL) /*!< SCU_PARITY PEFLAG: PEUSB (Bitfield-Mask: 0x01) */ 5767 #define SCU_PARITY_PEFLAG_PEETH0TX_Pos (17UL) /*!< SCU_PARITY PEFLAG: PEETH0TX (Bit 17) */ 5768 #define SCU_PARITY_PEFLAG_PEETH0TX_Msk (0x20000UL) /*!< SCU_PARITY PEFLAG: PEETH0TX (Bitfield-Mask: 0x01) */ 5769 #define SCU_PARITY_PEFLAG_PEETH0RX_Pos (18UL) /*!< SCU_PARITY PEFLAG: PEETH0RX (Bit 18) */ 5770 #define SCU_PARITY_PEFLAG_PEETH0RX_Msk (0x40000UL) /*!< SCU_PARITY PEFLAG: PEETH0RX (Bitfield-Mask: 0x01) */ 5771 #define SCU_PARITY_PEFLAG_PESD0_Pos (19UL) /*!< SCU_PARITY PEFLAG: PESD0 (Bit 19) */ 5772 #define SCU_PARITY_PEFLAG_PESD0_Msk (0x80000UL) /*!< SCU_PARITY PEFLAG: PESD0 (Bitfield-Mask: 0x01) */ 5773 #define SCU_PARITY_PEFLAG_PESD1_Pos (20UL) /*!< SCU_PARITY PEFLAG: PESD1 (Bit 20) */ 5774 #define SCU_PARITY_PEFLAG_PESD1_Msk (0x100000UL) /*!< SCU_PARITY PEFLAG: PESD1 (Bitfield-Mask: 0x01) */ 5775 5776 /* ------------------------------ SCU_PARITY_PMTPR ------------------------------ */ 5777 #define SCU_PARITY_PMTPR_PWR_Pos (0UL) /*!< SCU_PARITY PMTPR: PWR (Bit 0) */ 5778 #define SCU_PARITY_PMTPR_PWR_Msk (0xffUL) /*!< SCU_PARITY PMTPR: PWR (Bitfield-Mask: 0xff) */ 5779 #define SCU_PARITY_PMTPR_PRD_Pos (8UL) /*!< SCU_PARITY PMTPR: PRD (Bit 8) */ 5780 #define SCU_PARITY_PMTPR_PRD_Msk (0xff00UL) /*!< SCU_PARITY PMTPR: PRD (Bitfield-Mask: 0xff) */ 5781 5782 /* ------------------------------ SCU_PARITY_PMTSR ------------------------------ */ 5783 #define SCU_PARITY_PMTSR_MTENPS_Pos (0UL) /*!< SCU_PARITY PMTSR: MTENPS (Bit 0) */ 5784 #define SCU_PARITY_PMTSR_MTENPS_Msk (0x1UL) /*!< SCU_PARITY PMTSR: MTENPS (Bitfield-Mask: 0x01) */ 5785 #define SCU_PARITY_PMTSR_MTENDS1_Pos (1UL) /*!< SCU_PARITY PMTSR: MTENDS1 (Bit 1) */ 5786 #define SCU_PARITY_PMTSR_MTENDS1_Msk (0x2UL) /*!< SCU_PARITY PMTSR: MTENDS1 (Bitfield-Mask: 0x01) */ 5787 #define SCU_PARITY_PMTSR_MTENDS2_Pos (2UL) /*!< SCU_PARITY PMTSR: MTENDS2 (Bit 2) */ 5788 #define SCU_PARITY_PMTSR_MTENDS2_Msk (0x4UL) /*!< SCU_PARITY PMTSR: MTENDS2 (Bitfield-Mask: 0x01) */ 5789 #define SCU_PARITY_PMTSR_MTEU0_Pos (8UL) /*!< SCU_PARITY PMTSR: MTEU0 (Bit 8) */ 5790 #define SCU_PARITY_PMTSR_MTEU0_Msk (0x100UL) /*!< SCU_PARITY PMTSR: MTEU0 (Bitfield-Mask: 0x01) */ 5791 #define SCU_PARITY_PMTSR_MTEU1_Pos (9UL) /*!< SCU_PARITY PMTSR: MTEU1 (Bit 9) */ 5792 #define SCU_PARITY_PMTSR_MTEU1_Msk (0x200UL) /*!< SCU_PARITY PMTSR: MTEU1 (Bitfield-Mask: 0x01) */ 5793 #define SCU_PARITY_PMTSR_MTEU2_Pos (10UL) /*!< SCU_PARITY PMTSR: MTEU2 (Bit 10) */ 5794 #define SCU_PARITY_PMTSR_MTEU2_Msk (0x400UL) /*!< SCU_PARITY PMTSR: MTEU2 (Bitfield-Mask: 0x01) */ 5795 #define SCU_PARITY_PMTSR_MTEMC_Pos (12UL) /*!< SCU_PARITY PMTSR: MTEMC (Bit 12) */ 5796 #define SCU_PARITY_PMTSR_MTEMC_Msk (0x1000UL) /*!< SCU_PARITY PMTSR: MTEMC (Bitfield-Mask: 0x01) */ 5797 #define SCU_PARITY_PMTSR_MTEPPRF_Pos (13UL) /*!< SCU_PARITY PMTSR: MTEPPRF (Bit 13) */ 5798 #define SCU_PARITY_PMTSR_MTEPPRF_Msk (0x2000UL) /*!< SCU_PARITY PMTSR: MTEPPRF (Bitfield-Mask: 0x01) */ 5799 #define SCU_PARITY_PMTSR_MTUSB_Pos (16UL) /*!< SCU_PARITY PMTSR: MTUSB (Bit 16) */ 5800 #define SCU_PARITY_PMTSR_MTUSB_Msk (0x10000UL) /*!< SCU_PARITY PMTSR: MTUSB (Bitfield-Mask: 0x01) */ 5801 #define SCU_PARITY_PMTSR_MTETH0TX_Pos (17UL) /*!< SCU_PARITY PMTSR: MTETH0TX (Bit 17) */ 5802 #define SCU_PARITY_PMTSR_MTETH0TX_Msk (0x20000UL) /*!< SCU_PARITY PMTSR: MTETH0TX (Bitfield-Mask: 0x01) */ 5803 #define SCU_PARITY_PMTSR_MTETH0RX_Pos (18UL) /*!< SCU_PARITY PMTSR: MTETH0RX (Bit 18) */ 5804 #define SCU_PARITY_PMTSR_MTETH0RX_Msk (0x40000UL) /*!< SCU_PARITY PMTSR: MTETH0RX (Bitfield-Mask: 0x01) */ 5805 #define SCU_PARITY_PMTSR_MTSD0_Pos (19UL) /*!< SCU_PARITY PMTSR: MTSD0 (Bit 19) */ 5806 #define SCU_PARITY_PMTSR_MTSD0_Msk (0x80000UL) /*!< SCU_PARITY PMTSR: MTSD0 (Bitfield-Mask: 0x01) */ 5807 #define SCU_PARITY_PMTSR_MTSD1_Pos (20UL) /*!< SCU_PARITY PMTSR: MTSD1 (Bit 20) */ 5808 #define SCU_PARITY_PMTSR_MTSD1_Msk (0x100000UL) /*!< SCU_PARITY PMTSR: MTSD1 (Bitfield-Mask: 0x01) */ 5809 5810 5811 /* ================================================================================ */ 5812 /* ================ struct 'SCU_TRAP' Position & Mask ================ */ 5813 /* ================================================================================ */ 5814 5815 5816 /* ------------------------------ SCU_TRAP_TRAPSTAT ----------------------------- */ 5817 #define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT (Bit 0) */ 5818 #define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT (Bitfield-Mask: 0x01) */ 5819 #define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT (Bit 2) */ 5820 #define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT (Bitfield-Mask: 0x01) */ 5821 #define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT (Bit 3) */ 5822 #define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT (Bitfield-Mask: 0x01) */ 5823 #define SCU_TRAP_TRAPSTAT_PET_Pos (4UL) /*!< SCU_TRAP TRAPSTAT: PET (Bit 4) */ 5824 #define SCU_TRAP_TRAPSTAT_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPSTAT: PET (Bitfield-Mask: 0x01) */ 5825 #define SCU_TRAP_TRAPSTAT_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPSTAT: BRWNT (Bit 5) */ 5826 #define SCU_TRAP_TRAPSTAT_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPSTAT: BRWNT (Bitfield-Mask: 0x01) */ 5827 #define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos (6UL) /*!< SCU_TRAP TRAPSTAT: ULPWDGT (Bit 6) */ 5828 #define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk (0x40UL) /*!< SCU_TRAP TRAPSTAT: ULPWDGT (Bitfield-Mask: 0x01) */ 5829 #define SCU_TRAP_TRAPSTAT_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPSTAT: BWERR0T (Bit 7) */ 5830 #define SCU_TRAP_TRAPSTAT_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPSTAT: BWERR0T (Bitfield-Mask: 0x01) */ 5831 #define SCU_TRAP_TRAPSTAT_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPSTAT: BWERR1T (Bit 8) */ 5832 #define SCU_TRAP_TRAPSTAT_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPSTAT: BWERR1T (Bitfield-Mask: 0x01) */ 5833 5834 /* ------------------------------ SCU_TRAP_TRAPRAW ------------------------------ */ 5835 #define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPRAW: SOSCWDGT (Bit 0) */ 5836 #define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPRAW: SOSCWDGT (Bitfield-Mask: 0x01) */ 5837 #define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPRAW: SVCOLCKT (Bit 2) */ 5838 #define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPRAW: SVCOLCKT (Bitfield-Mask: 0x01) */ 5839 #define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPRAW: UVCOLCKT (Bit 3) */ 5840 #define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPRAW: UVCOLCKT (Bitfield-Mask: 0x01) */ 5841 #define SCU_TRAP_TRAPRAW_PET_Pos (4UL) /*!< SCU_TRAP TRAPRAW: PET (Bit 4) */ 5842 #define SCU_TRAP_TRAPRAW_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPRAW: PET (Bitfield-Mask: 0x01) */ 5843 #define SCU_TRAP_TRAPRAW_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPRAW: BRWNT (Bit 5) */ 5844 #define SCU_TRAP_TRAPRAW_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPRAW: BRWNT (Bitfield-Mask: 0x01) */ 5845 #define SCU_TRAP_TRAPRAW_ULPWDGT_Pos (6UL) /*!< SCU_TRAP TRAPRAW: ULPWDGT (Bit 6) */ 5846 #define SCU_TRAP_TRAPRAW_ULPWDGT_Msk (0x40UL) /*!< SCU_TRAP TRAPRAW: ULPWDGT (Bitfield-Mask: 0x01) */ 5847 #define SCU_TRAP_TRAPRAW_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPRAW: BWERR0T (Bit 7) */ 5848 #define SCU_TRAP_TRAPRAW_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPRAW: BWERR0T (Bitfield-Mask: 0x01) */ 5849 #define SCU_TRAP_TRAPRAW_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPRAW: BWERR1T (Bit 8) */ 5850 #define SCU_TRAP_TRAPRAW_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPRAW: BWERR1T (Bitfield-Mask: 0x01) */ 5851 5852 /* ------------------------------ SCU_TRAP_TRAPDIS ------------------------------ */ 5853 #define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPDIS: SOSCWDGT (Bit 0) */ 5854 #define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPDIS: SOSCWDGT (Bitfield-Mask: 0x01) */ 5855 #define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPDIS: SVCOLCKT (Bit 2) */ 5856 #define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPDIS: SVCOLCKT (Bitfield-Mask: 0x01) */ 5857 #define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPDIS: UVCOLCKT (Bit 3) */ 5858 #define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPDIS: UVCOLCKT (Bitfield-Mask: 0x01) */ 5859 #define SCU_TRAP_TRAPDIS_PET_Pos (4UL) /*!< SCU_TRAP TRAPDIS: PET (Bit 4) */ 5860 #define SCU_TRAP_TRAPDIS_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPDIS: PET (Bitfield-Mask: 0x01) */ 5861 #define SCU_TRAP_TRAPDIS_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPDIS: BRWNT (Bit 5) */ 5862 #define SCU_TRAP_TRAPDIS_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPDIS: BRWNT (Bitfield-Mask: 0x01) */ 5863 #define SCU_TRAP_TRAPDIS_ULPWDGT_Pos (6UL) /*!< SCU_TRAP TRAPDIS: ULPWDGT (Bit 6) */ 5864 #define SCU_TRAP_TRAPDIS_ULPWDGT_Msk (0x40UL) /*!< SCU_TRAP TRAPDIS: ULPWDGT (Bitfield-Mask: 0x01) */ 5865 #define SCU_TRAP_TRAPDIS_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPDIS: BWERR0T (Bit 7) */ 5866 #define SCU_TRAP_TRAPDIS_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPDIS: BWERR0T (Bitfield-Mask: 0x01) */ 5867 #define SCU_TRAP_TRAPDIS_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPDIS: BWERR1T (Bit 8) */ 5868 #define SCU_TRAP_TRAPDIS_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPDIS: BWERR1T (Bitfield-Mask: 0x01) */ 5869 5870 /* ------------------------------ SCU_TRAP_TRAPCLR ------------------------------ */ 5871 #define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPCLR: SOSCWDGT (Bit 0) */ 5872 #define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPCLR: SOSCWDGT (Bitfield-Mask: 0x01) */ 5873 #define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPCLR: SVCOLCKT (Bit 2) */ 5874 #define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPCLR: SVCOLCKT (Bitfield-Mask: 0x01) */ 5875 #define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPCLR: UVCOLCKT (Bit 3) */ 5876 #define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPCLR: UVCOLCKT (Bitfield-Mask: 0x01) */ 5877 #define SCU_TRAP_TRAPCLR_PET_Pos (4UL) /*!< SCU_TRAP TRAPCLR: PET (Bit 4) */ 5878 #define SCU_TRAP_TRAPCLR_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPCLR: PET (Bitfield-Mask: 0x01) */ 5879 #define SCU_TRAP_TRAPCLR_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPCLR: BRWNT (Bit 5) */ 5880 #define SCU_TRAP_TRAPCLR_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPCLR: BRWNT (Bitfield-Mask: 0x01) */ 5881 #define SCU_TRAP_TRAPCLR_ULPWDGT_Pos (6UL) /*!< SCU_TRAP TRAPCLR: ULPWDGT (Bit 6) */ 5882 #define SCU_TRAP_TRAPCLR_ULPWDGT_Msk (0x40UL) /*!< SCU_TRAP TRAPCLR: ULPWDGT (Bitfield-Mask: 0x01) */ 5883 #define SCU_TRAP_TRAPCLR_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPCLR: BWERR0T (Bit 7) */ 5884 #define SCU_TRAP_TRAPCLR_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPCLR: BWERR0T (Bitfield-Mask: 0x01) */ 5885 #define SCU_TRAP_TRAPCLR_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPCLR: BWERR1T (Bit 8) */ 5886 #define SCU_TRAP_TRAPCLR_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPCLR: BWERR1T (Bitfield-Mask: 0x01) */ 5887 5888 /* ------------------------------ SCU_TRAP_TRAPSET ------------------------------ */ 5889 #define SCU_TRAP_TRAPSET_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPSET: SOSCWDGT (Bit 0) */ 5890 #define SCU_TRAP_TRAPSET_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPSET: SOSCWDGT (Bitfield-Mask: 0x01) */ 5891 #define SCU_TRAP_TRAPSET_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPSET: SVCOLCKT (Bit 2) */ 5892 #define SCU_TRAP_TRAPSET_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPSET: SVCOLCKT (Bitfield-Mask: 0x01) */ 5893 #define SCU_TRAP_TRAPSET_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPSET: UVCOLCKT (Bit 3) */ 5894 #define SCU_TRAP_TRAPSET_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPSET: UVCOLCKT (Bitfield-Mask: 0x01) */ 5895 #define SCU_TRAP_TRAPSET_PET_Pos (4UL) /*!< SCU_TRAP TRAPSET: PET (Bit 4) */ 5896 #define SCU_TRAP_TRAPSET_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPSET: PET (Bitfield-Mask: 0x01) */ 5897 #define SCU_TRAP_TRAPSET_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPSET: BRWNT (Bit 5) */ 5898 #define SCU_TRAP_TRAPSET_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPSET: BRWNT (Bitfield-Mask: 0x01) */ 5899 #define SCU_TRAP_TRAPSET_ULPWDT_Pos (6UL) /*!< SCU_TRAP TRAPSET: ULPWDT (Bit 6) */ 5900 #define SCU_TRAP_TRAPSET_ULPWDT_Msk (0x40UL) /*!< SCU_TRAP TRAPSET: ULPWDT (Bitfield-Mask: 0x01) */ 5901 #define SCU_TRAP_TRAPSET_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPSET: BWERR0T (Bit 7) */ 5902 #define SCU_TRAP_TRAPSET_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPSET: BWERR0T (Bitfield-Mask: 0x01) */ 5903 #define SCU_TRAP_TRAPSET_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPSET: BWERR1T (Bit 8) */ 5904 #define SCU_TRAP_TRAPSET_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPSET: BWERR1T (Bitfield-Mask: 0x01) */ 5905 5906 5907 /* ================================================================================ */ 5908 /* ================ struct 'SCU_HIBERNATE' Position & Mask ================ */ 5909 /* ================================================================================ */ 5910 5911 5912 /* ---------------------------- SCU_HIBERNATE_HDSTAT ---------------------------- */ 5913 #define SCU_HIBERNATE_HDSTAT_EPEV_Pos (0UL) /*!< SCU_HIBERNATE HDSTAT: EPEV (Bit 0) */ 5914 #define SCU_HIBERNATE_HDSTAT_EPEV_Msk (0x1UL) /*!< SCU_HIBERNATE HDSTAT: EPEV (Bitfield-Mask: 0x01) */ 5915 #define SCU_HIBERNATE_HDSTAT_ENEV_Pos (1UL) /*!< SCU_HIBERNATE HDSTAT: ENEV (Bit 1) */ 5916 #define SCU_HIBERNATE_HDSTAT_ENEV_Msk (0x2UL) /*!< SCU_HIBERNATE HDSTAT: ENEV (Bitfield-Mask: 0x01) */ 5917 #define SCU_HIBERNATE_HDSTAT_RTCEV_Pos (2UL) /*!< SCU_HIBERNATE HDSTAT: RTCEV (Bit 2) */ 5918 #define SCU_HIBERNATE_HDSTAT_RTCEV_Msk (0x4UL) /*!< SCU_HIBERNATE HDSTAT: RTCEV (Bitfield-Mask: 0x01) */ 5919 #define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos (3UL) /*!< SCU_HIBERNATE HDSTAT: ULPWDG (Bit 3) */ 5920 #define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk (0x8UL) /*!< SCU_HIBERNATE HDSTAT: ULPWDG (Bitfield-Mask: 0x01) */ 5921 #define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos (4UL) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT (Bit 4) */ 5922 #define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk (0x10UL) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT (Bitfield-Mask: 0x01) */ 5923 5924 /* ----------------------------- SCU_HIBERNATE_HDCLR ---------------------------- */ 5925 #define SCU_HIBERNATE_HDCLR_EPEV_Pos (0UL) /*!< SCU_HIBERNATE HDCLR: EPEV (Bit 0) */ 5926 #define SCU_HIBERNATE_HDCLR_EPEV_Msk (0x1UL) /*!< SCU_HIBERNATE HDCLR: EPEV (Bitfield-Mask: 0x01) */ 5927 #define SCU_HIBERNATE_HDCLR_ENEV_Pos (1UL) /*!< SCU_HIBERNATE HDCLR: ENEV (Bit 1) */ 5928 #define SCU_HIBERNATE_HDCLR_ENEV_Msk (0x2UL) /*!< SCU_HIBERNATE HDCLR: ENEV (Bitfield-Mask: 0x01) */ 5929 #define SCU_HIBERNATE_HDCLR_RTCEV_Pos (2UL) /*!< SCU_HIBERNATE HDCLR: RTCEV (Bit 2) */ 5930 #define SCU_HIBERNATE_HDCLR_RTCEV_Msk (0x4UL) /*!< SCU_HIBERNATE HDCLR: RTCEV (Bitfield-Mask: 0x01) */ 5931 #define SCU_HIBERNATE_HDCLR_ULPWDG_Pos (3UL) /*!< SCU_HIBERNATE HDCLR: ULPWDG (Bit 3) */ 5932 #define SCU_HIBERNATE_HDCLR_ULPWDG_Msk (0x8UL) /*!< SCU_HIBERNATE HDCLR: ULPWDG (Bitfield-Mask: 0x01) */ 5933 5934 /* ----------------------------- SCU_HIBERNATE_HDSET ---------------------------- */ 5935 #define SCU_HIBERNATE_HDSET_EPEV_Pos (0UL) /*!< SCU_HIBERNATE HDSET: EPEV (Bit 0) */ 5936 #define SCU_HIBERNATE_HDSET_EPEV_Msk (0x1UL) /*!< SCU_HIBERNATE HDSET: EPEV (Bitfield-Mask: 0x01) */ 5937 #define SCU_HIBERNATE_HDSET_ENEV_Pos (1UL) /*!< SCU_HIBERNATE HDSET: ENEV (Bit 1) */ 5938 #define SCU_HIBERNATE_HDSET_ENEV_Msk (0x2UL) /*!< SCU_HIBERNATE HDSET: ENEV (Bitfield-Mask: 0x01) */ 5939 #define SCU_HIBERNATE_HDSET_RTCEV_Pos (2UL) /*!< SCU_HIBERNATE HDSET: RTCEV (Bit 2) */ 5940 #define SCU_HIBERNATE_HDSET_RTCEV_Msk (0x4UL) /*!< SCU_HIBERNATE HDSET: RTCEV (Bitfield-Mask: 0x01) */ 5941 #define SCU_HIBERNATE_HDSET_ULPWDG_Pos (3UL) /*!< SCU_HIBERNATE HDSET: ULPWDG (Bit 3) */ 5942 #define SCU_HIBERNATE_HDSET_ULPWDG_Msk (0x8UL) /*!< SCU_HIBERNATE HDSET: ULPWDG (Bitfield-Mask: 0x01) */ 5943 5944 /* ----------------------------- SCU_HIBERNATE_HDCR ----------------------------- */ 5945 #define SCU_HIBERNATE_HDCR_WKPEP_Pos (0UL) /*!< SCU_HIBERNATE HDCR: WKPEP (Bit 0) */ 5946 #define SCU_HIBERNATE_HDCR_WKPEP_Msk (0x1UL) /*!< SCU_HIBERNATE HDCR: WKPEP (Bitfield-Mask: 0x01) */ 5947 #define SCU_HIBERNATE_HDCR_WKPEN_Pos (1UL) /*!< SCU_HIBERNATE HDCR: WKPEN (Bit 1) */ 5948 #define SCU_HIBERNATE_HDCR_WKPEN_Msk (0x2UL) /*!< SCU_HIBERNATE HDCR: WKPEN (Bitfield-Mask: 0x01) */ 5949 #define SCU_HIBERNATE_HDCR_RTCE_Pos (2UL) /*!< SCU_HIBERNATE HDCR: RTCE (Bit 2) */ 5950 #define SCU_HIBERNATE_HDCR_RTCE_Msk (0x4UL) /*!< SCU_HIBERNATE HDCR: RTCE (Bitfield-Mask: 0x01) */ 5951 #define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos (3UL) /*!< SCU_HIBERNATE HDCR: ULPWDGEN (Bit 3) */ 5952 #define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk (0x8UL) /*!< SCU_HIBERNATE HDCR: ULPWDGEN (Bitfield-Mask: 0x01) */ 5953 #define SCU_HIBERNATE_HDCR_HIB_Pos (4UL) /*!< SCU_HIBERNATE HDCR: HIB (Bit 4) */ 5954 #define SCU_HIBERNATE_HDCR_HIB_Msk (0x10UL) /*!< SCU_HIBERNATE HDCR: HIB (Bitfield-Mask: 0x01) */ 5955 #define SCU_HIBERNATE_HDCR_RCS_Pos (6UL) /*!< SCU_HIBERNATE HDCR: RCS (Bit 6) */ 5956 #define SCU_HIBERNATE_HDCR_RCS_Msk (0x40UL) /*!< SCU_HIBERNATE HDCR: RCS (Bitfield-Mask: 0x01) */ 5957 #define SCU_HIBERNATE_HDCR_STDBYSEL_Pos (7UL) /*!< SCU_HIBERNATE HDCR: STDBYSEL (Bit 7) */ 5958 #define SCU_HIBERNATE_HDCR_STDBYSEL_Msk (0x80UL) /*!< SCU_HIBERNATE HDCR: STDBYSEL (Bitfield-Mask: 0x01) */ 5959 #define SCU_HIBERNATE_HDCR_WKUPSEL_Pos (8UL) /*!< SCU_HIBERNATE HDCR: WKUPSEL (Bit 8) */ 5960 #define SCU_HIBERNATE_HDCR_WKUPSEL_Msk (0x100UL) /*!< SCU_HIBERNATE HDCR: WKUPSEL (Bitfield-Mask: 0x01) */ 5961 #define SCU_HIBERNATE_HDCR_GPI0SEL_Pos (10UL) /*!< SCU_HIBERNATE HDCR: GPI0SEL (Bit 10) */ 5962 #define SCU_HIBERNATE_HDCR_GPI0SEL_Msk (0x400UL) /*!< SCU_HIBERNATE HDCR: GPI0SEL (Bitfield-Mask: 0x01) */ 5963 #define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos (12UL) /*!< SCU_HIBERNATE HDCR: HIBIO0POL (Bit 12) */ 5964 #define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk (0x1000UL) /*!< SCU_HIBERNATE HDCR: HIBIO0POL (Bitfield-Mask: 0x01) */ 5965 #define SCU_HIBERNATE_HDCR_HIBIO1POL_Pos (13UL) /*!< SCU_HIBERNATE HDCR: HIBIO1POL (Bit 13) */ 5966 #define SCU_HIBERNATE_HDCR_HIBIO1POL_Msk (0x2000UL) /*!< SCU_HIBERNATE HDCR: HIBIO1POL (Bitfield-Mask: 0x01) */ 5967 #define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos (16UL) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL (Bit 16) */ 5968 #define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk (0xf0000UL) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL (Bitfield-Mask: 0x0f) */ 5969 #define SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos (20UL) /*!< SCU_HIBERNATE HDCR: HIBIO1SEL (Bit 20) */ 5970 #define SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk (0xf00000UL) /*!< SCU_HIBERNATE HDCR: HIBIO1SEL (Bitfield-Mask: 0x0f) */ 5971 5972 /* --------------------------- SCU_HIBERNATE_OSCSICTRL -------------------------- */ 5973 #define SCU_HIBERNATE_OSCSICTRL_PWD_Pos (0UL) /*!< SCU_HIBERNATE OSCSICTRL: PWD (Bit 0) */ 5974 #define SCU_HIBERNATE_OSCSICTRL_PWD_Msk (0x1UL) /*!< SCU_HIBERNATE OSCSICTRL: PWD (Bitfield-Mask: 0x01) */ 5975 5976 /* --------------------------- SCU_HIBERNATE_OSCULSTAT -------------------------- */ 5977 #define SCU_HIBERNATE_OSCULSTAT_X1D_Pos (0UL) /*!< SCU_HIBERNATE OSCULSTAT: X1D (Bit 0) */ 5978 #define SCU_HIBERNATE_OSCULSTAT_X1D_Msk (0x1UL) /*!< SCU_HIBERNATE OSCULSTAT: X1D (Bitfield-Mask: 0x01) */ 5979 5980 /* --------------------------- SCU_HIBERNATE_OSCULCTRL -------------------------- */ 5981 #define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos (0UL) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN (Bit 0) */ 5982 #define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk (0x1UL) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN (Bitfield-Mask: 0x01) */ 5983 #define SCU_HIBERNATE_OSCULCTRL_MODE_Pos (4UL) /*!< SCU_HIBERNATE OSCULCTRL: MODE (Bit 4) */ 5984 #define SCU_HIBERNATE_OSCULCTRL_MODE_Msk (0x30UL) /*!< SCU_HIBERNATE OSCULCTRL: MODE (Bitfield-Mask: 0x03) */ 5985 5986 5987 /* ================================================================================ */ 5988 /* ================ struct 'SCU_POWER' Position & Mask ================ */ 5989 /* ================================================================================ */ 5990 5991 5992 /* ------------------------------ SCU_POWER_PWRSTAT ----------------------------- */ 5993 #define SCU_POWER_PWRSTAT_HIBEN_Pos (0UL) /*!< SCU_POWER PWRSTAT: HIBEN (Bit 0) */ 5994 #define SCU_POWER_PWRSTAT_HIBEN_Msk (0x1UL) /*!< SCU_POWER PWRSTAT: HIBEN (Bitfield-Mask: 0x01) */ 5995 #define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos (16UL) /*!< SCU_POWER PWRSTAT: USBPHYPDQ (Bit 16) */ 5996 #define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk (0x10000UL) /*!< SCU_POWER PWRSTAT: USBPHYPDQ (Bitfield-Mask: 0x01) */ 5997 #define SCU_POWER_PWRSTAT_USBOTGEN_Pos (17UL) /*!< SCU_POWER PWRSTAT: USBOTGEN (Bit 17) */ 5998 #define SCU_POWER_PWRSTAT_USBOTGEN_Msk (0x20000UL) /*!< SCU_POWER PWRSTAT: USBOTGEN (Bitfield-Mask: 0x01) */ 5999 #define SCU_POWER_PWRSTAT_USBPUWQ_Pos (18UL) /*!< SCU_POWER PWRSTAT: USBPUWQ (Bit 18) */ 6000 #define SCU_POWER_PWRSTAT_USBPUWQ_Msk (0x40000UL) /*!< SCU_POWER PWRSTAT: USBPUWQ (Bitfield-Mask: 0x01) */ 6001 6002 /* ------------------------------ SCU_POWER_PWRSET ------------------------------ */ 6003 #define SCU_POWER_PWRSET_HIB_Pos (0UL) /*!< SCU_POWER PWRSET: HIB (Bit 0) */ 6004 #define SCU_POWER_PWRSET_HIB_Msk (0x1UL) /*!< SCU_POWER PWRSET: HIB (Bitfield-Mask: 0x01) */ 6005 #define SCU_POWER_PWRSET_USBPHYPDQ_Pos (16UL) /*!< SCU_POWER PWRSET: USBPHYPDQ (Bit 16) */ 6006 #define SCU_POWER_PWRSET_USBPHYPDQ_Msk (0x10000UL) /*!< SCU_POWER PWRSET: USBPHYPDQ (Bitfield-Mask: 0x01) */ 6007 #define SCU_POWER_PWRSET_USBOTGEN_Pos (17UL) /*!< SCU_POWER PWRSET: USBOTGEN (Bit 17) */ 6008 #define SCU_POWER_PWRSET_USBOTGEN_Msk (0x20000UL) /*!< SCU_POWER PWRSET: USBOTGEN (Bitfield-Mask: 0x01) */ 6009 #define SCU_POWER_PWRSET_USBPUWQ_Pos (18UL) /*!< SCU_POWER PWRSET: USBPUWQ (Bit 18) */ 6010 #define SCU_POWER_PWRSET_USBPUWQ_Msk (0x40000UL) /*!< SCU_POWER PWRSET: USBPUWQ (Bitfield-Mask: 0x01) */ 6011 6012 /* ------------------------------ SCU_POWER_PWRCLR ------------------------------ */ 6013 #define SCU_POWER_PWRCLR_HIB_Pos (0UL) /*!< SCU_POWER PWRCLR: HIB (Bit 0) */ 6014 #define SCU_POWER_PWRCLR_HIB_Msk (0x1UL) /*!< SCU_POWER PWRCLR: HIB (Bitfield-Mask: 0x01) */ 6015 #define SCU_POWER_PWRCLR_USBPHYPDQ_Pos (16UL) /*!< SCU_POWER PWRCLR: USBPHYPDQ (Bit 16) */ 6016 #define SCU_POWER_PWRCLR_USBPHYPDQ_Msk (0x10000UL) /*!< SCU_POWER PWRCLR: USBPHYPDQ (Bitfield-Mask: 0x01) */ 6017 #define SCU_POWER_PWRCLR_USBOTGEN_Pos (17UL) /*!< SCU_POWER PWRCLR: USBOTGEN (Bit 17) */ 6018 #define SCU_POWER_PWRCLR_USBOTGEN_Msk (0x20000UL) /*!< SCU_POWER PWRCLR: USBOTGEN (Bitfield-Mask: 0x01) */ 6019 #define SCU_POWER_PWRCLR_USBPUWQ_Pos (18UL) /*!< SCU_POWER PWRCLR: USBPUWQ (Bit 18) */ 6020 #define SCU_POWER_PWRCLR_USBPUWQ_Msk (0x40000UL) /*!< SCU_POWER PWRCLR: USBPUWQ (Bitfield-Mask: 0x01) */ 6021 6022 /* ------------------------------ SCU_POWER_EVRSTAT ----------------------------- */ 6023 #define SCU_POWER_EVRSTAT_OV13_Pos (1UL) /*!< SCU_POWER EVRSTAT: OV13 (Bit 1) */ 6024 #define SCU_POWER_EVRSTAT_OV13_Msk (0x2UL) /*!< SCU_POWER EVRSTAT: OV13 (Bitfield-Mask: 0x01) */ 6025 6026 /* ---------------------------- SCU_POWER_EVRVADCSTAT --------------------------- */ 6027 #define SCU_POWER_EVRVADCSTAT_VADC13V_Pos (0UL) /*!< SCU_POWER EVRVADCSTAT: VADC13V (Bit 0) */ 6028 #define SCU_POWER_EVRVADCSTAT_VADC13V_Msk (0xffUL) /*!< SCU_POWER EVRVADCSTAT: VADC13V (Bitfield-Mask: 0xff) */ 6029 #define SCU_POWER_EVRVADCSTAT_VADC33V_Pos (8UL) /*!< SCU_POWER EVRVADCSTAT: VADC33V (Bit 8) */ 6030 #define SCU_POWER_EVRVADCSTAT_VADC33V_Msk (0xff00UL) /*!< SCU_POWER EVRVADCSTAT: VADC33V (Bitfield-Mask: 0xff) */ 6031 6032 /* ------------------------------ SCU_POWER_PWRMON ------------------------------ */ 6033 #define SCU_POWER_PWRMON_THRS_Pos (0UL) /*!< SCU_POWER PWRMON: THRS (Bit 0) */ 6034 #define SCU_POWER_PWRMON_THRS_Msk (0xffUL) /*!< SCU_POWER PWRMON: THRS (Bitfield-Mask: 0xff) */ 6035 #define SCU_POWER_PWRMON_INTV_Pos (8UL) /*!< SCU_POWER PWRMON: INTV (Bit 8) */ 6036 #define SCU_POWER_PWRMON_INTV_Msk (0xff00UL) /*!< SCU_POWER PWRMON: INTV (Bitfield-Mask: 0xff) */ 6037 #define SCU_POWER_PWRMON_ENB_Pos (16UL) /*!< SCU_POWER PWRMON: ENB (Bit 16) */ 6038 #define SCU_POWER_PWRMON_ENB_Msk (0x10000UL) /*!< SCU_POWER PWRMON: ENB (Bitfield-Mask: 0x01) */ 6039 6040 6041 /* ================================================================================ */ 6042 /* ================ struct 'SCU_RESET' Position & Mask ================ */ 6043 /* ================================================================================ */ 6044 6045 6046 /* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */ 6047 #define SCU_RESET_RSTSTAT_RSTSTAT_Pos (0UL) /*!< SCU_RESET RSTSTAT: RSTSTAT (Bit 0) */ 6048 #define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0xffUL) /*!< SCU_RESET RSTSTAT: RSTSTAT (Bitfield-Mask: 0xff) */ 6049 #define SCU_RESET_RSTSTAT_HIBWK_Pos (8UL) /*!< SCU_RESET RSTSTAT: HIBWK (Bit 8) */ 6050 #define SCU_RESET_RSTSTAT_HIBWK_Msk (0x100UL) /*!< SCU_RESET RSTSTAT: HIBWK (Bitfield-Mask: 0x01) */ 6051 #define SCU_RESET_RSTSTAT_HIBRS_Pos (9UL) /*!< SCU_RESET RSTSTAT: HIBRS (Bit 9) */ 6052 #define SCU_RESET_RSTSTAT_HIBRS_Msk (0x200UL) /*!< SCU_RESET RSTSTAT: HIBRS (Bitfield-Mask: 0x01) */ 6053 #define SCU_RESET_RSTSTAT_LCKEN_Pos (10UL) /*!< SCU_RESET RSTSTAT: LCKEN (Bit 10) */ 6054 #define SCU_RESET_RSTSTAT_LCKEN_Msk (0x400UL) /*!< SCU_RESET RSTSTAT: LCKEN (Bitfield-Mask: 0x01) */ 6055 6056 /* ------------------------------ SCU_RESET_RSTSET ------------------------------ */ 6057 #define SCU_RESET_RSTSET_HIBWK_Pos (8UL) /*!< SCU_RESET RSTSET: HIBWK (Bit 8) */ 6058 #define SCU_RESET_RSTSET_HIBWK_Msk (0x100UL) /*!< SCU_RESET RSTSET: HIBWK (Bitfield-Mask: 0x01) */ 6059 #define SCU_RESET_RSTSET_HIBRS_Pos (9UL) /*!< SCU_RESET RSTSET: HIBRS (Bit 9) */ 6060 #define SCU_RESET_RSTSET_HIBRS_Msk (0x200UL) /*!< SCU_RESET RSTSET: HIBRS (Bitfield-Mask: 0x01) */ 6061 #define SCU_RESET_RSTSET_LCKEN_Pos (10UL) /*!< SCU_RESET RSTSET: LCKEN (Bit 10) */ 6062 #define SCU_RESET_RSTSET_LCKEN_Msk (0x400UL) /*!< SCU_RESET RSTSET: LCKEN (Bitfield-Mask: 0x01) */ 6063 6064 /* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */ 6065 #define SCU_RESET_RSTCLR_RSCLR_Pos (0UL) /*!< SCU_RESET RSTCLR: RSCLR (Bit 0) */ 6066 #define SCU_RESET_RSTCLR_RSCLR_Msk (0x1UL) /*!< SCU_RESET RSTCLR: RSCLR (Bitfield-Mask: 0x01) */ 6067 #define SCU_RESET_RSTCLR_HIBWK_Pos (8UL) /*!< SCU_RESET RSTCLR: HIBWK (Bit 8) */ 6068 #define SCU_RESET_RSTCLR_HIBWK_Msk (0x100UL) /*!< SCU_RESET RSTCLR: HIBWK (Bitfield-Mask: 0x01) */ 6069 #define SCU_RESET_RSTCLR_HIBRS_Pos (9UL) /*!< SCU_RESET RSTCLR: HIBRS (Bit 9) */ 6070 #define SCU_RESET_RSTCLR_HIBRS_Msk (0x200UL) /*!< SCU_RESET RSTCLR: HIBRS (Bitfield-Mask: 0x01) */ 6071 #define SCU_RESET_RSTCLR_LCKEN_Pos (10UL) /*!< SCU_RESET RSTCLR: LCKEN (Bit 10) */ 6072 #define SCU_RESET_RSTCLR_LCKEN_Msk (0x400UL) /*!< SCU_RESET RSTCLR: LCKEN (Bitfield-Mask: 0x01) */ 6073 6074 /* ------------------------------ SCU_RESET_PRSTAT0 ----------------------------- */ 6075 #define SCU_RESET_PRSTAT0_VADCRS_Pos (0UL) /*!< SCU_RESET PRSTAT0: VADCRS (Bit 0) */ 6076 #define SCU_RESET_PRSTAT0_VADCRS_Msk (0x1UL) /*!< SCU_RESET PRSTAT0: VADCRS (Bitfield-Mask: 0x01) */ 6077 #define SCU_RESET_PRSTAT0_DSDRS_Pos (1UL) /*!< SCU_RESET PRSTAT0: DSDRS (Bit 1) */ 6078 #define SCU_RESET_PRSTAT0_DSDRS_Msk (0x2UL) /*!< SCU_RESET PRSTAT0: DSDRS (Bitfield-Mask: 0x01) */ 6079 #define SCU_RESET_PRSTAT0_CCU40RS_Pos (2UL) /*!< SCU_RESET PRSTAT0: CCU40RS (Bit 2) */ 6080 #define SCU_RESET_PRSTAT0_CCU40RS_Msk (0x4UL) /*!< SCU_RESET PRSTAT0: CCU40RS (Bitfield-Mask: 0x01) */ 6081 #define SCU_RESET_PRSTAT0_CCU41RS_Pos (3UL) /*!< SCU_RESET PRSTAT0: CCU41RS (Bit 3) */ 6082 #define SCU_RESET_PRSTAT0_CCU41RS_Msk (0x8UL) /*!< SCU_RESET PRSTAT0: CCU41RS (Bitfield-Mask: 0x01) */ 6083 #define SCU_RESET_PRSTAT0_CCU42RS_Pos (4UL) /*!< SCU_RESET PRSTAT0: CCU42RS (Bit 4) */ 6084 #define SCU_RESET_PRSTAT0_CCU42RS_Msk (0x10UL) /*!< SCU_RESET PRSTAT0: CCU42RS (Bitfield-Mask: 0x01) */ 6085 #define SCU_RESET_PRSTAT0_CCU80RS_Pos (7UL) /*!< SCU_RESET PRSTAT0: CCU80RS (Bit 7) */ 6086 #define SCU_RESET_PRSTAT0_CCU80RS_Msk (0x80UL) /*!< SCU_RESET PRSTAT0: CCU80RS (Bitfield-Mask: 0x01) */ 6087 #define SCU_RESET_PRSTAT0_CCU81RS_Pos (8UL) /*!< SCU_RESET PRSTAT0: CCU81RS (Bit 8) */ 6088 #define SCU_RESET_PRSTAT0_CCU81RS_Msk (0x100UL) /*!< SCU_RESET PRSTAT0: CCU81RS (Bitfield-Mask: 0x01) */ 6089 #define SCU_RESET_PRSTAT0_POSIF0RS_Pos (9UL) /*!< SCU_RESET PRSTAT0: POSIF0RS (Bit 9) */ 6090 #define SCU_RESET_PRSTAT0_POSIF0RS_Msk (0x200UL) /*!< SCU_RESET PRSTAT0: POSIF0RS (Bitfield-Mask: 0x01) */ 6091 #define SCU_RESET_PRSTAT0_POSIF1RS_Pos (10UL) /*!< SCU_RESET PRSTAT0: POSIF1RS (Bit 10) */ 6092 #define SCU_RESET_PRSTAT0_POSIF1RS_Msk (0x400UL) /*!< SCU_RESET PRSTAT0: POSIF1RS (Bitfield-Mask: 0x01) */ 6093 #define SCU_RESET_PRSTAT0_USIC0RS_Pos (11UL) /*!< SCU_RESET PRSTAT0: USIC0RS (Bit 11) */ 6094 #define SCU_RESET_PRSTAT0_USIC0RS_Msk (0x800UL) /*!< SCU_RESET PRSTAT0: USIC0RS (Bitfield-Mask: 0x01) */ 6095 #define SCU_RESET_PRSTAT0_ERU1RS_Pos (16UL) /*!< SCU_RESET PRSTAT0: ERU1RS (Bit 16) */ 6096 #define SCU_RESET_PRSTAT0_ERU1RS_Msk (0x10000UL) /*!< SCU_RESET PRSTAT0: ERU1RS (Bitfield-Mask: 0x01) */ 6097 6098 /* ------------------------------ SCU_RESET_PRSET0 ------------------------------ */ 6099 #define SCU_RESET_PRSET0_VADCRS_Pos (0UL) /*!< SCU_RESET PRSET0: VADCRS (Bit 0) */ 6100 #define SCU_RESET_PRSET0_VADCRS_Msk (0x1UL) /*!< SCU_RESET PRSET0: VADCRS (Bitfield-Mask: 0x01) */ 6101 #define SCU_RESET_PRSET0_DSDRS_Pos (1UL) /*!< SCU_RESET PRSET0: DSDRS (Bit 1) */ 6102 #define SCU_RESET_PRSET0_DSDRS_Msk (0x2UL) /*!< SCU_RESET PRSET0: DSDRS (Bitfield-Mask: 0x01) */ 6103 #define SCU_RESET_PRSET0_CCU40RS_Pos (2UL) /*!< SCU_RESET PRSET0: CCU40RS (Bit 2) */ 6104 #define SCU_RESET_PRSET0_CCU40RS_Msk (0x4UL) /*!< SCU_RESET PRSET0: CCU40RS (Bitfield-Mask: 0x01) */ 6105 #define SCU_RESET_PRSET0_CCU41RS_Pos (3UL) /*!< SCU_RESET PRSET0: CCU41RS (Bit 3) */ 6106 #define SCU_RESET_PRSET0_CCU41RS_Msk (0x8UL) /*!< SCU_RESET PRSET0: CCU41RS (Bitfield-Mask: 0x01) */ 6107 #define SCU_RESET_PRSET0_CCU42RS_Pos (4UL) /*!< SCU_RESET PRSET0: CCU42RS (Bit 4) */ 6108 #define SCU_RESET_PRSET0_CCU42RS_Msk (0x10UL) /*!< SCU_RESET PRSET0: CCU42RS (Bitfield-Mask: 0x01) */ 6109 #define SCU_RESET_PRSET0_CCU80RS_Pos (7UL) /*!< SCU_RESET PRSET0: CCU80RS (Bit 7) */ 6110 #define SCU_RESET_PRSET0_CCU80RS_Msk (0x80UL) /*!< SCU_RESET PRSET0: CCU80RS (Bitfield-Mask: 0x01) */ 6111 #define SCU_RESET_PRSET0_CCU81RS_Pos (8UL) /*!< SCU_RESET PRSET0: CCU81RS (Bit 8) */ 6112 #define SCU_RESET_PRSET0_CCU81RS_Msk (0x100UL) /*!< SCU_RESET PRSET0: CCU81RS (Bitfield-Mask: 0x01) */ 6113 #define SCU_RESET_PRSET0_POSIF0RS_Pos (9UL) /*!< SCU_RESET PRSET0: POSIF0RS (Bit 9) */ 6114 #define SCU_RESET_PRSET0_POSIF0RS_Msk (0x200UL) /*!< SCU_RESET PRSET0: POSIF0RS (Bitfield-Mask: 0x01) */ 6115 #define SCU_RESET_PRSET0_POSIF1RS_Pos (10UL) /*!< SCU_RESET PRSET0: POSIF1RS (Bit 10) */ 6116 #define SCU_RESET_PRSET0_POSIF1RS_Msk (0x400UL) /*!< SCU_RESET PRSET0: POSIF1RS (Bitfield-Mask: 0x01) */ 6117 #define SCU_RESET_PRSET0_USIC0RS_Pos (11UL) /*!< SCU_RESET PRSET0: USIC0RS (Bit 11) */ 6118 #define SCU_RESET_PRSET0_USIC0RS_Msk (0x800UL) /*!< SCU_RESET PRSET0: USIC0RS (Bitfield-Mask: 0x01) */ 6119 #define SCU_RESET_PRSET0_ERU1RS_Pos (16UL) /*!< SCU_RESET PRSET0: ERU1RS (Bit 16) */ 6120 #define SCU_RESET_PRSET0_ERU1RS_Msk (0x10000UL) /*!< SCU_RESET PRSET0: ERU1RS (Bitfield-Mask: 0x01) */ 6121 6122 /* ------------------------------ SCU_RESET_PRCLR0 ------------------------------ */ 6123 #define SCU_RESET_PRCLR0_VADCRS_Pos (0UL) /*!< SCU_RESET PRCLR0: VADCRS (Bit 0) */ 6124 #define SCU_RESET_PRCLR0_VADCRS_Msk (0x1UL) /*!< SCU_RESET PRCLR0: VADCRS (Bitfield-Mask: 0x01) */ 6125 #define SCU_RESET_PRCLR0_DSDRS_Pos (1UL) /*!< SCU_RESET PRCLR0: DSDRS (Bit 1) */ 6126 #define SCU_RESET_PRCLR0_DSDRS_Msk (0x2UL) /*!< SCU_RESET PRCLR0: DSDRS (Bitfield-Mask: 0x01) */ 6127 #define SCU_RESET_PRCLR0_CCU40RS_Pos (2UL) /*!< SCU_RESET PRCLR0: CCU40RS (Bit 2) */ 6128 #define SCU_RESET_PRCLR0_CCU40RS_Msk (0x4UL) /*!< SCU_RESET PRCLR0: CCU40RS (Bitfield-Mask: 0x01) */ 6129 #define SCU_RESET_PRCLR0_CCU41RS_Pos (3UL) /*!< SCU_RESET PRCLR0: CCU41RS (Bit 3) */ 6130 #define SCU_RESET_PRCLR0_CCU41RS_Msk (0x8UL) /*!< SCU_RESET PRCLR0: CCU41RS (Bitfield-Mask: 0x01) */ 6131 #define SCU_RESET_PRCLR0_CCU42RS_Pos (4UL) /*!< SCU_RESET PRCLR0: CCU42RS (Bit 4) */ 6132 #define SCU_RESET_PRCLR0_CCU42RS_Msk (0x10UL) /*!< SCU_RESET PRCLR0: CCU42RS (Bitfield-Mask: 0x01) */ 6133 #define SCU_RESET_PRCLR0_CCU80RS_Pos (7UL) /*!< SCU_RESET PRCLR0: CCU80RS (Bit 7) */ 6134 #define SCU_RESET_PRCLR0_CCU80RS_Msk (0x80UL) /*!< SCU_RESET PRCLR0: CCU80RS (Bitfield-Mask: 0x01) */ 6135 #define SCU_RESET_PRCLR0_CCU81RS_Pos (8UL) /*!< SCU_RESET PRCLR0: CCU81RS (Bit 8) */ 6136 #define SCU_RESET_PRCLR0_CCU81RS_Msk (0x100UL) /*!< SCU_RESET PRCLR0: CCU81RS (Bitfield-Mask: 0x01) */ 6137 #define SCU_RESET_PRCLR0_POSIF0RS_Pos (9UL) /*!< SCU_RESET PRCLR0: POSIF0RS (Bit 9) */ 6138 #define SCU_RESET_PRCLR0_POSIF0RS_Msk (0x200UL) /*!< SCU_RESET PRCLR0: POSIF0RS (Bitfield-Mask: 0x01) */ 6139 #define SCU_RESET_PRCLR0_POSIF1RS_Pos (10UL) /*!< SCU_RESET PRCLR0: POSIF1RS (Bit 10) */ 6140 #define SCU_RESET_PRCLR0_POSIF1RS_Msk (0x400UL) /*!< SCU_RESET PRCLR0: POSIF1RS (Bitfield-Mask: 0x01) */ 6141 #define SCU_RESET_PRCLR0_USIC0RS_Pos (11UL) /*!< SCU_RESET PRCLR0: USIC0RS (Bit 11) */ 6142 #define SCU_RESET_PRCLR0_USIC0RS_Msk (0x800UL) /*!< SCU_RESET PRCLR0: USIC0RS (Bitfield-Mask: 0x01) */ 6143 #define SCU_RESET_PRCLR0_ERU1RS_Pos (16UL) /*!< SCU_RESET PRCLR0: ERU1RS (Bit 16) */ 6144 #define SCU_RESET_PRCLR0_ERU1RS_Msk (0x10000UL) /*!< SCU_RESET PRCLR0: ERU1RS (Bitfield-Mask: 0x01) */ 6145 6146 /* ------------------------------ SCU_RESET_PRSTAT1 ----------------------------- */ 6147 #define SCU_RESET_PRSTAT1_CCU43RS_Pos (0UL) /*!< SCU_RESET PRSTAT1: CCU43RS (Bit 0) */ 6148 #define SCU_RESET_PRSTAT1_CCU43RS_Msk (0x1UL) /*!< SCU_RESET PRSTAT1: CCU43RS (Bitfield-Mask: 0x01) */ 6149 #define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos (3UL) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS (Bit 3) */ 6150 #define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk (0x8UL) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ 6151 #define SCU_RESET_PRSTAT1_MCAN0RS_Pos (4UL) /*!< SCU_RESET PRSTAT1: MCAN0RS (Bit 4) */ 6152 #define SCU_RESET_PRSTAT1_MCAN0RS_Msk (0x10UL) /*!< SCU_RESET PRSTAT1: MCAN0RS (Bitfield-Mask: 0x01) */ 6153 #define SCU_RESET_PRSTAT1_DACRS_Pos (5UL) /*!< SCU_RESET PRSTAT1: DACRS (Bit 5) */ 6154 #define SCU_RESET_PRSTAT1_DACRS_Msk (0x20UL) /*!< SCU_RESET PRSTAT1: DACRS (Bitfield-Mask: 0x01) */ 6155 #define SCU_RESET_PRSTAT1_MMCIRS_Pos (6UL) /*!< SCU_RESET PRSTAT1: MMCIRS (Bit 6) */ 6156 #define SCU_RESET_PRSTAT1_MMCIRS_Msk (0x40UL) /*!< SCU_RESET PRSTAT1: MMCIRS (Bitfield-Mask: 0x01) */ 6157 #define SCU_RESET_PRSTAT1_USIC1RS_Pos (7UL) /*!< SCU_RESET PRSTAT1: USIC1RS (Bit 7) */ 6158 #define SCU_RESET_PRSTAT1_USIC1RS_Msk (0x80UL) /*!< SCU_RESET PRSTAT1: USIC1RS (Bitfield-Mask: 0x01) */ 6159 #define SCU_RESET_PRSTAT1_USIC2RS_Pos (8UL) /*!< SCU_RESET PRSTAT1: USIC2RS (Bit 8) */ 6160 #define SCU_RESET_PRSTAT1_USIC2RS_Msk (0x100UL) /*!< SCU_RESET PRSTAT1: USIC2RS (Bitfield-Mask: 0x01) */ 6161 #define SCU_RESET_PRSTAT1_PPORTSRS_Pos (9UL) /*!< SCU_RESET PRSTAT1: PPORTSRS (Bit 9) */ 6162 #define SCU_RESET_PRSTAT1_PPORTSRS_Msk (0x200UL) /*!< SCU_RESET PRSTAT1: PPORTSRS (Bitfield-Mask: 0x01) */ 6163 6164 /* ------------------------------ SCU_RESET_PRSET1 ------------------------------ */ 6165 #define SCU_RESET_PRSET1_CCU43RS_Pos (0UL) /*!< SCU_RESET PRSET1: CCU43RS (Bit 0) */ 6166 #define SCU_RESET_PRSET1_CCU43RS_Msk (0x1UL) /*!< SCU_RESET PRSET1: CCU43RS (Bitfield-Mask: 0x01) */ 6167 #define SCU_RESET_PRSET1_LEDTSCU0RS_Pos (3UL) /*!< SCU_RESET PRSET1: LEDTSCU0RS (Bit 3) */ 6168 #define SCU_RESET_PRSET1_LEDTSCU0RS_Msk (0x8UL) /*!< SCU_RESET PRSET1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ 6169 #define SCU_RESET_PRSET1_MCAN0RS_Pos (4UL) /*!< SCU_RESET PRSET1: MCAN0RS (Bit 4) */ 6170 #define SCU_RESET_PRSET1_MCAN0RS_Msk (0x10UL) /*!< SCU_RESET PRSET1: MCAN0RS (Bitfield-Mask: 0x01) */ 6171 #define SCU_RESET_PRSET1_DACRS_Pos (5UL) /*!< SCU_RESET PRSET1: DACRS (Bit 5) */ 6172 #define SCU_RESET_PRSET1_DACRS_Msk (0x20UL) /*!< SCU_RESET PRSET1: DACRS (Bitfield-Mask: 0x01) */ 6173 #define SCU_RESET_PRSET1_MMCIRS_Pos (6UL) /*!< SCU_RESET PRSET1: MMCIRS (Bit 6) */ 6174 #define SCU_RESET_PRSET1_MMCIRS_Msk (0x40UL) /*!< SCU_RESET PRSET1: MMCIRS (Bitfield-Mask: 0x01) */ 6175 #define SCU_RESET_PRSET1_USIC1RS_Pos (7UL) /*!< SCU_RESET PRSET1: USIC1RS (Bit 7) */ 6176 #define SCU_RESET_PRSET1_USIC1RS_Msk (0x80UL) /*!< SCU_RESET PRSET1: USIC1RS (Bitfield-Mask: 0x01) */ 6177 #define SCU_RESET_PRSET1_USIC2RS_Pos (8UL) /*!< SCU_RESET PRSET1: USIC2RS (Bit 8) */ 6178 #define SCU_RESET_PRSET1_USIC2RS_Msk (0x100UL) /*!< SCU_RESET PRSET1: USIC2RS (Bitfield-Mask: 0x01) */ 6179 #define SCU_RESET_PRSET1_PPORTSRS_Pos (9UL) /*!< SCU_RESET PRSET1: PPORTSRS (Bit 9) */ 6180 #define SCU_RESET_PRSET1_PPORTSRS_Msk (0x200UL) /*!< SCU_RESET PRSET1: PPORTSRS (Bitfield-Mask: 0x01) */ 6181 6182 /* ------------------------------ SCU_RESET_PRCLR1 ------------------------------ */ 6183 #define SCU_RESET_PRCLR1_CCU43RS_Pos (0UL) /*!< SCU_RESET PRCLR1: CCU43RS (Bit 0) */ 6184 #define SCU_RESET_PRCLR1_CCU43RS_Msk (0x1UL) /*!< SCU_RESET PRCLR1: CCU43RS (Bitfield-Mask: 0x01) */ 6185 #define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos (3UL) /*!< SCU_RESET PRCLR1: LEDTSCU0RS (Bit 3) */ 6186 #define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk (0x8UL) /*!< SCU_RESET PRCLR1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ 6187 #define SCU_RESET_PRCLR1_MCAN0RS_Pos (4UL) /*!< SCU_RESET PRCLR1: MCAN0RS (Bit 4) */ 6188 #define SCU_RESET_PRCLR1_MCAN0RS_Msk (0x10UL) /*!< SCU_RESET PRCLR1: MCAN0RS (Bitfield-Mask: 0x01) */ 6189 #define SCU_RESET_PRCLR1_DACRS_Pos (5UL) /*!< SCU_RESET PRCLR1: DACRS (Bit 5) */ 6190 #define SCU_RESET_PRCLR1_DACRS_Msk (0x20UL) /*!< SCU_RESET PRCLR1: DACRS (Bitfield-Mask: 0x01) */ 6191 #define SCU_RESET_PRCLR1_MMCIRS_Pos (6UL) /*!< SCU_RESET PRCLR1: MMCIRS (Bit 6) */ 6192 #define SCU_RESET_PRCLR1_MMCIRS_Msk (0x40UL) /*!< SCU_RESET PRCLR1: MMCIRS (Bitfield-Mask: 0x01) */ 6193 #define SCU_RESET_PRCLR1_USIC1RS_Pos (7UL) /*!< SCU_RESET PRCLR1: USIC1RS (Bit 7) */ 6194 #define SCU_RESET_PRCLR1_USIC1RS_Msk (0x80UL) /*!< SCU_RESET PRCLR1: USIC1RS (Bitfield-Mask: 0x01) */ 6195 #define SCU_RESET_PRCLR1_USIC2RS_Pos (8UL) /*!< SCU_RESET PRCLR1: USIC2RS (Bit 8) */ 6196 #define SCU_RESET_PRCLR1_USIC2RS_Msk (0x100UL) /*!< SCU_RESET PRCLR1: USIC2RS (Bitfield-Mask: 0x01) */ 6197 #define SCU_RESET_PRCLR1_PPORTSRS_Pos (9UL) /*!< SCU_RESET PRCLR1: PPORTSRS (Bit 9) */ 6198 #define SCU_RESET_PRCLR1_PPORTSRS_Msk (0x200UL) /*!< SCU_RESET PRCLR1: PPORTSRS (Bitfield-Mask: 0x01) */ 6199 6200 /* ------------------------------ SCU_RESET_PRSTAT2 ----------------------------- */ 6201 #define SCU_RESET_PRSTAT2_WDTRS_Pos (1UL) /*!< SCU_RESET PRSTAT2: WDTRS (Bit 1) */ 6202 #define SCU_RESET_PRSTAT2_WDTRS_Msk (0x2UL) /*!< SCU_RESET PRSTAT2: WDTRS (Bitfield-Mask: 0x01) */ 6203 #define SCU_RESET_PRSTAT2_ETH0RS_Pos (2UL) /*!< SCU_RESET PRSTAT2: ETH0RS (Bit 2) */ 6204 #define SCU_RESET_PRSTAT2_ETH0RS_Msk (0x4UL) /*!< SCU_RESET PRSTAT2: ETH0RS (Bitfield-Mask: 0x01) */ 6205 #define SCU_RESET_PRSTAT2_DMA0RS_Pos (4UL) /*!< SCU_RESET PRSTAT2: DMA0RS (Bit 4) */ 6206 #define SCU_RESET_PRSTAT2_DMA0RS_Msk (0x10UL) /*!< SCU_RESET PRSTAT2: DMA0RS (Bitfield-Mask: 0x01) */ 6207 #define SCU_RESET_PRSTAT2_DMA1RS_Pos (5UL) /*!< SCU_RESET PRSTAT2: DMA1RS (Bit 5) */ 6208 #define SCU_RESET_PRSTAT2_DMA1RS_Msk (0x20UL) /*!< SCU_RESET PRSTAT2: DMA1RS (Bitfield-Mask: 0x01) */ 6209 #define SCU_RESET_PRSTAT2_FCERS_Pos (6UL) /*!< SCU_RESET PRSTAT2: FCERS (Bit 6) */ 6210 #define SCU_RESET_PRSTAT2_FCERS_Msk (0x40UL) /*!< SCU_RESET PRSTAT2: FCERS (Bitfield-Mask: 0x01) */ 6211 #define SCU_RESET_PRSTAT2_USBRS_Pos (7UL) /*!< SCU_RESET PRSTAT2: USBRS (Bit 7) */ 6212 #define SCU_RESET_PRSTAT2_USBRS_Msk (0x80UL) /*!< SCU_RESET PRSTAT2: USBRS (Bitfield-Mask: 0x01) */ 6213 6214 /* ------------------------------ SCU_RESET_PRSET2 ------------------------------ */ 6215 #define SCU_RESET_PRSET2_WDTRS_Pos (1UL) /*!< SCU_RESET PRSET2: WDTRS (Bit 1) */ 6216 #define SCU_RESET_PRSET2_WDTRS_Msk (0x2UL) /*!< SCU_RESET PRSET2: WDTRS (Bitfield-Mask: 0x01) */ 6217 #define SCU_RESET_PRSET2_ETH0RS_Pos (2UL) /*!< SCU_RESET PRSET2: ETH0RS (Bit 2) */ 6218 #define SCU_RESET_PRSET2_ETH0RS_Msk (0x4UL) /*!< SCU_RESET PRSET2: ETH0RS (Bitfield-Mask: 0x01) */ 6219 #define SCU_RESET_PRSET2_DMA0RS_Pos (4UL) /*!< SCU_RESET PRSET2: DMA0RS (Bit 4) */ 6220 #define SCU_RESET_PRSET2_DMA0RS_Msk (0x10UL) /*!< SCU_RESET PRSET2: DMA0RS (Bitfield-Mask: 0x01) */ 6221 #define SCU_RESET_PRSET2_DMA1RS_Pos (5UL) /*!< SCU_RESET PRSET2: DMA1RS (Bit 5) */ 6222 #define SCU_RESET_PRSET2_DMA1RS_Msk (0x20UL) /*!< SCU_RESET PRSET2: DMA1RS (Bitfield-Mask: 0x01) */ 6223 #define SCU_RESET_PRSET2_FCERS_Pos (6UL) /*!< SCU_RESET PRSET2: FCERS (Bit 6) */ 6224 #define SCU_RESET_PRSET2_FCERS_Msk (0x40UL) /*!< SCU_RESET PRSET2: FCERS (Bitfield-Mask: 0x01) */ 6225 #define SCU_RESET_PRSET2_USBRS_Pos (7UL) /*!< SCU_RESET PRSET2: USBRS (Bit 7) */ 6226 #define SCU_RESET_PRSET2_USBRS_Msk (0x80UL) /*!< SCU_RESET PRSET2: USBRS (Bitfield-Mask: 0x01) */ 6227 6228 /* ------------------------------ SCU_RESET_PRCLR2 ------------------------------ */ 6229 #define SCU_RESET_PRCLR2_WDTRS_Pos (1UL) /*!< SCU_RESET PRCLR2: WDTRS (Bit 1) */ 6230 #define SCU_RESET_PRCLR2_WDTRS_Msk (0x2UL) /*!< SCU_RESET PRCLR2: WDTRS (Bitfield-Mask: 0x01) */ 6231 #define SCU_RESET_PRCLR2_ETH0RS_Pos (2UL) /*!< SCU_RESET PRCLR2: ETH0RS (Bit 2) */ 6232 #define SCU_RESET_PRCLR2_ETH0RS_Msk (0x4UL) /*!< SCU_RESET PRCLR2: ETH0RS (Bitfield-Mask: 0x01) */ 6233 #define SCU_RESET_PRCLR2_DMA0RS_Pos (4UL) /*!< SCU_RESET PRCLR2: DMA0RS (Bit 4) */ 6234 #define SCU_RESET_PRCLR2_DMA0RS_Msk (0x10UL) /*!< SCU_RESET PRCLR2: DMA0RS (Bitfield-Mask: 0x01) */ 6235 #define SCU_RESET_PRCLR2_DMA1RS_Pos (5UL) /*!< SCU_RESET PRCLR2: DMA1RS (Bit 5) */ 6236 #define SCU_RESET_PRCLR2_DMA1RS_Msk (0x20UL) /*!< SCU_RESET PRCLR2: DMA1RS (Bitfield-Mask: 0x01) */ 6237 #define SCU_RESET_PRCLR2_FCERS_Pos (6UL) /*!< SCU_RESET PRCLR2: FCERS (Bit 6) */ 6238 #define SCU_RESET_PRCLR2_FCERS_Msk (0x40UL) /*!< SCU_RESET PRCLR2: FCERS (Bitfield-Mask: 0x01) */ 6239 #define SCU_RESET_PRCLR2_USBRS_Pos (7UL) /*!< SCU_RESET PRCLR2: USBRS (Bit 7) */ 6240 #define SCU_RESET_PRCLR2_USBRS_Msk (0x80UL) /*!< SCU_RESET PRCLR2: USBRS (Bitfield-Mask: 0x01) */ 6241 6242 /* ------------------------------ SCU_RESET_PRSTAT3 ----------------------------- */ 6243 #define SCU_RESET_PRSTAT3_EBURS_Pos (2UL) /*!< SCU_RESET PRSTAT3: EBURS (Bit 2) */ 6244 #define SCU_RESET_PRSTAT3_EBURS_Msk (0x4UL) /*!< SCU_RESET PRSTAT3: EBURS (Bitfield-Mask: 0x01) */ 6245 6246 /* ------------------------------ SCU_RESET_PRSET3 ------------------------------ */ 6247 #define SCU_RESET_PRSET3_EBURS_Pos (2UL) /*!< SCU_RESET PRSET3: EBURS (Bit 2) */ 6248 #define SCU_RESET_PRSET3_EBURS_Msk (0x4UL) /*!< SCU_RESET PRSET3: EBURS (Bitfield-Mask: 0x01) */ 6249 6250 /* ------------------------------ SCU_RESET_PRCLR3 ------------------------------ */ 6251 #define SCU_RESET_PRCLR3_EBURS_Pos (2UL) /*!< SCU_RESET PRCLR3: EBURS (Bit 2) */ 6252 #define SCU_RESET_PRCLR3_EBURS_Msk (0x4UL) /*!< SCU_RESET PRCLR3: EBURS (Bitfield-Mask: 0x01) */ 6253 6254 6255 /* ================================================================================ */ 6256 /* ================ Group 'LEDTS' Position & Mask ================ */ 6257 /* ================================================================================ */ 6258 6259 6260 /* ---------------------------------- LEDTS_ID ---------------------------------- */ 6261 #define LEDTS_ID_MOD_REV_Pos (0UL) /*!< LEDTS ID: MOD_REV (Bit 0) */ 6262 #define LEDTS_ID_MOD_REV_Msk (0xffUL) /*!< LEDTS ID: MOD_REV (Bitfield-Mask: 0xff) */ 6263 #define LEDTS_ID_MOD_TYPE_Pos (8UL) /*!< LEDTS ID: MOD_TYPE (Bit 8) */ 6264 #define LEDTS_ID_MOD_TYPE_Msk (0xff00UL) /*!< LEDTS ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 6265 #define LEDTS_ID_MOD_NUMBER_Pos (16UL) /*!< LEDTS ID: MOD_NUMBER (Bit 16) */ 6266 #define LEDTS_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< LEDTS ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 6267 6268 /* -------------------------------- LEDTS_GLOBCTL ------------------------------- */ 6269 #define LEDTS_GLOBCTL_TS_EN_Pos (0UL) /*!< LEDTS GLOBCTL: TS_EN (Bit 0) */ 6270 #define LEDTS_GLOBCTL_TS_EN_Msk (0x1UL) /*!< LEDTS GLOBCTL: TS_EN (Bitfield-Mask: 0x01) */ 6271 #define LEDTS_GLOBCTL_LD_EN_Pos (1UL) /*!< LEDTS GLOBCTL: LD_EN (Bit 1) */ 6272 #define LEDTS_GLOBCTL_LD_EN_Msk (0x2UL) /*!< LEDTS GLOBCTL: LD_EN (Bitfield-Mask: 0x01) */ 6273 #define LEDTS_GLOBCTL_CMTR_Pos (2UL) /*!< LEDTS GLOBCTL: CMTR (Bit 2) */ 6274 #define LEDTS_GLOBCTL_CMTR_Msk (0x4UL) /*!< LEDTS GLOBCTL: CMTR (Bitfield-Mask: 0x01) */ 6275 #define LEDTS_GLOBCTL_ENSYNC_Pos (3UL) /*!< LEDTS GLOBCTL: ENSYNC (Bit 3) */ 6276 #define LEDTS_GLOBCTL_ENSYNC_Msk (0x8UL) /*!< LEDTS GLOBCTL: ENSYNC (Bitfield-Mask: 0x01) */ 6277 #define LEDTS_GLOBCTL_SUSCFG_Pos (8UL) /*!< LEDTS GLOBCTL: SUSCFG (Bit 8) */ 6278 #define LEDTS_GLOBCTL_SUSCFG_Msk (0x100UL) /*!< LEDTS GLOBCTL: SUSCFG (Bitfield-Mask: 0x01) */ 6279 #define LEDTS_GLOBCTL_MASKVAL_Pos (9UL) /*!< LEDTS GLOBCTL: MASKVAL (Bit 9) */ 6280 #define LEDTS_GLOBCTL_MASKVAL_Msk (0xe00UL) /*!< LEDTS GLOBCTL: MASKVAL (Bitfield-Mask: 0x07) */ 6281 #define LEDTS_GLOBCTL_FENVAL_Pos (12UL) /*!< LEDTS GLOBCTL: FENVAL (Bit 12) */ 6282 #define LEDTS_GLOBCTL_FENVAL_Msk (0x1000UL) /*!< LEDTS GLOBCTL: FENVAL (Bitfield-Mask: 0x01) */ 6283 #define LEDTS_GLOBCTL_ITS_EN_Pos (13UL) /*!< LEDTS GLOBCTL: ITS_EN (Bit 13) */ 6284 #define LEDTS_GLOBCTL_ITS_EN_Msk (0x2000UL) /*!< LEDTS GLOBCTL: ITS_EN (Bitfield-Mask: 0x01) */ 6285 #define LEDTS_GLOBCTL_ITF_EN_Pos (14UL) /*!< LEDTS GLOBCTL: ITF_EN (Bit 14) */ 6286 #define LEDTS_GLOBCTL_ITF_EN_Msk (0x4000UL) /*!< LEDTS GLOBCTL: ITF_EN (Bitfield-Mask: 0x01) */ 6287 #define LEDTS_GLOBCTL_ITP_EN_Pos (15UL) /*!< LEDTS GLOBCTL: ITP_EN (Bit 15) */ 6288 #define LEDTS_GLOBCTL_ITP_EN_Msk (0x8000UL) /*!< LEDTS GLOBCTL: ITP_EN (Bitfield-Mask: 0x01) */ 6289 #define LEDTS_GLOBCTL_CLK_PS_Pos (16UL) /*!< LEDTS GLOBCTL: CLK_PS (Bit 16) */ 6290 #define LEDTS_GLOBCTL_CLK_PS_Msk (0xffff0000UL) /*!< LEDTS GLOBCTL: CLK_PS (Bitfield-Mask: 0xffff) */ 6291 6292 /* --------------------------------- LEDTS_FNCTL -------------------------------- */ 6293 #define LEDTS_FNCTL_PADT_Pos (0UL) /*!< LEDTS FNCTL: PADT (Bit 0) */ 6294 #define LEDTS_FNCTL_PADT_Msk (0x7UL) /*!< LEDTS FNCTL: PADT (Bitfield-Mask: 0x07) */ 6295 #define LEDTS_FNCTL_PADTSW_Pos (3UL) /*!< LEDTS FNCTL: PADTSW (Bit 3) */ 6296 #define LEDTS_FNCTL_PADTSW_Msk (0x8UL) /*!< LEDTS FNCTL: PADTSW (Bitfield-Mask: 0x01) */ 6297 #define LEDTS_FNCTL_EPULL_Pos (4UL) /*!< LEDTS FNCTL: EPULL (Bit 4) */ 6298 #define LEDTS_FNCTL_EPULL_Msk (0x10UL) /*!< LEDTS FNCTL: EPULL (Bitfield-Mask: 0x01) */ 6299 #define LEDTS_FNCTL_FNCOL_Pos (5UL) /*!< LEDTS FNCTL: FNCOL (Bit 5) */ 6300 #define LEDTS_FNCTL_FNCOL_Msk (0xe0UL) /*!< LEDTS FNCTL: FNCOL (Bitfield-Mask: 0x07) */ 6301 #define LEDTS_FNCTL_ACCCNT_Pos (16UL) /*!< LEDTS FNCTL: ACCCNT (Bit 16) */ 6302 #define LEDTS_FNCTL_ACCCNT_Msk (0xf0000UL) /*!< LEDTS FNCTL: ACCCNT (Bitfield-Mask: 0x0f) */ 6303 #define LEDTS_FNCTL_TSCCMP_Pos (20UL) /*!< LEDTS FNCTL: TSCCMP (Bit 20) */ 6304 #define LEDTS_FNCTL_TSCCMP_Msk (0x100000UL) /*!< LEDTS FNCTL: TSCCMP (Bitfield-Mask: 0x01) */ 6305 #define LEDTS_FNCTL_TSOEXT_Pos (21UL) /*!< LEDTS FNCTL: TSOEXT (Bit 21) */ 6306 #define LEDTS_FNCTL_TSOEXT_Msk (0x600000UL) /*!< LEDTS FNCTL: TSOEXT (Bitfield-Mask: 0x03) */ 6307 #define LEDTS_FNCTL_TSCTRR_Pos (23UL) /*!< LEDTS FNCTL: TSCTRR (Bit 23) */ 6308 #define LEDTS_FNCTL_TSCTRR_Msk (0x800000UL) /*!< LEDTS FNCTL: TSCTRR (Bitfield-Mask: 0x01) */ 6309 #define LEDTS_FNCTL_TSCTRSAT_Pos (24UL) /*!< LEDTS FNCTL: TSCTRSAT (Bit 24) */ 6310 #define LEDTS_FNCTL_TSCTRSAT_Msk (0x1000000UL) /*!< LEDTS FNCTL: TSCTRSAT (Bitfield-Mask: 0x01) */ 6311 #define LEDTS_FNCTL_NR_TSIN_Pos (25UL) /*!< LEDTS FNCTL: NR_TSIN (Bit 25) */ 6312 #define LEDTS_FNCTL_NR_TSIN_Msk (0xe000000UL) /*!< LEDTS FNCTL: NR_TSIN (Bitfield-Mask: 0x07) */ 6313 #define LEDTS_FNCTL_COLLEV_Pos (28UL) /*!< LEDTS FNCTL: COLLEV (Bit 28) */ 6314 #define LEDTS_FNCTL_COLLEV_Msk (0x10000000UL) /*!< LEDTS FNCTL: COLLEV (Bitfield-Mask: 0x01) */ 6315 #define LEDTS_FNCTL_NR_LEDCOL_Pos (29UL) /*!< LEDTS FNCTL: NR_LEDCOL (Bit 29) */ 6316 #define LEDTS_FNCTL_NR_LEDCOL_Msk (0xe0000000UL) /*!< LEDTS FNCTL: NR_LEDCOL (Bitfield-Mask: 0x07) */ 6317 6318 /* --------------------------------- LEDTS_EVFR --------------------------------- */ 6319 #define LEDTS_EVFR_TSF_Pos (0UL) /*!< LEDTS EVFR: TSF (Bit 0) */ 6320 #define LEDTS_EVFR_TSF_Msk (0x1UL) /*!< LEDTS EVFR: TSF (Bitfield-Mask: 0x01) */ 6321 #define LEDTS_EVFR_TFF_Pos (1UL) /*!< LEDTS EVFR: TFF (Bit 1) */ 6322 #define LEDTS_EVFR_TFF_Msk (0x2UL) /*!< LEDTS EVFR: TFF (Bitfield-Mask: 0x01) */ 6323 #define LEDTS_EVFR_TPF_Pos (2UL) /*!< LEDTS EVFR: TPF (Bit 2) */ 6324 #define LEDTS_EVFR_TPF_Msk (0x4UL) /*!< LEDTS EVFR: TPF (Bitfield-Mask: 0x01) */ 6325 #define LEDTS_EVFR_TSCTROVF_Pos (3UL) /*!< LEDTS EVFR: TSCTROVF (Bit 3) */ 6326 #define LEDTS_EVFR_TSCTROVF_Msk (0x8UL) /*!< LEDTS EVFR: TSCTROVF (Bitfield-Mask: 0x01) */ 6327 #define LEDTS_EVFR_CTSF_Pos (16UL) /*!< LEDTS EVFR: CTSF (Bit 16) */ 6328 #define LEDTS_EVFR_CTSF_Msk (0x10000UL) /*!< LEDTS EVFR: CTSF (Bitfield-Mask: 0x01) */ 6329 #define LEDTS_EVFR_CTFF_Pos (17UL) /*!< LEDTS EVFR: CTFF (Bit 17) */ 6330 #define LEDTS_EVFR_CTFF_Msk (0x20000UL) /*!< LEDTS EVFR: CTFF (Bitfield-Mask: 0x01) */ 6331 #define LEDTS_EVFR_CTPF_Pos (18UL) /*!< LEDTS EVFR: CTPF (Bit 18) */ 6332 #define LEDTS_EVFR_CTPF_Msk (0x40000UL) /*!< LEDTS EVFR: CTPF (Bitfield-Mask: 0x01) */ 6333 6334 /* --------------------------------- LEDTS_TSVAL -------------------------------- */ 6335 #define LEDTS_TSVAL_TSCTRVALR_Pos (0UL) /*!< LEDTS TSVAL: TSCTRVALR (Bit 0) */ 6336 #define LEDTS_TSVAL_TSCTRVALR_Msk (0xffffUL) /*!< LEDTS TSVAL: TSCTRVALR (Bitfield-Mask: 0xffff) */ 6337 #define LEDTS_TSVAL_TSCTRVAL_Pos (16UL) /*!< LEDTS TSVAL: TSCTRVAL (Bit 16) */ 6338 #define LEDTS_TSVAL_TSCTRVAL_Msk (0xffff0000UL) /*!< LEDTS TSVAL: TSCTRVAL (Bitfield-Mask: 0xffff) */ 6339 6340 /* --------------------------------- LEDTS_LINE0 -------------------------------- */ 6341 #define LEDTS_LINE0_LINE_0_Pos (0UL) /*!< LEDTS LINE0: LINE_0 (Bit 0) */ 6342 #define LEDTS_LINE0_LINE_0_Msk (0xffUL) /*!< LEDTS LINE0: LINE_0 (Bitfield-Mask: 0xff) */ 6343 #define LEDTS_LINE0_LINE_1_Pos (8UL) /*!< LEDTS LINE0: LINE_1 (Bit 8) */ 6344 #define LEDTS_LINE0_LINE_1_Msk (0xff00UL) /*!< LEDTS LINE0: LINE_1 (Bitfield-Mask: 0xff) */ 6345 #define LEDTS_LINE0_LINE_2_Pos (16UL) /*!< LEDTS LINE0: LINE_2 (Bit 16) */ 6346 #define LEDTS_LINE0_LINE_2_Msk (0xff0000UL) /*!< LEDTS LINE0: LINE_2 (Bitfield-Mask: 0xff) */ 6347 #define LEDTS_LINE0_LINE_3_Pos (24UL) /*!< LEDTS LINE0: LINE_3 (Bit 24) */ 6348 #define LEDTS_LINE0_LINE_3_Msk (0xff000000UL) /*!< LEDTS LINE0: LINE_3 (Bitfield-Mask: 0xff) */ 6349 6350 /* --------------------------------- LEDTS_LINE1 -------------------------------- */ 6351 #define LEDTS_LINE1_LINE_4_Pos (0UL) /*!< LEDTS LINE1: LINE_4 (Bit 0) */ 6352 #define LEDTS_LINE1_LINE_4_Msk (0xffUL) /*!< LEDTS LINE1: LINE_4 (Bitfield-Mask: 0xff) */ 6353 #define LEDTS_LINE1_LINE_5_Pos (8UL) /*!< LEDTS LINE1: LINE_5 (Bit 8) */ 6354 #define LEDTS_LINE1_LINE_5_Msk (0xff00UL) /*!< LEDTS LINE1: LINE_5 (Bitfield-Mask: 0xff) */ 6355 #define LEDTS_LINE1_LINE_6_Pos (16UL) /*!< LEDTS LINE1: LINE_6 (Bit 16) */ 6356 #define LEDTS_LINE1_LINE_6_Msk (0xff0000UL) /*!< LEDTS LINE1: LINE_6 (Bitfield-Mask: 0xff) */ 6357 #define LEDTS_LINE1_LINE_A_Pos (24UL) /*!< LEDTS LINE1: LINE_A (Bit 24) */ 6358 #define LEDTS_LINE1_LINE_A_Msk (0xff000000UL) /*!< LEDTS LINE1: LINE_A (Bitfield-Mask: 0xff) */ 6359 6360 /* -------------------------------- LEDTS_LDCMP0 -------------------------------- */ 6361 #define LEDTS_LDCMP0_CMP_LD0_Pos (0UL) /*!< LEDTS LDCMP0: CMP_LD0 (Bit 0) */ 6362 #define LEDTS_LDCMP0_CMP_LD0_Msk (0xffUL) /*!< LEDTS LDCMP0: CMP_LD0 (Bitfield-Mask: 0xff) */ 6363 #define LEDTS_LDCMP0_CMP_LD1_Pos (8UL) /*!< LEDTS LDCMP0: CMP_LD1 (Bit 8) */ 6364 #define LEDTS_LDCMP0_CMP_LD1_Msk (0xff00UL) /*!< LEDTS LDCMP0: CMP_LD1 (Bitfield-Mask: 0xff) */ 6365 #define LEDTS_LDCMP0_CMP_LD2_Pos (16UL) /*!< LEDTS LDCMP0: CMP_LD2 (Bit 16) */ 6366 #define LEDTS_LDCMP0_CMP_LD2_Msk (0xff0000UL) /*!< LEDTS LDCMP0: CMP_LD2 (Bitfield-Mask: 0xff) */ 6367 #define LEDTS_LDCMP0_CMP_LD3_Pos (24UL) /*!< LEDTS LDCMP0: CMP_LD3 (Bit 24) */ 6368 #define LEDTS_LDCMP0_CMP_LD3_Msk (0xff000000UL) /*!< LEDTS LDCMP0: CMP_LD3 (Bitfield-Mask: 0xff) */ 6369 6370 /* -------------------------------- LEDTS_LDCMP1 -------------------------------- */ 6371 #define LEDTS_LDCMP1_CMP_LD4_Pos (0UL) /*!< LEDTS LDCMP1: CMP_LD4 (Bit 0) */ 6372 #define LEDTS_LDCMP1_CMP_LD4_Msk (0xffUL) /*!< LEDTS LDCMP1: CMP_LD4 (Bitfield-Mask: 0xff) */ 6373 #define LEDTS_LDCMP1_CMP_LD5_Pos (8UL) /*!< LEDTS LDCMP1: CMP_LD5 (Bit 8) */ 6374 #define LEDTS_LDCMP1_CMP_LD5_Msk (0xff00UL) /*!< LEDTS LDCMP1: CMP_LD5 (Bitfield-Mask: 0xff) */ 6375 #define LEDTS_LDCMP1_CMP_LD6_Pos (16UL) /*!< LEDTS LDCMP1: CMP_LD6 (Bit 16) */ 6376 #define LEDTS_LDCMP1_CMP_LD6_Msk (0xff0000UL) /*!< LEDTS LDCMP1: CMP_LD6 (Bitfield-Mask: 0xff) */ 6377 #define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos (24UL) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM (Bit 24) */ 6378 #define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk (0xff000000UL) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM (Bitfield-Mask: 0xff) */ 6379 6380 /* -------------------------------- LEDTS_TSCMP0 -------------------------------- */ 6381 #define LEDTS_TSCMP0_CMP_TS0_Pos (0UL) /*!< LEDTS TSCMP0: CMP_TS0 (Bit 0) */ 6382 #define LEDTS_TSCMP0_CMP_TS0_Msk (0xffUL) /*!< LEDTS TSCMP0: CMP_TS0 (Bitfield-Mask: 0xff) */ 6383 #define LEDTS_TSCMP0_CMP_TS1_Pos (8UL) /*!< LEDTS TSCMP0: CMP_TS1 (Bit 8) */ 6384 #define LEDTS_TSCMP0_CMP_TS1_Msk (0xff00UL) /*!< LEDTS TSCMP0: CMP_TS1 (Bitfield-Mask: 0xff) */ 6385 #define LEDTS_TSCMP0_CMP_TS2_Pos (16UL) /*!< LEDTS TSCMP0: CMP_TS2 (Bit 16) */ 6386 #define LEDTS_TSCMP0_CMP_TS2_Msk (0xff0000UL) /*!< LEDTS TSCMP0: CMP_TS2 (Bitfield-Mask: 0xff) */ 6387 #define LEDTS_TSCMP0_CMP_TS3_Pos (24UL) /*!< LEDTS TSCMP0: CMP_TS3 (Bit 24) */ 6388 #define LEDTS_TSCMP0_CMP_TS3_Msk (0xff000000UL) /*!< LEDTS TSCMP0: CMP_TS3 (Bitfield-Mask: 0xff) */ 6389 6390 /* -------------------------------- LEDTS_TSCMP1 -------------------------------- */ 6391 #define LEDTS_TSCMP1_CMP_TS4_Pos (0UL) /*!< LEDTS TSCMP1: CMP_TS4 (Bit 0) */ 6392 #define LEDTS_TSCMP1_CMP_TS4_Msk (0xffUL) /*!< LEDTS TSCMP1: CMP_TS4 (Bitfield-Mask: 0xff) */ 6393 #define LEDTS_TSCMP1_CMP_TS5_Pos (8UL) /*!< LEDTS TSCMP1: CMP_TS5 (Bit 8) */ 6394 #define LEDTS_TSCMP1_CMP_TS5_Msk (0xff00UL) /*!< LEDTS TSCMP1: CMP_TS5 (Bitfield-Mask: 0xff) */ 6395 #define LEDTS_TSCMP1_CMP_TS6_Pos (16UL) /*!< LEDTS TSCMP1: CMP_TS6 (Bit 16) */ 6396 #define LEDTS_TSCMP1_CMP_TS6_Msk (0xff0000UL) /*!< LEDTS TSCMP1: CMP_TS6 (Bitfield-Mask: 0xff) */ 6397 #define LEDTS_TSCMP1_CMP_TS7_Pos (24UL) /*!< LEDTS TSCMP1: CMP_TS7 (Bit 24) */ 6398 #define LEDTS_TSCMP1_CMP_TS7_Msk (0xff000000UL) /*!< LEDTS TSCMP1: CMP_TS7 (Bitfield-Mask: 0xff) */ 6399 6400 6401 /* ================================================================================ */ 6402 /* ================ struct 'SDMMC' Position & Mask ================ */ 6403 /* ================================================================================ */ 6404 6405 6406 /* ------------------------------ SDMMC_BLOCK_SIZE ------------------------------ */ 6407 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos (0UL) /*!< SDMMC BLOCK_SIZE: TX_BLOCK_SIZE (Bit 0) */ 6408 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Msk (0xfffUL) /*!< SDMMC BLOCK_SIZE: TX_BLOCK_SIZE (Bitfield-Mask: 0xfff) */ 6409 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos (15UL) /*!< SDMMC BLOCK_SIZE: TX_BLOCK_SIZE_12 (Bit 15) */ 6410 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Msk (0x8000UL) /*!< SDMMC BLOCK_SIZE: TX_BLOCK_SIZE_12 (Bitfield-Mask: 0x01) */ 6411 6412 /* ------------------------------ SDMMC_BLOCK_COUNT ----------------------------- */ 6413 #define SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos (0UL) /*!< SDMMC BLOCK_COUNT: BLOCK_COUNT (Bit 0) */ 6414 #define SDMMC_BLOCK_COUNT_BLOCK_COUNT_Msk (0xffffUL) /*!< SDMMC BLOCK_COUNT: BLOCK_COUNT (Bitfield-Mask: 0xffff) */ 6415 6416 /* ------------------------------- SDMMC_ARGUMENT1 ------------------------------ */ 6417 #define SDMMC_ARGUMENT1_ARGUMENT1_Pos (0UL) /*!< SDMMC ARGUMENT1: ARGUMENT1 (Bit 0) */ 6418 #define SDMMC_ARGUMENT1_ARGUMENT1_Msk (0xffffffffUL) /*!< SDMMC ARGUMENT1: ARGUMENT1 (Bitfield-Mask: 0xffffffff) */ 6419 6420 /* ----------------------------- SDMMC_TRANSFER_MODE ---------------------------- */ 6421 #define SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos (1UL) /*!< SDMMC TRANSFER_MODE: BLOCK_COUNT_EN (Bit 1) */ 6422 #define SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk (0x2UL) /*!< SDMMC TRANSFER_MODE: BLOCK_COUNT_EN (Bitfield-Mask: 0x01) */ 6423 #define SDMMC_TRANSFER_MODE_ACMD_EN_Pos (2UL) /*!< SDMMC TRANSFER_MODE: ACMD_EN (Bit 2) */ 6424 #define SDMMC_TRANSFER_MODE_ACMD_EN_Msk (0xcUL) /*!< SDMMC TRANSFER_MODE: ACMD_EN (Bitfield-Mask: 0x03) */ 6425 #define SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos (4UL) /*!< SDMMC TRANSFER_MODE: TX_DIR_SELECT (Bit 4) */ 6426 #define SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk (0x10UL) /*!< SDMMC TRANSFER_MODE: TX_DIR_SELECT (Bitfield-Mask: 0x01) */ 6427 #define SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos (5UL) /*!< SDMMC TRANSFER_MODE: MULTI_BLOCK_SELECT (Bit 5) */ 6428 #define SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk (0x20UL) /*!< SDMMC TRANSFER_MODE: MULTI_BLOCK_SELECT (Bitfield-Mask: 0x01) */ 6429 #define SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos (6UL) /*!< SDMMC TRANSFER_MODE: CMD_COMP_ATA (Bit 6) */ 6430 #define SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Msk (0x40UL) /*!< SDMMC TRANSFER_MODE: CMD_COMP_ATA (Bitfield-Mask: 0x01) */ 6431 6432 /* -------------------------------- SDMMC_COMMAND ------------------------------- */ 6433 #define SDMMC_COMMAND_RESP_TYPE_SELECT_Pos (0UL) /*!< SDMMC COMMAND: RESP_TYPE_SELECT (Bit 0) */ 6434 #define SDMMC_COMMAND_RESP_TYPE_SELECT_Msk (0x3UL) /*!< SDMMC COMMAND: RESP_TYPE_SELECT (Bitfield-Mask: 0x03) */ 6435 #define SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos (3UL) /*!< SDMMC COMMAND: CMD_CRC_CHECK_EN (Bit 3) */ 6436 #define SDMMC_COMMAND_CMD_CRC_CHECK_EN_Msk (0x8UL) /*!< SDMMC COMMAND: CMD_CRC_CHECK_EN (Bitfield-Mask: 0x01) */ 6437 #define SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos (4UL) /*!< SDMMC COMMAND: CMD_IND_CHECK_EN (Bit 4) */ 6438 #define SDMMC_COMMAND_CMD_IND_CHECK_EN_Msk (0x10UL) /*!< SDMMC COMMAND: CMD_IND_CHECK_EN (Bitfield-Mask: 0x01) */ 6439 #define SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos (5UL) /*!< SDMMC COMMAND: DATA_PRESENT_SELECT (Bit 5) */ 6440 #define SDMMC_COMMAND_DATA_PRESENT_SELECT_Msk (0x20UL) /*!< SDMMC COMMAND: DATA_PRESENT_SELECT (Bitfield-Mask: 0x01) */ 6441 #define SDMMC_COMMAND_CMD_TYPE_Pos (6UL) /*!< SDMMC COMMAND: CMD_TYPE (Bit 6) */ 6442 #define SDMMC_COMMAND_CMD_TYPE_Msk (0xc0UL) /*!< SDMMC COMMAND: CMD_TYPE (Bitfield-Mask: 0x03) */ 6443 #define SDMMC_COMMAND_CMD_IND_Pos (8UL) /*!< SDMMC COMMAND: CMD_IND (Bit 8) */ 6444 #define SDMMC_COMMAND_CMD_IND_Msk (0x3f00UL) /*!< SDMMC COMMAND: CMD_IND (Bitfield-Mask: 0x3f) */ 6445 6446 /* ------------------------------- SDMMC_RESPONSE0 ------------------------------ */ 6447 #define SDMMC_RESPONSE0_RESPONSE0_Pos (0UL) /*!< SDMMC RESPONSE0: RESPONSE0 (Bit 0) */ 6448 #define SDMMC_RESPONSE0_RESPONSE0_Msk (0xffffUL) /*!< SDMMC RESPONSE0: RESPONSE0 (Bitfield-Mask: 0xffff) */ 6449 #define SDMMC_RESPONSE0_RESPONSE1_Pos (16UL) /*!< SDMMC RESPONSE0: RESPONSE1 (Bit 16) */ 6450 #define SDMMC_RESPONSE0_RESPONSE1_Msk (0xffff0000UL) /*!< SDMMC RESPONSE0: RESPONSE1 (Bitfield-Mask: 0xffff) */ 6451 6452 /* ------------------------------- SDMMC_RESPONSE2 ------------------------------ */ 6453 #define SDMMC_RESPONSE2_RESPONSE2_Pos (0UL) /*!< SDMMC RESPONSE2: RESPONSE2 (Bit 0) */ 6454 #define SDMMC_RESPONSE2_RESPONSE2_Msk (0xffffUL) /*!< SDMMC RESPONSE2: RESPONSE2 (Bitfield-Mask: 0xffff) */ 6455 #define SDMMC_RESPONSE2_RESPONSE3_Pos (16UL) /*!< SDMMC RESPONSE2: RESPONSE3 (Bit 16) */ 6456 #define SDMMC_RESPONSE2_RESPONSE3_Msk (0xffff0000UL) /*!< SDMMC RESPONSE2: RESPONSE3 (Bitfield-Mask: 0xffff) */ 6457 6458 /* ------------------------------- SDMMC_RESPONSE4 ------------------------------ */ 6459 #define SDMMC_RESPONSE4_RESPONSE4_Pos (0UL) /*!< SDMMC RESPONSE4: RESPONSE4 (Bit 0) */ 6460 #define SDMMC_RESPONSE4_RESPONSE4_Msk (0xffffUL) /*!< SDMMC RESPONSE4: RESPONSE4 (Bitfield-Mask: 0xffff) */ 6461 #define SDMMC_RESPONSE4_RESPONSE5_Pos (16UL) /*!< SDMMC RESPONSE4: RESPONSE5 (Bit 16) */ 6462 #define SDMMC_RESPONSE4_RESPONSE5_Msk (0xffff0000UL) /*!< SDMMC RESPONSE4: RESPONSE5 (Bitfield-Mask: 0xffff) */ 6463 6464 /* ------------------------------- SDMMC_RESPONSE6 ------------------------------ */ 6465 #define SDMMC_RESPONSE6_RESPONSE6_Pos (0UL) /*!< SDMMC RESPONSE6: RESPONSE6 (Bit 0) */ 6466 #define SDMMC_RESPONSE6_RESPONSE6_Msk (0xffffUL) /*!< SDMMC RESPONSE6: RESPONSE6 (Bitfield-Mask: 0xffff) */ 6467 #define SDMMC_RESPONSE6_RESPONSE7_Pos (16UL) /*!< SDMMC RESPONSE6: RESPONSE7 (Bit 16) */ 6468 #define SDMMC_RESPONSE6_RESPONSE7_Msk (0xffff0000UL) /*!< SDMMC RESPONSE6: RESPONSE7 (Bitfield-Mask: 0xffff) */ 6469 6470 /* ------------------------------ SDMMC_DATA_BUFFER ----------------------------- */ 6471 #define SDMMC_DATA_BUFFER_DATA_BUFFER_Pos (0UL) /*!< SDMMC DATA_BUFFER: DATA_BUFFER (Bit 0) */ 6472 #define SDMMC_DATA_BUFFER_DATA_BUFFER_Msk (0xffffffffUL) /*!< SDMMC DATA_BUFFER: DATA_BUFFER (Bitfield-Mask: 0xffffffff) */ 6473 6474 /* ----------------------------- SDMMC_PRESENT_STATE ---------------------------- */ 6475 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos (0UL) /*!< SDMMC PRESENT_STATE: COMMAND_INHIBIT_CMD (Bit 0) */ 6476 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Msk (0x1UL) /*!< SDMMC PRESENT_STATE: COMMAND_INHIBIT_CMD (Bitfield-Mask: 0x01) */ 6477 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos (1UL) /*!< SDMMC PRESENT_STATE: COMMAND_INHIBIT_DAT (Bit 1) */ 6478 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Msk (0x2UL) /*!< SDMMC PRESENT_STATE: COMMAND_INHIBIT_DAT (Bitfield-Mask: 0x01) */ 6479 #define SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos (2UL) /*!< SDMMC PRESENT_STATE: DAT_LINE_ACTIVE (Bit 2) */ 6480 #define SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Msk (0x4UL) /*!< SDMMC PRESENT_STATE: DAT_LINE_ACTIVE (Bitfield-Mask: 0x01) */ 6481 #define SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos (8UL) /*!< SDMMC PRESENT_STATE: WRITE_TRANSFER_ACTIVE (Bit 8) */ 6482 #define SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Msk (0x100UL) /*!< SDMMC PRESENT_STATE: WRITE_TRANSFER_ACTIVE (Bitfield-Mask: 0x01) */ 6483 #define SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos (9UL) /*!< SDMMC PRESENT_STATE: READ_TRANSFER_ACTIVE (Bit 9) */ 6484 #define SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Msk (0x200UL) /*!< SDMMC PRESENT_STATE: READ_TRANSFER_ACTIVE (Bitfield-Mask: 0x01) */ 6485 #define SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos (10UL) /*!< SDMMC PRESENT_STATE: BUFFER_WRITE_ENABLE (Bit 10) */ 6486 #define SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Msk (0x400UL) /*!< SDMMC PRESENT_STATE: BUFFER_WRITE_ENABLE (Bitfield-Mask: 0x01) */ 6487 #define SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos (11UL) /*!< SDMMC PRESENT_STATE: BUFFER_READ_ENABLE (Bit 11) */ 6488 #define SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Msk (0x800UL) /*!< SDMMC PRESENT_STATE: BUFFER_READ_ENABLE (Bitfield-Mask: 0x01) */ 6489 #define SDMMC_PRESENT_STATE_CARD_INSERTED_Pos (16UL) /*!< SDMMC PRESENT_STATE: CARD_INSERTED (Bit 16) */ 6490 #define SDMMC_PRESENT_STATE_CARD_INSERTED_Msk (0x10000UL) /*!< SDMMC PRESENT_STATE: CARD_INSERTED (Bitfield-Mask: 0x01) */ 6491 #define SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos (17UL) /*!< SDMMC PRESENT_STATE: CARD_STATE_STABLE (Bit 17) */ 6492 #define SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Msk (0x20000UL) /*!< SDMMC PRESENT_STATE: CARD_STATE_STABLE (Bitfield-Mask: 0x01) */ 6493 #define SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos (18UL) /*!< SDMMC PRESENT_STATE: CARD_DETECT_PIN_LEVEL (Bit 18) */ 6494 #define SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Msk (0x40000UL) /*!< SDMMC PRESENT_STATE: CARD_DETECT_PIN_LEVEL (Bitfield-Mask: 0x01) */ 6495 #define SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos (19UL) /*!< SDMMC PRESENT_STATE: WRITE_PROTECT_PIN_LEVEL (Bit 19) */ 6496 #define SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Msk (0x80000UL) /*!< SDMMC PRESENT_STATE: WRITE_PROTECT_PIN_LEVEL (Bitfield-Mask: 0x01) */ 6497 #define SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos (20UL) /*!< SDMMC PRESENT_STATE: DAT_3_0_PIN_LEVEL (Bit 20) */ 6498 #define SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk (0xf00000UL) /*!< SDMMC PRESENT_STATE: DAT_3_0_PIN_LEVEL (Bitfield-Mask: 0x0f) */ 6499 #define SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos (24UL) /*!< SDMMC PRESENT_STATE: CMD_LINE_LEVEL (Bit 24) */ 6500 #define SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Msk (0x1000000UL) /*!< SDMMC PRESENT_STATE: CMD_LINE_LEVEL (Bitfield-Mask: 0x01) */ 6501 #define SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos (25UL) /*!< SDMMC PRESENT_STATE: DAT_7_4_PIN_LEVEL (Bit 25) */ 6502 #define SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Msk (0x1e000000UL) /*!< SDMMC PRESENT_STATE: DAT_7_4_PIN_LEVEL (Bitfield-Mask: 0x0f) */ 6503 6504 /* ------------------------------- SDMMC_HOST_CTRL ------------------------------ */ 6505 #define SDMMC_HOST_CTRL_LED_CTRL_Pos (0UL) /*!< SDMMC HOST_CTRL: LED_CTRL (Bit 0) */ 6506 #define SDMMC_HOST_CTRL_LED_CTRL_Msk (0x1UL) /*!< SDMMC HOST_CTRL: LED_CTRL (Bitfield-Mask: 0x01) */ 6507 #define SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos (1UL) /*!< SDMMC HOST_CTRL: DATA_TX_WIDTH (Bit 1) */ 6508 #define SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk (0x2UL) /*!< SDMMC HOST_CTRL: DATA_TX_WIDTH (Bitfield-Mask: 0x01) */ 6509 #define SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos (2UL) /*!< SDMMC HOST_CTRL: HIGH_SPEED_EN (Bit 2) */ 6510 #define SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk (0x4UL) /*!< SDMMC HOST_CTRL: HIGH_SPEED_EN (Bitfield-Mask: 0x01) */ 6511 #define SDMMC_HOST_CTRL_SD_8BIT_MODE_Pos (5UL) /*!< SDMMC HOST_CTRL: SD_8BIT_MODE (Bit 5) */ 6512 #define SDMMC_HOST_CTRL_SD_8BIT_MODE_Msk (0x20UL) /*!< SDMMC HOST_CTRL: SD_8BIT_MODE (Bitfield-Mask: 0x01) */ 6513 #define SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos (6UL) /*!< SDMMC HOST_CTRL: CARD_DETECT_TEST_LEVEL (Bit 6) */ 6514 #define SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk (0x40UL) /*!< SDMMC HOST_CTRL: CARD_DETECT_TEST_LEVEL (Bitfield-Mask: 0x01) */ 6515 #define SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos (7UL) /*!< SDMMC HOST_CTRL: CARD_DET_SIGNAL_DETECT (Bit 7) */ 6516 #define SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk (0x80UL) /*!< SDMMC HOST_CTRL: CARD_DET_SIGNAL_DETECT (Bitfield-Mask: 0x01) */ 6517 6518 /* ------------------------------ SDMMC_POWER_CTRL ------------------------------ */ 6519 #define SDMMC_POWER_CTRL_SD_BUS_POWER_Pos (0UL) /*!< SDMMC POWER_CTRL: SD_BUS_POWER (Bit 0) */ 6520 #define SDMMC_POWER_CTRL_SD_BUS_POWER_Msk (0x1UL) /*!< SDMMC POWER_CTRL: SD_BUS_POWER (Bitfield-Mask: 0x01) */ 6521 #define SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos (1UL) /*!< SDMMC POWER_CTRL: SD_BUS_VOLTAGE_SEL (Bit 1) */ 6522 #define SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk (0xeUL) /*!< SDMMC POWER_CTRL: SD_BUS_VOLTAGE_SEL (Bitfield-Mask: 0x07) */ 6523 #define SDMMC_POWER_CTRL_HARDWARE_RESET_Pos (4UL) /*!< SDMMC POWER_CTRL: HARDWARE_RESET (Bit 4) */ 6524 #define SDMMC_POWER_CTRL_HARDWARE_RESET_Msk (0x10UL) /*!< SDMMC POWER_CTRL: HARDWARE_RESET (Bitfield-Mask: 0x01) */ 6525 6526 /* ---------------------------- SDMMC_BLOCK_GAP_CTRL ---------------------------- */ 6527 #define SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos (0UL) /*!< SDMMC BLOCK_GAP_CTRL: STOP_AT_BLOCK_GAP (Bit 0) */ 6528 #define SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Msk (0x1UL) /*!< SDMMC BLOCK_GAP_CTRL: STOP_AT_BLOCK_GAP (Bitfield-Mask: 0x01) */ 6529 #define SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos (1UL) /*!< SDMMC BLOCK_GAP_CTRL: CONTINUE_REQ (Bit 1) */ 6530 #define SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Msk (0x2UL) /*!< SDMMC BLOCK_GAP_CTRL: CONTINUE_REQ (Bitfield-Mask: 0x01) */ 6531 #define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos (2UL) /*!< SDMMC BLOCK_GAP_CTRL: READ_WAIT_CTRL (Bit 2) */ 6532 #define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk (0x4UL) /*!< SDMMC BLOCK_GAP_CTRL: READ_WAIT_CTRL (Bitfield-Mask: 0x01) */ 6533 #define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos (3UL) /*!< SDMMC BLOCK_GAP_CTRL: INT_AT_BLOCK_GAP (Bit 3) */ 6534 #define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk (0x8UL) /*!< SDMMC BLOCK_GAP_CTRL: INT_AT_BLOCK_GAP (Bitfield-Mask: 0x01) */ 6535 #define SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Pos (4UL) /*!< SDMMC BLOCK_GAP_CTRL: SPI_MODE (Bit 4) */ 6536 #define SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Msk (0x10UL) /*!< SDMMC BLOCK_GAP_CTRL: SPI_MODE (Bitfield-Mask: 0x01) */ 6537 6538 /* ------------------------------ SDMMC_WAKEUP_CTRL ----------------------------- */ 6539 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos (0UL) /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INT (Bit 0) */ 6540 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk (0x1UL) /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INT (Bitfield-Mask: 0x01) */ 6541 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos (1UL) /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INS (Bit 1) */ 6542 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk (0x2UL) /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INS (Bitfield-Mask: 0x01) */ 6543 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos (2UL) /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_REM (Bit 2) */ 6544 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Msk (0x4UL) /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_REM (Bitfield-Mask: 0x01) */ 6545 6546 /* ------------------------------ SDMMC_CLOCK_CTRL ------------------------------ */ 6547 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos (0UL) /*!< SDMMC CLOCK_CTRL: INTERNAL_CLOCK_EN (Bit 0) */ 6548 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk (0x1UL) /*!< SDMMC CLOCK_CTRL: INTERNAL_CLOCK_EN (Bitfield-Mask: 0x01) */ 6549 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos (1UL) /*!< SDMMC CLOCK_CTRL: INTERNAL_CLOCK_STABLE (Bit 1) */ 6550 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk (0x2UL) /*!< SDMMC CLOCK_CTRL: INTERNAL_CLOCK_STABLE (Bitfield-Mask: 0x01) */ 6551 #define SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos (2UL) /*!< SDMMC CLOCK_CTRL: SDCLOCK_EN (Bit 2) */ 6552 #define SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk (0x4UL) /*!< SDMMC CLOCK_CTRL: SDCLOCK_EN (Bitfield-Mask: 0x01) */ 6553 #define SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos (8UL) /*!< SDMMC CLOCK_CTRL: SDCLK_FREQ_SEL (Bit 8) */ 6554 #define SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk (0xff00UL) /*!< SDMMC CLOCK_CTRL: SDCLK_FREQ_SEL (Bitfield-Mask: 0xff) */ 6555 6556 /* ----------------------------- SDMMC_TIMEOUT_CTRL ----------------------------- */ 6557 #define SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos (0UL) /*!< SDMMC TIMEOUT_CTRL: DAT_TIMEOUT_CNT_VAL (Bit 0) */ 6558 #define SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk (0xfUL) /*!< SDMMC TIMEOUT_CTRL: DAT_TIMEOUT_CNT_VAL (Bitfield-Mask: 0x0f) */ 6559 6560 /* ------------------------------- SDMMC_SW_RESET ------------------------------- */ 6561 #define SDMMC_SW_RESET_SW_RST_ALL_Pos (0UL) /*!< SDMMC SW_RESET: SW_RST_ALL (Bit 0) */ 6562 #define SDMMC_SW_RESET_SW_RST_ALL_Msk (0x1UL) /*!< SDMMC SW_RESET: SW_RST_ALL (Bitfield-Mask: 0x01) */ 6563 #define SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos (1UL) /*!< SDMMC SW_RESET: SW_RST_CMD_LINE (Bit 1) */ 6564 #define SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk (0x2UL) /*!< SDMMC SW_RESET: SW_RST_CMD_LINE (Bitfield-Mask: 0x01) */ 6565 #define SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos (2UL) /*!< SDMMC SW_RESET: SW_RST_DAT_LINE (Bit 2) */ 6566 #define SDMMC_SW_RESET_SW_RST_DAT_LINE_Msk (0x4UL) /*!< SDMMC SW_RESET: SW_RST_DAT_LINE (Bitfield-Mask: 0x01) */ 6567 6568 /* ---------------------------- SDMMC_INT_STATUS_NORM --------------------------- */ 6569 #define SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos (0UL) /*!< SDMMC INT_STATUS_NORM: CMD_COMPLETE (Bit 0) */ 6570 #define SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Msk (0x1UL) /*!< SDMMC INT_STATUS_NORM: CMD_COMPLETE (Bitfield-Mask: 0x01) */ 6571 #define SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos (1UL) /*!< SDMMC INT_STATUS_NORM: TX_COMPLETE (Bit 1) */ 6572 #define SDMMC_INT_STATUS_NORM_TX_COMPLETE_Msk (0x2UL) /*!< SDMMC INT_STATUS_NORM: TX_COMPLETE (Bitfield-Mask: 0x01) */ 6573 #define SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos (2UL) /*!< SDMMC INT_STATUS_NORM: BLOCK_GAP_EVENT (Bit 2) */ 6574 #define SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Msk (0x4UL) /*!< SDMMC INT_STATUS_NORM: BLOCK_GAP_EVENT (Bitfield-Mask: 0x01) */ 6575 #define SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos (4UL) /*!< SDMMC INT_STATUS_NORM: BUFF_WRITE_READY (Bit 4) */ 6576 #define SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Msk (0x10UL) /*!< SDMMC INT_STATUS_NORM: BUFF_WRITE_READY (Bitfield-Mask: 0x01) */ 6577 #define SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos (5UL) /*!< SDMMC INT_STATUS_NORM: BUFF_READ_READY (Bit 5) */ 6578 #define SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Msk (0x20UL) /*!< SDMMC INT_STATUS_NORM: BUFF_READ_READY (Bitfield-Mask: 0x01) */ 6579 #define SDMMC_INT_STATUS_NORM_CARD_INS_Pos (6UL) /*!< SDMMC INT_STATUS_NORM: CARD_INS (Bit 6) */ 6580 #define SDMMC_INT_STATUS_NORM_CARD_INS_Msk (0x40UL) /*!< SDMMC INT_STATUS_NORM: CARD_INS (Bitfield-Mask: 0x01) */ 6581 #define SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos (7UL) /*!< SDMMC INT_STATUS_NORM: CARD_REMOVAL (Bit 7) */ 6582 #define SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Msk (0x80UL) /*!< SDMMC INT_STATUS_NORM: CARD_REMOVAL (Bitfield-Mask: 0x01) */ 6583 #define SDMMC_INT_STATUS_NORM_CARD_INT_Pos (8UL) /*!< SDMMC INT_STATUS_NORM: CARD_INT (Bit 8) */ 6584 #define SDMMC_INT_STATUS_NORM_CARD_INT_Msk (0x100UL) /*!< SDMMC INT_STATUS_NORM: CARD_INT (Bitfield-Mask: 0x01) */ 6585 #define SDMMC_INT_STATUS_NORM_ERR_INT_Pos (15UL) /*!< SDMMC INT_STATUS_NORM: ERR_INT (Bit 15) */ 6586 #define SDMMC_INT_STATUS_NORM_ERR_INT_Msk (0x8000UL) /*!< SDMMC INT_STATUS_NORM: ERR_INT (Bitfield-Mask: 0x01) */ 6587 6588 /* ---------------------------- SDMMC_INT_STATUS_ERR ---------------------------- */ 6589 #define SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos (0UL) /*!< SDMMC INT_STATUS_ERR: CMD_TIMEOUT_ERR (Bit 0) */ 6590 #define SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Msk (0x1UL) /*!< SDMMC INT_STATUS_ERR: CMD_TIMEOUT_ERR (Bitfield-Mask: 0x01) */ 6591 #define SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos (1UL) /*!< SDMMC INT_STATUS_ERR: CMD_CRC_ERR (Bit 1) */ 6592 #define SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Msk (0x2UL) /*!< SDMMC INT_STATUS_ERR: CMD_CRC_ERR (Bitfield-Mask: 0x01) */ 6593 #define SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos (2UL) /*!< SDMMC INT_STATUS_ERR: CMD_END_BIT_ERR (Bit 2) */ 6594 #define SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Msk (0x4UL) /*!< SDMMC INT_STATUS_ERR: CMD_END_BIT_ERR (Bitfield-Mask: 0x01) */ 6595 #define SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos (3UL) /*!< SDMMC INT_STATUS_ERR: CMD_IND_ERR (Bit 3) */ 6596 #define SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Msk (0x8UL) /*!< SDMMC INT_STATUS_ERR: CMD_IND_ERR (Bitfield-Mask: 0x01) */ 6597 #define SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos (4UL) /*!< SDMMC INT_STATUS_ERR: DATA_TIMEOUT_ERR (Bit 4) */ 6598 #define SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Msk (0x10UL) /*!< SDMMC INT_STATUS_ERR: DATA_TIMEOUT_ERR (Bitfield-Mask: 0x01) */ 6599 #define SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos (5UL) /*!< SDMMC INT_STATUS_ERR: DATA_CRC_ERR (Bit 5) */ 6600 #define SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Msk (0x20UL) /*!< SDMMC INT_STATUS_ERR: DATA_CRC_ERR (Bitfield-Mask: 0x01) */ 6601 #define SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos (6UL) /*!< SDMMC INT_STATUS_ERR: DATA_END_BIT_ERR (Bit 6) */ 6602 #define SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Msk (0x40UL) /*!< SDMMC INT_STATUS_ERR: DATA_END_BIT_ERR (Bitfield-Mask: 0x01) */ 6603 #define SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos (7UL) /*!< SDMMC INT_STATUS_ERR: CURRENT_LIMIT_ERR (Bit 7) */ 6604 #define SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Msk (0x80UL) /*!< SDMMC INT_STATUS_ERR: CURRENT_LIMIT_ERR (Bitfield-Mask: 0x01) */ 6605 #define SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos (8UL) /*!< SDMMC INT_STATUS_ERR: ACMD_ERR (Bit 8) */ 6606 #define SDMMC_INT_STATUS_ERR_ACMD_ERR_Msk (0x100UL) /*!< SDMMC INT_STATUS_ERR: ACMD_ERR (Bitfield-Mask: 0x01) */ 6607 #define SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos (13UL) /*!< SDMMC INT_STATUS_ERR: CEATA_ERR (Bit 13) */ 6608 #define SDMMC_INT_STATUS_ERR_CEATA_ERR_Msk (0x2000UL) /*!< SDMMC INT_STATUS_ERR: CEATA_ERR (Bitfield-Mask: 0x01) */ 6609 6610 /* -------------------------- SDMMC_EN_INT_STATUS_NORM -------------------------- */ 6611 #define SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos (0UL) /*!< SDMMC EN_INT_STATUS_NORM: CMD_COMPLETE_EN (Bit 0) */ 6612 #define SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Msk (0x1UL) /*!< SDMMC EN_INT_STATUS_NORM: CMD_COMPLETE_EN (Bitfield-Mask: 0x01) */ 6613 #define SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos (1UL) /*!< SDMMC EN_INT_STATUS_NORM: TX_COMPLETE_EN (Bit 1) */ 6614 #define SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Msk (0x2UL) /*!< SDMMC EN_INT_STATUS_NORM: TX_COMPLETE_EN (Bitfield-Mask: 0x01) */ 6615 #define SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos (2UL) /*!< SDMMC EN_INT_STATUS_NORM: BLOCK_GAP_EVENT_EN (Bit 2) */ 6616 #define SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Msk (0x4UL) /*!< SDMMC EN_INT_STATUS_NORM: BLOCK_GAP_EVENT_EN (Bitfield-Mask: 0x01) */ 6617 #define SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos (4UL) /*!< SDMMC EN_INT_STATUS_NORM: BUFF_WRITE_READY_EN (Bit 4) */ 6618 #define SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Msk (0x10UL) /*!< SDMMC EN_INT_STATUS_NORM: BUFF_WRITE_READY_EN (Bitfield-Mask: 0x01) */ 6619 #define SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos (5UL) /*!< SDMMC EN_INT_STATUS_NORM: BUFF_READ_READY_EN (Bit 5) */ 6620 #define SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Msk (0x20UL) /*!< SDMMC EN_INT_STATUS_NORM: BUFF_READ_READY_EN (Bitfield-Mask: 0x01) */ 6621 #define SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos (6UL) /*!< SDMMC EN_INT_STATUS_NORM: CARD_INS_EN (Bit 6) */ 6622 #define SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Msk (0x40UL) /*!< SDMMC EN_INT_STATUS_NORM: CARD_INS_EN (Bitfield-Mask: 0x01) */ 6623 #define SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos (7UL) /*!< SDMMC EN_INT_STATUS_NORM: CARD_REMOVAL_EN (Bit 7) */ 6624 #define SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Msk (0x80UL) /*!< SDMMC EN_INT_STATUS_NORM: CARD_REMOVAL_EN (Bitfield-Mask: 0x01) */ 6625 #define SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos (8UL) /*!< SDMMC EN_INT_STATUS_NORM: CARD_INT_EN (Bit 8) */ 6626 #define SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Msk (0x100UL) /*!< SDMMC EN_INT_STATUS_NORM: CARD_INT_EN (Bitfield-Mask: 0x01) */ 6627 #define SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos (15UL) /*!< SDMMC EN_INT_STATUS_NORM: FIXED_TO_0 (Bit 15) */ 6628 #define SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Msk (0x8000UL) /*!< SDMMC EN_INT_STATUS_NORM: FIXED_TO_0 (Bitfield-Mask: 0x01) */ 6629 6630 /* --------------------------- SDMMC_EN_INT_STATUS_ERR -------------------------- */ 6631 #define SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos (0UL) /*!< SDMMC EN_INT_STATUS_ERR: CMD_TIMEOUT_ERR_EN (Bit 0) */ 6632 #define SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x1UL) /*!< SDMMC EN_INT_STATUS_ERR: CMD_TIMEOUT_ERR_EN (Bitfield-Mask: 0x01) */ 6633 #define SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos (1UL) /*!< SDMMC EN_INT_STATUS_ERR: CMD_CRC_ERR_EN (Bit 1) */ 6634 #define SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Msk (0x2UL) /*!< SDMMC EN_INT_STATUS_ERR: CMD_CRC_ERR_EN (Bitfield-Mask: 0x01) */ 6635 #define SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos (2UL) /*!< SDMMC EN_INT_STATUS_ERR: CMD_END_BIT_ERR_EN (Bit 2) */ 6636 #define SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Msk (0x4UL) /*!< SDMMC EN_INT_STATUS_ERR: CMD_END_BIT_ERR_EN (Bitfield-Mask: 0x01) */ 6637 #define SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos (3UL) /*!< SDMMC EN_INT_STATUS_ERR: CMD_IND_ERR_EN (Bit 3) */ 6638 #define SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Msk (0x8UL) /*!< SDMMC EN_INT_STATUS_ERR: CMD_IND_ERR_EN (Bitfield-Mask: 0x01) */ 6639 #define SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos (4UL) /*!< SDMMC EN_INT_STATUS_ERR: DATA_TIMEOUT_ERR_EN (Bit 4) */ 6640 #define SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x10UL) /*!< SDMMC EN_INT_STATUS_ERR: DATA_TIMEOUT_ERR_EN (Bitfield-Mask: 0x01) */ 6641 #define SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos (5UL) /*!< SDMMC EN_INT_STATUS_ERR: DATA_CRC_ERR_EN (Bit 5) */ 6642 #define SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Msk (0x20UL) /*!< SDMMC EN_INT_STATUS_ERR: DATA_CRC_ERR_EN (Bitfield-Mask: 0x01) */ 6643 #define SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos (6UL) /*!< SDMMC EN_INT_STATUS_ERR: DATA_END_BIT_ERR_EN (Bit 6) */ 6644 #define SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Msk (0x40UL) /*!< SDMMC EN_INT_STATUS_ERR: DATA_END_BIT_ERR_EN (Bitfield-Mask: 0x01) */ 6645 #define SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos (7UL) /*!< SDMMC EN_INT_STATUS_ERR: CURRENT_LIMIT_ERR_EN (Bit 7) */ 6646 #define SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x80UL) /*!< SDMMC EN_INT_STATUS_ERR: CURRENT_LIMIT_ERR_EN (Bitfield-Mask: 0x01) */ 6647 #define SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos (8UL) /*!< SDMMC EN_INT_STATUS_ERR: ACMD_ERR_EN (Bit 8) */ 6648 #define SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Msk (0x100UL) /*!< SDMMC EN_INT_STATUS_ERR: ACMD_ERR_EN (Bitfield-Mask: 0x01) */ 6649 #define SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos (12UL) /*!< SDMMC EN_INT_STATUS_ERR: TARGET_RESP_ERR_EN (Bit 12) */ 6650 #define SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Msk (0x1000UL) /*!< SDMMC EN_INT_STATUS_ERR: TARGET_RESP_ERR_EN (Bitfield-Mask: 0x01) */ 6651 #define SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos (13UL) /*!< SDMMC EN_INT_STATUS_ERR: CEATA_ERR_EN (Bit 13) */ 6652 #define SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Msk (0x2000UL) /*!< SDMMC EN_INT_STATUS_ERR: CEATA_ERR_EN (Bitfield-Mask: 0x01) */ 6653 6654 /* -------------------------- SDMMC_EN_INT_SIGNAL_NORM -------------------------- */ 6655 #define SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos (0UL) /*!< SDMMC EN_INT_SIGNAL_NORM: CMD_COMPLETE_EN (Bit 0) */ 6656 #define SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Msk (0x1UL) /*!< SDMMC EN_INT_SIGNAL_NORM: CMD_COMPLETE_EN (Bitfield-Mask: 0x01) */ 6657 #define SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos (1UL) /*!< SDMMC EN_INT_SIGNAL_NORM: TX_COMPLETE_EN (Bit 1) */ 6658 #define SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Msk (0x2UL) /*!< SDMMC EN_INT_SIGNAL_NORM: TX_COMPLETE_EN (Bitfield-Mask: 0x01) */ 6659 #define SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos (2UL) /*!< SDMMC EN_INT_SIGNAL_NORM: BLOCK_GAP_EVENT_EN (Bit 2) */ 6660 #define SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Msk (0x4UL) /*!< SDMMC EN_INT_SIGNAL_NORM: BLOCK_GAP_EVENT_EN (Bitfield-Mask: 0x01) */ 6661 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos (4UL) /*!< SDMMC EN_INT_SIGNAL_NORM: BUFF_WRITE_READY_EN (Bit 4) */ 6662 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Msk (0x10UL) /*!< SDMMC EN_INT_SIGNAL_NORM: BUFF_WRITE_READY_EN (Bitfield-Mask: 0x01) */ 6663 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos (5UL) /*!< SDMMC EN_INT_SIGNAL_NORM: BUFF_READ_READY_EN (Bit 5) */ 6664 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Msk (0x20UL) /*!< SDMMC EN_INT_SIGNAL_NORM: BUFF_READ_READY_EN (Bitfield-Mask: 0x01) */ 6665 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos (6UL) /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_INS_EN (Bit 6) */ 6666 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Msk (0x40UL) /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_INS_EN (Bitfield-Mask: 0x01) */ 6667 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos (7UL) /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_REMOVAL_EN (Bit 7) */ 6668 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Msk (0x80UL) /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_REMOVAL_EN (Bitfield-Mask: 0x01) */ 6669 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos (8UL) /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_INT_EN (Bit 8) */ 6670 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Msk (0x100UL) /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_INT_EN (Bitfield-Mask: 0x01) */ 6671 #define SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos (15UL) /*!< SDMMC EN_INT_SIGNAL_NORM: FIXED_TO_0 (Bit 15) */ 6672 #define SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Msk (0x8000UL) /*!< SDMMC EN_INT_SIGNAL_NORM: FIXED_TO_0 (Bitfield-Mask: 0x01) */ 6673 6674 /* --------------------------- SDMMC_EN_INT_SIGNAL_ERR -------------------------- */ 6675 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos (0UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_TIMEOUT_ERR_EN (Bit 0) */ 6676 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x1UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_TIMEOUT_ERR_EN (Bitfield-Mask: 0x01) */ 6677 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos (1UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_CRC_ERR_EN (Bit 1) */ 6678 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Msk (0x2UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_CRC_ERR_EN (Bitfield-Mask: 0x01) */ 6679 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos (2UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_END_BIT_ERR_EN (Bit 2) */ 6680 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Msk (0x4UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_END_BIT_ERR_EN (Bitfield-Mask: 0x01) */ 6681 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos (3UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_IND_ERR_EN (Bit 3) */ 6682 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Msk (0x8UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_IND_ERR_EN (Bitfield-Mask: 0x01) */ 6683 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos (4UL) /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_TIMEOUT_ERR_EN (Bit 4) */ 6684 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x10UL) /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_TIMEOUT_ERR_EN (Bitfield-Mask: 0x01) */ 6685 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos (5UL) /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_CRC_ERR_EN (Bit 5) */ 6686 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Msk (0x20UL) /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_CRC_ERR_EN (Bitfield-Mask: 0x01) */ 6687 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos (6UL) /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_END_BIT_ERR_EN (Bit 6) */ 6688 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Msk (0x40UL) /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_END_BIT_ERR_EN (Bitfield-Mask: 0x01) */ 6689 #define SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos (7UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CURRENT_LIMIT_ERR_EN (Bit 7) */ 6690 #define SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x80UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CURRENT_LIMIT_ERR_EN (Bitfield-Mask: 0x01) */ 6691 #define SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos (8UL) /*!< SDMMC EN_INT_SIGNAL_ERR: ACMD_ERR_EN (Bit 8) */ 6692 #define SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Msk (0x100UL) /*!< SDMMC EN_INT_SIGNAL_ERR: ACMD_ERR_EN (Bitfield-Mask: 0x01) */ 6693 #define SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos (12UL) /*!< SDMMC EN_INT_SIGNAL_ERR: TARGET_RESP_ERR_EN (Bit 12) */ 6694 #define SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Msk (0x1000UL) /*!< SDMMC EN_INT_SIGNAL_ERR: TARGET_RESP_ERR_EN (Bitfield-Mask: 0x01) */ 6695 #define SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos (13UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CEATA_ERR_EN (Bit 13) */ 6696 #define SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Msk (0x2000UL) /*!< SDMMC EN_INT_SIGNAL_ERR: CEATA_ERR_EN (Bitfield-Mask: 0x01) */ 6697 6698 /* ---------------------------- SDMMC_ACMD_ERR_STATUS --------------------------- */ 6699 #define SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos (0UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD12_NOT_EXEC_ERR (Bit 0) */ 6700 #define SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk (0x1UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD12_NOT_EXEC_ERR (Bitfield-Mask: 0x01) */ 6701 #define SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos (1UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD_TIMEOUT_ERR (Bit 1) */ 6702 #define SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk (0x2UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD_TIMEOUT_ERR (Bitfield-Mask: 0x01) */ 6703 #define SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos (2UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD_CRC_ERR (Bit 2) */ 6704 #define SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Msk (0x4UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD_CRC_ERR (Bitfield-Mask: 0x01) */ 6705 #define SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos (3UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD_END_BIT_ERR (Bit 3) */ 6706 #define SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Msk (0x8UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD_END_BIT_ERR (Bitfield-Mask: 0x01) */ 6707 #define SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos (4UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD_IND_ERR (Bit 4) */ 6708 #define SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Msk (0x10UL) /*!< SDMMC ACMD_ERR_STATUS: ACMD_IND_ERR (Bitfield-Mask: 0x01) */ 6709 #define SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos (7UL) /*!< SDMMC ACMD_ERR_STATUS: CMD_NOT_ISSUED_BY_ACMD12_ERR (Bit 7) */ 6710 #define SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Msk (0x80UL) /*!< SDMMC ACMD_ERR_STATUS: CMD_NOT_ISSUED_BY_ACMD12_ERR (Bitfield-Mask: 0x01) */ 6711 6712 /* ----------------------------- SDMMC_CAPABILITIES ----------------------------- */ 6713 #define SDMMC_CAPABILITIES_TIMEOUT_CLOCK_FREQ_Pos (0UL) /*!< SDMMC CAPABILITIES: TIMEOUT_CLOCK_FREQ (Bit 0) */ 6714 #define SDMMC_CAPABILITIES_TIMEOUT_CLOCK_FREQ_Msk (0x3fUL) /*!< SDMMC CAPABILITIES: TIMEOUT_CLOCK_FREQ (Bitfield-Mask: 0x3f) */ 6715 #define SDMMC_CAPABILITIES_TIMEOUT_CLOCK_UNIT_Pos (7UL) /*!< SDMMC CAPABILITIES: TIMEOUT_CLOCK_UNIT (Bit 7) */ 6716 #define SDMMC_CAPABILITIES_TIMEOUT_CLOCK_UNIT_Msk (0x80UL) /*!< SDMMC CAPABILITIES: TIMEOUT_CLOCK_UNIT (Bitfield-Mask: 0x01) */ 6717 #define SDMMC_CAPABILITIES_BASE_SD_CLOCK_FREQ_Pos (8UL) /*!< SDMMC CAPABILITIES: BASE_SD_CLOCK_FREQ (Bit 8) */ 6718 #define SDMMC_CAPABILITIES_BASE_SD_CLOCK_FREQ_Msk (0xff00UL) /*!< SDMMC CAPABILITIES: BASE_SD_CLOCK_FREQ (Bitfield-Mask: 0xff) */ 6719 #define SDMMC_CAPABILITIES_MAX_BLOCK_LENGTH_Pos (16UL) /*!< SDMMC CAPABILITIES: MAX_BLOCK_LENGTH (Bit 16) */ 6720 #define SDMMC_CAPABILITIES_MAX_BLOCK_LENGTH_Msk (0x30000UL) /*!< SDMMC CAPABILITIES: MAX_BLOCK_LENGTH (Bitfield-Mask: 0x03) */ 6721 #define SDMMC_CAPABILITIES_EXT_MEDIA_BUS_SUPPORT_Pos (18UL) /*!< SDMMC CAPABILITIES: EXT_MEDIA_BUS_SUPPORT (Bit 18) */ 6722 #define SDMMC_CAPABILITIES_EXT_MEDIA_BUS_SUPPORT_Msk (0x40000UL) /*!< SDMMC CAPABILITIES: EXT_MEDIA_BUS_SUPPORT (Bitfield-Mask: 0x01) */ 6723 #define SDMMC_CAPABILITIES_ADMA2_SUPPORT_Pos (19UL) /*!< SDMMC CAPABILITIES: ADMA2_SUPPORT (Bit 19) */ 6724 #define SDMMC_CAPABILITIES_ADMA2_SUPPORT_Msk (0x80000UL) /*!< SDMMC CAPABILITIES: ADMA2_SUPPORT (Bitfield-Mask: 0x01) */ 6725 #define SDMMC_CAPABILITIES_HIGH_SPEED_SUPPORT_Pos (21UL) /*!< SDMMC CAPABILITIES: HIGH_SPEED_SUPPORT (Bit 21) */ 6726 #define SDMMC_CAPABILITIES_HIGH_SPEED_SUPPORT_Msk (0x200000UL) /*!< SDMMC CAPABILITIES: HIGH_SPEED_SUPPORT (Bitfield-Mask: 0x01) */ 6727 #define SDMMC_CAPABILITIES_SDMA_SUPPORT_Pos (22UL) /*!< SDMMC CAPABILITIES: SDMA_SUPPORT (Bit 22) */ 6728 #define SDMMC_CAPABILITIES_SDMA_SUPPORT_Msk (0x400000UL) /*!< SDMMC CAPABILITIES: SDMA_SUPPORT (Bitfield-Mask: 0x01) */ 6729 #define SDMMC_CAPABILITIES_SUSPEND_RESUME_SUPPORT_Pos (23UL) /*!< SDMMC CAPABILITIES: SUSPEND_RESUME_SUPPORT (Bit 23) */ 6730 #define SDMMC_CAPABILITIES_SUSPEND_RESUME_SUPPORT_Msk (0x800000UL) /*!< SDMMC CAPABILITIES: SUSPEND_RESUME_SUPPORT (Bitfield-Mask: 0x01) */ 6731 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3_3V_Pos (24UL) /*!< SDMMC CAPABILITIES: VOLTAGE_SUPPORT_3_3V (Bit 24) */ 6732 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3_3V_Msk (0x1000000UL) /*!< SDMMC CAPABILITIES: VOLTAGE_SUPPORT_3_3V (Bitfield-Mask: 0x01) */ 6733 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3V_Pos (25UL) /*!< SDMMC CAPABILITIES: VOLTAGE_SUPPORT_3V (Bit 25) */ 6734 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3V_Msk (0x2000000UL) /*!< SDMMC CAPABILITIES: VOLTAGE_SUPPORT_3V (Bitfield-Mask: 0x01) */ 6735 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_1_8V_Pos (26UL) /*!< SDMMC CAPABILITIES: VOLTAGE_SUPPORT_1_8V (Bit 26) */ 6736 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_1_8V_Msk (0x4000000UL) /*!< SDMMC CAPABILITIES: VOLTAGE_SUPPORT_1_8V (Bitfield-Mask: 0x01) */ 6737 #define SDMMC_CAPABILITIES_SYSBUS_64_SUPPORT_Pos (28UL) /*!< SDMMC CAPABILITIES: SYSBUS_64_SUPPORT (Bit 28) */ 6738 #define SDMMC_CAPABILITIES_SYSBUS_64_SUPPORT_Msk (0x10000000UL) /*!< SDMMC CAPABILITIES: SYSBUS_64_SUPPORT (Bitfield-Mask: 0x01) */ 6739 #define SDMMC_CAPABILITIES_ASYNC_INT_SUPPORT_Pos (29UL) /*!< SDMMC CAPABILITIES: ASYNC_INT_SUPPORT (Bit 29) */ 6740 #define SDMMC_CAPABILITIES_ASYNC_INT_SUPPORT_Msk (0x20000000UL) /*!< SDMMC CAPABILITIES: ASYNC_INT_SUPPORT (Bitfield-Mask: 0x01) */ 6741 #define SDMMC_CAPABILITIES_SLOT_TYPE_Pos (30UL) /*!< SDMMC CAPABILITIES: SLOT_TYPE (Bit 30) */ 6742 #define SDMMC_CAPABILITIES_SLOT_TYPE_Msk (0xc0000000UL) /*!< SDMMC CAPABILITIES: SLOT_TYPE (Bitfield-Mask: 0x03) */ 6743 6744 /* ---------------------------- SDMMC_CAPABILITIES_HI --------------------------- */ 6745 #define SDMMC_CAPABILITIES_HI_SDR50_SUPPORT_Pos (0UL) /*!< SDMMC CAPABILITIES_HI: SDR50_SUPPORT (Bit 0) */ 6746 #define SDMMC_CAPABILITIES_HI_SDR50_SUPPORT_Msk (0x1UL) /*!< SDMMC CAPABILITIES_HI: SDR50_SUPPORT (Bitfield-Mask: 0x01) */ 6747 #define SDMMC_CAPABILITIES_HI_SDR104_SUPPORT_Pos (1UL) /*!< SDMMC CAPABILITIES_HI: SDR104_SUPPORT (Bit 1) */ 6748 #define SDMMC_CAPABILITIES_HI_SDR104_SUPPORT_Msk (0x2UL) /*!< SDMMC CAPABILITIES_HI: SDR104_SUPPORT (Bitfield-Mask: 0x01) */ 6749 #define SDMMC_CAPABILITIES_HI_DDR50_SUPPORT_Pos (2UL) /*!< SDMMC CAPABILITIES_HI: DDR50_SUPPORT (Bit 2) */ 6750 #define SDMMC_CAPABILITIES_HI_DDR50_SUPPORT_Msk (0x4UL) /*!< SDMMC CAPABILITIES_HI: DDR50_SUPPORT (Bitfield-Mask: 0x01) */ 6751 #define SDMMC_CAPABILITIES_HI_DRV_A_SUPPORT_Pos (4UL) /*!< SDMMC CAPABILITIES_HI: DRV_A_SUPPORT (Bit 4) */ 6752 #define SDMMC_CAPABILITIES_HI_DRV_A_SUPPORT_Msk (0x10UL) /*!< SDMMC CAPABILITIES_HI: DRV_A_SUPPORT (Bitfield-Mask: 0x01) */ 6753 #define SDMMC_CAPABILITIES_HI_DRV_C_SUPPORT_Pos (5UL) /*!< SDMMC CAPABILITIES_HI: DRV_C_SUPPORT (Bit 5) */ 6754 #define SDMMC_CAPABILITIES_HI_DRV_C_SUPPORT_Msk (0x20UL) /*!< SDMMC CAPABILITIES_HI: DRV_C_SUPPORT (Bitfield-Mask: 0x01) */ 6755 #define SDMMC_CAPABILITIES_HI_DRV_D_SUPPORT_Pos (6UL) /*!< SDMMC CAPABILITIES_HI: DRV_D_SUPPORT (Bit 6) */ 6756 #define SDMMC_CAPABILITIES_HI_DRV_D_SUPPORT_Msk (0x40UL) /*!< SDMMC CAPABILITIES_HI: DRV_D_SUPPORT (Bitfield-Mask: 0x01) */ 6757 #define SDMMC_CAPABILITIES_HI_TIM_CNT_RETUNE_Pos (8UL) /*!< SDMMC CAPABILITIES_HI: TIM_CNT_RETUNE (Bit 8) */ 6758 #define SDMMC_CAPABILITIES_HI_TIM_CNT_RETUNE_Msk (0xf00UL) /*!< SDMMC CAPABILITIES_HI: TIM_CNT_RETUNE (Bitfield-Mask: 0x0f) */ 6759 #define SDMMC_CAPABILITIES_HI_USE_TUNING_SDR50_Pos (13UL) /*!< SDMMC CAPABILITIES_HI: USE_TUNING_SDR50 (Bit 13) */ 6760 #define SDMMC_CAPABILITIES_HI_USE_TUNING_SDR50_Msk (0x2000UL) /*!< SDMMC CAPABILITIES_HI: USE_TUNING_SDR50 (Bitfield-Mask: 0x01) */ 6761 #define SDMMC_CAPABILITIES_HI_RE_TUNING_MODES_Pos (14UL) /*!< SDMMC CAPABILITIES_HI: RE_TUNING_MODES (Bit 14) */ 6762 #define SDMMC_CAPABILITIES_HI_RE_TUNING_MODES_Msk (0xc000UL) /*!< SDMMC CAPABILITIES_HI: RE_TUNING_MODES (Bitfield-Mask: 0x03) */ 6763 #define SDMMC_CAPABILITIES_HI_CLK_MULT_Pos (16UL) /*!< SDMMC CAPABILITIES_HI: CLK_MULT (Bit 16) */ 6764 #define SDMMC_CAPABILITIES_HI_CLK_MULT_Msk (0xff0000UL) /*!< SDMMC CAPABILITIES_HI: CLK_MULT (Bitfield-Mask: 0xff) */ 6765 6766 /* ---------------------------- SDMMC_MAX_CURRENT_CAP --------------------------- */ 6767 #define SDMMC_MAX_CURRENT_CAP_MAX_CURRENT_FOR_3_3V_Pos (0UL) /*!< SDMMC MAX_CURRENT_CAP: MAX_CURRENT_FOR_3_3V (Bit 0) */ 6768 #define SDMMC_MAX_CURRENT_CAP_MAX_CURRENT_FOR_3_3V_Msk (0xffUL) /*!< SDMMC MAX_CURRENT_CAP: MAX_CURRENT_FOR_3_3V (Bitfield-Mask: 0xff) */ 6769 6770 /* ---------------------- SDMMC_FORCE_EVENT_ACMD_ERR_STATUS --------------------- */ 6771 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos (0UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_NOT_EXEC (Bit 0) */ 6772 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Msk (0x1UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_NOT_EXEC (Bitfield-Mask: 0x01) */ 6773 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos (1UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_TIMEOUT_ERR (Bit 1) */ 6774 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Msk (0x2UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_TIMEOUT_ERR (Bitfield-Mask: 0x01) */ 6775 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos (2UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_CRC_ERR (Bit 2) */ 6776 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Msk (0x4UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_CRC_ERR (Bitfield-Mask: 0x01) */ 6777 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos (3UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_END_BIT_ERR (Bit 3) */ 6778 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Msk (0x8UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_END_BIT_ERR (Bitfield-Mask: 0x01) */ 6779 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos (4UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_IND_ERR (Bit 4) */ 6780 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Msk (0x10UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_IND_ERR (Bitfield-Mask: 0x01) */ 6781 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos (7UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_CMD_NOT_ISSUED_ACMD12_ERR (Bit 7) */ 6782 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Msk (0x80UL) /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_CMD_NOT_ISSUED_ACMD12_ERR (Bitfield-Mask: 0x01) */ 6783 6784 /* ------------------------ SDMMC_FORCE_EVENT_ERR_STATUS ------------------------ */ 6785 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos (0UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_TIMEOUT_ERR (Bit 0) */ 6786 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Msk (0x1UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_TIMEOUT_ERR (Bitfield-Mask: 0x01) */ 6787 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos (1UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_CRC_ERR (Bit 1) */ 6788 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Msk (0x2UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_CRC_ERR (Bitfield-Mask: 0x01) */ 6789 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos (2UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_END_BIT_ERR (Bit 2) */ 6790 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Msk (0x4UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_END_BIT_ERR (Bitfield-Mask: 0x01) */ 6791 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos (3UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_IND_ERR (Bit 3) */ 6792 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Msk (0x8UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_IND_ERR (Bitfield-Mask: 0x01) */ 6793 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos (4UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_TIMEOUT_ERR (Bit 4) */ 6794 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Msk (0x10UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_TIMEOUT_ERR (Bitfield-Mask: 0x01) */ 6795 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos (5UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_CRC_ERR (Bit 5) */ 6796 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Msk (0x20UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_CRC_ERR (Bitfield-Mask: 0x01) */ 6797 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos (6UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_END_BIT_ERR (Bit 6) */ 6798 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Msk (0x40UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_END_BIT_ERR (Bitfield-Mask: 0x01) */ 6799 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos (7UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CURRENT_LIMIT_ERR (Bit 7) */ 6800 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Msk (0x80UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CURRENT_LIMIT_ERR (Bitfield-Mask: 0x01) */ 6801 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos (8UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_ACMD12_ERR (Bit 8) */ 6802 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Msk (0x100UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_ACMD12_ERR (Bitfield-Mask: 0x01) */ 6803 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos (12UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_TARGET_RESPONSE_ERR (Bit 12) */ 6804 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Msk (0x1000UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_TARGET_RESPONSE_ERR (Bitfield-Mask: 0x01) */ 6805 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos (13UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CEATA_ERR (Bit 13) */ 6806 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Msk (0x2000UL) /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CEATA_ERR (Bitfield-Mask: 0x01) */ 6807 6808 /* ------------------------------- SDMMC_DEBUG_SEL ------------------------------ */ 6809 #define SDMMC_DEBUG_SEL_DEBUG_SEL_Pos (0UL) /*!< SDMMC DEBUG_SEL: DEBUG_SEL (Bit 0) */ 6810 #define SDMMC_DEBUG_SEL_DEBUG_SEL_Msk (0x1UL) /*!< SDMMC DEBUG_SEL: DEBUG_SEL (Bitfield-Mask: 0x01) */ 6811 6812 /* ---------------------------------- SDMMC_SPI --------------------------------- */ 6813 #define SDMMC_SPI_SPI_INT_SUPPORT_Pos (0UL) /*!< SDMMC SPI: SPI_INT_SUPPORT (Bit 0) */ 6814 #define SDMMC_SPI_SPI_INT_SUPPORT_Msk (0xffUL) /*!< SDMMC SPI: SPI_INT_SUPPORT (Bitfield-Mask: 0xff) */ 6815 6816 /* ---------------------------- SDMMC_SLOT_INT_STATUS --------------------------- */ 6817 #define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos (0UL) /*!< SDMMC SLOT_INT_STATUS: SLOT_INT_STATUS (Bit 0) */ 6818 #define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Msk (0xffUL) /*!< SDMMC SLOT_INT_STATUS: SLOT_INT_STATUS (Bitfield-Mask: 0xff) */ 6819 6820 6821 /* ================================================================================ */ 6822 /* ================ struct 'EBU' Position & Mask ================ */ 6823 /* ================================================================================ */ 6824 6825 6826 /* ----------------------------------- EBU_CLC ---------------------------------- */ 6827 #define EBU_CLC_DISR_Pos (0UL) /*!< EBU CLC: DISR (Bit 0) */ 6828 #define EBU_CLC_DISR_Msk (0x1UL) /*!< EBU CLC: DISR (Bitfield-Mask: 0x01) */ 6829 #define EBU_CLC_DISS_Pos (1UL) /*!< EBU CLC: DISS (Bit 1) */ 6830 #define EBU_CLC_DISS_Msk (0x2UL) /*!< EBU CLC: DISS (Bitfield-Mask: 0x01) */ 6831 #define EBU_CLC_SYNC_Pos (16UL) /*!< EBU CLC: SYNC (Bit 16) */ 6832 #define EBU_CLC_SYNC_Msk (0x10000UL) /*!< EBU CLC: SYNC (Bitfield-Mask: 0x01) */ 6833 #define EBU_CLC_DIV2_Pos (17UL) /*!< EBU CLC: DIV2 (Bit 17) */ 6834 #define EBU_CLC_DIV2_Msk (0x20000UL) /*!< EBU CLC: DIV2 (Bitfield-Mask: 0x01) */ 6835 #define EBU_CLC_EBUDIV_Pos (18UL) /*!< EBU CLC: EBUDIV (Bit 18) */ 6836 #define EBU_CLC_EBUDIV_Msk (0xc0000UL) /*!< EBU CLC: EBUDIV (Bitfield-Mask: 0x03) */ 6837 #define EBU_CLC_SYNCACK_Pos (20UL) /*!< EBU CLC: SYNCACK (Bit 20) */ 6838 #define EBU_CLC_SYNCACK_Msk (0x100000UL) /*!< EBU CLC: SYNCACK (Bitfield-Mask: 0x01) */ 6839 #define EBU_CLC_DIV2ACK_Pos (21UL) /*!< EBU CLC: DIV2ACK (Bit 21) */ 6840 #define EBU_CLC_DIV2ACK_Msk (0x200000UL) /*!< EBU CLC: DIV2ACK (Bitfield-Mask: 0x01) */ 6841 #define EBU_CLC_EBUDIVACK_Pos (22UL) /*!< EBU CLC: EBUDIVACK (Bit 22) */ 6842 #define EBU_CLC_EBUDIVACK_Msk (0xc00000UL) /*!< EBU CLC: EBUDIVACK (Bitfield-Mask: 0x03) */ 6843 6844 /* --------------------------------- EBU_MODCON --------------------------------- */ 6845 #define EBU_MODCON_STS_Pos (0UL) /*!< EBU MODCON: STS (Bit 0) */ 6846 #define EBU_MODCON_STS_Msk (0x1UL) /*!< EBU MODCON: STS (Bitfield-Mask: 0x01) */ 6847 #define EBU_MODCON_LCKABRT_Pos (1UL) /*!< EBU MODCON: LCKABRT (Bit 1) */ 6848 #define EBU_MODCON_LCKABRT_Msk (0x2UL) /*!< EBU MODCON: LCKABRT (Bitfield-Mask: 0x01) */ 6849 #define EBU_MODCON_SDTRI_Pos (2UL) /*!< EBU MODCON: SDTRI (Bit 2) */ 6850 #define EBU_MODCON_SDTRI_Msk (0x4UL) /*!< EBU MODCON: SDTRI (Bitfield-Mask: 0x01) */ 6851 #define EBU_MODCON_EXTLOCK_Pos (4UL) /*!< EBU MODCON: EXTLOCK (Bit 4) */ 6852 #define EBU_MODCON_EXTLOCK_Msk (0x10UL) /*!< EBU MODCON: EXTLOCK (Bitfield-Mask: 0x01) */ 6853 #define EBU_MODCON_ARBSYNC_Pos (5UL) /*!< EBU MODCON: ARBSYNC (Bit 5) */ 6854 #define EBU_MODCON_ARBSYNC_Msk (0x20UL) /*!< EBU MODCON: ARBSYNC (Bitfield-Mask: 0x01) */ 6855 #define EBU_MODCON_ARBMODE_Pos (6UL) /*!< EBU MODCON: ARBMODE (Bit 6) */ 6856 #define EBU_MODCON_ARBMODE_Msk (0xc0UL) /*!< EBU MODCON: ARBMODE (Bitfield-Mask: 0x03) */ 6857 #define EBU_MODCON_TIMEOUTC_Pos (8UL) /*!< EBU MODCON: TIMEOUTC (Bit 8) */ 6858 #define EBU_MODCON_TIMEOUTC_Msk (0xff00UL) /*!< EBU MODCON: TIMEOUTC (Bitfield-Mask: 0xff) */ 6859 #define EBU_MODCON_LOCKTIMEOUT_Pos (16UL) /*!< EBU MODCON: LOCKTIMEOUT (Bit 16) */ 6860 #define EBU_MODCON_LOCKTIMEOUT_Msk (0xff0000UL) /*!< EBU MODCON: LOCKTIMEOUT (Bitfield-Mask: 0xff) */ 6861 #define EBU_MODCON_GLOBALCS_Pos (24UL) /*!< EBU MODCON: GLOBALCS (Bit 24) */ 6862 #define EBU_MODCON_GLOBALCS_Msk (0xf000000UL) /*!< EBU MODCON: GLOBALCS (Bitfield-Mask: 0x0f) */ 6863 #define EBU_MODCON_ACCSINH_Pos (28UL) /*!< EBU MODCON: ACCSINH (Bit 28) */ 6864 #define EBU_MODCON_ACCSINH_Msk (0x10000000UL) /*!< EBU MODCON: ACCSINH (Bitfield-Mask: 0x01) */ 6865 #define EBU_MODCON_ACCSINHACK_Pos (29UL) /*!< EBU MODCON: ACCSINHACK (Bit 29) */ 6866 #define EBU_MODCON_ACCSINHACK_Msk (0x20000000UL) /*!< EBU MODCON: ACCSINHACK (Bitfield-Mask: 0x01) */ 6867 #define EBU_MODCON_ALE_Pos (31UL) /*!< EBU MODCON: ALE (Bit 31) */ 6868 #define EBU_MODCON_ALE_Msk (0x80000000UL) /*!< EBU MODCON: ALE (Bitfield-Mask: 0x01) */ 6869 6870 /* ----------------------------------- EBU_ID ----------------------------------- */ 6871 #define EBU_ID_MOD_REV_Pos (0UL) /*!< EBU ID: MOD_REV (Bit 0) */ 6872 #define EBU_ID_MOD_REV_Msk (0xffUL) /*!< EBU ID: MOD_REV (Bitfield-Mask: 0xff) */ 6873 #define EBU_ID_MOD_TYPE_Pos (8UL) /*!< EBU ID: MOD_TYPE (Bit 8) */ 6874 #define EBU_ID_MOD_TYPE_Msk (0xff00UL) /*!< EBU ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 6875 #define EBU_ID_MOD_NUMBER_Pos (16UL) /*!< EBU ID: MOD_NUMBER (Bit 16) */ 6876 #define EBU_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< EBU ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 6877 6878 /* --------------------------------- EBU_USERCON -------------------------------- */ 6879 #define EBU_USERCON_DIP_Pos (0UL) /*!< EBU USERCON: DIP (Bit 0) */ 6880 #define EBU_USERCON_DIP_Msk (0x1UL) /*!< EBU USERCON: DIP (Bitfield-Mask: 0x01) */ 6881 #define EBU_USERCON_ADDIO_Pos (16UL) /*!< EBU USERCON: ADDIO (Bit 16) */ 6882 #define EBU_USERCON_ADDIO_Msk (0x1ff0000UL) /*!< EBU USERCON: ADDIO (Bitfield-Mask: 0x1ff) */ 6883 #define EBU_USERCON_ADVIO_Pos (25UL) /*!< EBU USERCON: ADVIO (Bit 25) */ 6884 #define EBU_USERCON_ADVIO_Msk (0x2000000UL) /*!< EBU USERCON: ADVIO (Bitfield-Mask: 0x01) */ 6885 6886 /* -------------------------------- EBU_ADDRSEL0 -------------------------------- */ 6887 #define EBU_ADDRSEL0_REGENAB_Pos (0UL) /*!< EBU ADDRSEL0: REGENAB (Bit 0) */ 6888 #define EBU_ADDRSEL0_REGENAB_Msk (0x1UL) /*!< EBU ADDRSEL0: REGENAB (Bitfield-Mask: 0x01) */ 6889 #define EBU_ADDRSEL0_ALTENAB_Pos (1UL) /*!< EBU ADDRSEL0: ALTENAB (Bit 1) */ 6890 #define EBU_ADDRSEL0_ALTENAB_Msk (0x2UL) /*!< EBU ADDRSEL0: ALTENAB (Bitfield-Mask: 0x01) */ 6891 #define EBU_ADDRSEL0_WPROT_Pos (2UL) /*!< EBU ADDRSEL0: WPROT (Bit 2) */ 6892 #define EBU_ADDRSEL0_WPROT_Msk (0x4UL) /*!< EBU ADDRSEL0: WPROT (Bitfield-Mask: 0x01) */ 6893 6894 /* -------------------------------- EBU_ADDRSEL1 -------------------------------- */ 6895 #define EBU_ADDRSEL1_REGENAB_Pos (0UL) /*!< EBU ADDRSEL1: REGENAB (Bit 0) */ 6896 #define EBU_ADDRSEL1_REGENAB_Msk (0x1UL) /*!< EBU ADDRSEL1: REGENAB (Bitfield-Mask: 0x01) */ 6897 #define EBU_ADDRSEL1_ALTENAB_Pos (1UL) /*!< EBU ADDRSEL1: ALTENAB (Bit 1) */ 6898 #define EBU_ADDRSEL1_ALTENAB_Msk (0x2UL) /*!< EBU ADDRSEL1: ALTENAB (Bitfield-Mask: 0x01) */ 6899 #define EBU_ADDRSEL1_WPROT_Pos (2UL) /*!< EBU ADDRSEL1: WPROT (Bit 2) */ 6900 #define EBU_ADDRSEL1_WPROT_Msk (0x4UL) /*!< EBU ADDRSEL1: WPROT (Bitfield-Mask: 0x01) */ 6901 6902 /* -------------------------------- EBU_ADDRSEL2 -------------------------------- */ 6903 #define EBU_ADDRSEL2_REGENAB_Pos (0UL) /*!< EBU ADDRSEL2: REGENAB (Bit 0) */ 6904 #define EBU_ADDRSEL2_REGENAB_Msk (0x1UL) /*!< EBU ADDRSEL2: REGENAB (Bitfield-Mask: 0x01) */ 6905 #define EBU_ADDRSEL2_ALTENAB_Pos (1UL) /*!< EBU ADDRSEL2: ALTENAB (Bit 1) */ 6906 #define EBU_ADDRSEL2_ALTENAB_Msk (0x2UL) /*!< EBU ADDRSEL2: ALTENAB (Bitfield-Mask: 0x01) */ 6907 #define EBU_ADDRSEL2_WPROT_Pos (2UL) /*!< EBU ADDRSEL2: WPROT (Bit 2) */ 6908 #define EBU_ADDRSEL2_WPROT_Msk (0x4UL) /*!< EBU ADDRSEL2: WPROT (Bitfield-Mask: 0x01) */ 6909 6910 /* -------------------------------- EBU_ADDRSEL3 -------------------------------- */ 6911 #define EBU_ADDRSEL3_REGENAB_Pos (0UL) /*!< EBU ADDRSEL3: REGENAB (Bit 0) */ 6912 #define EBU_ADDRSEL3_REGENAB_Msk (0x1UL) /*!< EBU ADDRSEL3: REGENAB (Bitfield-Mask: 0x01) */ 6913 #define EBU_ADDRSEL3_ALTENAB_Pos (1UL) /*!< EBU ADDRSEL3: ALTENAB (Bit 1) */ 6914 #define EBU_ADDRSEL3_ALTENAB_Msk (0x2UL) /*!< EBU ADDRSEL3: ALTENAB (Bitfield-Mask: 0x01) */ 6915 #define EBU_ADDRSEL3_WPROT_Pos (2UL) /*!< EBU ADDRSEL3: WPROT (Bit 2) */ 6916 #define EBU_ADDRSEL3_WPROT_Msk (0x4UL) /*!< EBU ADDRSEL3: WPROT (Bitfield-Mask: 0x01) */ 6917 6918 /* -------------------------------- EBU_BUSRCON0 -------------------------------- */ 6919 #define EBU_BUSRCON0_FETBLEN_Pos (0UL) /*!< EBU BUSRCON0: FETBLEN (Bit 0) */ 6920 #define EBU_BUSRCON0_FETBLEN_Msk (0x7UL) /*!< EBU BUSRCON0: FETBLEN (Bitfield-Mask: 0x07) */ 6921 #define EBU_BUSRCON0_FBBMSEL_Pos (3UL) /*!< EBU BUSRCON0: FBBMSEL (Bit 3) */ 6922 #define EBU_BUSRCON0_FBBMSEL_Msk (0x8UL) /*!< EBU BUSRCON0: FBBMSEL (Bitfield-Mask: 0x01) */ 6923 #define EBU_BUSRCON0_BFSSS_Pos (4UL) /*!< EBU BUSRCON0: BFSSS (Bit 4) */ 6924 #define EBU_BUSRCON0_BFSSS_Msk (0x10UL) /*!< EBU BUSRCON0: BFSSS (Bitfield-Mask: 0x01) */ 6925 #define EBU_BUSRCON0_FDBKEN_Pos (5UL) /*!< EBU BUSRCON0: FDBKEN (Bit 5) */ 6926 #define EBU_BUSRCON0_FDBKEN_Msk (0x20UL) /*!< EBU BUSRCON0: FDBKEN (Bitfield-Mask: 0x01) */ 6927 #define EBU_BUSRCON0_BFCMSEL_Pos (6UL) /*!< EBU BUSRCON0: BFCMSEL (Bit 6) */ 6928 #define EBU_BUSRCON0_BFCMSEL_Msk (0x40UL) /*!< EBU BUSRCON0: BFCMSEL (Bitfield-Mask: 0x01) */ 6929 #define EBU_BUSRCON0_NAA_Pos (7UL) /*!< EBU BUSRCON0: NAA (Bit 7) */ 6930 #define EBU_BUSRCON0_NAA_Msk (0x80UL) /*!< EBU BUSRCON0: NAA (Bitfield-Mask: 0x01) */ 6931 #define EBU_BUSRCON0_ECSE_Pos (16UL) /*!< EBU BUSRCON0: ECSE (Bit 16) */ 6932 #define EBU_BUSRCON0_ECSE_Msk (0x10000UL) /*!< EBU BUSRCON0: ECSE (Bitfield-Mask: 0x01) */ 6933 #define EBU_BUSRCON0_EBSE_Pos (17UL) /*!< EBU BUSRCON0: EBSE (Bit 17) */ 6934 #define EBU_BUSRCON0_EBSE_Msk (0x20000UL) /*!< EBU BUSRCON0: EBSE (Bitfield-Mask: 0x01) */ 6935 #define EBU_BUSRCON0_DBA_Pos (18UL) /*!< EBU BUSRCON0: DBA (Bit 18) */ 6936 #define EBU_BUSRCON0_DBA_Msk (0x40000UL) /*!< EBU BUSRCON0: DBA (Bitfield-Mask: 0x01) */ 6937 #define EBU_BUSRCON0_WAITINV_Pos (19UL) /*!< EBU BUSRCON0: WAITINV (Bit 19) */ 6938 #define EBU_BUSRCON0_WAITINV_Msk (0x80000UL) /*!< EBU BUSRCON0: WAITINV (Bitfield-Mask: 0x01) */ 6939 #define EBU_BUSRCON0_BCGEN_Pos (20UL) /*!< EBU BUSRCON0: BCGEN (Bit 20) */ 6940 #define EBU_BUSRCON0_BCGEN_Msk (0x300000UL) /*!< EBU BUSRCON0: BCGEN (Bitfield-Mask: 0x03) */ 6941 #define EBU_BUSRCON0_PORTW_Pos (22UL) /*!< EBU BUSRCON0: PORTW (Bit 22) */ 6942 #define EBU_BUSRCON0_PORTW_Msk (0xc00000UL) /*!< EBU BUSRCON0: PORTW (Bitfield-Mask: 0x03) */ 6943 #define EBU_BUSRCON0_WAIT_Pos (24UL) /*!< EBU BUSRCON0: WAIT (Bit 24) */ 6944 #define EBU_BUSRCON0_WAIT_Msk (0x3000000UL) /*!< EBU BUSRCON0: WAIT (Bitfield-Mask: 0x03) */ 6945 #define EBU_BUSRCON0_AAP_Pos (26UL) /*!< EBU BUSRCON0: AAP (Bit 26) */ 6946 #define EBU_BUSRCON0_AAP_Msk (0x4000000UL) /*!< EBU BUSRCON0: AAP (Bitfield-Mask: 0x01) */ 6947 #define EBU_BUSRCON0_AGEN_Pos (28UL) /*!< EBU BUSRCON0: AGEN (Bit 28) */ 6948 #define EBU_BUSRCON0_AGEN_Msk (0xf0000000UL) /*!< EBU BUSRCON0: AGEN (Bitfield-Mask: 0x0f) */ 6949 6950 /* --------------------------------- EBU_BUSRAP0 -------------------------------- */ 6951 #define EBU_BUSRAP0_RDDTACS_Pos (0UL) /*!< EBU BUSRAP0: RDDTACS (Bit 0) */ 6952 #define EBU_BUSRAP0_RDDTACS_Msk (0xfUL) /*!< EBU BUSRAP0: RDDTACS (Bitfield-Mask: 0x0f) */ 6953 #define EBU_BUSRAP0_RDRECOVC_Pos (4UL) /*!< EBU BUSRAP0: RDRECOVC (Bit 4) */ 6954 #define EBU_BUSRAP0_RDRECOVC_Msk (0x70UL) /*!< EBU BUSRAP0: RDRECOVC (Bitfield-Mask: 0x07) */ 6955 #define EBU_BUSRAP0_WAITRDC_Pos (7UL) /*!< EBU BUSRAP0: WAITRDC (Bit 7) */ 6956 #define EBU_BUSRAP0_WAITRDC_Msk (0xf80UL) /*!< EBU BUSRAP0: WAITRDC (Bitfield-Mask: 0x1f) */ 6957 #define EBU_BUSRAP0_DATAC_Pos (12UL) /*!< EBU BUSRAP0: DATAC (Bit 12) */ 6958 #define EBU_BUSRAP0_DATAC_Msk (0xf000UL) /*!< EBU BUSRAP0: DATAC (Bitfield-Mask: 0x0f) */ 6959 #define EBU_BUSRAP0_EXTCLOCK_Pos (16UL) /*!< EBU BUSRAP0: EXTCLOCK (Bit 16) */ 6960 #define EBU_BUSRAP0_EXTCLOCK_Msk (0x30000UL) /*!< EBU BUSRAP0: EXTCLOCK (Bitfield-Mask: 0x03) */ 6961 #define EBU_BUSRAP0_EXTDATA_Pos (18UL) /*!< EBU BUSRAP0: EXTDATA (Bit 18) */ 6962 #define EBU_BUSRAP0_EXTDATA_Msk (0xc0000UL) /*!< EBU BUSRAP0: EXTDATA (Bitfield-Mask: 0x03) */ 6963 #define EBU_BUSRAP0_CMDDELAY_Pos (20UL) /*!< EBU BUSRAP0: CMDDELAY (Bit 20) */ 6964 #define EBU_BUSRAP0_CMDDELAY_Msk (0xf00000UL) /*!< EBU BUSRAP0: CMDDELAY (Bitfield-Mask: 0x0f) */ 6965 #define EBU_BUSRAP0_AHOLDC_Pos (24UL) /*!< EBU BUSRAP0: AHOLDC (Bit 24) */ 6966 #define EBU_BUSRAP0_AHOLDC_Msk (0xf000000UL) /*!< EBU BUSRAP0: AHOLDC (Bitfield-Mask: 0x0f) */ 6967 #define EBU_BUSRAP0_ADDRC_Pos (28UL) /*!< EBU BUSRAP0: ADDRC (Bit 28) */ 6968 #define EBU_BUSRAP0_ADDRC_Msk (0xf0000000UL) /*!< EBU BUSRAP0: ADDRC (Bitfield-Mask: 0x0f) */ 6969 6970 /* -------------------------------- EBU_BUSWCON0 -------------------------------- */ 6971 #define EBU_BUSWCON0_FETBLEN_Pos (0UL) /*!< EBU BUSWCON0: FETBLEN (Bit 0) */ 6972 #define EBU_BUSWCON0_FETBLEN_Msk (0x7UL) /*!< EBU BUSWCON0: FETBLEN (Bitfield-Mask: 0x07) */ 6973 #define EBU_BUSWCON0_FBBMSEL_Pos (3UL) /*!< EBU BUSWCON0: FBBMSEL (Bit 3) */ 6974 #define EBU_BUSWCON0_FBBMSEL_Msk (0x8UL) /*!< EBU BUSWCON0: FBBMSEL (Bitfield-Mask: 0x01) */ 6975 #define EBU_BUSWCON0_NAA_Pos (7UL) /*!< EBU BUSWCON0: NAA (Bit 7) */ 6976 #define EBU_BUSWCON0_NAA_Msk (0x80UL) /*!< EBU BUSWCON0: NAA (Bitfield-Mask: 0x01) */ 6977 #define EBU_BUSWCON0_ECSE_Pos (16UL) /*!< EBU BUSWCON0: ECSE (Bit 16) */ 6978 #define EBU_BUSWCON0_ECSE_Msk (0x10000UL) /*!< EBU BUSWCON0: ECSE (Bitfield-Mask: 0x01) */ 6979 #define EBU_BUSWCON0_EBSE_Pos (17UL) /*!< EBU BUSWCON0: EBSE (Bit 17) */ 6980 #define EBU_BUSWCON0_EBSE_Msk (0x20000UL) /*!< EBU BUSWCON0: EBSE (Bitfield-Mask: 0x01) */ 6981 #define EBU_BUSWCON0_WAITINV_Pos (19UL) /*!< EBU BUSWCON0: WAITINV (Bit 19) */ 6982 #define EBU_BUSWCON0_WAITINV_Msk (0x80000UL) /*!< EBU BUSWCON0: WAITINV (Bitfield-Mask: 0x01) */ 6983 #define EBU_BUSWCON0_BCGEN_Pos (20UL) /*!< EBU BUSWCON0: BCGEN (Bit 20) */ 6984 #define EBU_BUSWCON0_BCGEN_Msk (0x300000UL) /*!< EBU BUSWCON0: BCGEN (Bitfield-Mask: 0x03) */ 6985 #define EBU_BUSWCON0_PORTW_Pos (22UL) /*!< EBU BUSWCON0: PORTW (Bit 22) */ 6986 #define EBU_BUSWCON0_PORTW_Msk (0xc00000UL) /*!< EBU BUSWCON0: PORTW (Bitfield-Mask: 0x03) */ 6987 #define EBU_BUSWCON0_WAIT_Pos (24UL) /*!< EBU BUSWCON0: WAIT (Bit 24) */ 6988 #define EBU_BUSWCON0_WAIT_Msk (0x3000000UL) /*!< EBU BUSWCON0: WAIT (Bitfield-Mask: 0x03) */ 6989 #define EBU_BUSWCON0_AAP_Pos (26UL) /*!< EBU BUSWCON0: AAP (Bit 26) */ 6990 #define EBU_BUSWCON0_AAP_Msk (0x4000000UL) /*!< EBU BUSWCON0: AAP (Bitfield-Mask: 0x01) */ 6991 #define EBU_BUSWCON0_LOCKCS_Pos (27UL) /*!< EBU BUSWCON0: LOCKCS (Bit 27) */ 6992 #define EBU_BUSWCON0_LOCKCS_Msk (0x8000000UL) /*!< EBU BUSWCON0: LOCKCS (Bitfield-Mask: 0x01) */ 6993 #define EBU_BUSWCON0_AGEN_Pos (28UL) /*!< EBU BUSWCON0: AGEN (Bit 28) */ 6994 #define EBU_BUSWCON0_AGEN_Msk (0xf0000000UL) /*!< EBU BUSWCON0: AGEN (Bitfield-Mask: 0x0f) */ 6995 6996 /* --------------------------------- EBU_BUSWAP0 -------------------------------- */ 6997 #define EBU_BUSWAP0_WRDTACS_Pos (0UL) /*!< EBU BUSWAP0: WRDTACS (Bit 0) */ 6998 #define EBU_BUSWAP0_WRDTACS_Msk (0xfUL) /*!< EBU BUSWAP0: WRDTACS (Bitfield-Mask: 0x0f) */ 6999 #define EBU_BUSWAP0_WRRECOVC_Pos (4UL) /*!< EBU BUSWAP0: WRRECOVC (Bit 4) */ 7000 #define EBU_BUSWAP0_WRRECOVC_Msk (0x70UL) /*!< EBU BUSWAP0: WRRECOVC (Bitfield-Mask: 0x07) */ 7001 #define EBU_BUSWAP0_WAITWRC_Pos (7UL) /*!< EBU BUSWAP0: WAITWRC (Bit 7) */ 7002 #define EBU_BUSWAP0_WAITWRC_Msk (0xf80UL) /*!< EBU BUSWAP0: WAITWRC (Bitfield-Mask: 0x1f) */ 7003 #define EBU_BUSWAP0_DATAC_Pos (12UL) /*!< EBU BUSWAP0: DATAC (Bit 12) */ 7004 #define EBU_BUSWAP0_DATAC_Msk (0xf000UL) /*!< EBU BUSWAP0: DATAC (Bitfield-Mask: 0x0f) */ 7005 #define EBU_BUSWAP0_EXTCLOCK_Pos (16UL) /*!< EBU BUSWAP0: EXTCLOCK (Bit 16) */ 7006 #define EBU_BUSWAP0_EXTCLOCK_Msk (0x30000UL) /*!< EBU BUSWAP0: EXTCLOCK (Bitfield-Mask: 0x03) */ 7007 #define EBU_BUSWAP0_EXTDATA_Pos (18UL) /*!< EBU BUSWAP0: EXTDATA (Bit 18) */ 7008 #define EBU_BUSWAP0_EXTDATA_Msk (0xc0000UL) /*!< EBU BUSWAP0: EXTDATA (Bitfield-Mask: 0x03) */ 7009 #define EBU_BUSWAP0_CMDDELAY_Pos (20UL) /*!< EBU BUSWAP0: CMDDELAY (Bit 20) */ 7010 #define EBU_BUSWAP0_CMDDELAY_Msk (0xf00000UL) /*!< EBU BUSWAP0: CMDDELAY (Bitfield-Mask: 0x0f) */ 7011 #define EBU_BUSWAP0_AHOLDC_Pos (24UL) /*!< EBU BUSWAP0: AHOLDC (Bit 24) */ 7012 #define EBU_BUSWAP0_AHOLDC_Msk (0xf000000UL) /*!< EBU BUSWAP0: AHOLDC (Bitfield-Mask: 0x0f) */ 7013 #define EBU_BUSWAP0_ADDRC_Pos (28UL) /*!< EBU BUSWAP0: ADDRC (Bit 28) */ 7014 #define EBU_BUSWAP0_ADDRC_Msk (0xf0000000UL) /*!< EBU BUSWAP0: ADDRC (Bitfield-Mask: 0x0f) */ 7015 7016 /* -------------------------------- EBU_BUSRCON1 -------------------------------- */ 7017 #define EBU_BUSRCON1_FETBLEN_Pos (0UL) /*!< EBU BUSRCON1: FETBLEN (Bit 0) */ 7018 #define EBU_BUSRCON1_FETBLEN_Msk (0x7UL) /*!< EBU BUSRCON1: FETBLEN (Bitfield-Mask: 0x07) */ 7019 #define EBU_BUSRCON1_FBBMSEL_Pos (3UL) /*!< EBU BUSRCON1: FBBMSEL (Bit 3) */ 7020 #define EBU_BUSRCON1_FBBMSEL_Msk (0x8UL) /*!< EBU BUSRCON1: FBBMSEL (Bitfield-Mask: 0x01) */ 7021 #define EBU_BUSRCON1_BFSSS_Pos (4UL) /*!< EBU BUSRCON1: BFSSS (Bit 4) */ 7022 #define EBU_BUSRCON1_BFSSS_Msk (0x10UL) /*!< EBU BUSRCON1: BFSSS (Bitfield-Mask: 0x01) */ 7023 #define EBU_BUSRCON1_FDBKEN_Pos (5UL) /*!< EBU BUSRCON1: FDBKEN (Bit 5) */ 7024 #define EBU_BUSRCON1_FDBKEN_Msk (0x20UL) /*!< EBU BUSRCON1: FDBKEN (Bitfield-Mask: 0x01) */ 7025 #define EBU_BUSRCON1_BFCMSEL_Pos (6UL) /*!< EBU BUSRCON1: BFCMSEL (Bit 6) */ 7026 #define EBU_BUSRCON1_BFCMSEL_Msk (0x40UL) /*!< EBU BUSRCON1: BFCMSEL (Bitfield-Mask: 0x01) */ 7027 #define EBU_BUSRCON1_NAA_Pos (7UL) /*!< EBU BUSRCON1: NAA (Bit 7) */ 7028 #define EBU_BUSRCON1_NAA_Msk (0x80UL) /*!< EBU BUSRCON1: NAA (Bitfield-Mask: 0x01) */ 7029 #define EBU_BUSRCON1_ECSE_Pos (16UL) /*!< EBU BUSRCON1: ECSE (Bit 16) */ 7030 #define EBU_BUSRCON1_ECSE_Msk (0x10000UL) /*!< EBU BUSRCON1: ECSE (Bitfield-Mask: 0x01) */ 7031 #define EBU_BUSRCON1_EBSE_Pos (17UL) /*!< EBU BUSRCON1: EBSE (Bit 17) */ 7032 #define EBU_BUSRCON1_EBSE_Msk (0x20000UL) /*!< EBU BUSRCON1: EBSE (Bitfield-Mask: 0x01) */ 7033 #define EBU_BUSRCON1_DBA_Pos (18UL) /*!< EBU BUSRCON1: DBA (Bit 18) */ 7034 #define EBU_BUSRCON1_DBA_Msk (0x40000UL) /*!< EBU BUSRCON1: DBA (Bitfield-Mask: 0x01) */ 7035 #define EBU_BUSRCON1_WAITINV_Pos (19UL) /*!< EBU BUSRCON1: WAITINV (Bit 19) */ 7036 #define EBU_BUSRCON1_WAITINV_Msk (0x80000UL) /*!< EBU BUSRCON1: WAITINV (Bitfield-Mask: 0x01) */ 7037 #define EBU_BUSRCON1_BCGEN_Pos (20UL) /*!< EBU BUSRCON1: BCGEN (Bit 20) */ 7038 #define EBU_BUSRCON1_BCGEN_Msk (0x300000UL) /*!< EBU BUSRCON1: BCGEN (Bitfield-Mask: 0x03) */ 7039 #define EBU_BUSRCON1_PORTW_Pos (22UL) /*!< EBU BUSRCON1: PORTW (Bit 22) */ 7040 #define EBU_BUSRCON1_PORTW_Msk (0xc00000UL) /*!< EBU BUSRCON1: PORTW (Bitfield-Mask: 0x03) */ 7041 #define EBU_BUSRCON1_WAIT_Pos (24UL) /*!< EBU BUSRCON1: WAIT (Bit 24) */ 7042 #define EBU_BUSRCON1_WAIT_Msk (0x3000000UL) /*!< EBU BUSRCON1: WAIT (Bitfield-Mask: 0x03) */ 7043 #define EBU_BUSRCON1_AAP_Pos (26UL) /*!< EBU BUSRCON1: AAP (Bit 26) */ 7044 #define EBU_BUSRCON1_AAP_Msk (0x4000000UL) /*!< EBU BUSRCON1: AAP (Bitfield-Mask: 0x01) */ 7045 #define EBU_BUSRCON1_AGEN_Pos (28UL) /*!< EBU BUSRCON1: AGEN (Bit 28) */ 7046 #define EBU_BUSRCON1_AGEN_Msk (0xf0000000UL) /*!< EBU BUSRCON1: AGEN (Bitfield-Mask: 0x0f) */ 7047 7048 /* --------------------------------- EBU_BUSRAP1 -------------------------------- */ 7049 #define EBU_BUSRAP1_RDDTACS_Pos (0UL) /*!< EBU BUSRAP1: RDDTACS (Bit 0) */ 7050 #define EBU_BUSRAP1_RDDTACS_Msk (0xfUL) /*!< EBU BUSRAP1: RDDTACS (Bitfield-Mask: 0x0f) */ 7051 #define EBU_BUSRAP1_RDRECOVC_Pos (4UL) /*!< EBU BUSRAP1: RDRECOVC (Bit 4) */ 7052 #define EBU_BUSRAP1_RDRECOVC_Msk (0x70UL) /*!< EBU BUSRAP1: RDRECOVC (Bitfield-Mask: 0x07) */ 7053 #define EBU_BUSRAP1_WAITRDC_Pos (7UL) /*!< EBU BUSRAP1: WAITRDC (Bit 7) */ 7054 #define EBU_BUSRAP1_WAITRDC_Msk (0xf80UL) /*!< EBU BUSRAP1: WAITRDC (Bitfield-Mask: 0x1f) */ 7055 #define EBU_BUSRAP1_DATAC_Pos (12UL) /*!< EBU BUSRAP1: DATAC (Bit 12) */ 7056 #define EBU_BUSRAP1_DATAC_Msk (0xf000UL) /*!< EBU BUSRAP1: DATAC (Bitfield-Mask: 0x0f) */ 7057 #define EBU_BUSRAP1_EXTCLOCK_Pos (16UL) /*!< EBU BUSRAP1: EXTCLOCK (Bit 16) */ 7058 #define EBU_BUSRAP1_EXTCLOCK_Msk (0x30000UL) /*!< EBU BUSRAP1: EXTCLOCK (Bitfield-Mask: 0x03) */ 7059 #define EBU_BUSRAP1_EXTDATA_Pos (18UL) /*!< EBU BUSRAP1: EXTDATA (Bit 18) */ 7060 #define EBU_BUSRAP1_EXTDATA_Msk (0xc0000UL) /*!< EBU BUSRAP1: EXTDATA (Bitfield-Mask: 0x03) */ 7061 #define EBU_BUSRAP1_CMDDELAY_Pos (20UL) /*!< EBU BUSRAP1: CMDDELAY (Bit 20) */ 7062 #define EBU_BUSRAP1_CMDDELAY_Msk (0xf00000UL) /*!< EBU BUSRAP1: CMDDELAY (Bitfield-Mask: 0x0f) */ 7063 #define EBU_BUSRAP1_AHOLDC_Pos (24UL) /*!< EBU BUSRAP1: AHOLDC (Bit 24) */ 7064 #define EBU_BUSRAP1_AHOLDC_Msk (0xf000000UL) /*!< EBU BUSRAP1: AHOLDC (Bitfield-Mask: 0x0f) */ 7065 #define EBU_BUSRAP1_ADDRC_Pos (28UL) /*!< EBU BUSRAP1: ADDRC (Bit 28) */ 7066 #define EBU_BUSRAP1_ADDRC_Msk (0xf0000000UL) /*!< EBU BUSRAP1: ADDRC (Bitfield-Mask: 0x0f) */ 7067 7068 /* -------------------------------- EBU_BUSWCON1 -------------------------------- */ 7069 #define EBU_BUSWCON1_FETBLEN_Pos (0UL) /*!< EBU BUSWCON1: FETBLEN (Bit 0) */ 7070 #define EBU_BUSWCON1_FETBLEN_Msk (0x7UL) /*!< EBU BUSWCON1: FETBLEN (Bitfield-Mask: 0x07) */ 7071 #define EBU_BUSWCON1_FBBMSEL_Pos (3UL) /*!< EBU BUSWCON1: FBBMSEL (Bit 3) */ 7072 #define EBU_BUSWCON1_FBBMSEL_Msk (0x8UL) /*!< EBU BUSWCON1: FBBMSEL (Bitfield-Mask: 0x01) */ 7073 #define EBU_BUSWCON1_NAA_Pos (7UL) /*!< EBU BUSWCON1: NAA (Bit 7) */ 7074 #define EBU_BUSWCON1_NAA_Msk (0x80UL) /*!< EBU BUSWCON1: NAA (Bitfield-Mask: 0x01) */ 7075 #define EBU_BUSWCON1_ECSE_Pos (16UL) /*!< EBU BUSWCON1: ECSE (Bit 16) */ 7076 #define EBU_BUSWCON1_ECSE_Msk (0x10000UL) /*!< EBU BUSWCON1: ECSE (Bitfield-Mask: 0x01) */ 7077 #define EBU_BUSWCON1_EBSE_Pos (17UL) /*!< EBU BUSWCON1: EBSE (Bit 17) */ 7078 #define EBU_BUSWCON1_EBSE_Msk (0x20000UL) /*!< EBU BUSWCON1: EBSE (Bitfield-Mask: 0x01) */ 7079 #define EBU_BUSWCON1_WAITINV_Pos (19UL) /*!< EBU BUSWCON1: WAITINV (Bit 19) */ 7080 #define EBU_BUSWCON1_WAITINV_Msk (0x80000UL) /*!< EBU BUSWCON1: WAITINV (Bitfield-Mask: 0x01) */ 7081 #define EBU_BUSWCON1_BCGEN_Pos (20UL) /*!< EBU BUSWCON1: BCGEN (Bit 20) */ 7082 #define EBU_BUSWCON1_BCGEN_Msk (0x300000UL) /*!< EBU BUSWCON1: BCGEN (Bitfield-Mask: 0x03) */ 7083 #define EBU_BUSWCON1_PORTW_Pos (22UL) /*!< EBU BUSWCON1: PORTW (Bit 22) */ 7084 #define EBU_BUSWCON1_PORTW_Msk (0xc00000UL) /*!< EBU BUSWCON1: PORTW (Bitfield-Mask: 0x03) */ 7085 #define EBU_BUSWCON1_WAIT_Pos (24UL) /*!< EBU BUSWCON1: WAIT (Bit 24) */ 7086 #define EBU_BUSWCON1_WAIT_Msk (0x3000000UL) /*!< EBU BUSWCON1: WAIT (Bitfield-Mask: 0x03) */ 7087 #define EBU_BUSWCON1_AAP_Pos (26UL) /*!< EBU BUSWCON1: AAP (Bit 26) */ 7088 #define EBU_BUSWCON1_AAP_Msk (0x4000000UL) /*!< EBU BUSWCON1: AAP (Bitfield-Mask: 0x01) */ 7089 #define EBU_BUSWCON1_LOCKCS_Pos (27UL) /*!< EBU BUSWCON1: LOCKCS (Bit 27) */ 7090 #define EBU_BUSWCON1_LOCKCS_Msk (0x8000000UL) /*!< EBU BUSWCON1: LOCKCS (Bitfield-Mask: 0x01) */ 7091 #define EBU_BUSWCON1_AGEN_Pos (28UL) /*!< EBU BUSWCON1: AGEN (Bit 28) */ 7092 #define EBU_BUSWCON1_AGEN_Msk (0xf0000000UL) /*!< EBU BUSWCON1: AGEN (Bitfield-Mask: 0x0f) */ 7093 7094 /* --------------------------------- EBU_BUSWAP1 -------------------------------- */ 7095 #define EBU_BUSWAP1_WRDTACS_Pos (0UL) /*!< EBU BUSWAP1: WRDTACS (Bit 0) */ 7096 #define EBU_BUSWAP1_WRDTACS_Msk (0xfUL) /*!< EBU BUSWAP1: WRDTACS (Bitfield-Mask: 0x0f) */ 7097 #define EBU_BUSWAP1_WRRECOVC_Pos (4UL) /*!< EBU BUSWAP1: WRRECOVC (Bit 4) */ 7098 #define EBU_BUSWAP1_WRRECOVC_Msk (0x70UL) /*!< EBU BUSWAP1: WRRECOVC (Bitfield-Mask: 0x07) */ 7099 #define EBU_BUSWAP1_WAITWRC_Pos (7UL) /*!< EBU BUSWAP1: WAITWRC (Bit 7) */ 7100 #define EBU_BUSWAP1_WAITWRC_Msk (0xf80UL) /*!< EBU BUSWAP1: WAITWRC (Bitfield-Mask: 0x1f) */ 7101 #define EBU_BUSWAP1_DATAC_Pos (12UL) /*!< EBU BUSWAP1: DATAC (Bit 12) */ 7102 #define EBU_BUSWAP1_DATAC_Msk (0xf000UL) /*!< EBU BUSWAP1: DATAC (Bitfield-Mask: 0x0f) */ 7103 #define EBU_BUSWAP1_EXTCLOCK_Pos (16UL) /*!< EBU BUSWAP1: EXTCLOCK (Bit 16) */ 7104 #define EBU_BUSWAP1_EXTCLOCK_Msk (0x30000UL) /*!< EBU BUSWAP1: EXTCLOCK (Bitfield-Mask: 0x03) */ 7105 #define EBU_BUSWAP1_EXTDATA_Pos (18UL) /*!< EBU BUSWAP1: EXTDATA (Bit 18) */ 7106 #define EBU_BUSWAP1_EXTDATA_Msk (0xc0000UL) /*!< EBU BUSWAP1: EXTDATA (Bitfield-Mask: 0x03) */ 7107 #define EBU_BUSWAP1_CMDDELAY_Pos (20UL) /*!< EBU BUSWAP1: CMDDELAY (Bit 20) */ 7108 #define EBU_BUSWAP1_CMDDELAY_Msk (0xf00000UL) /*!< EBU BUSWAP1: CMDDELAY (Bitfield-Mask: 0x0f) */ 7109 #define EBU_BUSWAP1_AHOLDC_Pos (24UL) /*!< EBU BUSWAP1: AHOLDC (Bit 24) */ 7110 #define EBU_BUSWAP1_AHOLDC_Msk (0xf000000UL) /*!< EBU BUSWAP1: AHOLDC (Bitfield-Mask: 0x0f) */ 7111 #define EBU_BUSWAP1_ADDRC_Pos (28UL) /*!< EBU BUSWAP1: ADDRC (Bit 28) */ 7112 #define EBU_BUSWAP1_ADDRC_Msk (0xf0000000UL) /*!< EBU BUSWAP1: ADDRC (Bitfield-Mask: 0x0f) */ 7113 7114 /* -------------------------------- EBU_BUSRCON2 -------------------------------- */ 7115 #define EBU_BUSRCON2_FETBLEN_Pos (0UL) /*!< EBU BUSRCON2: FETBLEN (Bit 0) */ 7116 #define EBU_BUSRCON2_FETBLEN_Msk (0x7UL) /*!< EBU BUSRCON2: FETBLEN (Bitfield-Mask: 0x07) */ 7117 #define EBU_BUSRCON2_FBBMSEL_Pos (3UL) /*!< EBU BUSRCON2: FBBMSEL (Bit 3) */ 7118 #define EBU_BUSRCON2_FBBMSEL_Msk (0x8UL) /*!< EBU BUSRCON2: FBBMSEL (Bitfield-Mask: 0x01) */ 7119 #define EBU_BUSRCON2_BFSSS_Pos (4UL) /*!< EBU BUSRCON2: BFSSS (Bit 4) */ 7120 #define EBU_BUSRCON2_BFSSS_Msk (0x10UL) /*!< EBU BUSRCON2: BFSSS (Bitfield-Mask: 0x01) */ 7121 #define EBU_BUSRCON2_FDBKEN_Pos (5UL) /*!< EBU BUSRCON2: FDBKEN (Bit 5) */ 7122 #define EBU_BUSRCON2_FDBKEN_Msk (0x20UL) /*!< EBU BUSRCON2: FDBKEN (Bitfield-Mask: 0x01) */ 7123 #define EBU_BUSRCON2_BFCMSEL_Pos (6UL) /*!< EBU BUSRCON2: BFCMSEL (Bit 6) */ 7124 #define EBU_BUSRCON2_BFCMSEL_Msk (0x40UL) /*!< EBU BUSRCON2: BFCMSEL (Bitfield-Mask: 0x01) */ 7125 #define EBU_BUSRCON2_NAA_Pos (7UL) /*!< EBU BUSRCON2: NAA (Bit 7) */ 7126 #define EBU_BUSRCON2_NAA_Msk (0x80UL) /*!< EBU BUSRCON2: NAA (Bitfield-Mask: 0x01) */ 7127 #define EBU_BUSRCON2_ECSE_Pos (16UL) /*!< EBU BUSRCON2: ECSE (Bit 16) */ 7128 #define EBU_BUSRCON2_ECSE_Msk (0x10000UL) /*!< EBU BUSRCON2: ECSE (Bitfield-Mask: 0x01) */ 7129 #define EBU_BUSRCON2_EBSE_Pos (17UL) /*!< EBU BUSRCON2: EBSE (Bit 17) */ 7130 #define EBU_BUSRCON2_EBSE_Msk (0x20000UL) /*!< EBU BUSRCON2: EBSE (Bitfield-Mask: 0x01) */ 7131 #define EBU_BUSRCON2_DBA_Pos (18UL) /*!< EBU BUSRCON2: DBA (Bit 18) */ 7132 #define EBU_BUSRCON2_DBA_Msk (0x40000UL) /*!< EBU BUSRCON2: DBA (Bitfield-Mask: 0x01) */ 7133 #define EBU_BUSRCON2_WAITINV_Pos (19UL) /*!< EBU BUSRCON2: WAITINV (Bit 19) */ 7134 #define EBU_BUSRCON2_WAITINV_Msk (0x80000UL) /*!< EBU BUSRCON2: WAITINV (Bitfield-Mask: 0x01) */ 7135 #define EBU_BUSRCON2_BCGEN_Pos (20UL) /*!< EBU BUSRCON2: BCGEN (Bit 20) */ 7136 #define EBU_BUSRCON2_BCGEN_Msk (0x300000UL) /*!< EBU BUSRCON2: BCGEN (Bitfield-Mask: 0x03) */ 7137 #define EBU_BUSRCON2_PORTW_Pos (22UL) /*!< EBU BUSRCON2: PORTW (Bit 22) */ 7138 #define EBU_BUSRCON2_PORTW_Msk (0xc00000UL) /*!< EBU BUSRCON2: PORTW (Bitfield-Mask: 0x03) */ 7139 #define EBU_BUSRCON2_WAIT_Pos (24UL) /*!< EBU BUSRCON2: WAIT (Bit 24) */ 7140 #define EBU_BUSRCON2_WAIT_Msk (0x3000000UL) /*!< EBU BUSRCON2: WAIT (Bitfield-Mask: 0x03) */ 7141 #define EBU_BUSRCON2_AAP_Pos (26UL) /*!< EBU BUSRCON2: AAP (Bit 26) */ 7142 #define EBU_BUSRCON2_AAP_Msk (0x4000000UL) /*!< EBU BUSRCON2: AAP (Bitfield-Mask: 0x01) */ 7143 #define EBU_BUSRCON2_AGEN_Pos (28UL) /*!< EBU BUSRCON2: AGEN (Bit 28) */ 7144 #define EBU_BUSRCON2_AGEN_Msk (0xf0000000UL) /*!< EBU BUSRCON2: AGEN (Bitfield-Mask: 0x0f) */ 7145 7146 /* --------------------------------- EBU_BUSRAP2 -------------------------------- */ 7147 #define EBU_BUSRAP2_RDDTACS_Pos (0UL) /*!< EBU BUSRAP2: RDDTACS (Bit 0) */ 7148 #define EBU_BUSRAP2_RDDTACS_Msk (0xfUL) /*!< EBU BUSRAP2: RDDTACS (Bitfield-Mask: 0x0f) */ 7149 #define EBU_BUSRAP2_RDRECOVC_Pos (4UL) /*!< EBU BUSRAP2: RDRECOVC (Bit 4) */ 7150 #define EBU_BUSRAP2_RDRECOVC_Msk (0x70UL) /*!< EBU BUSRAP2: RDRECOVC (Bitfield-Mask: 0x07) */ 7151 #define EBU_BUSRAP2_WAITRDC_Pos (7UL) /*!< EBU BUSRAP2: WAITRDC (Bit 7) */ 7152 #define EBU_BUSRAP2_WAITRDC_Msk (0xf80UL) /*!< EBU BUSRAP2: WAITRDC (Bitfield-Mask: 0x1f) */ 7153 #define EBU_BUSRAP2_DATAC_Pos (12UL) /*!< EBU BUSRAP2: DATAC (Bit 12) */ 7154 #define EBU_BUSRAP2_DATAC_Msk (0xf000UL) /*!< EBU BUSRAP2: DATAC (Bitfield-Mask: 0x0f) */ 7155 #define EBU_BUSRAP2_EXTCLOCK_Pos (16UL) /*!< EBU BUSRAP2: EXTCLOCK (Bit 16) */ 7156 #define EBU_BUSRAP2_EXTCLOCK_Msk (0x30000UL) /*!< EBU BUSRAP2: EXTCLOCK (Bitfield-Mask: 0x03) */ 7157 #define EBU_BUSRAP2_EXTDATA_Pos (18UL) /*!< EBU BUSRAP2: EXTDATA (Bit 18) */ 7158 #define EBU_BUSRAP2_EXTDATA_Msk (0xc0000UL) /*!< EBU BUSRAP2: EXTDATA (Bitfield-Mask: 0x03) */ 7159 #define EBU_BUSRAP2_CMDDELAY_Pos (20UL) /*!< EBU BUSRAP2: CMDDELAY (Bit 20) */ 7160 #define EBU_BUSRAP2_CMDDELAY_Msk (0xf00000UL) /*!< EBU BUSRAP2: CMDDELAY (Bitfield-Mask: 0x0f) */ 7161 #define EBU_BUSRAP2_AHOLDC_Pos (24UL) /*!< EBU BUSRAP2: AHOLDC (Bit 24) */ 7162 #define EBU_BUSRAP2_AHOLDC_Msk (0xf000000UL) /*!< EBU BUSRAP2: AHOLDC (Bitfield-Mask: 0x0f) */ 7163 #define EBU_BUSRAP2_ADDRC_Pos (28UL) /*!< EBU BUSRAP2: ADDRC (Bit 28) */ 7164 #define EBU_BUSRAP2_ADDRC_Msk (0xf0000000UL) /*!< EBU BUSRAP2: ADDRC (Bitfield-Mask: 0x0f) */ 7165 7166 /* -------------------------------- EBU_BUSWCON2 -------------------------------- */ 7167 #define EBU_BUSWCON2_FETBLEN_Pos (0UL) /*!< EBU BUSWCON2: FETBLEN (Bit 0) */ 7168 #define EBU_BUSWCON2_FETBLEN_Msk (0x7UL) /*!< EBU BUSWCON2: FETBLEN (Bitfield-Mask: 0x07) */ 7169 #define EBU_BUSWCON2_FBBMSEL_Pos (3UL) /*!< EBU BUSWCON2: FBBMSEL (Bit 3) */ 7170 #define EBU_BUSWCON2_FBBMSEL_Msk (0x8UL) /*!< EBU BUSWCON2: FBBMSEL (Bitfield-Mask: 0x01) */ 7171 #define EBU_BUSWCON2_NAA_Pos (7UL) /*!< EBU BUSWCON2: NAA (Bit 7) */ 7172 #define EBU_BUSWCON2_NAA_Msk (0x80UL) /*!< EBU BUSWCON2: NAA (Bitfield-Mask: 0x01) */ 7173 #define EBU_BUSWCON2_ECSE_Pos (16UL) /*!< EBU BUSWCON2: ECSE (Bit 16) */ 7174 #define EBU_BUSWCON2_ECSE_Msk (0x10000UL) /*!< EBU BUSWCON2: ECSE (Bitfield-Mask: 0x01) */ 7175 #define EBU_BUSWCON2_EBSE_Pos (17UL) /*!< EBU BUSWCON2: EBSE (Bit 17) */ 7176 #define EBU_BUSWCON2_EBSE_Msk (0x20000UL) /*!< EBU BUSWCON2: EBSE (Bitfield-Mask: 0x01) */ 7177 #define EBU_BUSWCON2_WAITINV_Pos (19UL) /*!< EBU BUSWCON2: WAITINV (Bit 19) */ 7178 #define EBU_BUSWCON2_WAITINV_Msk (0x80000UL) /*!< EBU BUSWCON2: WAITINV (Bitfield-Mask: 0x01) */ 7179 #define EBU_BUSWCON2_BCGEN_Pos (20UL) /*!< EBU BUSWCON2: BCGEN (Bit 20) */ 7180 #define EBU_BUSWCON2_BCGEN_Msk (0x300000UL) /*!< EBU BUSWCON2: BCGEN (Bitfield-Mask: 0x03) */ 7181 #define EBU_BUSWCON2_PORTW_Pos (22UL) /*!< EBU BUSWCON2: PORTW (Bit 22) */ 7182 #define EBU_BUSWCON2_PORTW_Msk (0xc00000UL) /*!< EBU BUSWCON2: PORTW (Bitfield-Mask: 0x03) */ 7183 #define EBU_BUSWCON2_WAIT_Pos (24UL) /*!< EBU BUSWCON2: WAIT (Bit 24) */ 7184 #define EBU_BUSWCON2_WAIT_Msk (0x3000000UL) /*!< EBU BUSWCON2: WAIT (Bitfield-Mask: 0x03) */ 7185 #define EBU_BUSWCON2_AAP_Pos (26UL) /*!< EBU BUSWCON2: AAP (Bit 26) */ 7186 #define EBU_BUSWCON2_AAP_Msk (0x4000000UL) /*!< EBU BUSWCON2: AAP (Bitfield-Mask: 0x01) */ 7187 #define EBU_BUSWCON2_LOCKCS_Pos (27UL) /*!< EBU BUSWCON2: LOCKCS (Bit 27) */ 7188 #define EBU_BUSWCON2_LOCKCS_Msk (0x8000000UL) /*!< EBU BUSWCON2: LOCKCS (Bitfield-Mask: 0x01) */ 7189 #define EBU_BUSWCON2_AGEN_Pos (28UL) /*!< EBU BUSWCON2: AGEN (Bit 28) */ 7190 #define EBU_BUSWCON2_AGEN_Msk (0xf0000000UL) /*!< EBU BUSWCON2: AGEN (Bitfield-Mask: 0x0f) */ 7191 7192 /* --------------------------------- EBU_BUSWAP2 -------------------------------- */ 7193 #define EBU_BUSWAP2_WRDTACS_Pos (0UL) /*!< EBU BUSWAP2: WRDTACS (Bit 0) */ 7194 #define EBU_BUSWAP2_WRDTACS_Msk (0xfUL) /*!< EBU BUSWAP2: WRDTACS (Bitfield-Mask: 0x0f) */ 7195 #define EBU_BUSWAP2_WRRECOVC_Pos (4UL) /*!< EBU BUSWAP2: WRRECOVC (Bit 4) */ 7196 #define EBU_BUSWAP2_WRRECOVC_Msk (0x70UL) /*!< EBU BUSWAP2: WRRECOVC (Bitfield-Mask: 0x07) */ 7197 #define EBU_BUSWAP2_WAITWRC_Pos (7UL) /*!< EBU BUSWAP2: WAITWRC (Bit 7) */ 7198 #define EBU_BUSWAP2_WAITWRC_Msk (0xf80UL) /*!< EBU BUSWAP2: WAITWRC (Bitfield-Mask: 0x1f) */ 7199 #define EBU_BUSWAP2_DATAC_Pos (12UL) /*!< EBU BUSWAP2: DATAC (Bit 12) */ 7200 #define EBU_BUSWAP2_DATAC_Msk (0xf000UL) /*!< EBU BUSWAP2: DATAC (Bitfield-Mask: 0x0f) */ 7201 #define EBU_BUSWAP2_EXTCLOCK_Pos (16UL) /*!< EBU BUSWAP2: EXTCLOCK (Bit 16) */ 7202 #define EBU_BUSWAP2_EXTCLOCK_Msk (0x30000UL) /*!< EBU BUSWAP2: EXTCLOCK (Bitfield-Mask: 0x03) */ 7203 #define EBU_BUSWAP2_EXTDATA_Pos (18UL) /*!< EBU BUSWAP2: EXTDATA (Bit 18) */ 7204 #define EBU_BUSWAP2_EXTDATA_Msk (0xc0000UL) /*!< EBU BUSWAP2: EXTDATA (Bitfield-Mask: 0x03) */ 7205 #define EBU_BUSWAP2_CMDDELAY_Pos (20UL) /*!< EBU BUSWAP2: CMDDELAY (Bit 20) */ 7206 #define EBU_BUSWAP2_CMDDELAY_Msk (0xf00000UL) /*!< EBU BUSWAP2: CMDDELAY (Bitfield-Mask: 0x0f) */ 7207 #define EBU_BUSWAP2_AHOLDC_Pos (24UL) /*!< EBU BUSWAP2: AHOLDC (Bit 24) */ 7208 #define EBU_BUSWAP2_AHOLDC_Msk (0xf000000UL) /*!< EBU BUSWAP2: AHOLDC (Bitfield-Mask: 0x0f) */ 7209 #define EBU_BUSWAP2_ADDRC_Pos (28UL) /*!< EBU BUSWAP2: ADDRC (Bit 28) */ 7210 #define EBU_BUSWAP2_ADDRC_Msk (0xf0000000UL) /*!< EBU BUSWAP2: ADDRC (Bitfield-Mask: 0x0f) */ 7211 7212 /* -------------------------------- EBU_BUSRCON3 -------------------------------- */ 7213 #define EBU_BUSRCON3_FETBLEN_Pos (0UL) /*!< EBU BUSRCON3: FETBLEN (Bit 0) */ 7214 #define EBU_BUSRCON3_FETBLEN_Msk (0x7UL) /*!< EBU BUSRCON3: FETBLEN (Bitfield-Mask: 0x07) */ 7215 #define EBU_BUSRCON3_FBBMSEL_Pos (3UL) /*!< EBU BUSRCON3: FBBMSEL (Bit 3) */ 7216 #define EBU_BUSRCON3_FBBMSEL_Msk (0x8UL) /*!< EBU BUSRCON3: FBBMSEL (Bitfield-Mask: 0x01) */ 7217 #define EBU_BUSRCON3_BFSSS_Pos (4UL) /*!< EBU BUSRCON3: BFSSS (Bit 4) */ 7218 #define EBU_BUSRCON3_BFSSS_Msk (0x10UL) /*!< EBU BUSRCON3: BFSSS (Bitfield-Mask: 0x01) */ 7219 #define EBU_BUSRCON3_FDBKEN_Pos (5UL) /*!< EBU BUSRCON3: FDBKEN (Bit 5) */ 7220 #define EBU_BUSRCON3_FDBKEN_Msk (0x20UL) /*!< EBU BUSRCON3: FDBKEN (Bitfield-Mask: 0x01) */ 7221 #define EBU_BUSRCON3_BFCMSEL_Pos (6UL) /*!< EBU BUSRCON3: BFCMSEL (Bit 6) */ 7222 #define EBU_BUSRCON3_BFCMSEL_Msk (0x40UL) /*!< EBU BUSRCON3: BFCMSEL (Bitfield-Mask: 0x01) */ 7223 #define EBU_BUSRCON3_NAA_Pos (7UL) /*!< EBU BUSRCON3: NAA (Bit 7) */ 7224 #define EBU_BUSRCON3_NAA_Msk (0x80UL) /*!< EBU BUSRCON3: NAA (Bitfield-Mask: 0x01) */ 7225 #define EBU_BUSRCON3_ECSE_Pos (16UL) /*!< EBU BUSRCON3: ECSE (Bit 16) */ 7226 #define EBU_BUSRCON3_ECSE_Msk (0x10000UL) /*!< EBU BUSRCON3: ECSE (Bitfield-Mask: 0x01) */ 7227 #define EBU_BUSRCON3_EBSE_Pos (17UL) /*!< EBU BUSRCON3: EBSE (Bit 17) */ 7228 #define EBU_BUSRCON3_EBSE_Msk (0x20000UL) /*!< EBU BUSRCON3: EBSE (Bitfield-Mask: 0x01) */ 7229 #define EBU_BUSRCON3_DBA_Pos (18UL) /*!< EBU BUSRCON3: DBA (Bit 18) */ 7230 #define EBU_BUSRCON3_DBA_Msk (0x40000UL) /*!< EBU BUSRCON3: DBA (Bitfield-Mask: 0x01) */ 7231 #define EBU_BUSRCON3_WAITINV_Pos (19UL) /*!< EBU BUSRCON3: WAITINV (Bit 19) */ 7232 #define EBU_BUSRCON3_WAITINV_Msk (0x80000UL) /*!< EBU BUSRCON3: WAITINV (Bitfield-Mask: 0x01) */ 7233 #define EBU_BUSRCON3_BCGEN_Pos (20UL) /*!< EBU BUSRCON3: BCGEN (Bit 20) */ 7234 #define EBU_BUSRCON3_BCGEN_Msk (0x300000UL) /*!< EBU BUSRCON3: BCGEN (Bitfield-Mask: 0x03) */ 7235 #define EBU_BUSRCON3_PORTW_Pos (22UL) /*!< EBU BUSRCON3: PORTW (Bit 22) */ 7236 #define EBU_BUSRCON3_PORTW_Msk (0xc00000UL) /*!< EBU BUSRCON3: PORTW (Bitfield-Mask: 0x03) */ 7237 #define EBU_BUSRCON3_WAIT_Pos (24UL) /*!< EBU BUSRCON3: WAIT (Bit 24) */ 7238 #define EBU_BUSRCON3_WAIT_Msk (0x3000000UL) /*!< EBU BUSRCON3: WAIT (Bitfield-Mask: 0x03) */ 7239 #define EBU_BUSRCON3_AAP_Pos (26UL) /*!< EBU BUSRCON3: AAP (Bit 26) */ 7240 #define EBU_BUSRCON3_AAP_Msk (0x4000000UL) /*!< EBU BUSRCON3: AAP (Bitfield-Mask: 0x01) */ 7241 #define EBU_BUSRCON3_AGEN_Pos (28UL) /*!< EBU BUSRCON3: AGEN (Bit 28) */ 7242 #define EBU_BUSRCON3_AGEN_Msk (0xf0000000UL) /*!< EBU BUSRCON3: AGEN (Bitfield-Mask: 0x0f) */ 7243 7244 /* --------------------------------- EBU_BUSRAP3 -------------------------------- */ 7245 #define EBU_BUSRAP3_RDDTACS_Pos (0UL) /*!< EBU BUSRAP3: RDDTACS (Bit 0) */ 7246 #define EBU_BUSRAP3_RDDTACS_Msk (0xfUL) /*!< EBU BUSRAP3: RDDTACS (Bitfield-Mask: 0x0f) */ 7247 #define EBU_BUSRAP3_RDRECOVC_Pos (4UL) /*!< EBU BUSRAP3: RDRECOVC (Bit 4) */ 7248 #define EBU_BUSRAP3_RDRECOVC_Msk (0x70UL) /*!< EBU BUSRAP3: RDRECOVC (Bitfield-Mask: 0x07) */ 7249 #define EBU_BUSRAP3_WAITRDC_Pos (7UL) /*!< EBU BUSRAP3: WAITRDC (Bit 7) */ 7250 #define EBU_BUSRAP3_WAITRDC_Msk (0xf80UL) /*!< EBU BUSRAP3: WAITRDC (Bitfield-Mask: 0x1f) */ 7251 #define EBU_BUSRAP3_DATAC_Pos (12UL) /*!< EBU BUSRAP3: DATAC (Bit 12) */ 7252 #define EBU_BUSRAP3_DATAC_Msk (0xf000UL) /*!< EBU BUSRAP3: DATAC (Bitfield-Mask: 0x0f) */ 7253 #define EBU_BUSRAP3_EXTCLOCK_Pos (16UL) /*!< EBU BUSRAP3: EXTCLOCK (Bit 16) */ 7254 #define EBU_BUSRAP3_EXTCLOCK_Msk (0x30000UL) /*!< EBU BUSRAP3: EXTCLOCK (Bitfield-Mask: 0x03) */ 7255 #define EBU_BUSRAP3_EXTDATA_Pos (18UL) /*!< EBU BUSRAP3: EXTDATA (Bit 18) */ 7256 #define EBU_BUSRAP3_EXTDATA_Msk (0xc0000UL) /*!< EBU BUSRAP3: EXTDATA (Bitfield-Mask: 0x03) */ 7257 #define EBU_BUSRAP3_CMDDELAY_Pos (20UL) /*!< EBU BUSRAP3: CMDDELAY (Bit 20) */ 7258 #define EBU_BUSRAP3_CMDDELAY_Msk (0xf00000UL) /*!< EBU BUSRAP3: CMDDELAY (Bitfield-Mask: 0x0f) */ 7259 #define EBU_BUSRAP3_AHOLDC_Pos (24UL) /*!< EBU BUSRAP3: AHOLDC (Bit 24) */ 7260 #define EBU_BUSRAP3_AHOLDC_Msk (0xf000000UL) /*!< EBU BUSRAP3: AHOLDC (Bitfield-Mask: 0x0f) */ 7261 #define EBU_BUSRAP3_ADDRC_Pos (28UL) /*!< EBU BUSRAP3: ADDRC (Bit 28) */ 7262 #define EBU_BUSRAP3_ADDRC_Msk (0xf0000000UL) /*!< EBU BUSRAP3: ADDRC (Bitfield-Mask: 0x0f) */ 7263 7264 /* -------------------------------- EBU_BUSWCON3 -------------------------------- */ 7265 #define EBU_BUSWCON3_FETBLEN_Pos (0UL) /*!< EBU BUSWCON3: FETBLEN (Bit 0) */ 7266 #define EBU_BUSWCON3_FETBLEN_Msk (0x7UL) /*!< EBU BUSWCON3: FETBLEN (Bitfield-Mask: 0x07) */ 7267 #define EBU_BUSWCON3_FBBMSEL_Pos (3UL) /*!< EBU BUSWCON3: FBBMSEL (Bit 3) */ 7268 #define EBU_BUSWCON3_FBBMSEL_Msk (0x8UL) /*!< EBU BUSWCON3: FBBMSEL (Bitfield-Mask: 0x01) */ 7269 #define EBU_BUSWCON3_NAA_Pos (7UL) /*!< EBU BUSWCON3: NAA (Bit 7) */ 7270 #define EBU_BUSWCON3_NAA_Msk (0x80UL) /*!< EBU BUSWCON3: NAA (Bitfield-Mask: 0x01) */ 7271 #define EBU_BUSWCON3_ECSE_Pos (16UL) /*!< EBU BUSWCON3: ECSE (Bit 16) */ 7272 #define EBU_BUSWCON3_ECSE_Msk (0x10000UL) /*!< EBU BUSWCON3: ECSE (Bitfield-Mask: 0x01) */ 7273 #define EBU_BUSWCON3_EBSE_Pos (17UL) /*!< EBU BUSWCON3: EBSE (Bit 17) */ 7274 #define EBU_BUSWCON3_EBSE_Msk (0x20000UL) /*!< EBU BUSWCON3: EBSE (Bitfield-Mask: 0x01) */ 7275 #define EBU_BUSWCON3_WAITINV_Pos (19UL) /*!< EBU BUSWCON3: WAITINV (Bit 19) */ 7276 #define EBU_BUSWCON3_WAITINV_Msk (0x80000UL) /*!< EBU BUSWCON3: WAITINV (Bitfield-Mask: 0x01) */ 7277 #define EBU_BUSWCON3_BCGEN_Pos (20UL) /*!< EBU BUSWCON3: BCGEN (Bit 20) */ 7278 #define EBU_BUSWCON3_BCGEN_Msk (0x300000UL) /*!< EBU BUSWCON3: BCGEN (Bitfield-Mask: 0x03) */ 7279 #define EBU_BUSWCON3_PORTW_Pos (22UL) /*!< EBU BUSWCON3: PORTW (Bit 22) */ 7280 #define EBU_BUSWCON3_PORTW_Msk (0xc00000UL) /*!< EBU BUSWCON3: PORTW (Bitfield-Mask: 0x03) */ 7281 #define EBU_BUSWCON3_WAIT_Pos (24UL) /*!< EBU BUSWCON3: WAIT (Bit 24) */ 7282 #define EBU_BUSWCON3_WAIT_Msk (0x3000000UL) /*!< EBU BUSWCON3: WAIT (Bitfield-Mask: 0x03) */ 7283 #define EBU_BUSWCON3_AAP_Pos (26UL) /*!< EBU BUSWCON3: AAP (Bit 26) */ 7284 #define EBU_BUSWCON3_AAP_Msk (0x4000000UL) /*!< EBU BUSWCON3: AAP (Bitfield-Mask: 0x01) */ 7285 #define EBU_BUSWCON3_LOCKCS_Pos (27UL) /*!< EBU BUSWCON3: LOCKCS (Bit 27) */ 7286 #define EBU_BUSWCON3_LOCKCS_Msk (0x8000000UL) /*!< EBU BUSWCON3: LOCKCS (Bitfield-Mask: 0x01) */ 7287 #define EBU_BUSWCON3_AGEN_Pos (28UL) /*!< EBU BUSWCON3: AGEN (Bit 28) */ 7288 #define EBU_BUSWCON3_AGEN_Msk (0xf0000000UL) /*!< EBU BUSWCON3: AGEN (Bitfield-Mask: 0x0f) */ 7289 7290 /* --------------------------------- EBU_BUSWAP3 -------------------------------- */ 7291 #define EBU_BUSWAP3_WRDTACS_Pos (0UL) /*!< EBU BUSWAP3: WRDTACS (Bit 0) */ 7292 #define EBU_BUSWAP3_WRDTACS_Msk (0xfUL) /*!< EBU BUSWAP3: WRDTACS (Bitfield-Mask: 0x0f) */ 7293 #define EBU_BUSWAP3_WRRECOVC_Pos (4UL) /*!< EBU BUSWAP3: WRRECOVC (Bit 4) */ 7294 #define EBU_BUSWAP3_WRRECOVC_Msk (0x70UL) /*!< EBU BUSWAP3: WRRECOVC (Bitfield-Mask: 0x07) */ 7295 #define EBU_BUSWAP3_WAITWRC_Pos (7UL) /*!< EBU BUSWAP3: WAITWRC (Bit 7) */ 7296 #define EBU_BUSWAP3_WAITWRC_Msk (0xf80UL) /*!< EBU BUSWAP3: WAITWRC (Bitfield-Mask: 0x1f) */ 7297 #define EBU_BUSWAP3_DATAC_Pos (12UL) /*!< EBU BUSWAP3: DATAC (Bit 12) */ 7298 #define EBU_BUSWAP3_DATAC_Msk (0xf000UL) /*!< EBU BUSWAP3: DATAC (Bitfield-Mask: 0x0f) */ 7299 #define EBU_BUSWAP3_EXTCLOCK_Pos (16UL) /*!< EBU BUSWAP3: EXTCLOCK (Bit 16) */ 7300 #define EBU_BUSWAP3_EXTCLOCK_Msk (0x30000UL) /*!< EBU BUSWAP3: EXTCLOCK (Bitfield-Mask: 0x03) */ 7301 #define EBU_BUSWAP3_EXTDATA_Pos (18UL) /*!< EBU BUSWAP3: EXTDATA (Bit 18) */ 7302 #define EBU_BUSWAP3_EXTDATA_Msk (0xc0000UL) /*!< EBU BUSWAP3: EXTDATA (Bitfield-Mask: 0x03) */ 7303 #define EBU_BUSWAP3_CMDDELAY_Pos (20UL) /*!< EBU BUSWAP3: CMDDELAY (Bit 20) */ 7304 #define EBU_BUSWAP3_CMDDELAY_Msk (0xf00000UL) /*!< EBU BUSWAP3: CMDDELAY (Bitfield-Mask: 0x0f) */ 7305 #define EBU_BUSWAP3_AHOLDC_Pos (24UL) /*!< EBU BUSWAP3: AHOLDC (Bit 24) */ 7306 #define EBU_BUSWAP3_AHOLDC_Msk (0xf000000UL) /*!< EBU BUSWAP3: AHOLDC (Bitfield-Mask: 0x0f) */ 7307 #define EBU_BUSWAP3_ADDRC_Pos (28UL) /*!< EBU BUSWAP3: ADDRC (Bit 28) */ 7308 #define EBU_BUSWAP3_ADDRC_Msk (0xf0000000UL) /*!< EBU BUSWAP3: ADDRC (Bitfield-Mask: 0x0f) */ 7309 7310 /* --------------------------------- EBU_SDRMCON -------------------------------- */ 7311 #define EBU_SDRMCON_CRAS_Pos (0UL) /*!< EBU SDRMCON: CRAS (Bit 0) */ 7312 #define EBU_SDRMCON_CRAS_Msk (0xfUL) /*!< EBU SDRMCON: CRAS (Bitfield-Mask: 0x0f) */ 7313 #define EBU_SDRMCON_CRFSH_Pos (4UL) /*!< EBU SDRMCON: CRFSH (Bit 4) */ 7314 #define EBU_SDRMCON_CRFSH_Msk (0xf0UL) /*!< EBU SDRMCON: CRFSH (Bitfield-Mask: 0x0f) */ 7315 #define EBU_SDRMCON_CRSC_Pos (8UL) /*!< EBU SDRMCON: CRSC (Bit 8) */ 7316 #define EBU_SDRMCON_CRSC_Msk (0x300UL) /*!< EBU SDRMCON: CRSC (Bitfield-Mask: 0x03) */ 7317 #define EBU_SDRMCON_CRP_Pos (10UL) /*!< EBU SDRMCON: CRP (Bit 10) */ 7318 #define EBU_SDRMCON_CRP_Msk (0xc00UL) /*!< EBU SDRMCON: CRP (Bitfield-Mask: 0x03) */ 7319 #define EBU_SDRMCON_AWIDTH_Pos (12UL) /*!< EBU SDRMCON: AWIDTH (Bit 12) */ 7320 #define EBU_SDRMCON_AWIDTH_Msk (0x3000UL) /*!< EBU SDRMCON: AWIDTH (Bitfield-Mask: 0x03) */ 7321 #define EBU_SDRMCON_CRCD_Pos (14UL) /*!< EBU SDRMCON: CRCD (Bit 14) */ 7322 #define EBU_SDRMCON_CRCD_Msk (0xc000UL) /*!< EBU SDRMCON: CRCD (Bitfield-Mask: 0x03) */ 7323 #define EBU_SDRMCON_CRC_Pos (16UL) /*!< EBU SDRMCON: CRC (Bit 16) */ 7324 #define EBU_SDRMCON_CRC_Msk (0x70000UL) /*!< EBU SDRMCON: CRC (Bitfield-Mask: 0x07) */ 7325 #define EBU_SDRMCON_ROWM_Pos (19UL) /*!< EBU SDRMCON: ROWM (Bit 19) */ 7326 #define EBU_SDRMCON_ROWM_Msk (0x380000UL) /*!< EBU SDRMCON: ROWM (Bitfield-Mask: 0x07) */ 7327 #define EBU_SDRMCON_BANKM_Pos (22UL) /*!< EBU SDRMCON: BANKM (Bit 22) */ 7328 #define EBU_SDRMCON_BANKM_Msk (0x1c00000UL) /*!< EBU SDRMCON: BANKM (Bitfield-Mask: 0x07) */ 7329 #define EBU_SDRMCON_CRCE_Pos (25UL) /*!< EBU SDRMCON: CRCE (Bit 25) */ 7330 #define EBU_SDRMCON_CRCE_Msk (0xe000000UL) /*!< EBU SDRMCON: CRCE (Bitfield-Mask: 0x07) */ 7331 #define EBU_SDRMCON_CLKDIS_Pos (28UL) /*!< EBU SDRMCON: CLKDIS (Bit 28) */ 7332 #define EBU_SDRMCON_CLKDIS_Msk (0x10000000UL) /*!< EBU SDRMCON: CLKDIS (Bitfield-Mask: 0x01) */ 7333 #define EBU_SDRMCON_PWR_MODE_Pos (29UL) /*!< EBU SDRMCON: PWR_MODE (Bit 29) */ 7334 #define EBU_SDRMCON_PWR_MODE_Msk (0x60000000UL) /*!< EBU SDRMCON: PWR_MODE (Bitfield-Mask: 0x03) */ 7335 #define EBU_SDRMCON_SDCMSEL_Pos (31UL) /*!< EBU SDRMCON: SDCMSEL (Bit 31) */ 7336 #define EBU_SDRMCON_SDCMSEL_Msk (0x80000000UL) /*!< EBU SDRMCON: SDCMSEL (Bitfield-Mask: 0x01) */ 7337 7338 /* --------------------------------- EBU_SDRMOD --------------------------------- */ 7339 #define EBU_SDRMOD_BURSTL_Pos (0UL) /*!< EBU SDRMOD: BURSTL (Bit 0) */ 7340 #define EBU_SDRMOD_BURSTL_Msk (0x7UL) /*!< EBU SDRMOD: BURSTL (Bitfield-Mask: 0x07) */ 7341 #define EBU_SDRMOD_BTYP_Pos (3UL) /*!< EBU SDRMOD: BTYP (Bit 3) */ 7342 #define EBU_SDRMOD_BTYP_Msk (0x8UL) /*!< EBU SDRMOD: BTYP (Bitfield-Mask: 0x01) */ 7343 #define EBU_SDRMOD_CASLAT_Pos (4UL) /*!< EBU SDRMOD: CASLAT (Bit 4) */ 7344 #define EBU_SDRMOD_CASLAT_Msk (0x70UL) /*!< EBU SDRMOD: CASLAT (Bitfield-Mask: 0x07) */ 7345 #define EBU_SDRMOD_OPMODE_Pos (7UL) /*!< EBU SDRMOD: OPMODE (Bit 7) */ 7346 #define EBU_SDRMOD_OPMODE_Msk (0x3f80UL) /*!< EBU SDRMOD: OPMODE (Bitfield-Mask: 0x7f) */ 7347 #define EBU_SDRMOD_COLDSTART_Pos (15UL) /*!< EBU SDRMOD: COLDSTART (Bit 15) */ 7348 #define EBU_SDRMOD_COLDSTART_Msk (0x8000UL) /*!< EBU SDRMOD: COLDSTART (Bitfield-Mask: 0x01) */ 7349 #define EBU_SDRMOD_XOPM_Pos (16UL) /*!< EBU SDRMOD: XOPM (Bit 16) */ 7350 #define EBU_SDRMOD_XOPM_Msk (0xfff0000UL) /*!< EBU SDRMOD: XOPM (Bitfield-Mask: 0xfff) */ 7351 #define EBU_SDRMOD_XBA_Pos (28UL) /*!< EBU SDRMOD: XBA (Bit 28) */ 7352 #define EBU_SDRMOD_XBA_Msk (0xf0000000UL) /*!< EBU SDRMOD: XBA (Bitfield-Mask: 0x0f) */ 7353 7354 /* --------------------------------- EBU_SDRMREF -------------------------------- */ 7355 #define EBU_SDRMREF_REFRESHC_Pos (0UL) /*!< EBU SDRMREF: REFRESHC (Bit 0) */ 7356 #define EBU_SDRMREF_REFRESHC_Msk (0x3fUL) /*!< EBU SDRMREF: REFRESHC (Bitfield-Mask: 0x3f) */ 7357 #define EBU_SDRMREF_REFRESHR_Pos (6UL) /*!< EBU SDRMREF: REFRESHR (Bit 6) */ 7358 #define EBU_SDRMREF_REFRESHR_Msk (0x1c0UL) /*!< EBU SDRMREF: REFRESHR (Bitfield-Mask: 0x07) */ 7359 #define EBU_SDRMREF_SELFREXST_Pos (9UL) /*!< EBU SDRMREF: SELFREXST (Bit 9) */ 7360 #define EBU_SDRMREF_SELFREXST_Msk (0x200UL) /*!< EBU SDRMREF: SELFREXST (Bitfield-Mask: 0x01) */ 7361 #define EBU_SDRMREF_SELFREX_Pos (10UL) /*!< EBU SDRMREF: SELFREX (Bit 10) */ 7362 #define EBU_SDRMREF_SELFREX_Msk (0x400UL) /*!< EBU SDRMREF: SELFREX (Bitfield-Mask: 0x01) */ 7363 #define EBU_SDRMREF_SELFRENST_Pos (11UL) /*!< EBU SDRMREF: SELFRENST (Bit 11) */ 7364 #define EBU_SDRMREF_SELFRENST_Msk (0x800UL) /*!< EBU SDRMREF: SELFRENST (Bitfield-Mask: 0x01) */ 7365 #define EBU_SDRMREF_SELFREN_Pos (12UL) /*!< EBU SDRMREF: SELFREN (Bit 12) */ 7366 #define EBU_SDRMREF_SELFREN_Msk (0x1000UL) /*!< EBU SDRMREF: SELFREN (Bitfield-Mask: 0x01) */ 7367 #define EBU_SDRMREF_AUTOSELFR_Pos (13UL) /*!< EBU SDRMREF: AUTOSELFR (Bit 13) */ 7368 #define EBU_SDRMREF_AUTOSELFR_Msk (0x2000UL) /*!< EBU SDRMREF: AUTOSELFR (Bitfield-Mask: 0x01) */ 7369 #define EBU_SDRMREF_ERFSHC_Pos (14UL) /*!< EBU SDRMREF: ERFSHC (Bit 14) */ 7370 #define EBU_SDRMREF_ERFSHC_Msk (0xc000UL) /*!< EBU SDRMREF: ERFSHC (Bitfield-Mask: 0x03) */ 7371 #define EBU_SDRMREF_SELFREX_DLY_Pos (16UL) /*!< EBU SDRMREF: SELFREX_DLY (Bit 16) */ 7372 #define EBU_SDRMREF_SELFREX_DLY_Msk (0xff0000UL) /*!< EBU SDRMREF: SELFREX_DLY (Bitfield-Mask: 0xff) */ 7373 #define EBU_SDRMREF_ARFSH_Pos (24UL) /*!< EBU SDRMREF: ARFSH (Bit 24) */ 7374 #define EBU_SDRMREF_ARFSH_Msk (0x1000000UL) /*!< EBU SDRMREF: ARFSH (Bitfield-Mask: 0x01) */ 7375 #define EBU_SDRMREF_RES_DLY_Pos (25UL) /*!< EBU SDRMREF: RES_DLY (Bit 25) */ 7376 #define EBU_SDRMREF_RES_DLY_Msk (0xe000000UL) /*!< EBU SDRMREF: RES_DLY (Bitfield-Mask: 0x07) */ 7377 7378 /* --------------------------------- EBU_SDRSTAT -------------------------------- */ 7379 #define EBU_SDRSTAT_REFERR_Pos (0UL) /*!< EBU SDRSTAT: REFERR (Bit 0) */ 7380 #define EBU_SDRSTAT_REFERR_Msk (0x1UL) /*!< EBU SDRSTAT: REFERR (Bitfield-Mask: 0x01) */ 7381 #define EBU_SDRSTAT_SDRMBUSY_Pos (1UL) /*!< EBU SDRSTAT: SDRMBUSY (Bit 1) */ 7382 #define EBU_SDRSTAT_SDRMBUSY_Msk (0x2UL) /*!< EBU SDRSTAT: SDRMBUSY (Bitfield-Mask: 0x01) */ 7383 #define EBU_SDRSTAT_SDERR_Pos (2UL) /*!< EBU SDRSTAT: SDERR (Bit 2) */ 7384 #define EBU_SDRSTAT_SDERR_Msk (0x4UL) /*!< EBU SDRSTAT: SDERR (Bitfield-Mask: 0x01) */ 7385 7386 7387 /* ================================================================================ */ 7388 /* ================ struct 'ETH0_CON' Position & Mask ================ */ 7389 /* ================================================================================ */ 7390 7391 7392 /* ------------------------------ ETH0_CON_ETH0_CON ----------------------------- */ 7393 #define ETH_CON_RXD0_Pos (0UL) /*!< ETH0_CON ETH0_CON: RXD0 (Bit 0) */ 7394 #define ETH_CON_RXD0_Msk (0x3UL) /*!< ETH0_CON ETH0_CON: RXD0 (Bitfield-Mask: 0x03) */ 7395 #define ETH_CON_RXD1_Pos (2UL) /*!< ETH0_CON ETH0_CON: RXD1 (Bit 2) */ 7396 #define ETH_CON_RXD1_Msk (0xcUL) /*!< ETH0_CON ETH0_CON: RXD1 (Bitfield-Mask: 0x03) */ 7397 #define ETH_CON_RXD2_Pos (4UL) /*!< ETH0_CON ETH0_CON: RXD2 (Bit 4) */ 7398 #define ETH_CON_RXD2_Msk (0x30UL) /*!< ETH0_CON ETH0_CON: RXD2 (Bitfield-Mask: 0x03) */ 7399 #define ETH_CON_RXD3_Pos (6UL) /*!< ETH0_CON ETH0_CON: RXD3 (Bit 6) */ 7400 #define ETH_CON_RXD3_Msk (0xc0UL) /*!< ETH0_CON ETH0_CON: RXD3 (Bitfield-Mask: 0x03) */ 7401 #define ETH_CON_CLK_RMII_Pos (8UL) /*!< ETH0_CON ETH0_CON: CLK_RMII (Bit 8) */ 7402 #define ETH_CON_CLK_RMII_Msk (0x300UL) /*!< ETH0_CON ETH0_CON: CLK_RMII (Bitfield-Mask: 0x03) */ 7403 #define ETH_CON_CRS_DV_Pos (10UL) /*!< ETH0_CON ETH0_CON: CRS_DV (Bit 10) */ 7404 #define ETH_CON_CRS_DV_Msk (0xc00UL) /*!< ETH0_CON ETH0_CON: CRS_DV (Bitfield-Mask: 0x03) */ 7405 #define ETH_CON_CRS_Pos (12UL) /*!< ETH0_CON ETH0_CON: CRS (Bit 12) */ 7406 #define ETH_CON_CRS_Msk (0x3000UL) /*!< ETH0_CON ETH0_CON: CRS (Bitfield-Mask: 0x03) */ 7407 #define ETH_CON_RXER_Pos (14UL) /*!< ETH0_CON ETH0_CON: RXER (Bit 14) */ 7408 #define ETH_CON_RXER_Msk (0xc000UL) /*!< ETH0_CON ETH0_CON: RXER (Bitfield-Mask: 0x03) */ 7409 #define ETH_CON_COL_Pos (16UL) /*!< ETH0_CON ETH0_CON: COL (Bit 16) */ 7410 #define ETH_CON_COL_Msk (0x30000UL) /*!< ETH0_CON ETH0_CON: COL (Bitfield-Mask: 0x03) */ 7411 #define ETH_CON_CLK_TX_Pos (18UL) /*!< ETH0_CON ETH0_CON: CLK_TX (Bit 18) */ 7412 #define ETH_CON_CLK_TX_Msk (0xc0000UL) /*!< ETH0_CON ETH0_CON: CLK_TX (Bitfield-Mask: 0x03) */ 7413 #define ETH_CON_MDIO_Pos (22UL) /*!< ETH0_CON ETH0_CON: MDIO (Bit 22) */ 7414 #define ETH_CON_MDIO_Msk (0xc00000UL) /*!< ETH0_CON ETH0_CON: MDIO (Bitfield-Mask: 0x03) */ 7415 #define ETH_CON_INFSEL_Pos (26UL) /*!< ETH0_CON ETH0_CON: INFSEL (Bit 26) */ 7416 #define ETH_CON_INFSEL_Msk (0x4000000UL) /*!< ETH0_CON ETH0_CON: INFSEL (Bitfield-Mask: 0x01) */ 7417 7418 7419 /* ================================================================================ */ 7420 /* ================ Group 'ETH' Position & Mask ================ */ 7421 /* ================================================================================ */ 7422 7423 7424 /* ---------------------------- ETH_MAC_CONFIGURATION --------------------------- */ 7425 #define ETH_MAC_CONFIGURATION_PRELEN_Pos (0UL) /*!< ETH MAC_CONFIGURATION: PRELEN (Bit 0) */ 7426 #define ETH_MAC_CONFIGURATION_PRELEN_Msk (0x3UL) /*!< ETH MAC_CONFIGURATION: PRELEN (Bitfield-Mask: 0x03) */ 7427 #define ETH_MAC_CONFIGURATION_RE_Pos (2UL) /*!< ETH MAC_CONFIGURATION: RE (Bit 2) */ 7428 #define ETH_MAC_CONFIGURATION_RE_Msk (0x4UL) /*!< ETH MAC_CONFIGURATION: RE (Bitfield-Mask: 0x01) */ 7429 #define ETH_MAC_CONFIGURATION_TE_Pos (3UL) /*!< ETH MAC_CONFIGURATION: TE (Bit 3) */ 7430 #define ETH_MAC_CONFIGURATION_TE_Msk (0x8UL) /*!< ETH MAC_CONFIGURATION: TE (Bitfield-Mask: 0x01) */ 7431 #define ETH_MAC_CONFIGURATION_DC_Pos (4UL) /*!< ETH MAC_CONFIGURATION: DC (Bit 4) */ 7432 #define ETH_MAC_CONFIGURATION_DC_Msk (0x10UL) /*!< ETH MAC_CONFIGURATION: DC (Bitfield-Mask: 0x01) */ 7433 #define ETH_MAC_CONFIGURATION_BL_Pos (5UL) /*!< ETH MAC_CONFIGURATION: BL (Bit 5) */ 7434 #define ETH_MAC_CONFIGURATION_BL_Msk (0x60UL) /*!< ETH MAC_CONFIGURATION: BL (Bitfield-Mask: 0x03) */ 7435 #define ETH_MAC_CONFIGURATION_ACS_Pos (7UL) /*!< ETH MAC_CONFIGURATION: ACS (Bit 7) */ 7436 #define ETH_MAC_CONFIGURATION_ACS_Msk (0x80UL) /*!< ETH MAC_CONFIGURATION: ACS (Bitfield-Mask: 0x01) */ 7437 #define ETH_MAC_CONFIGURATION_DR_Pos (9UL) /*!< ETH MAC_CONFIGURATION: DR (Bit 9) */ 7438 #define ETH_MAC_CONFIGURATION_DR_Msk (0x200UL) /*!< ETH MAC_CONFIGURATION: DR (Bitfield-Mask: 0x01) */ 7439 #define ETH_MAC_CONFIGURATION_IPC_Pos (10UL) /*!< ETH MAC_CONFIGURATION: IPC (Bit 10) */ 7440 #define ETH_MAC_CONFIGURATION_IPC_Msk (0x400UL) /*!< ETH MAC_CONFIGURATION: IPC (Bitfield-Mask: 0x01) */ 7441 #define ETH_MAC_CONFIGURATION_DM_Pos (11UL) /*!< ETH MAC_CONFIGURATION: DM (Bit 11) */ 7442 #define ETH_MAC_CONFIGURATION_DM_Msk (0x800UL) /*!< ETH MAC_CONFIGURATION: DM (Bitfield-Mask: 0x01) */ 7443 #define ETH_MAC_CONFIGURATION_LM_Pos (12UL) /*!< ETH MAC_CONFIGURATION: LM (Bit 12) */ 7444 #define ETH_MAC_CONFIGURATION_LM_Msk (0x1000UL) /*!< ETH MAC_CONFIGURATION: LM (Bitfield-Mask: 0x01) */ 7445 #define ETH_MAC_CONFIGURATION_DO_Pos (13UL) /*!< ETH MAC_CONFIGURATION: DO (Bit 13) */ 7446 #define ETH_MAC_CONFIGURATION_DO_Msk (0x2000UL) /*!< ETH MAC_CONFIGURATION: DO (Bitfield-Mask: 0x01) */ 7447 #define ETH_MAC_CONFIGURATION_FES_Pos (14UL) /*!< ETH MAC_CONFIGURATION: FES (Bit 14) */ 7448 #define ETH_MAC_CONFIGURATION_FES_Msk (0x4000UL) /*!< ETH MAC_CONFIGURATION: FES (Bitfield-Mask: 0x01) */ 7449 #define ETH_MAC_CONFIGURATION_DCRS_Pos (16UL) /*!< ETH MAC_CONFIGURATION: DCRS (Bit 16) */ 7450 #define ETH_MAC_CONFIGURATION_DCRS_Msk (0x10000UL) /*!< ETH MAC_CONFIGURATION: DCRS (Bitfield-Mask: 0x01) */ 7451 #define ETH_MAC_CONFIGURATION_IFG_Pos (17UL) /*!< ETH MAC_CONFIGURATION: IFG (Bit 17) */ 7452 #define ETH_MAC_CONFIGURATION_IFG_Msk (0xe0000UL) /*!< ETH MAC_CONFIGURATION: IFG (Bitfield-Mask: 0x07) */ 7453 #define ETH_MAC_CONFIGURATION_JE_Pos (20UL) /*!< ETH MAC_CONFIGURATION: JE (Bit 20) */ 7454 #define ETH_MAC_CONFIGURATION_JE_Msk (0x100000UL) /*!< ETH MAC_CONFIGURATION: JE (Bitfield-Mask: 0x01) */ 7455 #define ETH_MAC_CONFIGURATION_BE_Pos (21UL) /*!< ETH MAC_CONFIGURATION: BE (Bit 21) */ 7456 #define ETH_MAC_CONFIGURATION_BE_Msk (0x200000UL) /*!< ETH MAC_CONFIGURATION: BE (Bitfield-Mask: 0x01) */ 7457 #define ETH_MAC_CONFIGURATION_JD_Pos (22UL) /*!< ETH MAC_CONFIGURATION: JD (Bit 22) */ 7458 #define ETH_MAC_CONFIGURATION_JD_Msk (0x400000UL) /*!< ETH MAC_CONFIGURATION: JD (Bitfield-Mask: 0x01) */ 7459 #define ETH_MAC_CONFIGURATION_WD_Pos (23UL) /*!< ETH MAC_CONFIGURATION: WD (Bit 23) */ 7460 #define ETH_MAC_CONFIGURATION_WD_Msk (0x800000UL) /*!< ETH MAC_CONFIGURATION: WD (Bitfield-Mask: 0x01) */ 7461 #define ETH_MAC_CONFIGURATION_TC_Pos (24UL) /*!< ETH MAC_CONFIGURATION: TC (Bit 24) */ 7462 #define ETH_MAC_CONFIGURATION_TC_Msk (0x1000000UL) /*!< ETH MAC_CONFIGURATION: TC (Bitfield-Mask: 0x01) */ 7463 #define ETH_MAC_CONFIGURATION_CST_Pos (25UL) /*!< ETH MAC_CONFIGURATION: CST (Bit 25) */ 7464 #define ETH_MAC_CONFIGURATION_CST_Msk (0x2000000UL) /*!< ETH MAC_CONFIGURATION: CST (Bitfield-Mask: 0x01) */ 7465 #define ETH_MAC_CONFIGURATION_TWOKPE_Pos (27UL) /*!< ETH MAC_CONFIGURATION: TWOKPE (Bit 27) */ 7466 #define ETH_MAC_CONFIGURATION_TWOKPE_Msk (0x8000000UL) /*!< ETH MAC_CONFIGURATION: TWOKPE (Bitfield-Mask: 0x01) */ 7467 #define ETH_MAC_CONFIGURATION_SARC_Pos (28UL) /*!< ETH MAC_CONFIGURATION: SARC (Bit 28) */ 7468 #define ETH_MAC_CONFIGURATION_SARC_Msk (0x70000000UL) /*!< ETH MAC_CONFIGURATION: SARC (Bitfield-Mask: 0x07) */ 7469 7470 /* ---------------------------- ETH_MAC_FRAME_FILTER ---------------------------- */ 7471 #define ETH_MAC_FRAME_FILTER_PR_Pos (0UL) /*!< ETH MAC_FRAME_FILTER: PR (Bit 0) */ 7472 #define ETH_MAC_FRAME_FILTER_PR_Msk (0x1UL) /*!< ETH MAC_FRAME_FILTER: PR (Bitfield-Mask: 0x01) */ 7473 #define ETH_MAC_FRAME_FILTER_HUC_Pos (1UL) /*!< ETH MAC_FRAME_FILTER: HUC (Bit 1) */ 7474 #define ETH_MAC_FRAME_FILTER_HUC_Msk (0x2UL) /*!< ETH MAC_FRAME_FILTER: HUC (Bitfield-Mask: 0x01) */ 7475 #define ETH_MAC_FRAME_FILTER_HMC_Pos (2UL) /*!< ETH MAC_FRAME_FILTER: HMC (Bit 2) */ 7476 #define ETH_MAC_FRAME_FILTER_HMC_Msk (0x4UL) /*!< ETH MAC_FRAME_FILTER: HMC (Bitfield-Mask: 0x01) */ 7477 #define ETH_MAC_FRAME_FILTER_DAIF_Pos (3UL) /*!< ETH MAC_FRAME_FILTER: DAIF (Bit 3) */ 7478 #define ETH_MAC_FRAME_FILTER_DAIF_Msk (0x8UL) /*!< ETH MAC_FRAME_FILTER: DAIF (Bitfield-Mask: 0x01) */ 7479 #define ETH_MAC_FRAME_FILTER_PM_Pos (4UL) /*!< ETH MAC_FRAME_FILTER: PM (Bit 4) */ 7480 #define ETH_MAC_FRAME_FILTER_PM_Msk (0x10UL) /*!< ETH MAC_FRAME_FILTER: PM (Bitfield-Mask: 0x01) */ 7481 #define ETH_MAC_FRAME_FILTER_DBF_Pos (5UL) /*!< ETH MAC_FRAME_FILTER: DBF (Bit 5) */ 7482 #define ETH_MAC_FRAME_FILTER_DBF_Msk (0x20UL) /*!< ETH MAC_FRAME_FILTER: DBF (Bitfield-Mask: 0x01) */ 7483 #define ETH_MAC_FRAME_FILTER_PCF_Pos (6UL) /*!< ETH MAC_FRAME_FILTER: PCF (Bit 6) */ 7484 #define ETH_MAC_FRAME_FILTER_PCF_Msk (0xc0UL) /*!< ETH MAC_FRAME_FILTER: PCF (Bitfield-Mask: 0x03) */ 7485 #define ETH_MAC_FRAME_FILTER_SAIF_Pos (8UL) /*!< ETH MAC_FRAME_FILTER: SAIF (Bit 8) */ 7486 #define ETH_MAC_FRAME_FILTER_SAIF_Msk (0x100UL) /*!< ETH MAC_FRAME_FILTER: SAIF (Bitfield-Mask: 0x01) */ 7487 #define ETH_MAC_FRAME_FILTER_SAF_Pos (9UL) /*!< ETH MAC_FRAME_FILTER: SAF (Bit 9) */ 7488 #define ETH_MAC_FRAME_FILTER_SAF_Msk (0x200UL) /*!< ETH MAC_FRAME_FILTER: SAF (Bitfield-Mask: 0x01) */ 7489 #define ETH_MAC_FRAME_FILTER_HPF_Pos (10UL) /*!< ETH MAC_FRAME_FILTER: HPF (Bit 10) */ 7490 #define ETH_MAC_FRAME_FILTER_HPF_Msk (0x400UL) /*!< ETH MAC_FRAME_FILTER: HPF (Bitfield-Mask: 0x01) */ 7491 #define ETH_MAC_FRAME_FILTER_VTFE_Pos (16UL) /*!< ETH MAC_FRAME_FILTER: VTFE (Bit 16) */ 7492 #define ETH_MAC_FRAME_FILTER_VTFE_Msk (0x10000UL) /*!< ETH MAC_FRAME_FILTER: VTFE (Bitfield-Mask: 0x01) */ 7493 #define ETH_MAC_FRAME_FILTER_IPFE_Pos (20UL) /*!< ETH MAC_FRAME_FILTER: IPFE (Bit 20) */ 7494 #define ETH_MAC_FRAME_FILTER_IPFE_Msk (0x100000UL) /*!< ETH MAC_FRAME_FILTER: IPFE (Bitfield-Mask: 0x01) */ 7495 #define ETH_MAC_FRAME_FILTER_DNTU_Pos (21UL) /*!< ETH MAC_FRAME_FILTER: DNTU (Bit 21) */ 7496 #define ETH_MAC_FRAME_FILTER_DNTU_Msk (0x200000UL) /*!< ETH MAC_FRAME_FILTER: DNTU (Bitfield-Mask: 0x01) */ 7497 #define ETH_MAC_FRAME_FILTER_RA_Pos (31UL) /*!< ETH MAC_FRAME_FILTER: RA (Bit 31) */ 7498 #define ETH_MAC_FRAME_FILTER_RA_Msk (0x80000000UL) /*!< ETH MAC_FRAME_FILTER: RA (Bitfield-Mask: 0x01) */ 7499 7500 /* ----------------------------- ETH_HASH_TABLE_HIGH ---------------------------- */ 7501 #define ETH_HASH_TABLE_HIGH_HTH_Pos (0UL) /*!< ETH HASH_TABLE_HIGH: HTH (Bit 0) */ 7502 #define ETH_HASH_TABLE_HIGH_HTH_Msk (0xffffffffUL) /*!< ETH HASH_TABLE_HIGH: HTH (Bitfield-Mask: 0xffffffff) */ 7503 7504 /* ----------------------------- ETH_HASH_TABLE_LOW ----------------------------- */ 7505 #define ETH_HASH_TABLE_LOW_HTL_Pos (0UL) /*!< ETH HASH_TABLE_LOW: HTL (Bit 0) */ 7506 #define ETH_HASH_TABLE_LOW_HTL_Msk (0xffffffffUL) /*!< ETH HASH_TABLE_LOW: HTL (Bitfield-Mask: 0xffffffff) */ 7507 7508 /* ------------------------------ ETH_GMII_ADDRESS ------------------------------ */ 7509 #define ETH_GMII_ADDRESS_MB_Pos (0UL) /*!< ETH GMII_ADDRESS: MB (Bit 0) */ 7510 #define ETH_GMII_ADDRESS_MB_Msk (0x1UL) /*!< ETH GMII_ADDRESS: MB (Bitfield-Mask: 0x01) */ 7511 #define ETH_GMII_ADDRESS_MW_Pos (1UL) /*!< ETH GMII_ADDRESS: MW (Bit 1) */ 7512 #define ETH_GMII_ADDRESS_MW_Msk (0x2UL) /*!< ETH GMII_ADDRESS: MW (Bitfield-Mask: 0x01) */ 7513 #define ETH_GMII_ADDRESS_CR_Pos (2UL) /*!< ETH GMII_ADDRESS: CR (Bit 2) */ 7514 #define ETH_GMII_ADDRESS_CR_Msk (0x3cUL) /*!< ETH GMII_ADDRESS: CR (Bitfield-Mask: 0x0f) */ 7515 #define ETH_GMII_ADDRESS_MR_Pos (6UL) /*!< ETH GMII_ADDRESS: MR (Bit 6) */ 7516 #define ETH_GMII_ADDRESS_MR_Msk (0x7c0UL) /*!< ETH GMII_ADDRESS: MR (Bitfield-Mask: 0x1f) */ 7517 #define ETH_GMII_ADDRESS_PA_Pos (11UL) /*!< ETH GMII_ADDRESS: PA (Bit 11) */ 7518 #define ETH_GMII_ADDRESS_PA_Msk (0xf800UL) /*!< ETH GMII_ADDRESS: PA (Bitfield-Mask: 0x1f) */ 7519 7520 /* -------------------------------- ETH_GMII_DATA ------------------------------- */ 7521 #define ETH_GMII_DATA_MD_Pos (0UL) /*!< ETH GMII_DATA: MD (Bit 0) */ 7522 #define ETH_GMII_DATA_MD_Msk (0xffffUL) /*!< ETH GMII_DATA: MD (Bitfield-Mask: 0xffff) */ 7523 7524 /* ------------------------------ ETH_FLOW_CONTROL ------------------------------ */ 7525 #define ETH_FLOW_CONTROL_FCA_BPA_Pos (0UL) /*!< ETH FLOW_CONTROL: FCA_BPA (Bit 0) */ 7526 #define ETH_FLOW_CONTROL_FCA_BPA_Msk (0x1UL) /*!< ETH FLOW_CONTROL: FCA_BPA (Bitfield-Mask: 0x01) */ 7527 #define ETH_FLOW_CONTROL_TFE_Pos (1UL) /*!< ETH FLOW_CONTROL: TFE (Bit 1) */ 7528 #define ETH_FLOW_CONTROL_TFE_Msk (0x2UL) /*!< ETH FLOW_CONTROL: TFE (Bitfield-Mask: 0x01) */ 7529 #define ETH_FLOW_CONTROL_RFE_Pos (2UL) /*!< ETH FLOW_CONTROL: RFE (Bit 2) */ 7530 #define ETH_FLOW_CONTROL_RFE_Msk (0x4UL) /*!< ETH FLOW_CONTROL: RFE (Bitfield-Mask: 0x01) */ 7531 #define ETH_FLOW_CONTROL_UP_Pos (3UL) /*!< ETH FLOW_CONTROL: UP (Bit 3) */ 7532 #define ETH_FLOW_CONTROL_UP_Msk (0x8UL) /*!< ETH FLOW_CONTROL: UP (Bitfield-Mask: 0x01) */ 7533 #define ETH_FLOW_CONTROL_PLT_Pos (4UL) /*!< ETH FLOW_CONTROL: PLT (Bit 4) */ 7534 #define ETH_FLOW_CONTROL_PLT_Msk (0x30UL) /*!< ETH FLOW_CONTROL: PLT (Bitfield-Mask: 0x03) */ 7535 #define ETH_FLOW_CONTROL_DZPQ_Pos (7UL) /*!< ETH FLOW_CONTROL: DZPQ (Bit 7) */ 7536 #define ETH_FLOW_CONTROL_DZPQ_Msk (0x80UL) /*!< ETH FLOW_CONTROL: DZPQ (Bitfield-Mask: 0x01) */ 7537 #define ETH_FLOW_CONTROL_PT_Pos (16UL) /*!< ETH FLOW_CONTROL: PT (Bit 16) */ 7538 #define ETH_FLOW_CONTROL_PT_Msk (0xffff0000UL) /*!< ETH FLOW_CONTROL: PT (Bitfield-Mask: 0xffff) */ 7539 7540 /* -------------------------------- ETH_VLAN_TAG -------------------------------- */ 7541 #define ETH_VLAN_TAG_VL_Pos (0UL) /*!< ETH VLAN_TAG: VL (Bit 0) */ 7542 #define ETH_VLAN_TAG_VL_Msk (0xffffUL) /*!< ETH VLAN_TAG: VL (Bitfield-Mask: 0xffff) */ 7543 #define ETH_VLAN_TAG_ETV_Pos (16UL) /*!< ETH VLAN_TAG: ETV (Bit 16) */ 7544 #define ETH_VLAN_TAG_ETV_Msk (0x10000UL) /*!< ETH VLAN_TAG: ETV (Bitfield-Mask: 0x01) */ 7545 #define ETH_VLAN_TAG_VTIM_Pos (17UL) /*!< ETH VLAN_TAG: VTIM (Bit 17) */ 7546 #define ETH_VLAN_TAG_VTIM_Msk (0x20000UL) /*!< ETH VLAN_TAG: VTIM (Bitfield-Mask: 0x01) */ 7547 #define ETH_VLAN_TAG_ESVL_Pos (18UL) /*!< ETH VLAN_TAG: ESVL (Bit 18) */ 7548 #define ETH_VLAN_TAG_ESVL_Msk (0x40000UL) /*!< ETH VLAN_TAG: ESVL (Bitfield-Mask: 0x01) */ 7549 #define ETH_VLAN_TAG_VTHM_Pos (19UL) /*!< ETH VLAN_TAG: VTHM (Bit 19) */ 7550 #define ETH_VLAN_TAG_VTHM_Msk (0x80000UL) /*!< ETH VLAN_TAG: VTHM (Bitfield-Mask: 0x01) */ 7551 7552 /* --------------------------------- ETH_VERSION -------------------------------- */ 7553 #define ETH_VERSION_SNPSVER_Pos (0UL) /*!< ETH VERSION: SNPSVER (Bit 0) */ 7554 #define ETH_VERSION_SNPSVER_Msk (0xffUL) /*!< ETH VERSION: SNPSVER (Bitfield-Mask: 0xff) */ 7555 #define ETH_VERSION_USERVER_Pos (8UL) /*!< ETH VERSION: USERVER (Bit 8) */ 7556 #define ETH_VERSION_USERVER_Msk (0xff00UL) /*!< ETH VERSION: USERVER (Bitfield-Mask: 0xff) */ 7557 7558 /* ---------------------------------- ETH_DEBUG --------------------------------- */ 7559 #define ETH_DEBUG_RPESTS_Pos (0UL) /*!< ETH DEBUG: RPESTS (Bit 0) */ 7560 #define ETH_DEBUG_RPESTS_Msk (0x1UL) /*!< ETH DEBUG: RPESTS (Bitfield-Mask: 0x01) */ 7561 #define ETH_DEBUG_RFCFCSTS_Pos (1UL) /*!< ETH DEBUG: RFCFCSTS (Bit 1) */ 7562 #define ETH_DEBUG_RFCFCSTS_Msk (0x6UL) /*!< ETH DEBUG: RFCFCSTS (Bitfield-Mask: 0x03) */ 7563 #define ETH_DEBUG_RWCSTS_Pos (4UL) /*!< ETH DEBUG: RWCSTS (Bit 4) */ 7564 #define ETH_DEBUG_RWCSTS_Msk (0x10UL) /*!< ETH DEBUG: RWCSTS (Bitfield-Mask: 0x01) */ 7565 #define ETH_DEBUG_RRCSTS_Pos (5UL) /*!< ETH DEBUG: RRCSTS (Bit 5) */ 7566 #define ETH_DEBUG_RRCSTS_Msk (0x60UL) /*!< ETH DEBUG: RRCSTS (Bitfield-Mask: 0x03) */ 7567 #define ETH_DEBUG_RXFSTS_Pos (8UL) /*!< ETH DEBUG: RXFSTS (Bit 8) */ 7568 #define ETH_DEBUG_RXFSTS_Msk (0x300UL) /*!< ETH DEBUG: RXFSTS (Bitfield-Mask: 0x03) */ 7569 #define ETH_DEBUG_TPESTS_Pos (16UL) /*!< ETH DEBUG: TPESTS (Bit 16) */ 7570 #define ETH_DEBUG_TPESTS_Msk (0x10000UL) /*!< ETH DEBUG: TPESTS (Bitfield-Mask: 0x01) */ 7571 #define ETH_DEBUG_TFCSTS_Pos (17UL) /*!< ETH DEBUG: TFCSTS (Bit 17) */ 7572 #define ETH_DEBUG_TFCSTS_Msk (0x60000UL) /*!< ETH DEBUG: TFCSTS (Bitfield-Mask: 0x03) */ 7573 #define ETH_DEBUG_TXPAUSED_Pos (19UL) /*!< ETH DEBUG: TXPAUSED (Bit 19) */ 7574 #define ETH_DEBUG_TXPAUSED_Msk (0x80000UL) /*!< ETH DEBUG: TXPAUSED (Bitfield-Mask: 0x01) */ 7575 #define ETH_DEBUG_TRCSTS_Pos (20UL) /*!< ETH DEBUG: TRCSTS (Bit 20) */ 7576 #define ETH_DEBUG_TRCSTS_Msk (0x300000UL) /*!< ETH DEBUG: TRCSTS (Bitfield-Mask: 0x03) */ 7577 #define ETH_DEBUG_TWCSTS_Pos (22UL) /*!< ETH DEBUG: TWCSTS (Bit 22) */ 7578 #define ETH_DEBUG_TWCSTS_Msk (0x400000UL) /*!< ETH DEBUG: TWCSTS (Bitfield-Mask: 0x01) */ 7579 #define ETH_DEBUG_TXFSTS_Pos (24UL) /*!< ETH DEBUG: TXFSTS (Bit 24) */ 7580 #define ETH_DEBUG_TXFSTS_Msk (0x1000000UL) /*!< ETH DEBUG: TXFSTS (Bitfield-Mask: 0x01) */ 7581 #define ETH_DEBUG_TXSTSFSTS_Pos (25UL) /*!< ETH DEBUG: TXSTSFSTS (Bit 25) */ 7582 #define ETH_DEBUG_TXSTSFSTS_Msk (0x2000000UL) /*!< ETH DEBUG: TXSTSFSTS (Bitfield-Mask: 0x01) */ 7583 7584 /* ----------------------- ETH_REMOTE_WAKE_UP_FRAME_FILTER ---------------------- */ 7585 #define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos (0UL) /*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR (Bit 0) */ 7586 #define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk (0xffffffffUL) /*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR (Bitfield-Mask: 0xffffffff) */ 7587 7588 /* --------------------------- ETH_PMT_CONTROL_STATUS --------------------------- */ 7589 #define ETH_PMT_CONTROL_STATUS_PWRDWN_Pos (0UL) /*!< ETH PMT_CONTROL_STATUS: PWRDWN (Bit 0) */ 7590 #define ETH_PMT_CONTROL_STATUS_PWRDWN_Msk (0x1UL) /*!< ETH PMT_CONTROL_STATUS: PWRDWN (Bitfield-Mask: 0x01) */ 7591 #define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos (1UL) /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN (Bit 1) */ 7592 #define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk (0x2UL) /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN (Bitfield-Mask: 0x01) */ 7593 #define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos (2UL) /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN (Bit 2) */ 7594 #define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk (0x4UL) /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN (Bitfield-Mask: 0x01) */ 7595 #define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos (5UL) /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD (Bit 5) */ 7596 #define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk (0x20UL) /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD (Bitfield-Mask: 0x01) */ 7597 #define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos (6UL) /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD (Bit 6) */ 7598 #define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk (0x40UL) /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD (Bitfield-Mask: 0x01) */ 7599 #define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos (9UL) /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST (Bit 9) */ 7600 #define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk (0x200UL) /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST (Bitfield-Mask: 0x01) */ 7601 #define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos (31UL) /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST (Bit 31) */ 7602 #define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk (0x80000000UL) /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST (Bitfield-Mask: 0x01) */ 7603 7604 /* ---------------------------- ETH_INTERRUPT_STATUS ---------------------------- */ 7605 #define ETH_INTERRUPT_STATUS_PMTIS_Pos (3UL) /*!< ETH INTERRUPT_STATUS: PMTIS (Bit 3) */ 7606 #define ETH_INTERRUPT_STATUS_PMTIS_Msk (0x8UL) /*!< ETH INTERRUPT_STATUS: PMTIS (Bitfield-Mask: 0x01) */ 7607 #define ETH_INTERRUPT_STATUS_MMCIS_Pos (4UL) /*!< ETH INTERRUPT_STATUS: MMCIS (Bit 4) */ 7608 #define ETH_INTERRUPT_STATUS_MMCIS_Msk (0x10UL) /*!< ETH INTERRUPT_STATUS: MMCIS (Bitfield-Mask: 0x01) */ 7609 #define ETH_INTERRUPT_STATUS_MMCRXIS_Pos (5UL) /*!< ETH INTERRUPT_STATUS: MMCRXIS (Bit 5) */ 7610 #define ETH_INTERRUPT_STATUS_MMCRXIS_Msk (0x20UL) /*!< ETH INTERRUPT_STATUS: MMCRXIS (Bitfield-Mask: 0x01) */ 7611 #define ETH_INTERRUPT_STATUS_MMCTXIS_Pos (6UL) /*!< ETH INTERRUPT_STATUS: MMCTXIS (Bit 6) */ 7612 #define ETH_INTERRUPT_STATUS_MMCTXIS_Msk (0x40UL) /*!< ETH INTERRUPT_STATUS: MMCTXIS (Bitfield-Mask: 0x01) */ 7613 #define ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos (7UL) /*!< ETH INTERRUPT_STATUS: MMCRXIPIS (Bit 7) */ 7614 #define ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk (0x80UL) /*!< ETH INTERRUPT_STATUS: MMCRXIPIS (Bitfield-Mask: 0x01) */ 7615 #define ETH_INTERRUPT_STATUS_TSIS_Pos (9UL) /*!< ETH INTERRUPT_STATUS: TSIS (Bit 9) */ 7616 #define ETH_INTERRUPT_STATUS_TSIS_Msk (0x200UL) /*!< ETH INTERRUPT_STATUS: TSIS (Bitfield-Mask: 0x01) */ 7617 7618 /* ----------------------------- ETH_INTERRUPT_MASK ----------------------------- */ 7619 #define ETH_INTERRUPT_MASK_PMTIM_Pos (3UL) /*!< ETH INTERRUPT_MASK: PMTIM (Bit 3) */ 7620 #define ETH_INTERRUPT_MASK_PMTIM_Msk (0x8UL) /*!< ETH INTERRUPT_MASK: PMTIM (Bitfield-Mask: 0x01) */ 7621 #define ETH_INTERRUPT_MASK_TSIM_Pos (9UL) /*!< ETH INTERRUPT_MASK: TSIM (Bit 9) */ 7622 #define ETH_INTERRUPT_MASK_TSIM_Msk (0x200UL) /*!< ETH INTERRUPT_MASK: TSIM (Bitfield-Mask: 0x01) */ 7623 7624 /* ---------------------------- ETH_MAC_ADDRESS0_HIGH --------------------------- */ 7625 #define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos (0UL) /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI (Bit 0) */ 7626 #define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk (0xffffUL) /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI (Bitfield-Mask: 0xffff) */ 7627 #define ETH_MAC_ADDRESS0_HIGH_AE_Pos (31UL) /*!< ETH MAC_ADDRESS0_HIGH: AE (Bit 31) */ 7628 #define ETH_MAC_ADDRESS0_HIGH_AE_Msk (0x80000000UL) /*!< ETH MAC_ADDRESS0_HIGH: AE (Bitfield-Mask: 0x01) */ 7629 7630 /* ---------------------------- ETH_MAC_ADDRESS0_LOW ---------------------------- */ 7631 #define ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos (0UL) /*!< ETH MAC_ADDRESS0_LOW: ADDRLO (Bit 0) */ 7632 #define ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk (0xffffffffUL) /*!< ETH MAC_ADDRESS0_LOW: ADDRLO (Bitfield-Mask: 0xffffffff) */ 7633 7634 /* ---------------------------- ETH_MAC_ADDRESS1_HIGH --------------------------- */ 7635 #define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos (0UL) /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI (Bit 0) */ 7636 #define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk (0xffffUL) /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI (Bitfield-Mask: 0xffff) */ 7637 #define ETH_MAC_ADDRESS1_HIGH_MBC_Pos (24UL) /*!< ETH MAC_ADDRESS1_HIGH: MBC (Bit 24) */ 7638 #define ETH_MAC_ADDRESS1_HIGH_MBC_Msk (0x3f000000UL) /*!< ETH MAC_ADDRESS1_HIGH: MBC (Bitfield-Mask: 0x3f) */ 7639 #define ETH_MAC_ADDRESS1_HIGH_SA_Pos (30UL) /*!< ETH MAC_ADDRESS1_HIGH: SA (Bit 30) */ 7640 #define ETH_MAC_ADDRESS1_HIGH_SA_Msk (0x40000000UL) /*!< ETH MAC_ADDRESS1_HIGH: SA (Bitfield-Mask: 0x01) */ 7641 #define ETH_MAC_ADDRESS1_HIGH_AE_Pos (31UL) /*!< ETH MAC_ADDRESS1_HIGH: AE (Bit 31) */ 7642 #define ETH_MAC_ADDRESS1_HIGH_AE_Msk (0x80000000UL) /*!< ETH MAC_ADDRESS1_HIGH: AE (Bitfield-Mask: 0x01) */ 7643 7644 /* ---------------------------- ETH_MAC_ADDRESS1_LOW ---------------------------- */ 7645 #define ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos (0UL) /*!< ETH MAC_ADDRESS1_LOW: ADDRLO (Bit 0) */ 7646 #define ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk (0xffffffffUL) /*!< ETH MAC_ADDRESS1_LOW: ADDRLO (Bitfield-Mask: 0xffffffff) */ 7647 7648 /* ---------------------------- ETH_MAC_ADDRESS2_HIGH --------------------------- */ 7649 #define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos (0UL) /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI (Bit 0) */ 7650 #define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk (0xffffUL) /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI (Bitfield-Mask: 0xffff) */ 7651 #define ETH_MAC_ADDRESS2_HIGH_MBC_Pos (24UL) /*!< ETH MAC_ADDRESS2_HIGH: MBC (Bit 24) */ 7652 #define ETH_MAC_ADDRESS2_HIGH_MBC_Msk (0x3f000000UL) /*!< ETH MAC_ADDRESS2_HIGH: MBC (Bitfield-Mask: 0x3f) */ 7653 #define ETH_MAC_ADDRESS2_HIGH_SA_Pos (30UL) /*!< ETH MAC_ADDRESS2_HIGH: SA (Bit 30) */ 7654 #define ETH_MAC_ADDRESS2_HIGH_SA_Msk (0x40000000UL) /*!< ETH MAC_ADDRESS2_HIGH: SA (Bitfield-Mask: 0x01) */ 7655 #define ETH_MAC_ADDRESS2_HIGH_AE_Pos (31UL) /*!< ETH MAC_ADDRESS2_HIGH: AE (Bit 31) */ 7656 #define ETH_MAC_ADDRESS2_HIGH_AE_Msk (0x80000000UL) /*!< ETH MAC_ADDRESS2_HIGH: AE (Bitfield-Mask: 0x01) */ 7657 7658 /* ---------------------------- ETH_MAC_ADDRESS2_LOW ---------------------------- */ 7659 #define ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos (0UL) /*!< ETH MAC_ADDRESS2_LOW: ADDRLO (Bit 0) */ 7660 #define ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk (0xffffffffUL) /*!< ETH MAC_ADDRESS2_LOW: ADDRLO (Bitfield-Mask: 0xffffffff) */ 7661 7662 /* ---------------------------- ETH_MAC_ADDRESS3_HIGH --------------------------- */ 7663 #define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos (0UL) /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI (Bit 0) */ 7664 #define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk (0xffffUL) /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI (Bitfield-Mask: 0xffff) */ 7665 #define ETH_MAC_ADDRESS3_HIGH_MBC_Pos (24UL) /*!< ETH MAC_ADDRESS3_HIGH: MBC (Bit 24) */ 7666 #define ETH_MAC_ADDRESS3_HIGH_MBC_Msk (0x3f000000UL) /*!< ETH MAC_ADDRESS3_HIGH: MBC (Bitfield-Mask: 0x3f) */ 7667 #define ETH_MAC_ADDRESS3_HIGH_SA_Pos (30UL) /*!< ETH MAC_ADDRESS3_HIGH: SA (Bit 30) */ 7668 #define ETH_MAC_ADDRESS3_HIGH_SA_Msk (0x40000000UL) /*!< ETH MAC_ADDRESS3_HIGH: SA (Bitfield-Mask: 0x01) */ 7669 #define ETH_MAC_ADDRESS3_HIGH_AE_Pos (31UL) /*!< ETH MAC_ADDRESS3_HIGH: AE (Bit 31) */ 7670 #define ETH_MAC_ADDRESS3_HIGH_AE_Msk (0x80000000UL) /*!< ETH MAC_ADDRESS3_HIGH: AE (Bitfield-Mask: 0x01) */ 7671 7672 /* ---------------------------- ETH_MAC_ADDRESS3_LOW ---------------------------- */ 7673 #define ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos (0UL) /*!< ETH MAC_ADDRESS3_LOW: ADDRLO (Bit 0) */ 7674 #define ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk (0xffffffffUL) /*!< ETH MAC_ADDRESS3_LOW: ADDRLO (Bitfield-Mask: 0xffffffff) */ 7675 7676 /* ------------------------------- ETH_MMC_CONTROL ------------------------------ */ 7677 #define ETH_MMC_CONTROL_CNTRST_Pos (0UL) /*!< ETH MMC_CONTROL: CNTRST (Bit 0) */ 7678 #define ETH_MMC_CONTROL_CNTRST_Msk (0x1UL) /*!< ETH MMC_CONTROL: CNTRST (Bitfield-Mask: 0x01) */ 7679 #define ETH_MMC_CONTROL_CNTSTOPRO_Pos (1UL) /*!< ETH MMC_CONTROL: CNTSTOPRO (Bit 1) */ 7680 #define ETH_MMC_CONTROL_CNTSTOPRO_Msk (0x2UL) /*!< ETH MMC_CONTROL: CNTSTOPRO (Bitfield-Mask: 0x01) */ 7681 #define ETH_MMC_CONTROL_RSTONRD_Pos (2UL) /*!< ETH MMC_CONTROL: RSTONRD (Bit 2) */ 7682 #define ETH_MMC_CONTROL_RSTONRD_Msk (0x4UL) /*!< ETH MMC_CONTROL: RSTONRD (Bitfield-Mask: 0x01) */ 7683 #define ETH_MMC_CONTROL_CNTFREEZ_Pos (3UL) /*!< ETH MMC_CONTROL: CNTFREEZ (Bit 3) */ 7684 #define ETH_MMC_CONTROL_CNTFREEZ_Msk (0x8UL) /*!< ETH MMC_CONTROL: CNTFREEZ (Bitfield-Mask: 0x01) */ 7685 #define ETH_MMC_CONTROL_CNTPRST_Pos (4UL) /*!< ETH MMC_CONTROL: CNTPRST (Bit 4) */ 7686 #define ETH_MMC_CONTROL_CNTPRST_Msk (0x10UL) /*!< ETH MMC_CONTROL: CNTPRST (Bitfield-Mask: 0x01) */ 7687 #define ETH_MMC_CONTROL_CNTPRSTLVL_Pos (5UL) /*!< ETH MMC_CONTROL: CNTPRSTLVL (Bit 5) */ 7688 #define ETH_MMC_CONTROL_CNTPRSTLVL_Msk (0x20UL) /*!< ETH MMC_CONTROL: CNTPRSTLVL (Bitfield-Mask: 0x01) */ 7689 #define ETH_MMC_CONTROL_UCDBC_Pos (8UL) /*!< ETH MMC_CONTROL: UCDBC (Bit 8) */ 7690 #define ETH_MMC_CONTROL_UCDBC_Msk (0x100UL) /*!< ETH MMC_CONTROL: UCDBC (Bitfield-Mask: 0x01) */ 7691 7692 /* -------------------------- ETH_MMC_RECEIVE_INTERRUPT ------------------------- */ 7693 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos (0UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS (Bit 0) */ 7694 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk (0x1UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS (Bitfield-Mask: 0x01) */ 7695 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos (1UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS (Bit 1) */ 7696 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk (0x2UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS (Bitfield-Mask: 0x01) */ 7697 #define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos (2UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS (Bit 2) */ 7698 #define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk (0x4UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS (Bitfield-Mask: 0x01) */ 7699 #define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos (3UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS (Bit 3) */ 7700 #define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk (0x8UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS (Bitfield-Mask: 0x01) */ 7701 #define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos (4UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS (Bit 4) */ 7702 #define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk (0x10UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS (Bitfield-Mask: 0x01) */ 7703 #define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos (5UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS (Bit 5) */ 7704 #define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk (0x20UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS (Bitfield-Mask: 0x01) */ 7705 #define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos (6UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS (Bit 6) */ 7706 #define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk (0x40UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS (Bitfield-Mask: 0x01) */ 7707 #define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos (7UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS (Bit 7) */ 7708 #define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk (0x80UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS (Bitfield-Mask: 0x01) */ 7709 #define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos (8UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS (Bit 8) */ 7710 #define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk (0x100UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS (Bitfield-Mask: 0x01) */ 7711 #define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos (9UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS (Bit 9) */ 7712 #define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk (0x200UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS (Bitfield-Mask: 0x01) */ 7713 #define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos (10UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS (Bit 10) */ 7714 #define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk (0x400UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS (Bitfield-Mask: 0x01) */ 7715 #define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos (11UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS (Bit 11) */ 7716 #define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk (0x800UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS (Bitfield-Mask: 0x01) */ 7717 #define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos (12UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS (Bit 12) */ 7718 #define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk (0x1000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ 7719 #define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos (13UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS (Bit 13) */ 7720 #define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk (0x2000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ 7721 #define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos (14UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS (Bit 14) */ 7722 #define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk (0x4000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ 7723 #define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos (15UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS (Bit 15) */ 7724 #define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk (0x8000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ 7725 #define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos (16UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS (Bit 16) */ 7726 #define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk (0x10000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ 7727 #define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos (17UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS (Bit 17) */ 7728 #define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk (0x20000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS (Bitfield-Mask: 0x01) */ 7729 #define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos (18UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS (Bit 18) */ 7730 #define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk (0x40000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS (Bitfield-Mask: 0x01) */ 7731 #define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos (19UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS (Bit 19) */ 7732 #define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk (0x80000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS (Bitfield-Mask: 0x01) */ 7733 #define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos (20UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS (Bit 20) */ 7734 #define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk (0x100000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS (Bitfield-Mask: 0x01) */ 7735 #define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos (21UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS (Bit 21) */ 7736 #define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk (0x200000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS (Bitfield-Mask: 0x01) */ 7737 #define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos (22UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS (Bit 22) */ 7738 #define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk (0x400000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS (Bitfield-Mask: 0x01) */ 7739 #define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos (23UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS (Bit 23) */ 7740 #define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk (0x800000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS (Bitfield-Mask: 0x01) */ 7741 #define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos (24UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS (Bit 24) */ 7742 #define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk (0x1000000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS (Bitfield-Mask: 0x01) */ 7743 #define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos (25UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS (Bit 25) */ 7744 #define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk (0x2000000UL) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS (Bitfield-Mask: 0x01) */ 7745 7746 /* ------------------------- ETH_MMC_TRANSMIT_INTERRUPT ------------------------- */ 7747 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos (0UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS (Bit 0) */ 7748 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk (0x1UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS (Bitfield-Mask: 0x01) */ 7749 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos (1UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS (Bit 1) */ 7750 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk (0x2UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS (Bitfield-Mask: 0x01) */ 7751 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos (2UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS (Bit 2) */ 7752 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk (0x4UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS (Bitfield-Mask: 0x01) */ 7753 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos (3UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS (Bit 3) */ 7754 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk (0x8UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS (Bitfield-Mask: 0x01) */ 7755 #define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos (4UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS (Bit 4) */ 7756 #define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk (0x10UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS (Bitfield-Mask: 0x01) */ 7757 #define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos (5UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS (Bit 5) */ 7758 #define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk (0x20UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ 7759 #define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos (6UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS (Bit 6) */ 7760 #define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk (0x40UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ 7761 #define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos (7UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS (Bit 7) */ 7762 #define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk (0x80UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ 7763 #define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos (8UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS (Bit 8) */ 7764 #define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk (0x100UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ 7765 #define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos (9UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS (Bit 9) */ 7766 #define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk (0x200UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ 7767 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos (10UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS (Bit 10) */ 7768 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk (0x400UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS (Bitfield-Mask: 0x01) */ 7769 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos (11UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS (Bit 11) */ 7770 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk (0x800UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS (Bitfield-Mask: 0x01) */ 7771 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos (12UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS (Bit 12) */ 7772 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk (0x1000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS (Bitfield-Mask: 0x01) */ 7773 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos (13UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS (Bit 13) */ 7774 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk (0x2000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS (Bitfield-Mask: 0x01) */ 7775 #define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos (14UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS (Bit 14) */ 7776 #define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk (0x4000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS (Bitfield-Mask: 0x01) */ 7777 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos (15UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS (Bit 15) */ 7778 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk (0x8000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS (Bitfield-Mask: 0x01) */ 7779 #define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos (16UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS (Bit 16) */ 7780 #define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk (0x10000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS (Bitfield-Mask: 0x01) */ 7781 #define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos (17UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS (Bit 17) */ 7782 #define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk (0x20000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS (Bitfield-Mask: 0x01) */ 7783 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos (18UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS (Bit 18) */ 7784 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk (0x40000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS (Bitfield-Mask: 0x01) */ 7785 #define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos (19UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS (Bit 19) */ 7786 #define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk (0x80000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS (Bitfield-Mask: 0x01) */ 7787 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos (20UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS (Bit 20) */ 7788 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk (0x100000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS (Bitfield-Mask: 0x01) */ 7789 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos (21UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS (Bit 21) */ 7790 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk (0x200000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS (Bitfield-Mask: 0x01) */ 7791 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos (22UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS (Bit 22) */ 7792 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk (0x400000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS (Bitfield-Mask: 0x01) */ 7793 #define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos (23UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS (Bit 23) */ 7794 #define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk (0x800000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS (Bitfield-Mask: 0x01) */ 7795 #define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos (24UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS (Bit 24) */ 7796 #define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk (0x1000000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS (Bitfield-Mask: 0x01) */ 7797 #define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos (25UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS (Bit 25) */ 7798 #define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk (0x2000000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS (Bitfield-Mask: 0x01) */ 7799 7800 /* ----------------------- ETH_MMC_RECEIVE_INTERRUPT_MASK ----------------------- */ 7801 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos (0UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM (Bit 0) */ 7802 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk (0x1UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM (Bitfield-Mask: 0x01) */ 7803 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos (1UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM (Bit 1) */ 7804 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk (0x2UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM (Bitfield-Mask: 0x01) */ 7805 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos (2UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM (Bit 2) */ 7806 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk (0x4UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM (Bitfield-Mask: 0x01) */ 7807 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos (3UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM (Bit 3) */ 7808 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk (0x8UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM (Bitfield-Mask: 0x01) */ 7809 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos (4UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM (Bit 4) */ 7810 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk (0x10UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM (Bitfield-Mask: 0x01) */ 7811 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos (5UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM (Bit 5) */ 7812 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk (0x20UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM (Bitfield-Mask: 0x01) */ 7813 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos (6UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM (Bit 6) */ 7814 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk (0x40UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM (Bitfield-Mask: 0x01) */ 7815 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos (7UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM (Bit 7) */ 7816 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk (0x80UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM (Bitfield-Mask: 0x01) */ 7817 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos (8UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM (Bit 8) */ 7818 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk (0x100UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM (Bitfield-Mask: 0x01) */ 7819 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos (9UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM (Bit 9) */ 7820 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk (0x200UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM (Bitfield-Mask: 0x01) */ 7821 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos (10UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM (Bit 10) */ 7822 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk (0x400UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM (Bitfield-Mask: 0x01) */ 7823 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos (11UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM (Bit 11) */ 7824 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk (0x800UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM (Bitfield-Mask: 0x01) */ 7825 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos (12UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM (Bit 12) */ 7826 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk (0x1000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ 7827 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos (13UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM (Bit 13) */ 7828 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk (0x2000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ 7829 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos (14UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM (Bit 14) */ 7830 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk (0x4000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ 7831 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos (15UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM (Bit 15) */ 7832 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk (0x8000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ 7833 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos (16UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM (Bit 16) */ 7834 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk (0x10000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ 7835 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos (17UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM (Bit 17) */ 7836 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk (0x20000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM (Bitfield-Mask: 0x01) */ 7837 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos (18UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM (Bit 18) */ 7838 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk (0x40000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM (Bitfield-Mask: 0x01) */ 7839 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos (19UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM (Bit 19) */ 7840 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk (0x80000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM (Bitfield-Mask: 0x01) */ 7841 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos (20UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM (Bit 20) */ 7842 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk (0x100000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM (Bitfield-Mask: 0x01) */ 7843 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos (21UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM (Bit 21) */ 7844 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk (0x200000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM (Bitfield-Mask: 0x01) */ 7845 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos (22UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM (Bit 22) */ 7846 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk (0x400000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM (Bitfield-Mask: 0x01) */ 7847 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos (23UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM (Bit 23) */ 7848 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk (0x800000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM (Bitfield-Mask: 0x01) */ 7849 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos (24UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM (Bit 24) */ 7850 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk (0x1000000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM (Bitfield-Mask: 0x01) */ 7851 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos (25UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM (Bit 25) */ 7852 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk (0x2000000UL) /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM (Bitfield-Mask: 0x01) */ 7853 7854 /* ----------------------- ETH_MMC_TRANSMIT_INTERRUPT_MASK ---------------------- */ 7855 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos (0UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM (Bit 0) */ 7856 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk (0x1UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM (Bitfield-Mask: 0x01) */ 7857 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos (1UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM (Bit 1) */ 7858 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk (0x2UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM (Bitfield-Mask: 0x01) */ 7859 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos (2UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM (Bit 2) */ 7860 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk (0x4UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM (Bitfield-Mask: 0x01) */ 7861 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos (3UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM (Bit 3) */ 7862 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk (0x8UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM (Bitfield-Mask: 0x01) */ 7863 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos (4UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM (Bit 4) */ 7864 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk (0x10UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM (Bitfield-Mask: 0x01) */ 7865 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos (5UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM (Bit 5) */ 7866 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk (0x20UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ 7867 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos (6UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM (Bit 6) */ 7868 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk (0x40UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ 7869 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos (7UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM (Bit 7) */ 7870 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk (0x80UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ 7871 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos (8UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM (Bit 8) */ 7872 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk (0x100UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ 7873 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos (9UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM (Bit 9) */ 7874 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk (0x200UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ 7875 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos (10UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM (Bit 10) */ 7876 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk (0x400UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM (Bitfield-Mask: 0x01) */ 7877 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos (11UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM (Bit 11) */ 7878 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk (0x800UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM (Bitfield-Mask: 0x01) */ 7879 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos (12UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM (Bit 12) */ 7880 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk (0x1000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM (Bitfield-Mask: 0x01) */ 7881 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos (13UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM (Bit 13) */ 7882 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk (0x2000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM (Bitfield-Mask: 0x01) */ 7883 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos (14UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM (Bit 14) */ 7884 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk (0x4000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM (Bitfield-Mask: 0x01) */ 7885 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos (15UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM (Bit 15) */ 7886 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk (0x8000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM (Bitfield-Mask: 0x01) */ 7887 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos (16UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM (Bit 16) */ 7888 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk (0x10000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM (Bitfield-Mask: 0x01) */ 7889 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos (17UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM (Bit 17) */ 7890 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk (0x20000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM (Bitfield-Mask: 0x01) */ 7891 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos (18UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM (Bit 18) */ 7892 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk (0x40000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM (Bitfield-Mask: 0x01) */ 7893 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos (19UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM (Bit 19) */ 7894 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk (0x80000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM (Bitfield-Mask: 0x01) */ 7895 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos (20UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM (Bit 20) */ 7896 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk (0x100000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM (Bitfield-Mask: 0x01) */ 7897 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos (21UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM (Bit 21) */ 7898 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk (0x200000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM (Bitfield-Mask: 0x01) */ 7899 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos (22UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM (Bit 22) */ 7900 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk (0x400000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM (Bitfield-Mask: 0x01) */ 7901 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos (23UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM (Bit 23) */ 7902 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk (0x800000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM (Bitfield-Mask: 0x01) */ 7903 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos (24UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM (Bit 24) */ 7904 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk (0x1000000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM (Bitfield-Mask: 0x01) */ 7905 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos (25UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM (Bit 25) */ 7906 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk (0x2000000UL) /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM (Bitfield-Mask: 0x01) */ 7907 7908 /* ------------------------- ETH_TX_OCTET_COUNT_GOOD_BAD ------------------------ */ 7909 #define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos (0UL) /*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB (Bit 0) */ 7910 #define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk (0xffffffffUL) /*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB (Bitfield-Mask: 0xffffffff) */ 7911 7912 /* ------------------------- ETH_TX_FRAME_COUNT_GOOD_BAD ------------------------ */ 7913 #define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos (0UL) /*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB (Bit 0) */ 7914 #define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk (0xffffffffUL) /*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB (Bitfield-Mask: 0xffffffff) */ 7915 7916 /* ------------------------ ETH_TX_BROADCAST_FRAMES_GOOD ------------------------ */ 7917 #define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos (0UL) /*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG (Bit 0) */ 7918 #define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk (0xffffffffUL) /*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG (Bitfield-Mask: 0xffffffff) */ 7919 7920 /* ------------------------ ETH_TX_MULTICAST_FRAMES_GOOD ------------------------ */ 7921 #define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos (0UL) /*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG (Bit 0) */ 7922 #define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk (0xffffffffUL) /*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG (Bitfield-Mask: 0xffffffff) */ 7923 7924 /* ----------------------- ETH_TX_64OCTETS_FRAMES_GOOD_BAD ---------------------- */ 7925 #define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos (0UL) /*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB (Bit 0) */ 7926 #define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk (0xffffffffUL) /*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB (Bitfield-Mask: 0xffffffff) */ 7927 7928 /* -------------------- ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD -------------------- */ 7929 #define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos (0UL) /*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB (Bit 0) */ 7930 #define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk (0xffffffffUL) /*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB (Bitfield-Mask: 0xffffffff) */ 7931 7932 /* -------------------- ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD ------------------- */ 7933 #define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos (0UL) /*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB (Bit 0) */ 7934 #define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk (0xffffffffUL) /*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB (Bitfield-Mask: 0xffffffff) */ 7935 7936 /* -------------------- ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD ------------------- */ 7937 #define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos (0UL) /*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB (Bit 0) */ 7938 #define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk (0xffffffffUL) /*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB (Bitfield-Mask: 0xffffffff) */ 7939 7940 /* ------------------- ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD ------------------- */ 7941 #define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos (0UL) /*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB (Bit 0) */ 7942 #define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk (0xffffffffUL) /*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */ 7943 7944 /* ------------------- ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD ------------------- */ 7945 #define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos (0UL) /*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB (Bit 0) */ 7946 #define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk (0xffffffffUL) /*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */ 7947 7948 /* ----------------------- ETH_TX_UNICAST_FRAMES_GOOD_BAD ----------------------- */ 7949 #define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos (0UL) /*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB (Bit 0) */ 7950 #define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk (0xffffffffUL) /*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB (Bitfield-Mask: 0xffffffff) */ 7951 7952 /* ---------------------- ETH_TX_MULTICAST_FRAMES_GOOD_BAD ---------------------- */ 7953 #define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos (0UL) /*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB (Bit 0) */ 7954 #define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk (0xffffffffUL) /*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB (Bitfield-Mask: 0xffffffff) */ 7955 7956 /* ---------------------- ETH_TX_BROADCAST_FRAMES_GOOD_BAD ---------------------- */ 7957 #define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos (0UL) /*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB (Bit 0) */ 7958 #define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk (0xffffffffUL) /*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB (Bitfield-Mask: 0xffffffff) */ 7959 7960 /* ------------------------ ETH_TX_UNDERFLOW_ERROR_FRAMES ----------------------- */ 7961 #define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos (0UL) /*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW (Bit 0) */ 7962 #define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk (0xffffffffUL) /*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW (Bitfield-Mask: 0xffffffff) */ 7963 7964 /* --------------------- ETH_TX_SINGLE_COLLISION_GOOD_FRAMES -------------------- */ 7965 #define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos (0UL) /*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG (Bit 0) */ 7966 #define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk (0xffffffffUL) /*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG (Bitfield-Mask: 0xffffffff) */ 7967 7968 /* -------------------- ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES ------------------- */ 7969 #define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos (0UL) /*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG (Bit 0) */ 7970 #define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk (0xffffffffUL) /*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG (Bitfield-Mask: 0xffffffff) */ 7971 7972 /* --------------------------- ETH_TX_DEFERRED_FRAMES --------------------------- */ 7973 #define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos (0UL) /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD (Bit 0) */ 7974 #define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk (0xffffffffUL) /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD (Bitfield-Mask: 0xffffffff) */ 7975 7976 /* ------------------------ ETH_TX_LATE_COLLISION_FRAMES ------------------------ */ 7977 #define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos (0UL) /*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL (Bit 0) */ 7978 #define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk (0xffffffffUL) /*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL (Bitfield-Mask: 0xffffffff) */ 7979 7980 /* ---------------------- ETH_TX_EXCESSIVE_COLLISION_FRAMES --------------------- */ 7981 #define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos (0UL) /*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL (Bit 0) */ 7982 #define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk (0xffffffffUL) /*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL (Bitfield-Mask: 0xffffffff) */ 7983 7984 /* ------------------------- ETH_TX_CARRIER_ERROR_FRAMES ------------------------ */ 7985 #define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos (0UL) /*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR (Bit 0) */ 7986 #define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk (0xffffffffUL) /*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR (Bitfield-Mask: 0xffffffff) */ 7987 7988 /* --------------------------- ETH_TX_OCTET_COUNT_GOOD -------------------------- */ 7989 #define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos (0UL) /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG (Bit 0) */ 7990 #define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk (0xffffffffUL) /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG (Bitfield-Mask: 0xffffffff) */ 7991 7992 /* --------------------------- ETH_TX_FRAME_COUNT_GOOD -------------------------- */ 7993 #define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos (0UL) /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG (Bit 0) */ 7994 #define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk (0xffffffffUL) /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG (Bitfield-Mask: 0xffffffff) */ 7995 7996 /* ----------------------- ETH_TX_EXCESSIVE_DEFERRAL_ERROR ---------------------- */ 7997 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos (0UL) /*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF (Bit 0) */ 7998 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk (0xffffffffUL) /*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF (Bitfield-Mask: 0xffffffff) */ 7999 8000 /* ----------------------------- ETH_TX_PAUSE_FRAMES ---------------------------- */ 8001 #define ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos (0UL) /*!< ETH TX_PAUSE_FRAMES: TXPAUSE (Bit 0) */ 8002 #define ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk (0xffffffffUL) /*!< ETH TX_PAUSE_FRAMES: TXPAUSE (Bitfield-Mask: 0xffffffff) */ 8003 8004 /* --------------------------- ETH_TX_VLAN_FRAMES_GOOD -------------------------- */ 8005 #define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos (0UL) /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG (Bit 0) */ 8006 #define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk (0xffffffffUL) /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG (Bitfield-Mask: 0xffffffff) */ 8007 8008 /* -------------------------- ETH_TX_OSIZE_FRAMES_GOOD -------------------------- */ 8009 #define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos (0UL) /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG (Bit 0) */ 8010 #define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk (0xffffffffUL) /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG (Bitfield-Mask: 0xffffffff) */ 8011 8012 /* ------------------------ ETH_RX_FRAMES_COUNT_GOOD_BAD ------------------------ */ 8013 #define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos (0UL) /*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB (Bit 0) */ 8014 #define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk (0xffffffffUL) /*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB (Bitfield-Mask: 0xffffffff) */ 8015 8016 /* ------------------------- ETH_RX_OCTET_COUNT_GOOD_BAD ------------------------ */ 8017 #define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos (0UL) /*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB (Bit 0) */ 8018 #define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk (0xffffffffUL) /*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB (Bitfield-Mask: 0xffffffff) */ 8019 8020 /* --------------------------- ETH_RX_OCTET_COUNT_GOOD -------------------------- */ 8021 #define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos (0UL) /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG (Bit 0) */ 8022 #define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk (0xffffffffUL) /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG (Bitfield-Mask: 0xffffffff) */ 8023 8024 /* ------------------------ ETH_RX_BROADCAST_FRAMES_GOOD ------------------------ */ 8025 #define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos (0UL) /*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG (Bit 0) */ 8026 #define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk (0xffffffffUL) /*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG (Bitfield-Mask: 0xffffffff) */ 8027 8028 /* ------------------------ ETH_RX_MULTICAST_FRAMES_GOOD ------------------------ */ 8029 #define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos (0UL) /*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG (Bit 0) */ 8030 #define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk (0xffffffffUL) /*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG (Bitfield-Mask: 0xffffffff) */ 8031 8032 /* --------------------------- ETH_RX_CRC_ERROR_FRAMES -------------------------- */ 8033 #define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos (0UL) /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR (Bit 0) */ 8034 #define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk (0xffffffffUL) /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR (Bitfield-Mask: 0xffffffff) */ 8035 8036 /* ------------------------ ETH_RX_ALIGNMENT_ERROR_FRAMES ----------------------- */ 8037 #define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos (0UL) /*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR (Bit 0) */ 8038 #define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk (0xffffffffUL) /*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR (Bitfield-Mask: 0xffffffff) */ 8039 8040 /* -------------------------- ETH_RX_RUNT_ERROR_FRAMES -------------------------- */ 8041 #define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos (0UL) /*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR (Bit 0) */ 8042 #define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk (0xffffffffUL) /*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR (Bitfield-Mask: 0xffffffff) */ 8043 8044 /* ------------------------- ETH_RX_JABBER_ERROR_FRAMES ------------------------- */ 8045 #define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos (0UL) /*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR (Bit 0) */ 8046 #define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk (0xffffffffUL) /*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR (Bitfield-Mask: 0xffffffff) */ 8047 8048 /* ------------------------ ETH_RX_UNDERSIZE_FRAMES_GOOD ------------------------ */ 8049 #define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos (0UL) /*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG (Bit 0) */ 8050 #define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk (0xffffffffUL) /*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG (Bitfield-Mask: 0xffffffff) */ 8051 8052 /* ------------------------- ETH_RX_OVERSIZE_FRAMES_GOOD ------------------------ */ 8053 #define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos (0UL) /*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG (Bit 0) */ 8054 #define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk (0xffffffffUL) /*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG (Bitfield-Mask: 0xffffffff) */ 8055 8056 /* ----------------------- ETH_RX_64OCTETS_FRAMES_GOOD_BAD ---------------------- */ 8057 #define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos (0UL) /*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB (Bit 0) */ 8058 #define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk (0xffffffffUL) /*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB (Bitfield-Mask: 0xffffffff) */ 8059 8060 /* -------------------- ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD -------------------- */ 8061 #define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos (0UL) /*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB (Bit 0) */ 8062 #define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk (0xffffffffUL) /*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB (Bitfield-Mask: 0xffffffff) */ 8063 8064 /* -------------------- ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD ------------------- */ 8065 #define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos (0UL) /*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB (Bit 0) */ 8066 #define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk (0xffffffffUL) /*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB (Bitfield-Mask: 0xffffffff) */ 8067 8068 /* -------------------- ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD ------------------- */ 8069 #define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos (0UL) /*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB (Bit 0) */ 8070 #define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk (0xffffffffUL) /*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB (Bitfield-Mask: 0xffffffff) */ 8071 8072 /* ------------------- ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD ------------------- */ 8073 #define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos (0UL) /*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB (Bit 0) */ 8074 #define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk (0xffffffffUL) /*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */ 8075 8076 /* ------------------- ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD ------------------- */ 8077 #define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos (0UL) /*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB (Bit 0) */ 8078 #define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk (0xffffffffUL) /*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */ 8079 8080 /* ------------------------- ETH_RX_UNICAST_FRAMES_GOOD ------------------------- */ 8081 #define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos (0UL) /*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG (Bit 0) */ 8082 #define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk (0xffffffffUL) /*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG (Bitfield-Mask: 0xffffffff) */ 8083 8084 /* ------------------------- ETH_RX_LENGTH_ERROR_FRAMES ------------------------- */ 8085 #define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos (0UL) /*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR (Bit 0) */ 8086 #define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk (0xffffffffUL) /*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR (Bitfield-Mask: 0xffffffff) */ 8087 8088 /* ----------------------- ETH_RX_OUT_OF_RANGE_TYPE_FRAMES ---------------------- */ 8089 #define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos (0UL) /*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG (Bit 0) */ 8090 #define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk (0xffffffffUL) /*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG (Bitfield-Mask: 0xffffffff) */ 8091 8092 /* ----------------------------- ETH_RX_PAUSE_FRAMES ---------------------------- */ 8093 #define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos (0UL) /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM (Bit 0) */ 8094 #define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk (0xffffffffUL) /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM (Bitfield-Mask: 0xffffffff) */ 8095 8096 /* ------------------------- ETH_RX_FIFO_OVERFLOW_FRAMES ------------------------ */ 8097 #define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos (0UL) /*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL (Bit 0) */ 8098 #define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk (0xffffffffUL) /*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL (Bitfield-Mask: 0xffffffff) */ 8099 8100 /* ------------------------- ETH_RX_VLAN_FRAMES_GOOD_BAD ------------------------ */ 8101 #define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos (0UL) /*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB (Bit 0) */ 8102 #define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk (0xffffffffUL) /*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB (Bitfield-Mask: 0xffffffff) */ 8103 8104 /* ------------------------ ETH_RX_WATCHDOG_ERROR_FRAMES ------------------------ */ 8105 #define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos (0UL) /*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR (Bit 0) */ 8106 #define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk (0xffffffffUL) /*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR (Bitfield-Mask: 0xffffffff) */ 8107 8108 /* ------------------------- ETH_RX_RECEIVE_ERROR_FRAMES ------------------------ */ 8109 #define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos (0UL) /*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR (Bit 0) */ 8110 #define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk (0xffffffffUL) /*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR (Bitfield-Mask: 0xffffffff) */ 8111 8112 /* ------------------------- ETH_RX_CONTROL_FRAMES_GOOD ------------------------- */ 8113 #define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos (0UL) /*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG (Bit 0) */ 8114 #define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk (0xffffffffUL) /*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG (Bitfield-Mask: 0xffffffff) */ 8115 8116 /* --------------------- ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK --------------------- */ 8117 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos (0UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM (Bit 0) */ 8118 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk (0x1UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM (Bitfield-Mask: 0x01) */ 8119 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos (1UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM (Bit 1) */ 8120 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk (0x2UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM (Bitfield-Mask: 0x01) */ 8121 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos (2UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM (Bit 2) */ 8122 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk (0x4UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM (Bitfield-Mask: 0x01) */ 8123 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos (3UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM (Bit 3) */ 8124 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk (0x8UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM (Bitfield-Mask: 0x01) */ 8125 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos (4UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM (Bit 4) */ 8126 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk (0x10UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM (Bitfield-Mask: 0x01) */ 8127 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos (5UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM (Bit 5) */ 8128 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk (0x20UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM (Bitfield-Mask: 0x01) */ 8129 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos (6UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM (Bit 6) */ 8130 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk (0x40UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM (Bitfield-Mask: 0x01) */ 8131 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos (7UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM (Bit 7) */ 8132 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk (0x80UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM (Bitfield-Mask: 0x01) */ 8133 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos (8UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM (Bit 8) */ 8134 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk (0x100UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM (Bitfield-Mask: 0x01) */ 8135 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos (9UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM (Bit 9) */ 8136 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk (0x200UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM (Bitfield-Mask: 0x01) */ 8137 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos (10UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM (Bit 10) */ 8138 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk (0x400UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM (Bitfield-Mask: 0x01) */ 8139 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos (11UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM (Bit 11) */ 8140 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk (0x800UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM (Bitfield-Mask: 0x01) */ 8141 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos (12UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM (Bit 12) */ 8142 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk (0x1000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM (Bitfield-Mask: 0x01) */ 8143 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos (13UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM (Bit 13) */ 8144 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk (0x2000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM (Bitfield-Mask: 0x01) */ 8145 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos (16UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM (Bit 16) */ 8146 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk (0x10000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM (Bitfield-Mask: 0x01) */ 8147 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos (17UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM (Bit 17) */ 8148 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk (0x20000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM (Bitfield-Mask: 0x01) */ 8149 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos (18UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM (Bit 18) */ 8150 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk (0x40000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM (Bitfield-Mask: 0x01) */ 8151 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos (19UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM (Bit 19) */ 8152 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk (0x80000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM (Bitfield-Mask: 0x01) */ 8153 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos (20UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM (Bit 20) */ 8154 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk (0x100000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM (Bitfield-Mask: 0x01) */ 8155 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos (21UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM (Bit 21) */ 8156 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk (0x200000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM (Bitfield-Mask: 0x01) */ 8157 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos (22UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM (Bit 22) */ 8158 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk (0x400000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM (Bitfield-Mask: 0x01) */ 8159 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos (23UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM (Bit 23) */ 8160 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk (0x800000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM (Bitfield-Mask: 0x01) */ 8161 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos (24UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM (Bit 24) */ 8162 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk (0x1000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM (Bitfield-Mask: 0x01) */ 8163 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos (25UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM (Bit 25) */ 8164 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk (0x2000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM (Bitfield-Mask: 0x01) */ 8165 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos (26UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM (Bit 26) */ 8166 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk (0x4000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM (Bitfield-Mask: 0x01) */ 8167 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos (27UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM (Bit 27) */ 8168 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk (0x8000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM (Bitfield-Mask: 0x01) */ 8169 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos (28UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM (Bit 28) */ 8170 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk (0x10000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM (Bitfield-Mask: 0x01) */ 8171 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos (29UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM (Bit 29) */ 8172 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk (0x20000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM (Bitfield-Mask: 0x01) */ 8173 8174 /* ------------------------ ETH_MMC_IPC_RECEIVE_INTERRUPT ----------------------- */ 8175 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos (0UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS (Bit 0) */ 8176 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk (0x1UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS (Bitfield-Mask: 0x01) */ 8177 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos (1UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS (Bit 1) */ 8178 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk (0x2UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS (Bitfield-Mask: 0x01) */ 8179 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos (2UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS (Bit 2) */ 8180 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk (0x4UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS (Bitfield-Mask: 0x01) */ 8181 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos (3UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS (Bit 3) */ 8182 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk (0x8UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS (Bitfield-Mask: 0x01) */ 8183 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos (4UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS (Bit 4) */ 8184 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk (0x10UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS (Bitfield-Mask: 0x01) */ 8185 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos (5UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS (Bit 5) */ 8186 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk (0x20UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS (Bitfield-Mask: 0x01) */ 8187 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos (6UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS (Bit 6) */ 8188 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk (0x40UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS (Bitfield-Mask: 0x01) */ 8189 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos (7UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS (Bit 7) */ 8190 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk (0x80UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS (Bitfield-Mask: 0x01) */ 8191 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos (8UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS (Bit 8) */ 8192 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk (0x100UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS (Bitfield-Mask: 0x01) */ 8193 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos (9UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS (Bit 9) */ 8194 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk (0x200UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS (Bitfield-Mask: 0x01) */ 8195 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos (10UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS (Bit 10) */ 8196 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk (0x400UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS (Bitfield-Mask: 0x01) */ 8197 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos (11UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS (Bit 11) */ 8198 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk (0x800UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS (Bitfield-Mask: 0x01) */ 8199 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos (12UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS (Bit 12) */ 8200 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk (0x1000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS (Bitfield-Mask: 0x01) */ 8201 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos (13UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS (Bit 13) */ 8202 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk (0x2000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS (Bitfield-Mask: 0x01) */ 8203 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos (16UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS (Bit 16) */ 8204 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk (0x10000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS (Bitfield-Mask: 0x01) */ 8205 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos (17UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS (Bit 17) */ 8206 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk (0x20000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS (Bitfield-Mask: 0x01) */ 8207 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos (18UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS (Bit 18) */ 8208 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk (0x40000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS (Bitfield-Mask: 0x01) */ 8209 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos (19UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS (Bit 19) */ 8210 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk (0x80000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS (Bitfield-Mask: 0x01) */ 8211 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos (20UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS (Bit 20) */ 8212 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk (0x100000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS (Bitfield-Mask: 0x01) */ 8213 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos (21UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS (Bit 21) */ 8214 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk (0x200000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS (Bitfield-Mask: 0x01) */ 8215 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos (22UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS (Bit 22) */ 8216 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk (0x400000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS (Bitfield-Mask: 0x01) */ 8217 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos (23UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS (Bit 23) */ 8218 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk (0x800000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS (Bitfield-Mask: 0x01) */ 8219 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos (24UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS (Bit 24) */ 8220 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk (0x1000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS (Bitfield-Mask: 0x01) */ 8221 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos (25UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS (Bit 25) */ 8222 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk (0x2000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS (Bitfield-Mask: 0x01) */ 8223 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos (26UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS (Bit 26) */ 8224 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk (0x4000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS (Bitfield-Mask: 0x01) */ 8225 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos (27UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS (Bit 27) */ 8226 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk (0x8000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS (Bitfield-Mask: 0x01) */ 8227 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos (28UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS (Bit 28) */ 8228 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk (0x10000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS (Bitfield-Mask: 0x01) */ 8229 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos (29UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS (Bit 29) */ 8230 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk (0x20000000UL) /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS (Bitfield-Mask: 0x01) */ 8231 8232 /* --------------------------- ETH_RXIPV4_GOOD_FRAMES --------------------------- */ 8233 #define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos (0UL) /*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM (Bit 0) */ 8234 #define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk (0xffffffffUL) /*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM (Bitfield-Mask: 0xffffffff) */ 8235 8236 /* ----------------------- ETH_RXIPV4_HEADER_ERROR_FRAMES ----------------------- */ 8237 #define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos (0UL) /*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM (Bit 0) */ 8238 #define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk (0xffffffffUL) /*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM (Bitfield-Mask: 0xffffffff) */ 8239 8240 /* ------------------------ ETH_RXIPV4_NO_PAYLOAD_FRAMES ------------------------ */ 8241 #define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos (0UL) /*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM (Bit 0) */ 8242 #define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk (0xffffffffUL) /*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM (Bitfield-Mask: 0xffffffff) */ 8243 8244 /* ------------------------ ETH_RXIPV4_FRAGMENTED_FRAMES ------------------------ */ 8245 #define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos (0UL) /*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM (Bit 0) */ 8246 #define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk (0xffffffffUL) /*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM (Bitfield-Mask: 0xffffffff) */ 8247 8248 /* ------------------- ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES ------------------ */ 8249 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos (0UL) /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM (Bit 0) */ 8250 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk (0xffffffffUL) /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM (Bitfield-Mask: 0xffffffff) */ 8251 8252 /* --------------------------- ETH_RXIPV6_GOOD_FRAMES --------------------------- */ 8253 #define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos (0UL) /*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM (Bit 0) */ 8254 #define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk (0xffffffffUL) /*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM (Bitfield-Mask: 0xffffffff) */ 8255 8256 /* ----------------------- ETH_RXIPV6_HEADER_ERROR_FRAMES ----------------------- */ 8257 #define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos (0UL) /*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM (Bit 0) */ 8258 #define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk (0xffffffffUL) /*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM (Bitfield-Mask: 0xffffffff) */ 8259 8260 /* ------------------------ ETH_RXIPV6_NO_PAYLOAD_FRAMES ------------------------ */ 8261 #define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos (0UL) /*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM (Bit 0) */ 8262 #define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk (0xffffffffUL) /*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM (Bitfield-Mask: 0xffffffff) */ 8263 8264 /* ---------------------------- ETH_RXUDP_GOOD_FRAMES --------------------------- */ 8265 #define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos (0UL) /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM (Bit 0) */ 8266 #define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk (0xffffffffUL) /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM (Bitfield-Mask: 0xffffffff) */ 8267 8268 /* --------------------------- ETH_RXUDP_ERROR_FRAMES --------------------------- */ 8269 #define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos (0UL) /*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM (Bit 0) */ 8270 #define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk (0xffffffffUL) /*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM (Bitfield-Mask: 0xffffffff) */ 8271 8272 /* ---------------------------- ETH_RXTCP_GOOD_FRAMES --------------------------- */ 8273 #define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos (0UL) /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM (Bit 0) */ 8274 #define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk (0xffffffffUL) /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM (Bitfield-Mask: 0xffffffff) */ 8275 8276 /* --------------------------- ETH_RXTCP_ERROR_FRAMES --------------------------- */ 8277 #define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos (0UL) /*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM (Bit 0) */ 8278 #define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk (0xffffffffUL) /*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM (Bitfield-Mask: 0xffffffff) */ 8279 8280 /* --------------------------- ETH_RXICMP_GOOD_FRAMES --------------------------- */ 8281 #define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos (0UL) /*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM (Bit 0) */ 8282 #define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk (0xffffffffUL) /*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM (Bitfield-Mask: 0xffffffff) */ 8283 8284 /* --------------------------- ETH_RXICMP_ERROR_FRAMES -------------------------- */ 8285 #define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos (0UL) /*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM (Bit 0) */ 8286 #define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk (0xffffffffUL) /*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM (Bitfield-Mask: 0xffffffff) */ 8287 8288 /* --------------------------- ETH_RXIPV4_GOOD_OCTETS --------------------------- */ 8289 #define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos (0UL) /*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT (Bit 0) */ 8290 #define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk (0xffffffffUL) /*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT (Bitfield-Mask: 0xffffffff) */ 8291 8292 /* ----------------------- ETH_RXIPV4_HEADER_ERROR_OCTETS ----------------------- */ 8293 #define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos (0UL) /*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT (Bit 0) */ 8294 #define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk (0xffffffffUL) /*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT (Bitfield-Mask: 0xffffffff) */ 8295 8296 /* ------------------------ ETH_RXIPV4_NO_PAYLOAD_OCTETS ------------------------ */ 8297 #define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos (0UL) /*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT (Bit 0) */ 8298 #define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk (0xffffffffUL) /*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT (Bitfield-Mask: 0xffffffff) */ 8299 8300 /* ------------------------ ETH_RXIPV4_FRAGMENTED_OCTETS ------------------------ */ 8301 #define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos (0UL) /*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT (Bit 0) */ 8302 #define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk (0xffffffffUL) /*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT (Bitfield-Mask: 0xffffffff) */ 8303 8304 /* ------------------- ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS ------------------- */ 8305 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos (0UL) /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT (Bit 0) */ 8306 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk (0xffffffffUL) /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT (Bitfield-Mask: 0xffffffff) */ 8307 8308 /* --------------------------- ETH_RXIPV6_GOOD_OCTETS --------------------------- */ 8309 #define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos (0UL) /*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT (Bit 0) */ 8310 #define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk (0xffffffffUL) /*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT (Bitfield-Mask: 0xffffffff) */ 8311 8312 /* ----------------------- ETH_RXIPV6_HEADER_ERROR_OCTETS ----------------------- */ 8313 #define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos (0UL) /*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT (Bit 0) */ 8314 #define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk (0xffffffffUL) /*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT (Bitfield-Mask: 0xffffffff) */ 8315 8316 /* ------------------------ ETH_RXIPV6_NO_PAYLOAD_OCTETS ------------------------ */ 8317 #define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos (0UL) /*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT (Bit 0) */ 8318 #define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk (0xffffffffUL) /*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT (Bitfield-Mask: 0xffffffff) */ 8319 8320 /* ---------------------------- ETH_RXUDP_GOOD_OCTETS --------------------------- */ 8321 #define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos (0UL) /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT (Bit 0) */ 8322 #define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk (0xffffffffUL) /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT (Bitfield-Mask: 0xffffffff) */ 8323 8324 /* --------------------------- ETH_RXUDP_ERROR_OCTETS --------------------------- */ 8325 #define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos (0UL) /*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT (Bit 0) */ 8326 #define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk (0xffffffffUL) /*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT (Bitfield-Mask: 0xffffffff) */ 8327 8328 /* ---------------------------- ETH_RXTCP_GOOD_OCTETS --------------------------- */ 8329 #define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos (0UL) /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT (Bit 0) */ 8330 #define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk (0xffffffffUL) /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT (Bitfield-Mask: 0xffffffff) */ 8331 8332 /* --------------------------- ETH_RXTCP_ERROR_OCTETS --------------------------- */ 8333 #define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos (0UL) /*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT (Bit 0) */ 8334 #define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk (0xffffffffUL) /*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT (Bitfield-Mask: 0xffffffff) */ 8335 8336 /* --------------------------- ETH_RXICMP_GOOD_OCTETS --------------------------- */ 8337 #define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos (0UL) /*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT (Bit 0) */ 8338 #define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk (0xffffffffUL) /*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT (Bitfield-Mask: 0xffffffff) */ 8339 8340 /* --------------------------- ETH_RXICMP_ERROR_OCTETS -------------------------- */ 8341 #define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos (0UL) /*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT (Bit 0) */ 8342 #define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk (0xffffffffUL) /*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT (Bitfield-Mask: 0xffffffff) */ 8343 8344 /* ---------------------------- ETH_TIMESTAMP_CONTROL --------------------------- */ 8345 #define ETH_TIMESTAMP_CONTROL_TSENA_Pos (0UL) /*!< ETH TIMESTAMP_CONTROL: TSENA (Bit 0) */ 8346 #define ETH_TIMESTAMP_CONTROL_TSENA_Msk (0x1UL) /*!< ETH TIMESTAMP_CONTROL: TSENA (Bitfield-Mask: 0x01) */ 8347 #define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos (1UL) /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT (Bit 1) */ 8348 #define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk (0x2UL) /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT (Bitfield-Mask: 0x01) */ 8349 #define ETH_TIMESTAMP_CONTROL_TSINIT_Pos (2UL) /*!< ETH TIMESTAMP_CONTROL: TSINIT (Bit 2) */ 8350 #define ETH_TIMESTAMP_CONTROL_TSINIT_Msk (0x4UL) /*!< ETH TIMESTAMP_CONTROL: TSINIT (Bitfield-Mask: 0x01) */ 8351 #define ETH_TIMESTAMP_CONTROL_TSUPDT_Pos (3UL) /*!< ETH TIMESTAMP_CONTROL: TSUPDT (Bit 3) */ 8352 #define ETH_TIMESTAMP_CONTROL_TSUPDT_Msk (0x8UL) /*!< ETH TIMESTAMP_CONTROL: TSUPDT (Bitfield-Mask: 0x01) */ 8353 #define ETH_TIMESTAMP_CONTROL_TSTRIG_Pos (4UL) /*!< ETH TIMESTAMP_CONTROL: TSTRIG (Bit 4) */ 8354 #define ETH_TIMESTAMP_CONTROL_TSTRIG_Msk (0x10UL) /*!< ETH TIMESTAMP_CONTROL: TSTRIG (Bitfield-Mask: 0x01) */ 8355 #define ETH_TIMESTAMP_CONTROL_TSADDREG_Pos (5UL) /*!< ETH TIMESTAMP_CONTROL: TSADDREG (Bit 5) */ 8356 #define ETH_TIMESTAMP_CONTROL_TSADDREG_Msk (0x20UL) /*!< ETH TIMESTAMP_CONTROL: TSADDREG (Bitfield-Mask: 0x01) */ 8357 #define ETH_TIMESTAMP_CONTROL_TSENALL_Pos (8UL) /*!< ETH TIMESTAMP_CONTROL: TSENALL (Bit 8) */ 8358 #define ETH_TIMESTAMP_CONTROL_TSENALL_Msk (0x100UL) /*!< ETH TIMESTAMP_CONTROL: TSENALL (Bitfield-Mask: 0x01) */ 8359 #define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos (9UL) /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR (Bit 9) */ 8360 #define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk (0x200UL) /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR (Bitfield-Mask: 0x01) */ 8361 #define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos (10UL) /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA (Bit 10) */ 8362 #define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk (0x400UL) /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA (Bitfield-Mask: 0x01) */ 8363 #define ETH_TIMESTAMP_CONTROL_TSIPENA_Pos (11UL) /*!< ETH TIMESTAMP_CONTROL: TSIPENA (Bit 11) */ 8364 #define ETH_TIMESTAMP_CONTROL_TSIPENA_Msk (0x800UL) /*!< ETH TIMESTAMP_CONTROL: TSIPENA (Bitfield-Mask: 0x01) */ 8365 #define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos (12UL) /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA (Bit 12) */ 8366 #define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk (0x1000UL) /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA (Bitfield-Mask: 0x01) */ 8367 #define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos (13UL) /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA (Bit 13) */ 8368 #define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk (0x2000UL) /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA (Bitfield-Mask: 0x01) */ 8369 #define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos (14UL) /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA (Bit 14) */ 8370 #define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk (0x4000UL) /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA (Bitfield-Mask: 0x01) */ 8371 #define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos (15UL) /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA (Bit 15) */ 8372 #define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk (0x8000UL) /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA (Bitfield-Mask: 0x01) */ 8373 #define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos (16UL) /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL (Bit 16) */ 8374 #define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk (0x30000UL) /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL (Bitfield-Mask: 0x03) */ 8375 #define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos (18UL) /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR (Bit 18) */ 8376 #define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk (0x40000UL) /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR (Bitfield-Mask: 0x01) */ 8377 8378 /* -------------------------- ETH_SUB_SECOND_INCREMENT -------------------------- */ 8379 #define ETH_SUB_SECOND_INCREMENT_SSINC_Pos (0UL) /*!< ETH SUB_SECOND_INCREMENT: SSINC (Bit 0) */ 8380 #define ETH_SUB_SECOND_INCREMENT_SSINC_Msk (0xffUL) /*!< ETH SUB_SECOND_INCREMENT: SSINC (Bitfield-Mask: 0xff) */ 8381 8382 /* --------------------------- ETH_SYSTEM_TIME_SECONDS -------------------------- */ 8383 #define ETH_SYSTEM_TIME_SECONDS_TSS_Pos (0UL) /*!< ETH SYSTEM_TIME_SECONDS: TSS (Bit 0) */ 8384 #define ETH_SYSTEM_TIME_SECONDS_TSS_Msk (0xffffffffUL) /*!< ETH SYSTEM_TIME_SECONDS: TSS (Bitfield-Mask: 0xffffffff) */ 8385 8386 /* ------------------------- ETH_SYSTEM_TIME_NANOSECONDS ------------------------ */ 8387 #define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos (0UL) /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS (Bit 0) */ 8388 #define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk (0x7fffffffUL) /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS (Bitfield-Mask: 0x7fffffff) */ 8389 8390 /* ----------------------- ETH_SYSTEM_TIME_SECONDS_UPDATE ----------------------- */ 8391 #define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos (0UL) /*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS (Bit 0) */ 8392 #define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk (0xffffffffUL) /*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS (Bitfield-Mask: 0xffffffff) */ 8393 8394 /* --------------------- ETH_SYSTEM_TIME_NANOSECONDS_UPDATE --------------------- */ 8395 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos (0UL) /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS (Bit 0) */ 8396 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk (0x7fffffffUL) /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS (Bitfield-Mask: 0x7fffffff) */ 8397 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos (31UL) /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB (Bit 31) */ 8398 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk (0x80000000UL) /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB (Bitfield-Mask: 0x01) */ 8399 8400 /* ---------------------------- ETH_TIMESTAMP_ADDEND ---------------------------- */ 8401 #define ETH_TIMESTAMP_ADDEND_TSAR_Pos (0UL) /*!< ETH TIMESTAMP_ADDEND: TSAR (Bit 0) */ 8402 #define ETH_TIMESTAMP_ADDEND_TSAR_Msk (0xffffffffUL) /*!< ETH TIMESTAMP_ADDEND: TSAR (Bitfield-Mask: 0xffffffff) */ 8403 8404 /* --------------------------- ETH_TARGET_TIME_SECONDS -------------------------- */ 8405 #define ETH_TARGET_TIME_SECONDS_TSTR_Pos (0UL) /*!< ETH TARGET_TIME_SECONDS: TSTR (Bit 0) */ 8406 #define ETH_TARGET_TIME_SECONDS_TSTR_Msk (0xffffffffUL) /*!< ETH TARGET_TIME_SECONDS: TSTR (Bitfield-Mask: 0xffffffff) */ 8407 8408 /* ------------------------- ETH_TARGET_TIME_NANOSECONDS ------------------------ */ 8409 #define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos (0UL) /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO (Bit 0) */ 8410 #define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk (0x7fffffffUL) /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO (Bitfield-Mask: 0x7fffffff) */ 8411 #define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos (31UL) /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY (Bit 31) */ 8412 #define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk (0x80000000UL) /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY (Bitfield-Mask: 0x01) */ 8413 8414 /* --------------------- ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS -------------------- */ 8415 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos (0UL) /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR (Bit 0) */ 8416 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk (0xffffUL) /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR (Bitfield-Mask: 0xffff) */ 8417 8418 /* ---------------------------- ETH_TIMESTAMP_STATUS ---------------------------- */ 8419 #define ETH_TIMESTAMP_STATUS_TSSOVF_Pos (0UL) /*!< ETH TIMESTAMP_STATUS: TSSOVF (Bit 0) */ 8420 #define ETH_TIMESTAMP_STATUS_TSSOVF_Msk (0x1UL) /*!< ETH TIMESTAMP_STATUS: TSSOVF (Bitfield-Mask: 0x01) */ 8421 #define ETH_TIMESTAMP_STATUS_TSTARGT_Pos (1UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT (Bit 1) */ 8422 #define ETH_TIMESTAMP_STATUS_TSTARGT_Msk (0x2UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT (Bitfield-Mask: 0x01) */ 8423 #define ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos (3UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR (Bit 3) */ 8424 #define ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk (0x8UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR (Bitfield-Mask: 0x01) */ 8425 #define ETH_TIMESTAMP_STATUS_TSTARGT1_Pos (4UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT1 (Bit 4) */ 8426 #define ETH_TIMESTAMP_STATUS_TSTARGT1_Msk (0x10UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT1 (Bitfield-Mask: 0x01) */ 8427 #define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos (5UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 (Bit 5) */ 8428 #define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk (0x20UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 (Bitfield-Mask: 0x01) */ 8429 #define ETH_TIMESTAMP_STATUS_TSTARGT2_Pos (6UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT2 (Bit 6) */ 8430 #define ETH_TIMESTAMP_STATUS_TSTARGT2_Msk (0x40UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT2 (Bitfield-Mask: 0x01) */ 8431 #define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos (7UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 (Bit 7) */ 8432 #define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk (0x80UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 (Bitfield-Mask: 0x01) */ 8433 #define ETH_TIMESTAMP_STATUS_TSTARGT3_Pos (8UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT3 (Bit 8) */ 8434 #define ETH_TIMESTAMP_STATUS_TSTARGT3_Msk (0x100UL) /*!< ETH TIMESTAMP_STATUS: TSTARGT3 (Bitfield-Mask: 0x01) */ 8435 #define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos (9UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 (Bit 9) */ 8436 #define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk (0x200UL) /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 (Bitfield-Mask: 0x01) */ 8437 8438 /* ------------------------------- ETH_PPS_CONTROL ------------------------------ */ 8439 #define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos (0UL) /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD (Bit 0) */ 8440 #define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Msk (0xfUL) /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD (Bitfield-Mask: 0x0f) */ 8441 #define ETH_PPS_CONTROL_PPSEN0_Pos (4UL) /*!< ETH PPS_CONTROL: PPSEN0 (Bit 4) */ 8442 #define ETH_PPS_CONTROL_PPSEN0_Msk (0x10UL) /*!< ETH PPS_CONTROL: PPSEN0 (Bitfield-Mask: 0x01) */ 8443 #define ETH_PPS_CONTROL_TRGTMODSEL0_Pos (5UL) /*!< ETH PPS_CONTROL: TRGTMODSEL0 (Bit 5) */ 8444 #define ETH_PPS_CONTROL_TRGTMODSEL0_Msk (0x60UL) /*!< ETH PPS_CONTROL: TRGTMODSEL0 (Bitfield-Mask: 0x03) */ 8445 #define ETH_PPS_CONTROL_PPSCMD1_Pos (8UL) /*!< ETH PPS_CONTROL: PPSCMD1 (Bit 8) */ 8446 #define ETH_PPS_CONTROL_PPSCMD1_Msk (0x700UL) /*!< ETH PPS_CONTROL: PPSCMD1 (Bitfield-Mask: 0x07) */ 8447 #define ETH_PPS_CONTROL_TRGTMODSEL1_Pos (13UL) /*!< ETH PPS_CONTROL: TRGTMODSEL1 (Bit 13) */ 8448 #define ETH_PPS_CONTROL_TRGTMODSEL1_Msk (0x6000UL) /*!< ETH PPS_CONTROL: TRGTMODSEL1 (Bitfield-Mask: 0x03) */ 8449 #define ETH_PPS_CONTROL_PPSCMD2_Pos (16UL) /*!< ETH PPS_CONTROL: PPSCMD2 (Bit 16) */ 8450 #define ETH_PPS_CONTROL_PPSCMD2_Msk (0x70000UL) /*!< ETH PPS_CONTROL: PPSCMD2 (Bitfield-Mask: 0x07) */ 8451 #define ETH_PPS_CONTROL_TRGTMODSEL2_Pos (21UL) /*!< ETH PPS_CONTROL: TRGTMODSEL2 (Bit 21) */ 8452 #define ETH_PPS_CONTROL_TRGTMODSEL2_Msk (0x600000UL) /*!< ETH PPS_CONTROL: TRGTMODSEL2 (Bitfield-Mask: 0x03) */ 8453 #define ETH_PPS_CONTROL_PPSCMD3_Pos (24UL) /*!< ETH PPS_CONTROL: PPSCMD3 (Bit 24) */ 8454 #define ETH_PPS_CONTROL_PPSCMD3_Msk (0x7000000UL) /*!< ETH PPS_CONTROL: PPSCMD3 (Bitfield-Mask: 0x07) */ 8455 #define ETH_PPS_CONTROL_TRGTMODSEL3_Pos (29UL) /*!< ETH PPS_CONTROL: TRGTMODSEL3 (Bit 29) */ 8456 #define ETH_PPS_CONTROL_TRGTMODSEL3_Msk (0x60000000UL) /*!< ETH PPS_CONTROL: TRGTMODSEL3 (Bitfield-Mask: 0x03) */ 8457 8458 /* -------------------------------- ETH_BUS_MODE -------------------------------- */ 8459 #define ETH_BUS_MODE_SWR_Pos (0UL) /*!< ETH BUS_MODE: SWR (Bit 0) */ 8460 #define ETH_BUS_MODE_SWR_Msk (0x1UL) /*!< ETH BUS_MODE: SWR (Bitfield-Mask: 0x01) */ 8461 #define ETH_BUS_MODE_DA_Pos (1UL) /*!< ETH BUS_MODE: DA (Bit 1) */ 8462 #define ETH_BUS_MODE_DA_Msk (0x2UL) /*!< ETH BUS_MODE: DA (Bitfield-Mask: 0x01) */ 8463 #define ETH_BUS_MODE_DSL_Pos (2UL) /*!< ETH BUS_MODE: DSL (Bit 2) */ 8464 #define ETH_BUS_MODE_DSL_Msk (0x7cUL) /*!< ETH BUS_MODE: DSL (Bitfield-Mask: 0x1f) */ 8465 #define ETH_BUS_MODE_ATDS_Pos (7UL) /*!< ETH BUS_MODE: ATDS (Bit 7) */ 8466 #define ETH_BUS_MODE_ATDS_Msk (0x80UL) /*!< ETH BUS_MODE: ATDS (Bitfield-Mask: 0x01) */ 8467 #define ETH_BUS_MODE_PBL_Pos (8UL) /*!< ETH BUS_MODE: PBL (Bit 8) */ 8468 #define ETH_BUS_MODE_PBL_Msk (0x3f00UL) /*!< ETH BUS_MODE: PBL (Bitfield-Mask: 0x3f) */ 8469 #define ETH_BUS_MODE_PR_Pos (14UL) /*!< ETH BUS_MODE: PR (Bit 14) */ 8470 #define ETH_BUS_MODE_PR_Msk (0xc000UL) /*!< ETH BUS_MODE: PR (Bitfield-Mask: 0x03) */ 8471 #define ETH_BUS_MODE_FB_Pos (16UL) /*!< ETH BUS_MODE: FB (Bit 16) */ 8472 #define ETH_BUS_MODE_FB_Msk (0x10000UL) /*!< ETH BUS_MODE: FB (Bitfield-Mask: 0x01) */ 8473 #define ETH_BUS_MODE_RPBL_Pos (17UL) /*!< ETH BUS_MODE: RPBL (Bit 17) */ 8474 #define ETH_BUS_MODE_RPBL_Msk (0x7e0000UL) /*!< ETH BUS_MODE: RPBL (Bitfield-Mask: 0x3f) */ 8475 #define ETH_BUS_MODE_USP_Pos (23UL) /*!< ETH BUS_MODE: USP (Bit 23) */ 8476 #define ETH_BUS_MODE_USP_Msk (0x800000UL) /*!< ETH BUS_MODE: USP (Bitfield-Mask: 0x01) */ 8477 #define ETH_BUS_MODE_PBLX8_Pos (24UL) /*!< ETH BUS_MODE: PBLX8 (Bit 24) */ 8478 #define ETH_BUS_MODE_PBLX8_Msk (0x1000000UL) /*!< ETH BUS_MODE: PBLX8 (Bitfield-Mask: 0x01) */ 8479 #define ETH_BUS_MODE_AAL_Pos (25UL) /*!< ETH BUS_MODE: AAL (Bit 25) */ 8480 #define ETH_BUS_MODE_AAL_Msk (0x2000000UL) /*!< ETH BUS_MODE: AAL (Bitfield-Mask: 0x01) */ 8481 #define ETH_BUS_MODE_MB_Pos (26UL) /*!< ETH BUS_MODE: MB (Bit 26) */ 8482 #define ETH_BUS_MODE_MB_Msk (0x4000000UL) /*!< ETH BUS_MODE: MB (Bitfield-Mask: 0x01) */ 8483 #define ETH_BUS_MODE_TXPR_Pos (27UL) /*!< ETH BUS_MODE: TXPR (Bit 27) */ 8484 #define ETH_BUS_MODE_TXPR_Msk (0x8000000UL) /*!< ETH BUS_MODE: TXPR (Bitfield-Mask: 0x01) */ 8485 #define ETH_BUS_MODE_PRWG_Pos (28UL) /*!< ETH BUS_MODE: PRWG (Bit 28) */ 8486 #define ETH_BUS_MODE_PRWG_Msk (0x30000000UL) /*!< ETH BUS_MODE: PRWG (Bitfield-Mask: 0x03) */ 8487 8488 /* -------------------------- ETH_TRANSMIT_POLL_DEMAND -------------------------- */ 8489 #define ETH_TRANSMIT_POLL_DEMAND_TPD_Pos (0UL) /*!< ETH TRANSMIT_POLL_DEMAND: TPD (Bit 0) */ 8490 #define ETH_TRANSMIT_POLL_DEMAND_TPD_Msk (0xffffffffUL) /*!< ETH TRANSMIT_POLL_DEMAND: TPD (Bitfield-Mask: 0xffffffff) */ 8491 8492 /* --------------------------- ETH_RECEIVE_POLL_DEMAND -------------------------- */ 8493 #define ETH_RECEIVE_POLL_DEMAND_RPD_Pos (0UL) /*!< ETH RECEIVE_POLL_DEMAND: RPD (Bit 0) */ 8494 #define ETH_RECEIVE_POLL_DEMAND_RPD_Msk (0xffffffffUL) /*!< ETH RECEIVE_POLL_DEMAND: RPD (Bitfield-Mask: 0xffffffff) */ 8495 8496 /* --------------------- ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS -------------------- */ 8497 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos (2UL) /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit (Bit 2) */ 8498 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk (0xfffffffcUL) /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit (Bitfield-Mask: 0x3fffffff) */ 8499 8500 /* -------------------- ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS -------------------- */ 8501 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos (2UL) /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit (Bit 2) */ 8502 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk (0xfffffffcUL) /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit (Bitfield-Mask: 0x3fffffff) */ 8503 8504 /* --------------------------------- ETH_STATUS --------------------------------- */ 8505 #define ETH_STATUS_TI_Pos (0UL) /*!< ETH STATUS: TI (Bit 0) */ 8506 #define ETH_STATUS_TI_Msk (0x1UL) /*!< ETH STATUS: TI (Bitfield-Mask: 0x01) */ 8507 #define ETH_STATUS_TPS_Pos (1UL) /*!< ETH STATUS: TPS (Bit 1) */ 8508 #define ETH_STATUS_TPS_Msk (0x2UL) /*!< ETH STATUS: TPS (Bitfield-Mask: 0x01) */ 8509 #define ETH_STATUS_TU_Pos (2UL) /*!< ETH STATUS: TU (Bit 2) */ 8510 #define ETH_STATUS_TU_Msk (0x4UL) /*!< ETH STATUS: TU (Bitfield-Mask: 0x01) */ 8511 #define ETH_STATUS_TJT_Pos (3UL) /*!< ETH STATUS: TJT (Bit 3) */ 8512 #define ETH_STATUS_TJT_Msk (0x8UL) /*!< ETH STATUS: TJT (Bitfield-Mask: 0x01) */ 8513 #define ETH_STATUS_OVF_Pos (4UL) /*!< ETH STATUS: OVF (Bit 4) */ 8514 #define ETH_STATUS_OVF_Msk (0x10UL) /*!< ETH STATUS: OVF (Bitfield-Mask: 0x01) */ 8515 #define ETH_STATUS_UNF_Pos (5UL) /*!< ETH STATUS: UNF (Bit 5) */ 8516 #define ETH_STATUS_UNF_Msk (0x20UL) /*!< ETH STATUS: UNF (Bitfield-Mask: 0x01) */ 8517 #define ETH_STATUS_RI_Pos (6UL) /*!< ETH STATUS: RI (Bit 6) */ 8518 #define ETH_STATUS_RI_Msk (0x40UL) /*!< ETH STATUS: RI (Bitfield-Mask: 0x01) */ 8519 #define ETH_STATUS_RU_Pos (7UL) /*!< ETH STATUS: RU (Bit 7) */ 8520 #define ETH_STATUS_RU_Msk (0x80UL) /*!< ETH STATUS: RU (Bitfield-Mask: 0x01) */ 8521 #define ETH_STATUS_RPS_Pos (8UL) /*!< ETH STATUS: RPS (Bit 8) */ 8522 #define ETH_STATUS_RPS_Msk (0x100UL) /*!< ETH STATUS: RPS (Bitfield-Mask: 0x01) */ 8523 #define ETH_STATUS_RWT_Pos (9UL) /*!< ETH STATUS: RWT (Bit 9) */ 8524 #define ETH_STATUS_RWT_Msk (0x200UL) /*!< ETH STATUS: RWT (Bitfield-Mask: 0x01) */ 8525 #define ETH_STATUS_ETI_Pos (10UL) /*!< ETH STATUS: ETI (Bit 10) */ 8526 #define ETH_STATUS_ETI_Msk (0x400UL) /*!< ETH STATUS: ETI (Bitfield-Mask: 0x01) */ 8527 #define ETH_STATUS_FBI_Pos (13UL) /*!< ETH STATUS: FBI (Bit 13) */ 8528 #define ETH_STATUS_FBI_Msk (0x2000UL) /*!< ETH STATUS: FBI (Bitfield-Mask: 0x01) */ 8529 #define ETH_STATUS_ERI_Pos (14UL) /*!< ETH STATUS: ERI (Bit 14) */ 8530 #define ETH_STATUS_ERI_Msk (0x4000UL) /*!< ETH STATUS: ERI (Bitfield-Mask: 0x01) */ 8531 #define ETH_STATUS_AIS_Pos (15UL) /*!< ETH STATUS: AIS (Bit 15) */ 8532 #define ETH_STATUS_AIS_Msk (0x8000UL) /*!< ETH STATUS: AIS (Bitfield-Mask: 0x01) */ 8533 #define ETH_STATUS_NIS_Pos (16UL) /*!< ETH STATUS: NIS (Bit 16) */ 8534 #define ETH_STATUS_NIS_Msk (0x10000UL) /*!< ETH STATUS: NIS (Bitfield-Mask: 0x01) */ 8535 #define ETH_STATUS_RS_Pos (17UL) /*!< ETH STATUS: RS (Bit 17) */ 8536 #define ETH_STATUS_RS_Msk (0xe0000UL) /*!< ETH STATUS: RS (Bitfield-Mask: 0x07) */ 8537 #define ETH_STATUS_TS_Pos (20UL) /*!< ETH STATUS: TS (Bit 20) */ 8538 #define ETH_STATUS_TS_Msk (0x700000UL) /*!< ETH STATUS: TS (Bitfield-Mask: 0x07) */ 8539 #define ETH_STATUS_EB_Pos (23UL) /*!< ETH STATUS: EB (Bit 23) */ 8540 #define ETH_STATUS_EB_Msk (0x3800000UL) /*!< ETH STATUS: EB (Bitfield-Mask: 0x07) */ 8541 #define ETH_STATUS_EMI_Pos (27UL) /*!< ETH STATUS: EMI (Bit 27) */ 8542 #define ETH_STATUS_EMI_Msk (0x8000000UL) /*!< ETH STATUS: EMI (Bitfield-Mask: 0x01) */ 8543 #define ETH_STATUS_EPI_Pos (28UL) /*!< ETH STATUS: EPI (Bit 28) */ 8544 #define ETH_STATUS_EPI_Msk (0x10000000UL) /*!< ETH STATUS: EPI (Bitfield-Mask: 0x01) */ 8545 #define ETH_STATUS_TTI_Pos (29UL) /*!< ETH STATUS: TTI (Bit 29) */ 8546 #define ETH_STATUS_TTI_Msk (0x20000000UL) /*!< ETH STATUS: TTI (Bitfield-Mask: 0x01) */ 8547 8548 /* ----------------------------- ETH_OPERATION_MODE ----------------------------- */ 8549 #define ETH_OPERATION_MODE_SR_Pos (1UL) /*!< ETH OPERATION_MODE: SR (Bit 1) */ 8550 #define ETH_OPERATION_MODE_SR_Msk (0x2UL) /*!< ETH OPERATION_MODE: SR (Bitfield-Mask: 0x01) */ 8551 #define ETH_OPERATION_MODE_OSF_Pos (2UL) /*!< ETH OPERATION_MODE: OSF (Bit 2) */ 8552 #define ETH_OPERATION_MODE_OSF_Msk (0x4UL) /*!< ETH OPERATION_MODE: OSF (Bitfield-Mask: 0x01) */ 8553 #define ETH_OPERATION_MODE_RTC_Pos (3UL) /*!< ETH OPERATION_MODE: RTC (Bit 3) */ 8554 #define ETH_OPERATION_MODE_RTC_Msk (0x18UL) /*!< ETH OPERATION_MODE: RTC (Bitfield-Mask: 0x03) */ 8555 #define ETH_OPERATION_MODE_FUF_Pos (6UL) /*!< ETH OPERATION_MODE: FUF (Bit 6) */ 8556 #define ETH_OPERATION_MODE_FUF_Msk (0x40UL) /*!< ETH OPERATION_MODE: FUF (Bitfield-Mask: 0x01) */ 8557 #define ETH_OPERATION_MODE_FEF_Pos (7UL) /*!< ETH OPERATION_MODE: FEF (Bit 7) */ 8558 #define ETH_OPERATION_MODE_FEF_Msk (0x80UL) /*!< ETH OPERATION_MODE: FEF (Bitfield-Mask: 0x01) */ 8559 #define ETH_OPERATION_MODE_ST_Pos (13UL) /*!< ETH OPERATION_MODE: ST (Bit 13) */ 8560 #define ETH_OPERATION_MODE_ST_Msk (0x2000UL) /*!< ETH OPERATION_MODE: ST (Bitfield-Mask: 0x01) */ 8561 #define ETH_OPERATION_MODE_TTC_Pos (14UL) /*!< ETH OPERATION_MODE: TTC (Bit 14) */ 8562 #define ETH_OPERATION_MODE_TTC_Msk (0x1c000UL) /*!< ETH OPERATION_MODE: TTC (Bitfield-Mask: 0x07) */ 8563 #define ETH_OPERATION_MODE_FTF_Pos (20UL) /*!< ETH OPERATION_MODE: FTF (Bit 20) */ 8564 #define ETH_OPERATION_MODE_FTF_Msk (0x100000UL) /*!< ETH OPERATION_MODE: FTF (Bitfield-Mask: 0x01) */ 8565 #define ETH_OPERATION_MODE_TSF_Pos (21UL) /*!< ETH OPERATION_MODE: TSF (Bit 21) */ 8566 #define ETH_OPERATION_MODE_TSF_Msk (0x200000UL) /*!< ETH OPERATION_MODE: TSF (Bitfield-Mask: 0x01) */ 8567 #define ETH_OPERATION_MODE_DFF_Pos (24UL) /*!< ETH OPERATION_MODE: DFF (Bit 24) */ 8568 #define ETH_OPERATION_MODE_DFF_Msk (0x1000000UL) /*!< ETH OPERATION_MODE: DFF (Bitfield-Mask: 0x01) */ 8569 #define ETH_OPERATION_MODE_RSF_Pos (25UL) /*!< ETH OPERATION_MODE: RSF (Bit 25) */ 8570 #define ETH_OPERATION_MODE_RSF_Msk (0x2000000UL) /*!< ETH OPERATION_MODE: RSF (Bitfield-Mask: 0x01) */ 8571 #define ETH_OPERATION_MODE_DT_Pos (26UL) /*!< ETH OPERATION_MODE: DT (Bit 26) */ 8572 #define ETH_OPERATION_MODE_DT_Msk (0x4000000UL) /*!< ETH OPERATION_MODE: DT (Bitfield-Mask: 0x01) */ 8573 8574 /* ---------------------------- ETH_INTERRUPT_ENABLE ---------------------------- */ 8575 #define ETH_INTERRUPT_ENABLE_TIE_Pos (0UL) /*!< ETH INTERRUPT_ENABLE: TIE (Bit 0) */ 8576 #define ETH_INTERRUPT_ENABLE_TIE_Msk (0x1UL) /*!< ETH INTERRUPT_ENABLE: TIE (Bitfield-Mask: 0x01) */ 8577 #define ETH_INTERRUPT_ENABLE_TSE_Pos (1UL) /*!< ETH INTERRUPT_ENABLE: TSE (Bit 1) */ 8578 #define ETH_INTERRUPT_ENABLE_TSE_Msk (0x2UL) /*!< ETH INTERRUPT_ENABLE: TSE (Bitfield-Mask: 0x01) */ 8579 #define ETH_INTERRUPT_ENABLE_TUE_Pos (2UL) /*!< ETH INTERRUPT_ENABLE: TUE (Bit 2) */ 8580 #define ETH_INTERRUPT_ENABLE_TUE_Msk (0x4UL) /*!< ETH INTERRUPT_ENABLE: TUE (Bitfield-Mask: 0x01) */ 8581 #define ETH_INTERRUPT_ENABLE_TJE_Pos (3UL) /*!< ETH INTERRUPT_ENABLE: TJE (Bit 3) */ 8582 #define ETH_INTERRUPT_ENABLE_TJE_Msk (0x8UL) /*!< ETH INTERRUPT_ENABLE: TJE (Bitfield-Mask: 0x01) */ 8583 #define ETH_INTERRUPT_ENABLE_OVE_Pos (4UL) /*!< ETH INTERRUPT_ENABLE: OVE (Bit 4) */ 8584 #define ETH_INTERRUPT_ENABLE_OVE_Msk (0x10UL) /*!< ETH INTERRUPT_ENABLE: OVE (Bitfield-Mask: 0x01) */ 8585 #define ETH_INTERRUPT_ENABLE_UNE_Pos (5UL) /*!< ETH INTERRUPT_ENABLE: UNE (Bit 5) */ 8586 #define ETH_INTERRUPT_ENABLE_UNE_Msk (0x20UL) /*!< ETH INTERRUPT_ENABLE: UNE (Bitfield-Mask: 0x01) */ 8587 #define ETH_INTERRUPT_ENABLE_RIE_Pos (6UL) /*!< ETH INTERRUPT_ENABLE: RIE (Bit 6) */ 8588 #define ETH_INTERRUPT_ENABLE_RIE_Msk (0x40UL) /*!< ETH INTERRUPT_ENABLE: RIE (Bitfield-Mask: 0x01) */ 8589 #define ETH_INTERRUPT_ENABLE_RUE_Pos (7UL) /*!< ETH INTERRUPT_ENABLE: RUE (Bit 7) */ 8590 #define ETH_INTERRUPT_ENABLE_RUE_Msk (0x80UL) /*!< ETH INTERRUPT_ENABLE: RUE (Bitfield-Mask: 0x01) */ 8591 #define ETH_INTERRUPT_ENABLE_RSE_Pos (8UL) /*!< ETH INTERRUPT_ENABLE: RSE (Bit 8) */ 8592 #define ETH_INTERRUPT_ENABLE_RSE_Msk (0x100UL) /*!< ETH INTERRUPT_ENABLE: RSE (Bitfield-Mask: 0x01) */ 8593 #define ETH_INTERRUPT_ENABLE_RWE_Pos (9UL) /*!< ETH INTERRUPT_ENABLE: RWE (Bit 9) */ 8594 #define ETH_INTERRUPT_ENABLE_RWE_Msk (0x200UL) /*!< ETH INTERRUPT_ENABLE: RWE (Bitfield-Mask: 0x01) */ 8595 #define ETH_INTERRUPT_ENABLE_ETE_Pos (10UL) /*!< ETH INTERRUPT_ENABLE: ETE (Bit 10) */ 8596 #define ETH_INTERRUPT_ENABLE_ETE_Msk (0x400UL) /*!< ETH INTERRUPT_ENABLE: ETE (Bitfield-Mask: 0x01) */ 8597 #define ETH_INTERRUPT_ENABLE_FBE_Pos (13UL) /*!< ETH INTERRUPT_ENABLE: FBE (Bit 13) */ 8598 #define ETH_INTERRUPT_ENABLE_FBE_Msk (0x2000UL) /*!< ETH INTERRUPT_ENABLE: FBE (Bitfield-Mask: 0x01) */ 8599 #define ETH_INTERRUPT_ENABLE_ERE_Pos (14UL) /*!< ETH INTERRUPT_ENABLE: ERE (Bit 14) */ 8600 #define ETH_INTERRUPT_ENABLE_ERE_Msk (0x4000UL) /*!< ETH INTERRUPT_ENABLE: ERE (Bitfield-Mask: 0x01) */ 8601 #define ETH_INTERRUPT_ENABLE_AIE_Pos (15UL) /*!< ETH INTERRUPT_ENABLE: AIE (Bit 15) */ 8602 #define ETH_INTERRUPT_ENABLE_AIE_Msk (0x8000UL) /*!< ETH INTERRUPT_ENABLE: AIE (Bitfield-Mask: 0x01) */ 8603 #define ETH_INTERRUPT_ENABLE_NIE_Pos (16UL) /*!< ETH INTERRUPT_ENABLE: NIE (Bit 16) */ 8604 #define ETH_INTERRUPT_ENABLE_NIE_Msk (0x10000UL) /*!< ETH INTERRUPT_ENABLE: NIE (Bitfield-Mask: 0x01) */ 8605 8606 /* ---------------- ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER ---------------- */ 8607 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos (0UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT (Bit 0) */ 8608 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk (0xffffUL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT (Bitfield-Mask: 0xffff) */ 8609 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos (16UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF (Bit 16) */ 8610 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk (0x10000UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF (Bitfield-Mask: 0x01) */ 8611 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos (17UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT (Bit 17) */ 8612 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk (0xffe0000UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT (Bitfield-Mask: 0x7ff) */ 8613 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos (28UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF (Bit 28) */ 8614 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk (0x10000000UL) /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF (Bitfield-Mask: 0x01) */ 8615 8616 /* -------------------- ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER -------------------- */ 8617 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos (0UL) /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT (Bit 0) */ 8618 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk (0xffUL) /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT (Bitfield-Mask: 0xff) */ 8619 8620 /* ------------------------------- ETH_AHB_STATUS ------------------------------- */ 8621 #define ETH_AHB_STATUS_AHBMS_Pos (0UL) /*!< ETH AHB_STATUS: AHBMS (Bit 0) */ 8622 #define ETH_AHB_STATUS_AHBMS_Msk (0x1UL) /*!< ETH AHB_STATUS: AHBMS (Bitfield-Mask: 0x01) */ 8623 8624 /* -------------------- ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR -------------------- */ 8625 #define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos (0UL) /*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR (Bit 0) */ 8626 #define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk (0xffffffffUL) /*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR (Bitfield-Mask: 0xffffffff) */ 8627 8628 /* --------------------- ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR -------------------- */ 8629 #define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos (0UL) /*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR (Bit 0) */ 8630 #define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk (0xffffffffUL) /*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR (Bitfield-Mask: 0xffffffff) */ 8631 8632 /* ------------------ ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS ------------------ */ 8633 #define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos (0UL) /*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR (Bit 0) */ 8634 #define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk (0xffffffffUL) /*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR (Bitfield-Mask: 0xffffffff) */ 8635 8636 /* ------------------- ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS ------------------ */ 8637 #define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos (0UL) /*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR (Bit 0) */ 8638 #define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk (0xffffffffUL) /*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR (Bitfield-Mask: 0xffffffff) */ 8639 8640 /* ------------------------------- ETH_HW_FEATURE ------------------------------- */ 8641 #define ETH_HW_FEATURE_MIISEL_Pos (0UL) /*!< ETH HW_FEATURE: MIISEL (Bit 0) */ 8642 #define ETH_HW_FEATURE_MIISEL_Msk (0x1UL) /*!< ETH HW_FEATURE: MIISEL (Bitfield-Mask: 0x01) */ 8643 #define ETH_HW_FEATURE_GMIISEL_Pos (1UL) /*!< ETH HW_FEATURE: GMIISEL (Bit 1) */ 8644 #define ETH_HW_FEATURE_GMIISEL_Msk (0x2UL) /*!< ETH HW_FEATURE: GMIISEL (Bitfield-Mask: 0x01) */ 8645 #define ETH_HW_FEATURE_HDSEL_Pos (2UL) /*!< ETH HW_FEATURE: HDSEL (Bit 2) */ 8646 #define ETH_HW_FEATURE_HDSEL_Msk (0x4UL) /*!< ETH HW_FEATURE: HDSEL (Bitfield-Mask: 0x01) */ 8647 #define ETH_HW_FEATURE_EXTHASHEN_Pos (3UL) /*!< ETH HW_FEATURE: EXTHASHEN (Bit 3) */ 8648 #define ETH_HW_FEATURE_EXTHASHEN_Msk (0x8UL) /*!< ETH HW_FEATURE: EXTHASHEN (Bitfield-Mask: 0x01) */ 8649 #define ETH_HW_FEATURE_HASHSEL_Pos (4UL) /*!< ETH HW_FEATURE: HASHSEL (Bit 4) */ 8650 #define ETH_HW_FEATURE_HASHSEL_Msk (0x10UL) /*!< ETH HW_FEATURE: HASHSEL (Bitfield-Mask: 0x01) */ 8651 #define ETH_HW_FEATURE_ADDMACADRSEL_Pos (5UL) /*!< ETH HW_FEATURE: ADDMACADRSEL (Bit 5) */ 8652 #define ETH_HW_FEATURE_ADDMACADRSEL_Msk (0x20UL) /*!< ETH HW_FEATURE: ADDMACADRSEL (Bitfield-Mask: 0x01) */ 8653 #define ETH_HW_FEATURE_PCSSEL_Pos (6UL) /*!< ETH HW_FEATURE: PCSSEL (Bit 6) */ 8654 #define ETH_HW_FEATURE_PCSSEL_Msk (0x40UL) /*!< ETH HW_FEATURE: PCSSEL (Bitfield-Mask: 0x01) */ 8655 #define ETH_HW_FEATURE_L3L4FLTREN_Pos (7UL) /*!< ETH HW_FEATURE: L3L4FLTREN (Bit 7) */ 8656 #define ETH_HW_FEATURE_L3L4FLTREN_Msk (0x80UL) /*!< ETH HW_FEATURE: L3L4FLTREN (Bitfield-Mask: 0x01) */ 8657 #define ETH_HW_FEATURE_SMASEL_Pos (8UL) /*!< ETH HW_FEATURE: SMASEL (Bit 8) */ 8658 #define ETH_HW_FEATURE_SMASEL_Msk (0x100UL) /*!< ETH HW_FEATURE: SMASEL (Bitfield-Mask: 0x01) */ 8659 #define ETH_HW_FEATURE_RWKSEL_Pos (9UL) /*!< ETH HW_FEATURE: RWKSEL (Bit 9) */ 8660 #define ETH_HW_FEATURE_RWKSEL_Msk (0x200UL) /*!< ETH HW_FEATURE: RWKSEL (Bitfield-Mask: 0x01) */ 8661 #define ETH_HW_FEATURE_MGKSEL_Pos (10UL) /*!< ETH HW_FEATURE: MGKSEL (Bit 10) */ 8662 #define ETH_HW_FEATURE_MGKSEL_Msk (0x400UL) /*!< ETH HW_FEATURE: MGKSEL (Bitfield-Mask: 0x01) */ 8663 #define ETH_HW_FEATURE_MMCSEL_Pos (11UL) /*!< ETH HW_FEATURE: MMCSEL (Bit 11) */ 8664 #define ETH_HW_FEATURE_MMCSEL_Msk (0x800UL) /*!< ETH HW_FEATURE: MMCSEL (Bitfield-Mask: 0x01) */ 8665 #define ETH_HW_FEATURE_TSVER1SEL_Pos (12UL) /*!< ETH HW_FEATURE: TSVER1SEL (Bit 12) */ 8666 #define ETH_HW_FEATURE_TSVER1SEL_Msk (0x1000UL) /*!< ETH HW_FEATURE: TSVER1SEL (Bitfield-Mask: 0x01) */ 8667 #define ETH_HW_FEATURE_TSVER2SEL_Pos (13UL) /*!< ETH HW_FEATURE: TSVER2SEL (Bit 13) */ 8668 #define ETH_HW_FEATURE_TSVER2SEL_Msk (0x2000UL) /*!< ETH HW_FEATURE: TSVER2SEL (Bitfield-Mask: 0x01) */ 8669 #define ETH_HW_FEATURE_EEESEL_Pos (14UL) /*!< ETH HW_FEATURE: EEESEL (Bit 14) */ 8670 #define ETH_HW_FEATURE_EEESEL_Msk (0x4000UL) /*!< ETH HW_FEATURE: EEESEL (Bitfield-Mask: 0x01) */ 8671 #define ETH_HW_FEATURE_AVSEL_Pos (15UL) /*!< ETH HW_FEATURE: AVSEL (Bit 15) */ 8672 #define ETH_HW_FEATURE_AVSEL_Msk (0x8000UL) /*!< ETH HW_FEATURE: AVSEL (Bitfield-Mask: 0x01) */ 8673 #define ETH_HW_FEATURE_TXCOESEL_Pos (16UL) /*!< ETH HW_FEATURE: TXCOESEL (Bit 16) */ 8674 #define ETH_HW_FEATURE_TXCOESEL_Msk (0x10000UL) /*!< ETH HW_FEATURE: TXCOESEL (Bitfield-Mask: 0x01) */ 8675 #define ETH_HW_FEATURE_RXTYP1COE_Pos (17UL) /*!< ETH HW_FEATURE: RXTYP1COE (Bit 17) */ 8676 #define ETH_HW_FEATURE_RXTYP1COE_Msk (0x20000UL) /*!< ETH HW_FEATURE: RXTYP1COE (Bitfield-Mask: 0x01) */ 8677 #define ETH_HW_FEATURE_RXTYP2COE_Pos (18UL) /*!< ETH HW_FEATURE: RXTYP2COE (Bit 18) */ 8678 #define ETH_HW_FEATURE_RXTYP2COE_Msk (0x40000UL) /*!< ETH HW_FEATURE: RXTYP2COE (Bitfield-Mask: 0x01) */ 8679 #define ETH_HW_FEATURE_RXFIFOSIZE_Pos (19UL) /*!< ETH HW_FEATURE: RXFIFOSIZE (Bit 19) */ 8680 #define ETH_HW_FEATURE_RXFIFOSIZE_Msk (0x80000UL) /*!< ETH HW_FEATURE: RXFIFOSIZE (Bitfield-Mask: 0x01) */ 8681 #define ETH_HW_FEATURE_RXCHCNT_Pos (20UL) /*!< ETH HW_FEATURE: RXCHCNT (Bit 20) */ 8682 #define ETH_HW_FEATURE_RXCHCNT_Msk (0x300000UL) /*!< ETH HW_FEATURE: RXCHCNT (Bitfield-Mask: 0x03) */ 8683 #define ETH_HW_FEATURE_TXCHCNT_Pos (22UL) /*!< ETH HW_FEATURE: TXCHCNT (Bit 22) */ 8684 #define ETH_HW_FEATURE_TXCHCNT_Msk (0xc00000UL) /*!< ETH HW_FEATURE: TXCHCNT (Bitfield-Mask: 0x03) */ 8685 #define ETH_HW_FEATURE_ENHDESSEL_Pos (24UL) /*!< ETH HW_FEATURE: ENHDESSEL (Bit 24) */ 8686 #define ETH_HW_FEATURE_ENHDESSEL_Msk (0x1000000UL) /*!< ETH HW_FEATURE: ENHDESSEL (Bitfield-Mask: 0x01) */ 8687 #define ETH_HW_FEATURE_INTTSEN_Pos (25UL) /*!< ETH HW_FEATURE: INTTSEN (Bit 25) */ 8688 #define ETH_HW_FEATURE_INTTSEN_Msk (0x2000000UL) /*!< ETH HW_FEATURE: INTTSEN (Bitfield-Mask: 0x01) */ 8689 #define ETH_HW_FEATURE_FLEXIPPSEN_Pos (26UL) /*!< ETH HW_FEATURE: FLEXIPPSEN (Bit 26) */ 8690 #define ETH_HW_FEATURE_FLEXIPPSEN_Msk (0x4000000UL) /*!< ETH HW_FEATURE: FLEXIPPSEN (Bitfield-Mask: 0x01) */ 8691 #define ETH_HW_FEATURE_SAVLANINS_Pos (27UL) /*!< ETH HW_FEATURE: SAVLANINS (Bit 27) */ 8692 #define ETH_HW_FEATURE_SAVLANINS_Msk (0x8000000UL) /*!< ETH HW_FEATURE: SAVLANINS (Bitfield-Mask: 0x01) */ 8693 #define ETH_HW_FEATURE_ACTPHYIF_Pos (28UL) /*!< ETH HW_FEATURE: ACTPHYIF (Bit 28) */ 8694 #define ETH_HW_FEATURE_ACTPHYIF_Msk (0x70000000UL) /*!< ETH HW_FEATURE: ACTPHYIF (Bitfield-Mask: 0x07) */ 8695 8696 8697 /* ================================================================================ */ 8698 /* ================ Group 'USB' Position & Mask ================ */ 8699 /* ================================================================================ */ 8700 8701 8702 /* --------------------------------- USB_GOTGCTL -------------------------------- */ 8703 #define USB_GOTGCTL_SesReqScs_Pos (0UL) /*!< USB GOTGCTL: SesReqScs (Bit 0) */ 8704 #define USB_GOTGCTL_SesReqScs_Msk (0x1UL) /*!< USB GOTGCTL: SesReqScs (Bitfield-Mask: 0x01) */ 8705 #define USB_GOTGCTL_SesReq_Pos (1UL) /*!< USB GOTGCTL: SesReq (Bit 1) */ 8706 #define USB_GOTGCTL_SesReq_Msk (0x2UL) /*!< USB GOTGCTL: SesReq (Bitfield-Mask: 0x01) */ 8707 #define USB_GOTGCTL_VbvalidOvEn_Pos (2UL) /*!< USB GOTGCTL: VbvalidOvEn (Bit 2) */ 8708 #define USB_GOTGCTL_VbvalidOvEn_Msk (0x4UL) /*!< USB GOTGCTL: VbvalidOvEn (Bitfield-Mask: 0x01) */ 8709 #define USB_GOTGCTL_VbvalidOvVal_Pos (3UL) /*!< USB GOTGCTL: VbvalidOvVal (Bit 3) */ 8710 #define USB_GOTGCTL_VbvalidOvVal_Msk (0x8UL) /*!< USB GOTGCTL: VbvalidOvVal (Bitfield-Mask: 0x01) */ 8711 #define USB_GOTGCTL_AvalidOvEn_Pos (4UL) /*!< USB GOTGCTL: AvalidOvEn (Bit 4) */ 8712 #define USB_GOTGCTL_AvalidOvEn_Msk (0x10UL) /*!< USB GOTGCTL: AvalidOvEn (Bitfield-Mask: 0x01) */ 8713 #define USB_GOTGCTL_AvalidOvVal_Pos (5UL) /*!< USB GOTGCTL: AvalidOvVal (Bit 5) */ 8714 #define USB_GOTGCTL_AvalidOvVal_Msk (0x20UL) /*!< USB GOTGCTL: AvalidOvVal (Bitfield-Mask: 0x01) */ 8715 #define USB_GOTGCTL_BvalidOvEn_Pos (6UL) /*!< USB GOTGCTL: BvalidOvEn (Bit 6) */ 8716 #define USB_GOTGCTL_BvalidOvEn_Msk (0x40UL) /*!< USB GOTGCTL: BvalidOvEn (Bitfield-Mask: 0x01) */ 8717 #define USB_GOTGCTL_BvalidOvVal_Pos (7UL) /*!< USB GOTGCTL: BvalidOvVal (Bit 7) */ 8718 #define USB_GOTGCTL_BvalidOvVal_Msk (0x80UL) /*!< USB GOTGCTL: BvalidOvVal (Bitfield-Mask: 0x01) */ 8719 #define USB_GOTGCTL_HstNegScs_Pos (8UL) /*!< USB GOTGCTL: HstNegScs (Bit 8) */ 8720 #define USB_GOTGCTL_HstNegScs_Msk (0x100UL) /*!< USB GOTGCTL: HstNegScs (Bitfield-Mask: 0x01) */ 8721 #define USB_GOTGCTL_HNPReq_Pos (9UL) /*!< USB GOTGCTL: HNPReq (Bit 9) */ 8722 #define USB_GOTGCTL_HNPReq_Msk (0x200UL) /*!< USB GOTGCTL: HNPReq (Bitfield-Mask: 0x01) */ 8723 #define USB_GOTGCTL_HstSetHNPEn_Pos (10UL) /*!< USB GOTGCTL: HstSetHNPEn (Bit 10) */ 8724 #define USB_GOTGCTL_HstSetHNPEn_Msk (0x400UL) /*!< USB GOTGCTL: HstSetHNPEn (Bitfield-Mask: 0x01) */ 8725 #define USB_GOTGCTL_DevHNPEn_Pos (11UL) /*!< USB GOTGCTL: DevHNPEn (Bit 11) */ 8726 #define USB_GOTGCTL_DevHNPEn_Msk (0x800UL) /*!< USB GOTGCTL: DevHNPEn (Bitfield-Mask: 0x01) */ 8727 #define USB_GOTGCTL_ConlDSts_Pos (16UL) /*!< USB GOTGCTL: ConlDSts (Bit 16) */ 8728 #define USB_GOTGCTL_ConlDSts_Msk (0x10000UL) /*!< USB GOTGCTL: ConlDSts (Bitfield-Mask: 0x01) */ 8729 #define USB_GOTGCTL_DbncTime_Pos (17UL) /*!< USB GOTGCTL: DbncTime (Bit 17) */ 8730 #define USB_GOTGCTL_DbncTime_Msk (0x20000UL) /*!< USB GOTGCTL: DbncTime (Bitfield-Mask: 0x01) */ 8731 #define USB_GOTGCTL_ASesVId_Pos (18UL) /*!< USB GOTGCTL: ASesVId (Bit 18) */ 8732 #define USB_GOTGCTL_ASesVId_Msk (0x40000UL) /*!< USB GOTGCTL: ASesVId (Bitfield-Mask: 0x01) */ 8733 #define USB_GOTGCTL_BSesVld_Pos (19UL) /*!< USB GOTGCTL: BSesVld (Bit 19) */ 8734 #define USB_GOTGCTL_BSesVld_Msk (0x80000UL) /*!< USB GOTGCTL: BSesVld (Bitfield-Mask: 0x01) */ 8735 #define USB_GOTGCTL_OTGVer_Pos (20UL) /*!< USB GOTGCTL: OTGVer (Bit 20) */ 8736 #define USB_GOTGCTL_OTGVer_Msk (0x100000UL) /*!< USB GOTGCTL: OTGVer (Bitfield-Mask: 0x01) */ 8737 8738 /* --------------------------------- USB_GOTGINT -------------------------------- */ 8739 #define USB_GOTGINT_SesEndDet_Pos (2UL) /*!< USB GOTGINT: SesEndDet (Bit 2) */ 8740 #define USB_GOTGINT_SesEndDet_Msk (0x4UL) /*!< USB GOTGINT: SesEndDet (Bitfield-Mask: 0x01) */ 8741 #define USB_GOTGINT_SesReqSucStsChng_Pos (8UL) /*!< USB GOTGINT: SesReqSucStsChng (Bit 8) */ 8742 #define USB_GOTGINT_SesReqSucStsChng_Msk (0x100UL) /*!< USB GOTGINT: SesReqSucStsChng (Bitfield-Mask: 0x01) */ 8743 #define USB_GOTGINT_HstNegSucStsChng_Pos (9UL) /*!< USB GOTGINT: HstNegSucStsChng (Bit 9) */ 8744 #define USB_GOTGINT_HstNegSucStsChng_Msk (0x200UL) /*!< USB GOTGINT: HstNegSucStsChng (Bitfield-Mask: 0x01) */ 8745 #define USB_GOTGINT_HstNegDet_Pos (17UL) /*!< USB GOTGINT: HstNegDet (Bit 17) */ 8746 #define USB_GOTGINT_HstNegDet_Msk (0x20000UL) /*!< USB GOTGINT: HstNegDet (Bitfield-Mask: 0x01) */ 8747 #define USB_GOTGINT_ADevTOUTChg_Pos (18UL) /*!< USB GOTGINT: ADevTOUTChg (Bit 18) */ 8748 #define USB_GOTGINT_ADevTOUTChg_Msk (0x40000UL) /*!< USB GOTGINT: ADevTOUTChg (Bitfield-Mask: 0x01) */ 8749 #define USB_GOTGINT_DbnceDone_Pos (19UL) /*!< USB GOTGINT: DbnceDone (Bit 19) */ 8750 #define USB_GOTGINT_DbnceDone_Msk (0x80000UL) /*!< USB GOTGINT: DbnceDone (Bitfield-Mask: 0x01) */ 8751 8752 /* --------------------------------- USB_GAHBCFG -------------------------------- */ 8753 #define USB_GAHBCFG_GlblIntrMsk_Pos (0UL) /*!< USB GAHBCFG: GlblIntrMsk (Bit 0) */ 8754 #define USB_GAHBCFG_GlblIntrMsk_Msk (0x1UL) /*!< USB GAHBCFG: GlblIntrMsk (Bitfield-Mask: 0x01) */ 8755 #define USB_GAHBCFG_HBstLen_Pos (1UL) /*!< USB GAHBCFG: HBstLen (Bit 1) */ 8756 #define USB_GAHBCFG_HBstLen_Msk (0x1eUL) /*!< USB GAHBCFG: HBstLen (Bitfield-Mask: 0x0f) */ 8757 #define USB_GAHBCFG_DMAEn_Pos (5UL) /*!< USB GAHBCFG: DMAEn (Bit 5) */ 8758 #define USB_GAHBCFG_DMAEn_Msk (0x20UL) /*!< USB GAHBCFG: DMAEn (Bitfield-Mask: 0x01) */ 8759 #define USB_GAHBCFG_NPTxFEmpLvl_Pos (7UL) /*!< USB GAHBCFG: NPTxFEmpLvl (Bit 7) */ 8760 #define USB_GAHBCFG_NPTxFEmpLvl_Msk (0x80UL) /*!< USB GAHBCFG: NPTxFEmpLvl (Bitfield-Mask: 0x01) */ 8761 #define USB_GAHBCFG_PTxFEmpLvl_Pos (8UL) /*!< USB GAHBCFG: PTxFEmpLvl (Bit 8) */ 8762 #define USB_GAHBCFG_PTxFEmpLvl_Msk (0x100UL) /*!< USB GAHBCFG: PTxFEmpLvl (Bitfield-Mask: 0x01) */ 8763 8764 /* --------------------------------- USB_GUSBCFG -------------------------------- */ 8765 #define USB_GUSBCFG_TOutCal_Pos (0UL) /*!< USB GUSBCFG: TOutCal (Bit 0) */ 8766 #define USB_GUSBCFG_TOutCal_Msk (0x7UL) /*!< USB GUSBCFG: TOutCal (Bitfield-Mask: 0x07) */ 8767 #define USB_GUSBCFG_PHYSel_Pos (6UL) /*!< USB GUSBCFG: PHYSel (Bit 6) */ 8768 #define USB_GUSBCFG_PHYSel_Msk (0x40UL) /*!< USB GUSBCFG: PHYSel (Bitfield-Mask: 0x01) */ 8769 #define USB_GUSBCFG_SRPCap_Pos (8UL) /*!< USB GUSBCFG: SRPCap (Bit 8) */ 8770 #define USB_GUSBCFG_SRPCap_Msk (0x100UL) /*!< USB GUSBCFG: SRPCap (Bitfield-Mask: 0x01) */ 8771 #define USB_GUSBCFG_HNPCap_Pos (9UL) /*!< USB GUSBCFG: HNPCap (Bit 9) */ 8772 #define USB_GUSBCFG_HNPCap_Msk (0x200UL) /*!< USB GUSBCFG: HNPCap (Bitfield-Mask: 0x01) */ 8773 #define USB_GUSBCFG_USBTrdTim_Pos (10UL) /*!< USB GUSBCFG: USBTrdTim (Bit 10) */ 8774 #define USB_GUSBCFG_USBTrdTim_Msk (0x3c00UL) /*!< USB GUSBCFG: USBTrdTim (Bitfield-Mask: 0x0f) */ 8775 #define USB_GUSBCFG_OtgI2CSel_Pos (16UL) /*!< USB GUSBCFG: OtgI2CSel (Bit 16) */ 8776 #define USB_GUSBCFG_OtgI2CSel_Msk (0x10000UL) /*!< USB GUSBCFG: OtgI2CSel (Bitfield-Mask: 0x01) */ 8777 #define USB_GUSBCFG_TxEndDelay_Pos (28UL) /*!< USB GUSBCFG: TxEndDelay (Bit 28) */ 8778 #define USB_GUSBCFG_TxEndDelay_Msk (0x10000000UL) /*!< USB GUSBCFG: TxEndDelay (Bitfield-Mask: 0x01) */ 8779 #define USB_GUSBCFG_ForceHstMode_Pos (29UL) /*!< USB GUSBCFG: ForceHstMode (Bit 29) */ 8780 #define USB_GUSBCFG_ForceHstMode_Msk (0x20000000UL) /*!< USB GUSBCFG: ForceHstMode (Bitfield-Mask: 0x01) */ 8781 #define USB_GUSBCFG_ForceDevMode_Pos (30UL) /*!< USB GUSBCFG: ForceDevMode (Bit 30) */ 8782 #define USB_GUSBCFG_ForceDevMode_Msk (0x40000000UL) /*!< USB GUSBCFG: ForceDevMode (Bitfield-Mask: 0x01) */ 8783 #define USB_GUSBCFG_CTP_Pos (31UL) /*!< USB GUSBCFG: CTP (Bit 31) */ 8784 #define USB_GUSBCFG_CTP_Msk (0x80000000UL) /*!< USB GUSBCFG: CTP (Bitfield-Mask: 0x01) */ 8785 8786 /* --------------------------------- USB_GRSTCTL -------------------------------- */ 8787 #define USB_GRSTCTL_CSftRst_Pos (0UL) /*!< USB GRSTCTL: CSftRst (Bit 0) */ 8788 #define USB_GRSTCTL_CSftRst_Msk (0x1UL) /*!< USB GRSTCTL: CSftRst (Bitfield-Mask: 0x01) */ 8789 #define USB_GRSTCTL_FrmCntrRst_Pos (2UL) /*!< USB GRSTCTL: FrmCntrRst (Bit 2) */ 8790 #define USB_GRSTCTL_FrmCntrRst_Msk (0x4UL) /*!< USB GRSTCTL: FrmCntrRst (Bitfield-Mask: 0x01) */ 8791 #define USB_GRSTCTL_RxFFlsh_Pos (4UL) /*!< USB GRSTCTL: RxFFlsh (Bit 4) */ 8792 #define USB_GRSTCTL_RxFFlsh_Msk (0x10UL) /*!< USB GRSTCTL: RxFFlsh (Bitfield-Mask: 0x01) */ 8793 #define USB_GRSTCTL_TxFFlsh_Pos (5UL) /*!< USB GRSTCTL: TxFFlsh (Bit 5) */ 8794 #define USB_GRSTCTL_TxFFlsh_Msk (0x20UL) /*!< USB GRSTCTL: TxFFlsh (Bitfield-Mask: 0x01) */ 8795 #define USB_GRSTCTL_TxFNum_Pos (6UL) /*!< USB GRSTCTL: TxFNum (Bit 6) */ 8796 #define USB_GRSTCTL_TxFNum_Msk (0x7c0UL) /*!< USB GRSTCTL: TxFNum (Bitfield-Mask: 0x1f) */ 8797 #define USB_GRSTCTL_DMAReq_Pos (30UL) /*!< USB GRSTCTL: DMAReq (Bit 30) */ 8798 #define USB_GRSTCTL_DMAReq_Msk (0x40000000UL) /*!< USB GRSTCTL: DMAReq (Bitfield-Mask: 0x01) */ 8799 #define USB_GRSTCTL_AHBIdle_Pos (31UL) /*!< USB GRSTCTL: AHBIdle (Bit 31) */ 8800 #define USB_GRSTCTL_AHBIdle_Msk (0x80000000UL) /*!< USB GRSTCTL: AHBIdle (Bitfield-Mask: 0x01) */ 8801 8802 /* ---------------------------- USB_GINTSTS_HOSTMODE ---------------------------- */ 8803 #define USB_GINTSTS_HOSTMODE_CurMod_Pos (0UL) /*!< USB GINTSTS_HOSTMODE: CurMod (Bit 0) */ 8804 #define USB_GINTSTS_HOSTMODE_CurMod_Msk (0x1UL) /*!< USB GINTSTS_HOSTMODE: CurMod (Bitfield-Mask: 0x01) */ 8805 #define USB_GINTSTS_HOSTMODE_ModeMis_Pos (1UL) /*!< USB GINTSTS_HOSTMODE: ModeMis (Bit 1) */ 8806 #define USB_GINTSTS_HOSTMODE_ModeMis_Msk (0x2UL) /*!< USB GINTSTS_HOSTMODE: ModeMis (Bitfield-Mask: 0x01) */ 8807 #define USB_GINTSTS_HOSTMODE_OTGInt_Pos (2UL) /*!< USB GINTSTS_HOSTMODE: OTGInt (Bit 2) */ 8808 #define USB_GINTSTS_HOSTMODE_OTGInt_Msk (0x4UL) /*!< USB GINTSTS_HOSTMODE: OTGInt (Bitfield-Mask: 0x01) */ 8809 #define USB_GINTSTS_HOSTMODE_Sof_Pos (3UL) /*!< USB GINTSTS_HOSTMODE: Sof (Bit 3) */ 8810 #define USB_GINTSTS_HOSTMODE_Sof_Msk (0x8UL) /*!< USB GINTSTS_HOSTMODE: Sof (Bitfield-Mask: 0x01) */ 8811 #define USB_GINTSTS_HOSTMODE_RxFLvl_Pos (4UL) /*!< USB GINTSTS_HOSTMODE: RxFLvl (Bit 4) */ 8812 #define USB_GINTSTS_HOSTMODE_RxFLvl_Msk (0x10UL) /*!< USB GINTSTS_HOSTMODE: RxFLvl (Bitfield-Mask: 0x01) */ 8813 #define USB_GINTSTS_HOSTMODE_incomplP_Pos (21UL) /*!< USB GINTSTS_HOSTMODE: incomplP (Bit 21) */ 8814 #define USB_GINTSTS_HOSTMODE_incomplP_Msk (0x200000UL) /*!< USB GINTSTS_HOSTMODE: incomplP (Bitfield-Mask: 0x01) */ 8815 #define USB_GINTSTS_HOSTMODE_PrtInt_Pos (24UL) /*!< USB GINTSTS_HOSTMODE: PrtInt (Bit 24) */ 8816 #define USB_GINTSTS_HOSTMODE_PrtInt_Msk (0x1000000UL) /*!< USB GINTSTS_HOSTMODE: PrtInt (Bitfield-Mask: 0x01) */ 8817 #define USB_GINTSTS_HOSTMODE_HChInt_Pos (25UL) /*!< USB GINTSTS_HOSTMODE: HChInt (Bit 25) */ 8818 #define USB_GINTSTS_HOSTMODE_HChInt_Msk (0x2000000UL) /*!< USB GINTSTS_HOSTMODE: HChInt (Bitfield-Mask: 0x01) */ 8819 #define USB_GINTSTS_HOSTMODE_PTxFEmp_Pos (26UL) /*!< USB GINTSTS_HOSTMODE: PTxFEmp (Bit 26) */ 8820 #define USB_GINTSTS_HOSTMODE_PTxFEmp_Msk (0x4000000UL) /*!< USB GINTSTS_HOSTMODE: PTxFEmp (Bitfield-Mask: 0x01) */ 8821 #define USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos (28UL) /*!< USB GINTSTS_HOSTMODE: ConIDStsChng (Bit 28) */ 8822 #define USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk (0x10000000UL) /*!< USB GINTSTS_HOSTMODE: ConIDStsChng (Bitfield-Mask: 0x01) */ 8823 #define USB_GINTSTS_HOSTMODE_DisconnInt_Pos (29UL) /*!< USB GINTSTS_HOSTMODE: DisconnInt (Bit 29) */ 8824 #define USB_GINTSTS_HOSTMODE_DisconnInt_Msk (0x20000000UL) /*!< USB GINTSTS_HOSTMODE: DisconnInt (Bitfield-Mask: 0x01) */ 8825 #define USB_GINTSTS_HOSTMODE_SessReqInt_Pos (30UL) /*!< USB GINTSTS_HOSTMODE: SessReqInt (Bit 30) */ 8826 #define USB_GINTSTS_HOSTMODE_SessReqInt_Msk (0x40000000UL) /*!< USB GINTSTS_HOSTMODE: SessReqInt (Bitfield-Mask: 0x01) */ 8827 #define USB_GINTSTS_HOSTMODE_WkUpInt_Pos (31UL) /*!< USB GINTSTS_HOSTMODE: WkUpInt (Bit 31) */ 8828 #define USB_GINTSTS_HOSTMODE_WkUpInt_Msk (0x80000000UL) /*!< USB GINTSTS_HOSTMODE: WkUpInt (Bitfield-Mask: 0x01) */ 8829 8830 /* --------------------------- USB_GINTSTS_DEVICEMODE --------------------------- */ 8831 #define USB_GINTSTS_DEVICEMODE_CurMod_Pos (0UL) /*!< USB GINTSTS_DEVICEMODE: CurMod (Bit 0) */ 8832 #define USB_GINTSTS_DEVICEMODE_CurMod_Msk (0x1UL) /*!< USB GINTSTS_DEVICEMODE: CurMod (Bitfield-Mask: 0x01) */ 8833 #define USB_GINTSTS_DEVICEMODE_ModeMis_Pos (1UL) /*!< USB GINTSTS_DEVICEMODE: ModeMis (Bit 1) */ 8834 #define USB_GINTSTS_DEVICEMODE_ModeMis_Msk (0x2UL) /*!< USB GINTSTS_DEVICEMODE: ModeMis (Bitfield-Mask: 0x01) */ 8835 #define USB_GINTSTS_DEVICEMODE_OTGInt_Pos (2UL) /*!< USB GINTSTS_DEVICEMODE: OTGInt (Bit 2) */ 8836 #define USB_GINTSTS_DEVICEMODE_OTGInt_Msk (0x4UL) /*!< USB GINTSTS_DEVICEMODE: OTGInt (Bitfield-Mask: 0x01) */ 8837 #define USB_GINTSTS_DEVICEMODE_Sof_Pos (3UL) /*!< USB GINTSTS_DEVICEMODE: Sof (Bit 3) */ 8838 #define USB_GINTSTS_DEVICEMODE_Sof_Msk (0x8UL) /*!< USB GINTSTS_DEVICEMODE: Sof (Bitfield-Mask: 0x01) */ 8839 #define USB_GINTSTS_DEVICEMODE_RxFLvl_Pos (4UL) /*!< USB GINTSTS_DEVICEMODE: RxFLvl (Bit 4) */ 8840 #define USB_GINTSTS_DEVICEMODE_RxFLvl_Msk (0x10UL) /*!< USB GINTSTS_DEVICEMODE: RxFLvl (Bitfield-Mask: 0x01) */ 8841 #define USB_GINTSTS_DEVICEMODE_GINNakEff_Pos (6UL) /*!< USB GINTSTS_DEVICEMODE: GINNakEff (Bit 6) */ 8842 #define USB_GINTSTS_DEVICEMODE_GINNakEff_Msk (0x40UL) /*!< USB GINTSTS_DEVICEMODE: GINNakEff (Bitfield-Mask: 0x01) */ 8843 #define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos (7UL) /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff (Bit 7) */ 8844 #define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk (0x80UL) /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff (Bitfield-Mask: 0x01) */ 8845 #define USB_GINTSTS_DEVICEMODE_ErlySusp_Pos (10UL) /*!< USB GINTSTS_DEVICEMODE: ErlySusp (Bit 10) */ 8846 #define USB_GINTSTS_DEVICEMODE_ErlySusp_Msk (0x400UL) /*!< USB GINTSTS_DEVICEMODE: ErlySusp (Bitfield-Mask: 0x01) */ 8847 #define USB_GINTSTS_DEVICEMODE_USBSusp_Pos (11UL) /*!< USB GINTSTS_DEVICEMODE: USBSusp (Bit 11) */ 8848 #define USB_GINTSTS_DEVICEMODE_USBSusp_Msk (0x800UL) /*!< USB GINTSTS_DEVICEMODE: USBSusp (Bitfield-Mask: 0x01) */ 8849 #define USB_GINTSTS_DEVICEMODE_USBRst_Pos (12UL) /*!< USB GINTSTS_DEVICEMODE: USBRst (Bit 12) */ 8850 #define USB_GINTSTS_DEVICEMODE_USBRst_Msk (0x1000UL) /*!< USB GINTSTS_DEVICEMODE: USBRst (Bitfield-Mask: 0x01) */ 8851 #define USB_GINTSTS_DEVICEMODE_EnumDone_Pos (13UL) /*!< USB GINTSTS_DEVICEMODE: EnumDone (Bit 13) */ 8852 #define USB_GINTSTS_DEVICEMODE_EnumDone_Msk (0x2000UL) /*!< USB GINTSTS_DEVICEMODE: EnumDone (Bitfield-Mask: 0x01) */ 8853 #define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos (14UL) /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop (Bit 14) */ 8854 #define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk (0x4000UL) /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop (Bitfield-Mask: 0x01) */ 8855 #define USB_GINTSTS_DEVICEMODE_EOPF_Pos (15UL) /*!< USB GINTSTS_DEVICEMODE: EOPF (Bit 15) */ 8856 #define USB_GINTSTS_DEVICEMODE_EOPF_Msk (0x8000UL) /*!< USB GINTSTS_DEVICEMODE: EOPF (Bitfield-Mask: 0x01) */ 8857 #define USB_GINTSTS_DEVICEMODE_IEPInt_Pos (18UL) /*!< USB GINTSTS_DEVICEMODE: IEPInt (Bit 18) */ 8858 #define USB_GINTSTS_DEVICEMODE_IEPInt_Msk (0x40000UL) /*!< USB GINTSTS_DEVICEMODE: IEPInt (Bitfield-Mask: 0x01) */ 8859 #define USB_GINTSTS_DEVICEMODE_OEPInt_Pos (19UL) /*!< USB GINTSTS_DEVICEMODE: OEPInt (Bit 19) */ 8860 #define USB_GINTSTS_DEVICEMODE_OEPInt_Msk (0x80000UL) /*!< USB GINTSTS_DEVICEMODE: OEPInt (Bitfield-Mask: 0x01) */ 8861 #define USB_GINTSTS_DEVICEMODE_incompISOIN_Pos (20UL) /*!< USB GINTSTS_DEVICEMODE: incompISOIN (Bit 20) */ 8862 #define USB_GINTSTS_DEVICEMODE_incompISOIN_Msk (0x100000UL) /*!< USB GINTSTS_DEVICEMODE: incompISOIN (Bitfield-Mask: 0x01) */ 8863 #define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos (21UL) /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT (Bit 21) */ 8864 #define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk (0x200000UL) /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT (Bitfield-Mask: 0x01) */ 8865 #define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos (28UL) /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng (Bit 28) */ 8866 #define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk (0x10000000UL) /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng (Bitfield-Mask: 0x01) */ 8867 #define USB_GINTSTS_DEVICEMODE_SessReqInt_Pos (30UL) /*!< USB GINTSTS_DEVICEMODE: SessReqInt (Bit 30) */ 8868 #define USB_GINTSTS_DEVICEMODE_SessReqInt_Msk (0x40000000UL) /*!< USB GINTSTS_DEVICEMODE: SessReqInt (Bitfield-Mask: 0x01) */ 8869 #define USB_GINTSTS_DEVICEMODE_WkUpInt_Pos (31UL) /*!< USB GINTSTS_DEVICEMODE: WkUpInt (Bit 31) */ 8870 #define USB_GINTSTS_DEVICEMODE_WkUpInt_Msk (0x80000000UL) /*!< USB GINTSTS_DEVICEMODE: WkUpInt (Bitfield-Mask: 0x01) */ 8871 8872 /* ---------------------------- USB_GINTMSK_HOSTMODE ---------------------------- */ 8873 #define USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos (1UL) /*!< USB GINTMSK_HOSTMODE: ModeMisMsk (Bit 1) */ 8874 #define USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk (0x2UL) /*!< USB GINTMSK_HOSTMODE: ModeMisMsk (Bitfield-Mask: 0x01) */ 8875 #define USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos (2UL) /*!< USB GINTMSK_HOSTMODE: OTGIntMsk (Bit 2) */ 8876 #define USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk (0x4UL) /*!< USB GINTMSK_HOSTMODE: OTGIntMsk (Bitfield-Mask: 0x01) */ 8877 #define USB_GINTMSK_HOSTMODE_SofMsk_Pos (3UL) /*!< USB GINTMSK_HOSTMODE: SofMsk (Bit 3) */ 8878 #define USB_GINTMSK_HOSTMODE_SofMsk_Msk (0x8UL) /*!< USB GINTMSK_HOSTMODE: SofMsk (Bitfield-Mask: 0x01) */ 8879 #define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos (4UL) /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk (Bit 4) */ 8880 #define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk (0x10UL) /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk (Bitfield-Mask: 0x01) */ 8881 #define USB_GINTMSK_HOSTMODE_incomplPMsk_Pos (21UL) /*!< USB GINTMSK_HOSTMODE: incomplPMsk (Bit 21) */ 8882 #define USB_GINTMSK_HOSTMODE_incomplPMsk_Msk (0x200000UL) /*!< USB GINTMSK_HOSTMODE: incomplPMsk (Bitfield-Mask: 0x01) */ 8883 #define USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos (24UL) /*!< USB GINTMSK_HOSTMODE: PrtIntMsk (Bit 24) */ 8884 #define USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk (0x1000000UL) /*!< USB GINTMSK_HOSTMODE: PrtIntMsk (Bitfield-Mask: 0x01) */ 8885 #define USB_GINTMSK_HOSTMODE_HChIntMsk_Pos (25UL) /*!< USB GINTMSK_HOSTMODE: HChIntMsk (Bit 25) */ 8886 #define USB_GINTMSK_HOSTMODE_HChIntMsk_Msk (0x2000000UL) /*!< USB GINTMSK_HOSTMODE: HChIntMsk (Bitfield-Mask: 0x01) */ 8887 #define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos (26UL) /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk (Bit 26) */ 8888 #define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk (0x4000000UL) /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk (Bitfield-Mask: 0x01) */ 8889 #define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos (28UL) /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk (Bit 28) */ 8890 #define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk (0x10000000UL) /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk (Bitfield-Mask: 0x01) */ 8891 #define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos (29UL) /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk (Bit 29) */ 8892 #define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk (0x20000000UL) /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk (Bitfield-Mask: 0x01) */ 8893 #define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos (30UL) /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk (Bit 30) */ 8894 #define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk (0x40000000UL) /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk (Bitfield-Mask: 0x01) */ 8895 #define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos (31UL) /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk (Bit 31) */ 8896 #define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk (0x80000000UL) /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk (Bitfield-Mask: 0x01) */ 8897 8898 /* --------------------------- USB_GINTMSK_DEVICEMODE --------------------------- */ 8899 #define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos (1UL) /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk (Bit 1) */ 8900 #define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk (0x2UL) /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk (Bitfield-Mask: 0x01) */ 8901 #define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos (2UL) /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk (Bit 2) */ 8902 #define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk (0x4UL) /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk (Bitfield-Mask: 0x01) */ 8903 #define USB_GINTMSK_DEVICEMODE_SofMsk_Pos (3UL) /*!< USB GINTMSK_DEVICEMODE: SofMsk (Bit 3) */ 8904 #define USB_GINTMSK_DEVICEMODE_SofMsk_Msk (0x8UL) /*!< USB GINTMSK_DEVICEMODE: SofMsk (Bitfield-Mask: 0x01) */ 8905 #define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos (4UL) /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk (Bit 4) */ 8906 #define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk (0x10UL) /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk (Bitfield-Mask: 0x01) */ 8907 #define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos (6UL) /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk (Bit 6) */ 8908 #define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk (0x40UL) /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk (Bitfield-Mask: 0x01) */ 8909 #define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos (7UL) /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk (Bit 7) */ 8910 #define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk (0x80UL) /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk (Bitfield-Mask: 0x01) */ 8911 #define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos (10UL) /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk (Bit 10) */ 8912 #define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk (0x400UL) /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk (Bitfield-Mask: 0x01) */ 8913 #define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos (11UL) /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk (Bit 11) */ 8914 #define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk (0x800UL) /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk (Bitfield-Mask: 0x01) */ 8915 #define USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos (12UL) /*!< USB GINTMSK_DEVICEMODE: USBRstMsk (Bit 12) */ 8916 #define USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk (0x1000UL) /*!< USB GINTMSK_DEVICEMODE: USBRstMsk (Bitfield-Mask: 0x01) */ 8917 #define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos (13UL) /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk (Bit 13) */ 8918 #define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk (0x2000UL) /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk (Bitfield-Mask: 0x01) */ 8919 #define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos (14UL) /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk (Bit 14) */ 8920 #define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk (0x4000UL) /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk (Bitfield-Mask: 0x01) */ 8921 #define USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos (15UL) /*!< USB GINTMSK_DEVICEMODE: EOPFMsk (Bit 15) */ 8922 #define USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk (0x8000UL) /*!< USB GINTMSK_DEVICEMODE: EOPFMsk (Bitfield-Mask: 0x01) */ 8923 #define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos (18UL) /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk (Bit 18) */ 8924 #define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk (0x40000UL) /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk (Bitfield-Mask: 0x01) */ 8925 #define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos (19UL) /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk (Bit 19) */ 8926 #define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk (0x80000UL) /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk (Bitfield-Mask: 0x01) */ 8927 #define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos (20UL) /*!< USB GINTMSK_DEVICEMODE: incompISOINMsk (Bit 20) */ 8928 #define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk (0x100000UL) /*!< USB GINTMSK_DEVICEMODE: incompISOINMsk (Bitfield-Mask: 0x01) */ 8929 #define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos (21UL) /*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk (Bit 21) */ 8930 #define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk (0x200000UL) /*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk (Bitfield-Mask: 0x01) */ 8931 #define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos (28UL) /*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk (Bit 28) */ 8932 #define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk (0x10000000UL) /*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk (Bitfield-Mask: 0x01) */ 8933 #define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos (30UL) /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk (Bit 30) */ 8934 #define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk (0x40000000UL) /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk (Bitfield-Mask: 0x01) */ 8935 #define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos (31UL) /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk (Bit 31) */ 8936 #define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk (0x80000000UL) /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk (Bitfield-Mask: 0x01) */ 8937 8938 /* ---------------------------- USB_GRXSTSR_HOSTMODE ---------------------------- */ 8939 #define USB_GRXSTSR_HOSTMODE_ChNum_Pos (0UL) /*!< USB GRXSTSR_HOSTMODE: ChNum (Bit 0) */ 8940 #define USB_GRXSTSR_HOSTMODE_ChNum_Msk (0xfUL) /*!< USB GRXSTSR_HOSTMODE: ChNum (Bitfield-Mask: 0x0f) */ 8941 #define USB_GRXSTSR_HOSTMODE_BCnt_Pos (4UL) /*!< USB GRXSTSR_HOSTMODE: BCnt (Bit 4) */ 8942 #define USB_GRXSTSR_HOSTMODE_BCnt_Msk (0x7ff0UL) /*!< USB GRXSTSR_HOSTMODE: BCnt (Bitfield-Mask: 0x7ff) */ 8943 #define USB_GRXSTSR_HOSTMODE_DPID_Pos (15UL) /*!< USB GRXSTSR_HOSTMODE: DPID (Bit 15) */ 8944 #define USB_GRXSTSR_HOSTMODE_DPID_Msk (0x18000UL) /*!< USB GRXSTSR_HOSTMODE: DPID (Bitfield-Mask: 0x03) */ 8945 #define USB_GRXSTSR_HOSTMODE_PktSts_Pos (17UL) /*!< USB GRXSTSR_HOSTMODE: PktSts (Bit 17) */ 8946 #define USB_GRXSTSR_HOSTMODE_PktSts_Msk (0x1e0000UL) /*!< USB GRXSTSR_HOSTMODE: PktSts (Bitfield-Mask: 0x0f) */ 8947 8948 /* --------------------------- USB_GRXSTSR_DEVICEMODE --------------------------- */ 8949 #define USB_GRXSTSR_DEVICEMODE_EPNum_Pos (0UL) /*!< USB GRXSTSR_DEVICEMODE: EPNum (Bit 0) */ 8950 #define USB_GRXSTSR_DEVICEMODE_EPNum_Msk (0xfUL) /*!< USB GRXSTSR_DEVICEMODE: EPNum (Bitfield-Mask: 0x0f) */ 8951 #define USB_GRXSTSR_DEVICEMODE_BCnt_Pos (4UL) /*!< USB GRXSTSR_DEVICEMODE: BCnt (Bit 4) */ 8952 #define USB_GRXSTSR_DEVICEMODE_BCnt_Msk (0x7ff0UL) /*!< USB GRXSTSR_DEVICEMODE: BCnt (Bitfield-Mask: 0x7ff) */ 8953 #define USB_GRXSTSR_DEVICEMODE_DPID_Pos (15UL) /*!< USB GRXSTSR_DEVICEMODE: DPID (Bit 15) */ 8954 #define USB_GRXSTSR_DEVICEMODE_DPID_Msk (0x18000UL) /*!< USB GRXSTSR_DEVICEMODE: DPID (Bitfield-Mask: 0x03) */ 8955 #define USB_GRXSTSR_DEVICEMODE_PktSts_Pos (17UL) /*!< USB GRXSTSR_DEVICEMODE: PktSts (Bit 17) */ 8956 #define USB_GRXSTSR_DEVICEMODE_PktSts_Msk (0x1e0000UL) /*!< USB GRXSTSR_DEVICEMODE: PktSts (Bitfield-Mask: 0x0f) */ 8957 #define USB_GRXSTSR_DEVICEMODE_FN_Pos (21UL) /*!< USB GRXSTSR_DEVICEMODE: FN (Bit 21) */ 8958 #define USB_GRXSTSR_DEVICEMODE_FN_Msk (0x1e00000UL) /*!< USB GRXSTSR_DEVICEMODE: FN (Bitfield-Mask: 0x0f) */ 8959 8960 /* ---------------------------- USB_GRXSTSP_HOSTMODE ---------------------------- */ 8961 #define USB_GRXSTSP_HOSTMODE_ChNum_Pos (0UL) /*!< USB GRXSTSP_HOSTMODE: ChNum (Bit 0) */ 8962 #define USB_GRXSTSP_HOSTMODE_ChNum_Msk (0xfUL) /*!< USB GRXSTSP_HOSTMODE: ChNum (Bitfield-Mask: 0x0f) */ 8963 #define USB_GRXSTSP_HOSTMODE_BCnt_Pos (4UL) /*!< USB GRXSTSP_HOSTMODE: BCnt (Bit 4) */ 8964 #define USB_GRXSTSP_HOSTMODE_BCnt_Msk (0x7ff0UL) /*!< USB GRXSTSP_HOSTMODE: BCnt (Bitfield-Mask: 0x7ff) */ 8965 #define USB_GRXSTSP_HOSTMODE_DPID_Pos (15UL) /*!< USB GRXSTSP_HOSTMODE: DPID (Bit 15) */ 8966 #define USB_GRXSTSP_HOSTMODE_DPID_Msk (0x18000UL) /*!< USB GRXSTSP_HOSTMODE: DPID (Bitfield-Mask: 0x03) */ 8967 #define USB_GRXSTSP_HOSTMODE_PktSts_Pos (17UL) /*!< USB GRXSTSP_HOSTMODE: PktSts (Bit 17) */ 8968 #define USB_GRXSTSP_HOSTMODE_PktSts_Msk (0x1e0000UL) /*!< USB GRXSTSP_HOSTMODE: PktSts (Bitfield-Mask: 0x0f) */ 8969 8970 /* --------------------------- USB_GRXSTSP_DEVICEMODE --------------------------- */ 8971 #define USB_GRXSTSP_DEVICEMODE_EPNum_Pos (0UL) /*!< USB GRXSTSP_DEVICEMODE: EPNum (Bit 0) */ 8972 #define USB_GRXSTSP_DEVICEMODE_EPNum_Msk (0xfUL) /*!< USB GRXSTSP_DEVICEMODE: EPNum (Bitfield-Mask: 0x0f) */ 8973 #define USB_GRXSTSP_DEVICEMODE_BCnt_Pos (4UL) /*!< USB GRXSTSP_DEVICEMODE: BCnt (Bit 4) */ 8974 #define USB_GRXSTSP_DEVICEMODE_BCnt_Msk (0x7ff0UL) /*!< USB GRXSTSP_DEVICEMODE: BCnt (Bitfield-Mask: 0x7ff) */ 8975 #define USB_GRXSTSP_DEVICEMODE_DPID_Pos (15UL) /*!< USB GRXSTSP_DEVICEMODE: DPID (Bit 15) */ 8976 #define USB_GRXSTSP_DEVICEMODE_DPID_Msk (0x18000UL) /*!< USB GRXSTSP_DEVICEMODE: DPID (Bitfield-Mask: 0x03) */ 8977 #define USB_GRXSTSP_DEVICEMODE_PktSts_Pos (17UL) /*!< USB GRXSTSP_DEVICEMODE: PktSts (Bit 17) */ 8978 #define USB_GRXSTSP_DEVICEMODE_PktSts_Msk (0x1e0000UL) /*!< USB GRXSTSP_DEVICEMODE: PktSts (Bitfield-Mask: 0x0f) */ 8979 #define USB_GRXSTSP_DEVICEMODE_FN_Pos (21UL) /*!< USB GRXSTSP_DEVICEMODE: FN (Bit 21) */ 8980 #define USB_GRXSTSP_DEVICEMODE_FN_Msk (0x1e00000UL) /*!< USB GRXSTSP_DEVICEMODE: FN (Bitfield-Mask: 0x0f) */ 8981 8982 /* --------------------------------- USB_GRXFSIZ -------------------------------- */ 8983 #define USB_GRXFSIZ_RxFDep_Pos (0UL) /*!< USB GRXFSIZ: RxFDep (Bit 0) */ 8984 #define USB_GRXFSIZ_RxFDep_Msk (0xffffUL) /*!< USB GRXFSIZ: RxFDep (Bitfield-Mask: 0xffff) */ 8985 8986 /* --------------------------- USB_GNPTXFSIZ_HOSTMODE --------------------------- */ 8987 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos (0UL) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr (Bit 0) */ 8988 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk (0xffffUL) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr (Bitfield-Mask: 0xffff) */ 8989 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos (16UL) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep (Bit 16) */ 8990 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk (0xffff0000UL) /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep (Bitfield-Mask: 0xffff) */ 8991 8992 /* -------------------------- USB_GNPTXFSIZ_DEVICEMODE -------------------------- */ 8993 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos (0UL) /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr (Bit 0) */ 8994 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Msk (0xffffUL) /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr (Bitfield-Mask: 0xffff) */ 8995 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos (16UL) /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep (Bit 16) */ 8996 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk (0xffff0000UL) /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep (Bitfield-Mask: 0xffff) */ 8997 8998 /* -------------------------------- USB_GNPTXSTS -------------------------------- */ 8999 #define USB_GNPTXSTS_NPTxFSpcAvail_Pos (0UL) /*!< USB GNPTXSTS: NPTxFSpcAvail (Bit 0) */ 9000 #define USB_GNPTXSTS_NPTxFSpcAvail_Msk (0xffffUL) /*!< USB GNPTXSTS: NPTxFSpcAvail (Bitfield-Mask: 0xffff) */ 9001 #define USB_GNPTXSTS_NPTxQSpcAvail_Pos (16UL) /*!< USB GNPTXSTS: NPTxQSpcAvail (Bit 16) */ 9002 #define USB_GNPTXSTS_NPTxQSpcAvail_Msk (0xff0000UL) /*!< USB GNPTXSTS: NPTxQSpcAvail (Bitfield-Mask: 0xff) */ 9003 #define USB_GNPTXSTS_NPTxQTop_Pos (24UL) /*!< USB GNPTXSTS: NPTxQTop (Bit 24) */ 9004 #define USB_GNPTXSTS_NPTxQTop_Msk (0x7f000000UL) /*!< USB GNPTXSTS: NPTxQTop (Bitfield-Mask: 0x7f) */ 9005 9006 /* ---------------------------------- USB_GUID ---------------------------------- */ 9007 #define USB_GUID_MOD_REV_Pos (0UL) /*!< USB GUID: MOD_REV (Bit 0) */ 9008 #define USB_GUID_MOD_REV_Msk (0xffUL) /*!< USB GUID: MOD_REV (Bitfield-Mask: 0xff) */ 9009 #define USB_GUID_MOD_TYPE_Pos (8UL) /*!< USB GUID: MOD_TYPE (Bit 8) */ 9010 #define USB_GUID_MOD_TYPE_Msk (0xff00UL) /*!< USB GUID: MOD_TYPE (Bitfield-Mask: 0xff) */ 9011 #define USB_GUID_MOD_NUMBER_Pos (16UL) /*!< USB GUID: MOD_NUMBER (Bit 16) */ 9012 #define USB_GUID_MOD_NUMBER_Msk (0xffff0000UL) /*!< USB GUID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 9013 9014 /* -------------------------------- USB_GDFIFOCFG ------------------------------- */ 9015 #define USB_GDFIFOCFG_GDFIFOCfg_Pos (0UL) /*!< USB GDFIFOCFG: GDFIFOCfg (Bit 0) */ 9016 #define USB_GDFIFOCFG_GDFIFOCfg_Msk (0xffffUL) /*!< USB GDFIFOCFG: GDFIFOCfg (Bitfield-Mask: 0xffff) */ 9017 #define USB_GDFIFOCFG_EPInfoBaseAddr_Pos (16UL) /*!< USB GDFIFOCFG: EPInfoBaseAddr (Bit 16) */ 9018 #define USB_GDFIFOCFG_EPInfoBaseAddr_Msk (0xffff0000UL) /*!< USB GDFIFOCFG: EPInfoBaseAddr (Bitfield-Mask: 0xffff) */ 9019 9020 /* -------------------------------- USB_HPTXFSIZ -------------------------------- */ 9021 #define USB_HPTXFSIZ_PTxFStAddr_Pos (0UL) /*!< USB HPTXFSIZ: PTxFStAddr (Bit 0) */ 9022 #define USB_HPTXFSIZ_PTxFStAddr_Msk (0xffffUL) /*!< USB HPTXFSIZ: PTxFStAddr (Bitfield-Mask: 0xffff) */ 9023 #define USB_HPTXFSIZ_PTxFSize_Pos (16UL) /*!< USB HPTXFSIZ: PTxFSize (Bit 16) */ 9024 #define USB_HPTXFSIZ_PTxFSize_Msk (0xffff0000UL) /*!< USB HPTXFSIZ: PTxFSize (Bitfield-Mask: 0xffff) */ 9025 9026 /* -------------------------------- USB_DIEPTXF1 -------------------------------- */ 9027 #define USB_DIEPTXF1_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF1: INEPnTxFStAddr (Bit 0) */ 9028 #define USB_DIEPTXF1_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF1: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ 9029 #define USB_DIEPTXF1_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF1: INEPnTxFDep (Bit 16) */ 9030 #define USB_DIEPTXF1_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF1: INEPnTxFDep (Bitfield-Mask: 0xffff) */ 9031 9032 /* -------------------------------- USB_DIEPTXF2 -------------------------------- */ 9033 #define USB_DIEPTXF2_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF2: INEPnTxFStAddr (Bit 0) */ 9034 #define USB_DIEPTXF2_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF2: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ 9035 #define USB_DIEPTXF2_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF2: INEPnTxFDep (Bit 16) */ 9036 #define USB_DIEPTXF2_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF2: INEPnTxFDep (Bitfield-Mask: 0xffff) */ 9037 9038 /* -------------------------------- USB_DIEPTXF3 -------------------------------- */ 9039 #define USB_DIEPTXF3_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF3: INEPnTxFStAddr (Bit 0) */ 9040 #define USB_DIEPTXF3_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF3: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ 9041 #define USB_DIEPTXF3_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF3: INEPnTxFDep (Bit 16) */ 9042 #define USB_DIEPTXF3_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF3: INEPnTxFDep (Bitfield-Mask: 0xffff) */ 9043 9044 /* -------------------------------- USB_DIEPTXF4 -------------------------------- */ 9045 #define USB_DIEPTXF4_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF4: INEPnTxFStAddr (Bit 0) */ 9046 #define USB_DIEPTXF4_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF4: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ 9047 #define USB_DIEPTXF4_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF4: INEPnTxFDep (Bit 16) */ 9048 #define USB_DIEPTXF4_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF4: INEPnTxFDep (Bitfield-Mask: 0xffff) */ 9049 9050 /* -------------------------------- USB_DIEPTXF5 -------------------------------- */ 9051 #define USB_DIEPTXF5_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF5: INEPnTxFStAddr (Bit 0) */ 9052 #define USB_DIEPTXF5_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF5: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ 9053 #define USB_DIEPTXF5_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF5: INEPnTxFDep (Bit 16) */ 9054 #define USB_DIEPTXF5_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF5: INEPnTxFDep (Bitfield-Mask: 0xffff) */ 9055 9056 /* -------------------------------- USB_DIEPTXF6 -------------------------------- */ 9057 #define USB_DIEPTXF6_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF6: INEPnTxFStAddr (Bit 0) */ 9058 #define USB_DIEPTXF6_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF6: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ 9059 #define USB_DIEPTXF6_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF6: INEPnTxFDep (Bit 16) */ 9060 #define USB_DIEPTXF6_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF6: INEPnTxFDep (Bitfield-Mask: 0xffff) */ 9061 9062 /* ---------------------------------- USB_HCFG ---------------------------------- */ 9063 #define USB_HCFG_FSLSPclkSel_Pos (0UL) /*!< USB HCFG: FSLSPclkSel (Bit 0) */ 9064 #define USB_HCFG_FSLSPclkSel_Msk (0x3UL) /*!< USB HCFG: FSLSPclkSel (Bitfield-Mask: 0x03) */ 9065 #define USB_HCFG_FSLSSupp_Pos (2UL) /*!< USB HCFG: FSLSSupp (Bit 2) */ 9066 #define USB_HCFG_FSLSSupp_Msk (0x4UL) /*!< USB HCFG: FSLSSupp (Bitfield-Mask: 0x01) */ 9067 #define USB_HCFG_DescDMA_Pos (23UL) /*!< USB HCFG: DescDMA (Bit 23) */ 9068 #define USB_HCFG_DescDMA_Msk (0x800000UL) /*!< USB HCFG: DescDMA (Bitfield-Mask: 0x01) */ 9069 #define USB_HCFG_FrListEn_Pos (24UL) /*!< USB HCFG: FrListEn (Bit 24) */ 9070 #define USB_HCFG_FrListEn_Msk (0x3000000UL) /*!< USB HCFG: FrListEn (Bitfield-Mask: 0x03) */ 9071 #define USB_HCFG_PerSchedEna_Pos (26UL) /*!< USB HCFG: PerSchedEna (Bit 26) */ 9072 #define USB_HCFG_PerSchedEna_Msk (0x4000000UL) /*!< USB HCFG: PerSchedEna (Bitfield-Mask: 0x01) */ 9073 9074 /* ---------------------------------- USB_HFIR ---------------------------------- */ 9075 #define USB_HFIR_FrInt_Pos (0UL) /*!< USB HFIR: FrInt (Bit 0) */ 9076 #define USB_HFIR_FrInt_Msk (0xffffUL) /*!< USB HFIR: FrInt (Bitfield-Mask: 0xffff) */ 9077 #define USB_HFIR_HFIRRldCtrl_Pos (16UL) /*!< USB HFIR: HFIRRldCtrl (Bit 16) */ 9078 #define USB_HFIR_HFIRRldCtrl_Msk (0x10000UL) /*!< USB HFIR: HFIRRldCtrl (Bitfield-Mask: 0x01) */ 9079 9080 /* ---------------------------------- USB_HFNUM --------------------------------- */ 9081 #define USB_HFNUM_FrNum_Pos (0UL) /*!< USB HFNUM: FrNum (Bit 0) */ 9082 #define USB_HFNUM_FrNum_Msk (0xffffUL) /*!< USB HFNUM: FrNum (Bitfield-Mask: 0xffff) */ 9083 #define USB_HFNUM_FrRem_Pos (16UL) /*!< USB HFNUM: FrRem (Bit 16) */ 9084 #define USB_HFNUM_FrRem_Msk (0xffff0000UL) /*!< USB HFNUM: FrRem (Bitfield-Mask: 0xffff) */ 9085 9086 /* --------------------------------- USB_HPTXSTS -------------------------------- */ 9087 #define USB_HPTXSTS_PTxFSpcAvail_Pos (0UL) /*!< USB HPTXSTS: PTxFSpcAvail (Bit 0) */ 9088 #define USB_HPTXSTS_PTxFSpcAvail_Msk (0xffffUL) /*!< USB HPTXSTS: PTxFSpcAvail (Bitfield-Mask: 0xffff) */ 9089 #define USB_HPTXSTS_PTxQSpcAvail_Pos (16UL) /*!< USB HPTXSTS: PTxQSpcAvail (Bit 16) */ 9090 #define USB_HPTXSTS_PTxQSpcAvail_Msk (0xff0000UL) /*!< USB HPTXSTS: PTxQSpcAvail (Bitfield-Mask: 0xff) */ 9091 #define USB_HPTXSTS_PTxQTop_Pos (24UL) /*!< USB HPTXSTS: PTxQTop (Bit 24) */ 9092 #define USB_HPTXSTS_PTxQTop_Msk (0xff000000UL) /*!< USB HPTXSTS: PTxQTop (Bitfield-Mask: 0xff) */ 9093 9094 /* ---------------------------------- USB_HAINT --------------------------------- */ 9095 #define USB_HAINT_HAINT_Pos (0UL) /*!< USB HAINT: HAINT (Bit 0) */ 9096 #define USB_HAINT_HAINT_Msk (0x3fffUL) /*!< USB HAINT: HAINT (Bitfield-Mask: 0x3fff) */ 9097 9098 /* -------------------------------- USB_HAINTMSK -------------------------------- */ 9099 #define USB_HAINTMSK_HAINTMsk_Pos (0UL) /*!< USB HAINTMSK: HAINTMsk (Bit 0) */ 9100 #define USB_HAINTMSK_HAINTMsk_Msk (0x3fffUL) /*!< USB HAINTMSK: HAINTMsk (Bitfield-Mask: 0x3fff) */ 9101 9102 /* -------------------------------- USB_HFLBADDR -------------------------------- */ 9103 #define USB_HFLBADDR_Starting_Address_Pos (0UL) /*!< USB HFLBADDR: Starting_Address (Bit 0) */ 9104 #define USB_HFLBADDR_Starting_Address_Msk (0xffffffffUL) /*!< USB HFLBADDR: Starting_Address (Bitfield-Mask: 0xffffffff) */ 9105 9106 /* ---------------------------------- USB_HPRT ---------------------------------- */ 9107 #define USB_HPRT_PrtConnSts_Pos (0UL) /*!< USB HPRT: PrtConnSts (Bit 0) */ 9108 #define USB_HPRT_PrtConnSts_Msk (0x1UL) /*!< USB HPRT: PrtConnSts (Bitfield-Mask: 0x01) */ 9109 #define USB_HPRT_PrtConnDet_Pos (1UL) /*!< USB HPRT: PrtConnDet (Bit 1) */ 9110 #define USB_HPRT_PrtConnDet_Msk (0x2UL) /*!< USB HPRT: PrtConnDet (Bitfield-Mask: 0x01) */ 9111 #define USB_HPRT_PrtEna_Pos (2UL) /*!< USB HPRT: PrtEna (Bit 2) */ 9112 #define USB_HPRT_PrtEna_Msk (0x4UL) /*!< USB HPRT: PrtEna (Bitfield-Mask: 0x01) */ 9113 #define USB_HPRT_PrtEnChng_Pos (3UL) /*!< USB HPRT: PrtEnChng (Bit 3) */ 9114 #define USB_HPRT_PrtEnChng_Msk (0x8UL) /*!< USB HPRT: PrtEnChng (Bitfield-Mask: 0x01) */ 9115 #define USB_HPRT_PrtOvrCurrAct_Pos (4UL) /*!< USB HPRT: PrtOvrCurrAct (Bit 4) */ 9116 #define USB_HPRT_PrtOvrCurrAct_Msk (0x10UL) /*!< USB HPRT: PrtOvrCurrAct (Bitfield-Mask: 0x01) */ 9117 #define USB_HPRT_PrtOvrCurrChng_Pos (5UL) /*!< USB HPRT: PrtOvrCurrChng (Bit 5) */ 9118 #define USB_HPRT_PrtOvrCurrChng_Msk (0x20UL) /*!< USB HPRT: PrtOvrCurrChng (Bitfield-Mask: 0x01) */ 9119 #define USB_HPRT_PrtRes_Pos (6UL) /*!< USB HPRT: PrtRes (Bit 6) */ 9120 #define USB_HPRT_PrtRes_Msk (0x40UL) /*!< USB HPRT: PrtRes (Bitfield-Mask: 0x01) */ 9121 #define USB_HPRT_PrtSusp_Pos (7UL) /*!< USB HPRT: PrtSusp (Bit 7) */ 9122 #define USB_HPRT_PrtSusp_Msk (0x80UL) /*!< USB HPRT: PrtSusp (Bitfield-Mask: 0x01) */ 9123 #define USB_HPRT_PrtRst_Pos (8UL) /*!< USB HPRT: PrtRst (Bit 8) */ 9124 #define USB_HPRT_PrtRst_Msk (0x100UL) /*!< USB HPRT: PrtRst (Bitfield-Mask: 0x01) */ 9125 #define USB_HPRT_PrtLnSts_Pos (10UL) /*!< USB HPRT: PrtLnSts (Bit 10) */ 9126 #define USB_HPRT_PrtLnSts_Msk (0xc00UL) /*!< USB HPRT: PrtLnSts (Bitfield-Mask: 0x03) */ 9127 #define USB_HPRT_PrtPwr_Pos (12UL) /*!< USB HPRT: PrtPwr (Bit 12) */ 9128 #define USB_HPRT_PrtPwr_Msk (0x1000UL) /*!< USB HPRT: PrtPwr (Bitfield-Mask: 0x01) */ 9129 #define USB_HPRT_PrtSpd_Pos (17UL) /*!< USB HPRT: PrtSpd (Bit 17) */ 9130 #define USB_HPRT_PrtSpd_Msk (0x60000UL) /*!< USB HPRT: PrtSpd (Bitfield-Mask: 0x03) */ 9131 9132 /* ---------------------------------- USB_DCFG ---------------------------------- */ 9133 #define USB_DCFG_DevSpd_Pos (0UL) /*!< USB DCFG: DevSpd (Bit 0) */ 9134 #define USB_DCFG_DevSpd_Msk (0x3UL) /*!< USB DCFG: DevSpd (Bitfield-Mask: 0x03) */ 9135 #define USB_DCFG_NZStsOUTHShk_Pos (2UL) /*!< USB DCFG: NZStsOUTHShk (Bit 2) */ 9136 #define USB_DCFG_NZStsOUTHShk_Msk (0x4UL) /*!< USB DCFG: NZStsOUTHShk (Bitfield-Mask: 0x01) */ 9137 #define USB_DCFG_DevAddr_Pos (4UL) /*!< USB DCFG: DevAddr (Bit 4) */ 9138 #define USB_DCFG_DevAddr_Msk (0x7f0UL) /*!< USB DCFG: DevAddr (Bitfield-Mask: 0x7f) */ 9139 #define USB_DCFG_PerFrInt_Pos (11UL) /*!< USB DCFG: PerFrInt (Bit 11) */ 9140 #define USB_DCFG_PerFrInt_Msk (0x1800UL) /*!< USB DCFG: PerFrInt (Bitfield-Mask: 0x03) */ 9141 #define USB_DCFG_DescDMA_Pos (23UL) /*!< USB DCFG: DescDMA (Bit 23) */ 9142 #define USB_DCFG_DescDMA_Msk (0x800000UL) /*!< USB DCFG: DescDMA (Bitfield-Mask: 0x01) */ 9143 #define USB_DCFG_PerSchIntvl_Pos (24UL) /*!< USB DCFG: PerSchIntvl (Bit 24) */ 9144 #define USB_DCFG_PerSchIntvl_Msk (0x3000000UL) /*!< USB DCFG: PerSchIntvl (Bitfield-Mask: 0x03) */ 9145 9146 /* ---------------------------------- USB_DCTL ---------------------------------- */ 9147 #define USB_DCTL_RmtWkUpSig_Pos (0UL) /*!< USB DCTL: RmtWkUpSig (Bit 0) */ 9148 #define USB_DCTL_RmtWkUpSig_Msk (0x1UL) /*!< USB DCTL: RmtWkUpSig (Bitfield-Mask: 0x01) */ 9149 #define USB_DCTL_SftDiscon_Pos (1UL) /*!< USB DCTL: SftDiscon (Bit 1) */ 9150 #define USB_DCTL_SftDiscon_Msk (0x2UL) /*!< USB DCTL: SftDiscon (Bitfield-Mask: 0x01) */ 9151 #define USB_DCTL_GNPINNakSts_Pos (2UL) /*!< USB DCTL: GNPINNakSts (Bit 2) */ 9152 #define USB_DCTL_GNPINNakSts_Msk (0x4UL) /*!< USB DCTL: GNPINNakSts (Bitfield-Mask: 0x01) */ 9153 #define USB_DCTL_GOUTNakSts_Pos (3UL) /*!< USB DCTL: GOUTNakSts (Bit 3) */ 9154 #define USB_DCTL_GOUTNakSts_Msk (0x8UL) /*!< USB DCTL: GOUTNakSts (Bitfield-Mask: 0x01) */ 9155 #define USB_DCTL_SGNPInNak_Pos (7UL) /*!< USB DCTL: SGNPInNak (Bit 7) */ 9156 #define USB_DCTL_SGNPInNak_Msk (0x80UL) /*!< USB DCTL: SGNPInNak (Bitfield-Mask: 0x01) */ 9157 #define USB_DCTL_CGNPInNak_Pos (8UL) /*!< USB DCTL: CGNPInNak (Bit 8) */ 9158 #define USB_DCTL_CGNPInNak_Msk (0x100UL) /*!< USB DCTL: CGNPInNak (Bitfield-Mask: 0x01) */ 9159 #define USB_DCTL_SGOUTNak_Pos (9UL) /*!< USB DCTL: SGOUTNak (Bit 9) */ 9160 #define USB_DCTL_SGOUTNak_Msk (0x200UL) /*!< USB DCTL: SGOUTNak (Bitfield-Mask: 0x01) */ 9161 #define USB_DCTL_CGOUTNak_Pos (10UL) /*!< USB DCTL: CGOUTNak (Bit 10) */ 9162 #define USB_DCTL_CGOUTNak_Msk (0x400UL) /*!< USB DCTL: CGOUTNak (Bitfield-Mask: 0x01) */ 9163 #define USB_DCTL_GMC_Pos (13UL) /*!< USB DCTL: GMC (Bit 13) */ 9164 #define USB_DCTL_GMC_Msk (0x6000UL) /*!< USB DCTL: GMC (Bitfield-Mask: 0x03) */ 9165 #define USB_DCTL_IgnrFrmNum_Pos (15UL) /*!< USB DCTL: IgnrFrmNum (Bit 15) */ 9166 #define USB_DCTL_IgnrFrmNum_Msk (0x8000UL) /*!< USB DCTL: IgnrFrmNum (Bitfield-Mask: 0x01) */ 9167 #define USB_DCTL_NakOnBble_Pos (16UL) /*!< USB DCTL: NakOnBble (Bit 16) */ 9168 #define USB_DCTL_NakOnBble_Msk (0x10000UL) /*!< USB DCTL: NakOnBble (Bitfield-Mask: 0x01) */ 9169 9170 /* ---------------------------------- USB_DSTS ---------------------------------- */ 9171 #define USB_DSTS_SuspSts_Pos (0UL) /*!< USB DSTS: SuspSts (Bit 0) */ 9172 #define USB_DSTS_SuspSts_Msk (0x1UL) /*!< USB DSTS: SuspSts (Bitfield-Mask: 0x01) */ 9173 #define USB_DSTS_EnumSpd_Pos (1UL) /*!< USB DSTS: EnumSpd (Bit 1) */ 9174 #define USB_DSTS_EnumSpd_Msk (0x6UL) /*!< USB DSTS: EnumSpd (Bitfield-Mask: 0x03) */ 9175 #define USB_DSTS_ErrticErr_Pos (3UL) /*!< USB DSTS: ErrticErr (Bit 3) */ 9176 #define USB_DSTS_ErrticErr_Msk (0x8UL) /*!< USB DSTS: ErrticErr (Bitfield-Mask: 0x01) */ 9177 #define USB_DSTS_SOFFN_Pos (8UL) /*!< USB DSTS: SOFFN (Bit 8) */ 9178 #define USB_DSTS_SOFFN_Msk (0x3fff00UL) /*!< USB DSTS: SOFFN (Bitfield-Mask: 0x3fff) */ 9179 9180 /* --------------------------------- USB_DIEPMSK -------------------------------- */ 9181 #define USB_DIEPMSK_XferComplMsk_Pos (0UL) /*!< USB DIEPMSK: XferComplMsk (Bit 0) */ 9182 #define USB_DIEPMSK_XferComplMsk_Msk (0x1UL) /*!< USB DIEPMSK: XferComplMsk (Bitfield-Mask: 0x01) */ 9183 #define USB_DIEPMSK_EPDisbldMsk_Pos (1UL) /*!< USB DIEPMSK: EPDisbldMsk (Bit 1) */ 9184 #define USB_DIEPMSK_EPDisbldMsk_Msk (0x2UL) /*!< USB DIEPMSK: EPDisbldMsk (Bitfield-Mask: 0x01) */ 9185 #define USB_DIEPMSK_AHBErrMsk_Pos (2UL) /*!< USB DIEPMSK: AHBErrMsk (Bit 2) */ 9186 #define USB_DIEPMSK_AHBErrMsk_Msk (0x4UL) /*!< USB DIEPMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ 9187 #define USB_DIEPMSK_TimeOUTMsk_Pos (3UL) /*!< USB DIEPMSK: TimeOUTMsk (Bit 3) */ 9188 #define USB_DIEPMSK_TimeOUTMsk_Msk (0x8UL) /*!< USB DIEPMSK: TimeOUTMsk (Bitfield-Mask: 0x01) */ 9189 #define USB_DIEPMSK_INTknTXFEmpMsk_Pos (4UL) /*!< USB DIEPMSK: INTknTXFEmpMsk (Bit 4) */ 9190 #define USB_DIEPMSK_INTknTXFEmpMsk_Msk (0x10UL) /*!< USB DIEPMSK: INTknTXFEmpMsk (Bitfield-Mask: 0x01) */ 9191 #define USB_DIEPMSK_INEPNakEffMsk_Pos (6UL) /*!< USB DIEPMSK: INEPNakEffMsk (Bit 6) */ 9192 #define USB_DIEPMSK_INEPNakEffMsk_Msk (0x40UL) /*!< USB DIEPMSK: INEPNakEffMsk (Bitfield-Mask: 0x01) */ 9193 #define USB_DIEPMSK_TxfifoUndrnMsk_Pos (8UL) /*!< USB DIEPMSK: TxfifoUndrnMsk (Bit 8) */ 9194 #define USB_DIEPMSK_TxfifoUndrnMsk_Msk (0x100UL) /*!< USB DIEPMSK: TxfifoUndrnMsk (Bitfield-Mask: 0x01) */ 9195 #define USB_DIEPMSK_BNAInIntrMsk_Pos (9UL) /*!< USB DIEPMSK: BNAInIntrMsk (Bit 9) */ 9196 #define USB_DIEPMSK_BNAInIntrMsk_Msk (0x200UL) /*!< USB DIEPMSK: BNAInIntrMsk (Bitfield-Mask: 0x01) */ 9197 #define USB_DIEPMSK_NAKMsk_Pos (13UL) /*!< USB DIEPMSK: NAKMsk (Bit 13) */ 9198 #define USB_DIEPMSK_NAKMsk_Msk (0x2000UL) /*!< USB DIEPMSK: NAKMsk (Bitfield-Mask: 0x01) */ 9199 9200 /* --------------------------------- USB_DOEPMSK -------------------------------- */ 9201 #define USB_DOEPMSK_XferComplMsk_Pos (0UL) /*!< USB DOEPMSK: XferComplMsk (Bit 0) */ 9202 #define USB_DOEPMSK_XferComplMsk_Msk (0x1UL) /*!< USB DOEPMSK: XferComplMsk (Bitfield-Mask: 0x01) */ 9203 #define USB_DOEPMSK_EPDisbldMsk_Pos (1UL) /*!< USB DOEPMSK: EPDisbldMsk (Bit 1) */ 9204 #define USB_DOEPMSK_EPDisbldMsk_Msk (0x2UL) /*!< USB DOEPMSK: EPDisbldMsk (Bitfield-Mask: 0x01) */ 9205 #define USB_DOEPMSK_AHBErrMsk_Pos (2UL) /*!< USB DOEPMSK: AHBErrMsk (Bit 2) */ 9206 #define USB_DOEPMSK_AHBErrMsk_Msk (0x4UL) /*!< USB DOEPMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ 9207 #define USB_DOEPMSK_SetUPMsk_Pos (3UL) /*!< USB DOEPMSK: SetUPMsk (Bit 3) */ 9208 #define USB_DOEPMSK_SetUPMsk_Msk (0x8UL) /*!< USB DOEPMSK: SetUPMsk (Bitfield-Mask: 0x01) */ 9209 #define USB_DOEPMSK_OUTTknEPdisMsk_Pos (4UL) /*!< USB DOEPMSK: OUTTknEPdisMsk (Bit 4) */ 9210 #define USB_DOEPMSK_OUTTknEPdisMsk_Msk (0x10UL) /*!< USB DOEPMSK: OUTTknEPdisMsk (Bitfield-Mask: 0x01) */ 9211 #define USB_DOEPMSK_Back2BackSETup_Pos (6UL) /*!< USB DOEPMSK: Back2BackSETup (Bit 6) */ 9212 #define USB_DOEPMSK_Back2BackSETup_Msk (0x40UL) /*!< USB DOEPMSK: Back2BackSETup (Bitfield-Mask: 0x01) */ 9213 #define USB_DOEPMSK_OutPktErrMsk_Pos (8UL) /*!< USB DOEPMSK: OutPktErrMsk (Bit 8) */ 9214 #define USB_DOEPMSK_OutPktErrMsk_Msk (0x100UL) /*!< USB DOEPMSK: OutPktErrMsk (Bitfield-Mask: 0x01) */ 9215 #define USB_DOEPMSK_BnaOutIntrMsk_Pos (9UL) /*!< USB DOEPMSK: BnaOutIntrMsk (Bit 9) */ 9216 #define USB_DOEPMSK_BnaOutIntrMsk_Msk (0x200UL) /*!< USB DOEPMSK: BnaOutIntrMsk (Bitfield-Mask: 0x01) */ 9217 #define USB_DOEPMSK_BbleErrMsk_Pos (12UL) /*!< USB DOEPMSK: BbleErrMsk (Bit 12) */ 9218 #define USB_DOEPMSK_BbleErrMsk_Msk (0x1000UL) /*!< USB DOEPMSK: BbleErrMsk (Bitfield-Mask: 0x01) */ 9219 #define USB_DOEPMSK_NAKMsk_Pos (13UL) /*!< USB DOEPMSK: NAKMsk (Bit 13) */ 9220 #define USB_DOEPMSK_NAKMsk_Msk (0x2000UL) /*!< USB DOEPMSK: NAKMsk (Bitfield-Mask: 0x01) */ 9221 #define USB_DOEPMSK_NYETMsk_Pos (14UL) /*!< USB DOEPMSK: NYETMsk (Bit 14) */ 9222 #define USB_DOEPMSK_NYETMsk_Msk (0x4000UL) /*!< USB DOEPMSK: NYETMsk (Bitfield-Mask: 0x01) */ 9223 9224 /* ---------------------------------- USB_DAINT --------------------------------- */ 9225 #define USB_DAINT_InEpInt_Pos (0UL) /*!< USB DAINT: InEpInt (Bit 0) */ 9226 #define USB_DAINT_InEpInt_Msk (0xffffUL) /*!< USB DAINT: InEpInt (Bitfield-Mask: 0xffff) */ 9227 #define USB_DAINT_OutEPInt_Pos (16UL) /*!< USB DAINT: OutEPInt (Bit 16) */ 9228 #define USB_DAINT_OutEPInt_Msk (0xffff0000UL) /*!< USB DAINT: OutEPInt (Bitfield-Mask: 0xffff) */ 9229 9230 /* -------------------------------- USB_DAINTMSK -------------------------------- */ 9231 #define USB_DAINTMSK_InEpMsk_Pos (0UL) /*!< USB DAINTMSK: InEpMsk (Bit 0) */ 9232 #define USB_DAINTMSK_InEpMsk_Msk (0xffffUL) /*!< USB DAINTMSK: InEpMsk (Bitfield-Mask: 0xffff) */ 9233 #define USB_DAINTMSK_OutEpMsk_Pos (16UL) /*!< USB DAINTMSK: OutEpMsk (Bit 16) */ 9234 #define USB_DAINTMSK_OutEpMsk_Msk (0xffff0000UL) /*!< USB DAINTMSK: OutEpMsk (Bitfield-Mask: 0xffff) */ 9235 9236 /* -------------------------------- USB_DVBUSDIS -------------------------------- */ 9237 #define USB_DVBUSDIS_DVBUSDis_Pos (0UL) /*!< USB DVBUSDIS: DVBUSDis (Bit 0) */ 9238 #define USB_DVBUSDIS_DVBUSDis_Msk (0xffffUL) /*!< USB DVBUSDIS: DVBUSDis (Bitfield-Mask: 0xffff) */ 9239 9240 /* ------------------------------- USB_DVBUSPULSE ------------------------------- */ 9241 #define USB_DVBUSPULSE_DVBUSPulse_Pos (0UL) /*!< USB DVBUSPULSE: DVBUSPulse (Bit 0) */ 9242 #define USB_DVBUSPULSE_DVBUSPulse_Msk (0xfffUL) /*!< USB DVBUSPULSE: DVBUSPulse (Bitfield-Mask: 0xfff) */ 9243 9244 /* ------------------------------- USB_DIEPEMPMSK ------------------------------- */ 9245 #define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos (0UL) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk (Bit 0) */ 9246 #define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk (0xffffUL) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk (Bitfield-Mask: 0xffff) */ 9247 9248 /* --------------------------------- USB_PCGCCTL -------------------------------- */ 9249 #define USB_PCGCCTL_StopPclk_Pos (0UL) /*!< USB PCGCCTL: StopPclk (Bit 0) */ 9250 #define USB_PCGCCTL_StopPclk_Msk (0x1UL) /*!< USB PCGCCTL: StopPclk (Bitfield-Mask: 0x01) */ 9251 #define USB_PCGCCTL_GateHclk_Pos (1UL) /*!< USB PCGCCTL: GateHclk (Bit 1) */ 9252 #define USB_PCGCCTL_GateHclk_Msk (0x2UL) /*!< USB PCGCCTL: GateHclk (Bitfield-Mask: 0x01) */ 9253 9254 9255 /* ================================================================================ */ 9256 /* ================ struct 'USB0_EP0' Position & Mask ================ */ 9257 /* ================================================================================ */ 9258 9259 9260 /* ------------------------------ USB_EP_DIEPCTL0 ----------------------------- */ 9261 #define USB_EP_DIEPCTL0_MPS_Pos (0UL) /*!< USB0_EP0 DIEPCTL0: MPS (Bit 0) */ 9262 #define USB_EP_DIEPCTL0_MPS_Msk (0x3UL) /*!< USB0_EP0 DIEPCTL0: MPS (Bitfield-Mask: 0x03) */ 9263 #define USB_EP_DIEPCTL0_USBActEP_Pos (15UL) /*!< USB0_EP0 DIEPCTL0: USBActEP (Bit 15) */ 9264 #define USB_EP_DIEPCTL0_USBActEP_Msk (0x8000UL) /*!< USB0_EP0 DIEPCTL0: USBActEP (Bitfield-Mask: 0x01) */ 9265 #define USB_EP_DIEPCTL0_NAKSts_Pos (17UL) /*!< USB0_EP0 DIEPCTL0: NAKSts (Bit 17) */ 9266 #define USB_EP_DIEPCTL0_NAKSts_Msk (0x20000UL) /*!< USB0_EP0 DIEPCTL0: NAKSts (Bitfield-Mask: 0x01) */ 9267 #define USB_EP_DIEPCTL0_EPType_Pos (18UL) /*!< USB0_EP0 DIEPCTL0: EPType (Bit 18) */ 9268 #define USB_EP_DIEPCTL0_EPType_Msk (0xc0000UL) /*!< USB0_EP0 DIEPCTL0: EPType (Bitfield-Mask: 0x03) */ 9269 #define USB_EP_DIEPCTL0_Stall_Pos (21UL) /*!< USB0_EP0 DIEPCTL0: Stall (Bit 21) */ 9270 #define USB_EP_DIEPCTL0_Stall_Msk (0x200000UL) /*!< USB0_EP0 DIEPCTL0: Stall (Bitfield-Mask: 0x01) */ 9271 #define USB_EP_DIEPCTL0_TxFNum_Pos (22UL) /*!< USB0_EP0 DIEPCTL0: TxFNum (Bit 22) */ 9272 #define USB_EP_DIEPCTL0_TxFNum_Msk (0x3c00000UL) /*!< USB0_EP0 DIEPCTL0: TxFNum (Bitfield-Mask: 0x0f) */ 9273 #define USB_EP_DIEPCTL0_CNAK_Pos (26UL) /*!< USB0_EP0 DIEPCTL0: CNAK (Bit 26) */ 9274 #define USB_EP_DIEPCTL0_CNAK_Msk (0x4000000UL) /*!< USB0_EP0 DIEPCTL0: CNAK (Bitfield-Mask: 0x01) */ 9275 #define USB_EP_DIEPCTL0_SNAK_Pos (27UL) /*!< USB0_EP0 DIEPCTL0: SNAK (Bit 27) */ 9276 #define USB_EP_DIEPCTL0_SNAK_Msk (0x8000000UL) /*!< USB0_EP0 DIEPCTL0: SNAK (Bitfield-Mask: 0x01) */ 9277 #define USB_EP_DIEPCTL0_EPDis_Pos (30UL) /*!< USB0_EP0 DIEPCTL0: EPDis (Bit 30) */ 9278 #define USB_EP_DIEPCTL0_EPDis_Msk (0x40000000UL) /*!< USB0_EP0 DIEPCTL0: EPDis (Bitfield-Mask: 0x01) */ 9279 #define USB_EP_DIEPCTL0_EPEna_Pos (31UL) /*!< USB0_EP0 DIEPCTL0: EPEna (Bit 31) */ 9280 #define USB_EP_DIEPCTL0_EPEna_Msk (0x80000000UL) /*!< USB0_EP0 DIEPCTL0: EPEna (Bitfield-Mask: 0x01) */ 9281 9282 /* ------------------------------ USB_EP_DIEPINT0 ----------------------------- */ 9283 #define USB_EP_DIEPINT0_XferCompl_Pos (0UL) /*!< USB0_EP0 DIEPINT0: XferCompl (Bit 0) */ 9284 #define USB_EP_DIEPINT0_XferCompl_Msk (0x1UL) /*!< USB0_EP0 DIEPINT0: XferCompl (Bitfield-Mask: 0x01) */ 9285 #define USB_EP_DIEPINT0_EPDisbld_Pos (1UL) /*!< USB0_EP0 DIEPINT0: EPDisbld (Bit 1) */ 9286 #define USB_EP_DIEPINT0_EPDisbld_Msk (0x2UL) /*!< USB0_EP0 DIEPINT0: EPDisbld (Bitfield-Mask: 0x01) */ 9287 #define USB_EP_DIEPINT0_AHBErr_Pos (2UL) /*!< USB0_EP0 DIEPINT0: AHBErr (Bit 2) */ 9288 #define USB_EP_DIEPINT0_AHBErr_Msk (0x4UL) /*!< USB0_EP0 DIEPINT0: AHBErr (Bitfield-Mask: 0x01) */ 9289 #define USB_EP_DIEPINT0_TimeOUT_Pos (3UL) /*!< USB0_EP0 DIEPINT0: TimeOUT (Bit 3) */ 9290 #define USB_EP_DIEPINT0_TimeOUT_Msk (0x8UL) /*!< USB0_EP0 DIEPINT0: TimeOUT (Bitfield-Mask: 0x01) */ 9291 #define USB_EP_DIEPINT0_INTknTXFEmp_Pos (4UL) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp (Bit 4) */ 9292 #define USB_EP_DIEPINT0_INTknTXFEmp_Msk (0x10UL) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp (Bitfield-Mask: 0x01) */ 9293 #define USB_EP_DIEPINT0_INEPNakEff_Pos (6UL) /*!< USB0_EP0 DIEPINT0: INEPNakEff (Bit 6) */ 9294 #define USB_EP_DIEPINT0_INEPNakEff_Msk (0x40UL) /*!< USB0_EP0 DIEPINT0: INEPNakEff (Bitfield-Mask: 0x01) */ 9295 #define USB_EP_DIEPINT0_TxFEmp_Pos (7UL) /*!< USB0_EP0 DIEPINT0: TxFEmp (Bit 7) */ 9296 #define USB_EP_DIEPINT0_TxFEmp_Msk (0x80UL) /*!< USB0_EP0 DIEPINT0: TxFEmp (Bitfield-Mask: 0x01) */ 9297 #define USB_EP_DIEPINT0_BNAIntr_Pos (9UL) /*!< USB0_EP0 DIEPINT0: BNAIntr (Bit 9) */ 9298 #define USB_EP_DIEPINT0_BNAIntr_Msk (0x200UL) /*!< USB0_EP0 DIEPINT0: BNAIntr (Bitfield-Mask: 0x01) */ 9299 9300 /* ----------------------------- USB_EP_DIEPTSIZ0 ----------------------------- */ 9301 #define USB_EP_DIEPTSIZ0_XferSize_Pos (0UL) /*!< USB0_EP0 DIEPTSIZ0: XferSize (Bit 0) */ 9302 #define USB_EP_DIEPTSIZ0_XferSize_Msk (0x7fUL) /*!< USB0_EP0 DIEPTSIZ0: XferSize (Bitfield-Mask: 0x7f) */ 9303 #define USB_EP_DIEPTSIZ0_PktCnt_Pos (19UL) /*!< USB0_EP0 DIEPTSIZ0: PktCnt (Bit 19) */ 9304 #define USB_EP_DIEPTSIZ0_PktCnt_Msk (0x180000UL) /*!< USB0_EP0 DIEPTSIZ0: PktCnt (Bitfield-Mask: 0x03) */ 9305 9306 /* ------------------------------ USB_EP_DIEPDMA0 ----------------------------- */ 9307 #define USB_EP_DIEPDMA0_DMAAddr_Pos (0UL) /*!< USB0_EP0 DIEPDMA0: DMAAddr (Bit 0) */ 9308 #define USB_EP_DIEPDMA0_DMAAddr_Msk (0xffffffffUL) /*!< USB0_EP0 DIEPDMA0: DMAAddr (Bitfield-Mask: 0xffffffff) */ 9309 9310 /* ------------------------------ USB_EP_DTXFSTS0 ----------------------------- */ 9311 #define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos (0UL) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail (Bit 0) */ 9312 #define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0xffffUL) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail (Bitfield-Mask: 0xffff) */ 9313 9314 /* ----------------------------- USB_EP_DIEPDMAB0 ----------------------------- */ 9315 #define USB_EP_DIEPDMAB0_DMABufferAddr_Pos (0UL) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr (Bit 0) */ 9316 #define USB_EP_DIEPDMAB0_DMABufferAddr_Msk (0xffffffffUL) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ 9317 9318 /* ------------------------------ USB_EP_DOEPCTL0 ----------------------------- */ 9319 #define USB_EP_DOEPCTL0_MPS_Pos (0UL) /*!< USB0_EP0 DOEPCTL0: MPS (Bit 0) */ 9320 #define USB_EP_DOEPCTL0_MPS_Msk (0x3UL) /*!< USB0_EP0 DOEPCTL0: MPS (Bitfield-Mask: 0x03) */ 9321 #define USB_EP_DOEPCTL0_USBActEP_Pos (15UL) /*!< USB0_EP0 DOEPCTL0: USBActEP (Bit 15) */ 9322 #define USB_EP_DOEPCTL0_USBActEP_Msk (0x8000UL) /*!< USB0_EP0 DOEPCTL0: USBActEP (Bitfield-Mask: 0x01) */ 9323 #define USB_EP_DOEPCTL0_NAKSts_Pos (17UL) /*!< USB0_EP0 DOEPCTL0: NAKSts (Bit 17) */ 9324 #define USB_EP_DOEPCTL0_NAKSts_Msk (0x20000UL) /*!< USB0_EP0 DOEPCTL0: NAKSts (Bitfield-Mask: 0x01) */ 9325 #define USB_EP_DOEPCTL0_EPType_Pos (18UL) /*!< USB0_EP0 DOEPCTL0: EPType (Bit 18) */ 9326 #define USB_EP_DOEPCTL0_EPType_Msk (0xc0000UL) /*!< USB0_EP0 DOEPCTL0: EPType (Bitfield-Mask: 0x03) */ 9327 #define USB_EP_DOEPCTL0_Snp_Pos (20UL) /*!< USB0_EP0 DOEPCTL0: Snp (Bit 20) */ 9328 #define USB_EP_DOEPCTL0_Snp_Msk (0x100000UL) /*!< USB0_EP0 DOEPCTL0: Snp (Bitfield-Mask: 0x01) */ 9329 #define USB_EP_DOEPCTL0_Stall_Pos (21UL) /*!< USB0_EP0 DOEPCTL0: Stall (Bit 21) */ 9330 #define USB_EP_DOEPCTL0_Stall_Msk (0x200000UL) /*!< USB0_EP0 DOEPCTL0: Stall (Bitfield-Mask: 0x01) */ 9331 #define USB_EP_DOEPCTL0_CNAK_Pos (26UL) /*!< USB0_EP0 DOEPCTL0: CNAK (Bit 26) */ 9332 #define USB_EP_DOEPCTL0_CNAK_Msk (0x4000000UL) /*!< USB0_EP0 DOEPCTL0: CNAK (Bitfield-Mask: 0x01) */ 9333 #define USB_EP_DOEPCTL0_SNAK_Pos (27UL) /*!< USB0_EP0 DOEPCTL0: SNAK (Bit 27) */ 9334 #define USB_EP_DOEPCTL0_SNAK_Msk (0x8000000UL) /*!< USB0_EP0 DOEPCTL0: SNAK (Bitfield-Mask: 0x01) */ 9335 #define USB_EP_DOEPCTL0_EPDis_Pos (30UL) /*!< USB0_EP0 DOEPCTL0: EPDis (Bit 30) */ 9336 #define USB_EP_DOEPCTL0_EPDis_Msk (0x40000000UL) /*!< USB0_EP0 DOEPCTL0: EPDis (Bitfield-Mask: 0x01) */ 9337 #define USB_EP_DOEPCTL0_EPEna_Pos (31UL) /*!< USB0_EP0 DOEPCTL0: EPEna (Bit 31) */ 9338 #define USB_EP_DOEPCTL0_EPEna_Msk (0x80000000UL) /*!< USB0_EP0 DOEPCTL0: EPEna (Bitfield-Mask: 0x01) */ 9339 9340 /* ------------------------------ USB_EP_DOEPINT0 ----------------------------- */ 9341 #define USB_EP_DOEPINT0_XferCompl_Pos (0UL) /*!< USB0_EP0 DOEPINT0: XferCompl (Bit 0) */ 9342 #define USB_EP_DOEPINT0_XferCompl_Msk (0x1UL) /*!< USB0_EP0 DOEPINT0: XferCompl (Bitfield-Mask: 0x01) */ 9343 #define USB_EP_DOEPINT0_EPDisbld_Pos (1UL) /*!< USB0_EP0 DOEPINT0: EPDisbld (Bit 1) */ 9344 #define USB_EP_DOEPINT0_EPDisbld_Msk (0x2UL) /*!< USB0_EP0 DOEPINT0: EPDisbld (Bitfield-Mask: 0x01) */ 9345 #define USB_EP_DOEPINT0_AHBErr_Pos (2UL) /*!< USB0_EP0 DOEPINT0: AHBErr (Bit 2) */ 9346 #define USB_EP_DOEPINT0_AHBErr_Msk (0x4UL) /*!< USB0_EP0 DOEPINT0: AHBErr (Bitfield-Mask: 0x01) */ 9347 #define USB_EP_DOEPINT0_SetUp_Pos (3UL) /*!< USB0_EP0 DOEPINT0: SetUp (Bit 3) */ 9348 #define USB_EP_DOEPINT0_SetUp_Msk (0x8UL) /*!< USB0_EP0 DOEPINT0: SetUp (Bitfield-Mask: 0x01) */ 9349 #define USB_EP_DOEPINT0_OUTTknEPdis_Pos (4UL) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis (Bit 4) */ 9350 #define USB_EP_DOEPINT0_OUTTknEPdis_Msk (0x10UL) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis (Bitfield-Mask: 0x01) */ 9351 #define USB_EP_DOEPINT0_StsPhseRcvd_Pos (5UL) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd (Bit 5) */ 9352 #define USB_EP_DOEPINT0_StsPhseRcvd_Msk (0x20UL) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd (Bitfield-Mask: 0x01) */ 9353 #define USB_EP_DOEPINT0_Back2BackSETup_Pos (6UL) /*!< USB0_EP0 DOEPINT0: Back2BackSETup (Bit 6) */ 9354 #define USB_EP_DOEPINT0_Back2BackSETup_Msk (0x40UL) /*!< USB0_EP0 DOEPINT0: Back2BackSETup (Bitfield-Mask: 0x01) */ 9355 #define USB_EP_DOEPINT0_BNAIntr_Pos (9UL) /*!< USB0_EP0 DOEPINT0: BNAIntr (Bit 9) */ 9356 #define USB_EP_DOEPINT0_BNAIntr_Msk (0x200UL) /*!< USB0_EP0 DOEPINT0: BNAIntr (Bitfield-Mask: 0x01) */ 9357 #define USB_EP_DOEPINT0_PktDrpSts_Pos (11UL) /*!< USB0_EP0 DOEPINT0: PktDrpSts (Bit 11) */ 9358 #define USB_EP_DOEPINT0_PktDrpSts_Msk (0x800UL) /*!< USB0_EP0 DOEPINT0: PktDrpSts (Bitfield-Mask: 0x01) */ 9359 #define USB_EP_DOEPINT0_BbleErrIntrpt_Pos (12UL) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt (Bit 12) */ 9360 #define USB_EP_DOEPINT0_BbleErrIntrpt_Msk (0x1000UL) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt (Bitfield-Mask: 0x01) */ 9361 #define USB_EP_DOEPINT0_NAKIntrpt_Pos (13UL) /*!< USB0_EP0 DOEPINT0: NAKIntrpt (Bit 13) */ 9362 #define USB_EP_DOEPINT0_NAKIntrpt_Msk (0x2000UL) /*!< USB0_EP0 DOEPINT0: NAKIntrpt (Bitfield-Mask: 0x01) */ 9363 #define USB_EP_DOEPINT0_NYETIntrpt_Pos (14UL) /*!< USB0_EP0 DOEPINT0: NYETIntrpt (Bit 14) */ 9364 #define USB_EP_DOEPINT0_NYETIntrpt_Msk (0x4000UL) /*!< USB0_EP0 DOEPINT0: NYETIntrpt (Bitfield-Mask: 0x01) */ 9365 9366 /* ----------------------------- USB_EP_DOEPTSIZ0 ----------------------------- */ 9367 #define USB_EP_DOEPTSIZ0_XferSize_Pos (0UL) /*!< USB0_EP0 DOEPTSIZ0: XferSize (Bit 0) */ 9368 #define USB_EP_DOEPTSIZ0_XferSize_Msk (0x7fUL) /*!< USB0_EP0 DOEPTSIZ0: XferSize (Bitfield-Mask: 0x7f) */ 9369 #define USB_EP_DOEPTSIZ0_PktCnt_Pos (19UL) /*!< USB0_EP0 DOEPTSIZ0: PktCnt (Bit 19) */ 9370 #define USB_EP_DOEPTSIZ0_PktCnt_Msk (0x180000UL) /*!< USB0_EP0 DOEPTSIZ0: PktCnt (Bitfield-Mask: 0x03) */ 9371 #define USB_EP_DOEPTSIZ0_SUPCnt_Pos (29UL) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt (Bit 29) */ 9372 #define USB_EP_DOEPTSIZ0_SUPCnt_Msk (0x60000000UL) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt (Bitfield-Mask: 0x03) */ 9373 9374 /* ------------------------------ USB_EP_DOEPDMA0 ----------------------------- */ 9375 #define USB_EP_DOEPDMA0_DMAAddr_Pos (0UL) /*!< USB0_EP0 DOEPDMA0: DMAAddr (Bit 0) */ 9376 #define USB_EP_DOEPDMA0_DMAAddr_Msk (0xffffffffUL) /*!< USB0_EP0 DOEPDMA0: DMAAddr (Bitfield-Mask: 0xffffffff) */ 9377 9378 /* ----------------------------- USB_EP_DOEPDMAB0 ----------------------------- */ 9379 #define USB_EP_DOEPDMAB0_DMABufferAddr_Pos (0UL) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr (Bit 0) */ 9380 #define USB_EP_DOEPDMAB0_DMABufferAddr_Msk (0xffffffffUL) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ 9381 9382 9383 /* ================================================================================ */ 9384 /* ================ Group 'USB_EP' Position & Mask ================ */ 9385 /* ================================================================================ */ 9386 9387 9388 /* --------------------------- USB_EP_DIEPCTL_ISOCONT --------------------------- */ 9389 #define USB_EP_DIEPCTL_ISOCONT_MPS_Pos (0UL) /*!< USB_EP DIEPCTL_ISOCONT: MPS (Bit 0) */ 9390 #define USB_EP_DIEPCTL_ISOCONT_MPS_Msk (0x7ffUL) /*!< USB_EP DIEPCTL_ISOCONT: MPS (Bitfield-Mask: 0x7ff) */ 9391 #define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos (15UL) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP (Bit 15) */ 9392 #define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk (0x8000UL) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP (Bitfield-Mask: 0x01) */ 9393 #define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos (16UL) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum (Bit 16) */ 9394 #define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk (0x10000UL) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum (Bitfield-Mask: 0x01) */ 9395 #define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos (17UL) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts (Bit 17) */ 9396 #define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk (0x20000UL) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts (Bitfield-Mask: 0x01) */ 9397 #define USB_EP_DIEPCTL_ISOCONT_EPType_Pos (18UL) /*!< USB_EP DIEPCTL_ISOCONT: EPType (Bit 18) */ 9398 #define USB_EP_DIEPCTL_ISOCONT_EPType_Msk (0xc0000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPType (Bitfield-Mask: 0x03) */ 9399 #define USB_EP_DIEPCTL_ISOCONT_Snp_Pos (20UL) /*!< USB_EP DIEPCTL_ISOCONT: Snp (Bit 20) */ 9400 #define USB_EP_DIEPCTL_ISOCONT_Snp_Msk (0x100000UL) /*!< USB_EP DIEPCTL_ISOCONT: Snp (Bitfield-Mask: 0x01) */ 9401 #define USB_EP_DIEPCTL_ISOCONT_Stall_Pos (21UL) /*!< USB_EP DIEPCTL_ISOCONT: Stall (Bit 21) */ 9402 #define USB_EP_DIEPCTL_ISOCONT_Stall_Msk (0x200000UL) /*!< USB_EP DIEPCTL_ISOCONT: Stall (Bitfield-Mask: 0x01) */ 9403 #define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos (22UL) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum (Bit 22) */ 9404 #define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk (0x3c00000UL) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum (Bitfield-Mask: 0x0f) */ 9405 #define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos (26UL) /*!< USB_EP DIEPCTL_ISOCONT: CNAK (Bit 26) */ 9406 #define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk (0x4000000UL) /*!< USB_EP DIEPCTL_ISOCONT: CNAK (Bitfield-Mask: 0x01) */ 9407 #define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos (27UL) /*!< USB_EP DIEPCTL_ISOCONT: SNAK (Bit 27) */ 9408 #define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk (0x8000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SNAK (Bitfield-Mask: 0x01) */ 9409 #define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos (28UL) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr (Bit 28) */ 9410 #define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk (0x10000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr (Bitfield-Mask: 0x01) */ 9411 #define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos (29UL) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr (Bit 29) */ 9412 #define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk (0x20000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr (Bitfield-Mask: 0x01) */ 9413 #define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos (30UL) /*!< USB_EP DIEPCTL_ISOCONT: EPDis (Bit 30) */ 9414 #define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk (0x40000000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPDis (Bitfield-Mask: 0x01) */ 9415 #define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos (31UL) /*!< USB_EP DIEPCTL_ISOCONT: EPEna (Bit 31) */ 9416 #define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk (0x80000000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPEna (Bitfield-Mask: 0x01) */ 9417 9418 /* --------------------------- USB_EP_DIEPCTL_INTBULK --------------------------- */ 9419 #define USB_EP_DIEPCTL_INTBULK_MPS_Pos (0UL) /*!< USB_EP DIEPCTL_INTBULK: MPS (Bit 0) */ 9420 #define USB_EP_DIEPCTL_INTBULK_MPS_Msk (0x7ffUL) /*!< USB_EP DIEPCTL_INTBULK: MPS (Bitfield-Mask: 0x7ff) */ 9421 #define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos (15UL) /*!< USB_EP DIEPCTL_INTBULK: USBActEP (Bit 15) */ 9422 #define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk (0x8000UL) /*!< USB_EP DIEPCTL_INTBULK: USBActEP (Bitfield-Mask: 0x01) */ 9423 #define USB_EP_DIEPCTL_INTBULK_DPID_Pos (16UL) /*!< USB_EP DIEPCTL_INTBULK: DPID (Bit 16) */ 9424 #define USB_EP_DIEPCTL_INTBULK_DPID_Msk (0x10000UL) /*!< USB_EP DIEPCTL_INTBULK: DPID (Bitfield-Mask: 0x01) */ 9425 #define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos (17UL) /*!< USB_EP DIEPCTL_INTBULK: NAKSts (Bit 17) */ 9426 #define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk (0x20000UL) /*!< USB_EP DIEPCTL_INTBULK: NAKSts (Bitfield-Mask: 0x01) */ 9427 #define USB_EP_DIEPCTL_INTBULK_EPType_Pos (18UL) /*!< USB_EP DIEPCTL_INTBULK: EPType (Bit 18) */ 9428 #define USB_EP_DIEPCTL_INTBULK_EPType_Msk (0xc0000UL) /*!< USB_EP DIEPCTL_INTBULK: EPType (Bitfield-Mask: 0x03) */ 9429 #define USB_EP_DIEPCTL_INTBULK_Snp_Pos (20UL) /*!< USB_EP DIEPCTL_INTBULK: Snp (Bit 20) */ 9430 #define USB_EP_DIEPCTL_INTBULK_Snp_Msk (0x100000UL) /*!< USB_EP DIEPCTL_INTBULK: Snp (Bitfield-Mask: 0x01) */ 9431 #define USB_EP_DIEPCTL_INTBULK_Stall_Pos (21UL) /*!< USB_EP DIEPCTL_INTBULK: Stall (Bit 21) */ 9432 #define USB_EP_DIEPCTL_INTBULK_Stall_Msk (0x200000UL) /*!< USB_EP DIEPCTL_INTBULK: Stall (Bitfield-Mask: 0x01) */ 9433 #define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos (22UL) /*!< USB_EP DIEPCTL_INTBULK: TxFNum (Bit 22) */ 9434 #define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk (0x3c00000UL) /*!< USB_EP DIEPCTL_INTBULK: TxFNum (Bitfield-Mask: 0x0f) */ 9435 #define USB_EP_DIEPCTL_INTBULK_CNAK_Pos (26UL) /*!< USB_EP DIEPCTL_INTBULK: CNAK (Bit 26) */ 9436 #define USB_EP_DIEPCTL_INTBULK_CNAK_Msk (0x4000000UL) /*!< USB_EP DIEPCTL_INTBULK: CNAK (Bitfield-Mask: 0x01) */ 9437 #define USB_EP_DIEPCTL_INTBULK_SNAK_Pos (27UL) /*!< USB_EP DIEPCTL_INTBULK: SNAK (Bit 27) */ 9438 #define USB_EP_DIEPCTL_INTBULK_SNAK_Msk (0x8000000UL) /*!< USB_EP DIEPCTL_INTBULK: SNAK (Bitfield-Mask: 0x01) */ 9439 #define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos (28UL) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID (Bit 28) */ 9440 #define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk (0x10000000UL) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID (Bitfield-Mask: 0x01) */ 9441 #define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos (29UL) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID (Bit 29) */ 9442 #define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk (0x20000000UL) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID (Bitfield-Mask: 0x01) */ 9443 #define USB_EP_DIEPCTL_INTBULK_EPDis_Pos (30UL) /*!< USB_EP DIEPCTL_INTBULK: EPDis (Bit 30) */ 9444 #define USB_EP_DIEPCTL_INTBULK_EPDis_Msk (0x40000000UL) /*!< USB_EP DIEPCTL_INTBULK: EPDis (Bitfield-Mask: 0x01) */ 9445 #define USB_EP_DIEPCTL_INTBULK_EPEna_Pos (31UL) /*!< USB_EP DIEPCTL_INTBULK: EPEna (Bit 31) */ 9446 #define USB_EP_DIEPCTL_INTBULK_EPEna_Msk (0x80000000UL) /*!< USB_EP DIEPCTL_INTBULK: EPEna (Bitfield-Mask: 0x01) */ 9447 9448 /* ------------------------------- USB_EP_DIEPINT ------------------------------- */ 9449 #define USB_EP_DIEPINT_XferCompl_Pos (0UL) /*!< USB_EP DIEPINT: XferCompl (Bit 0) */ 9450 #define USB_EP_DIEPINT_XferCompl_Msk (0x1UL) /*!< USB_EP DIEPINT: XferCompl (Bitfield-Mask: 0x01) */ 9451 #define USB_EP_DIEPINT_EPDisbld_Pos (1UL) /*!< USB_EP DIEPINT: EPDisbld (Bit 1) */ 9452 #define USB_EP_DIEPINT_EPDisbld_Msk (0x2UL) /*!< USB_EP DIEPINT: EPDisbld (Bitfield-Mask: 0x01) */ 9453 #define USB_EP_DIEPINT_AHBErr_Pos (2UL) /*!< USB_EP DIEPINT: AHBErr (Bit 2) */ 9454 #define USB_EP_DIEPINT_AHBErr_Msk (0x4UL) /*!< USB_EP DIEPINT: AHBErr (Bitfield-Mask: 0x01) */ 9455 #define USB_EP_DIEPINT_TimeOUT_Pos (3UL) /*!< USB_EP DIEPINT: TimeOUT (Bit 3) */ 9456 #define USB_EP_DIEPINT_TimeOUT_Msk (0x8UL) /*!< USB_EP DIEPINT: TimeOUT (Bitfield-Mask: 0x01) */ 9457 #define USB_EP_DIEPINT_INTknTXFEmp_Pos (4UL) /*!< USB_EP DIEPINT: INTknTXFEmp (Bit 4) */ 9458 #define USB_EP_DIEPINT_INTknTXFEmp_Msk (0x10UL) /*!< USB_EP DIEPINT: INTknTXFEmp (Bitfield-Mask: 0x01) */ 9459 #define USB_EP_DIEPINT_INEPNakEff_Pos (6UL) /*!< USB_EP DIEPINT: INEPNakEff (Bit 6) */ 9460 #define USB_EP_DIEPINT_INEPNakEff_Msk (0x40UL) /*!< USB_EP DIEPINT: INEPNakEff (Bitfield-Mask: 0x01) */ 9461 #define USB_EP_DIEPINT_TxFEmp_Pos (7UL) /*!< USB_EP DIEPINT: TxFEmp (Bit 7) */ 9462 #define USB_EP_DIEPINT_TxFEmp_Msk (0x80UL) /*!< USB_EP DIEPINT: TxFEmp (Bitfield-Mask: 0x01) */ 9463 #define USB_EP_DIEPINT_BNAIntr_Pos (9UL) /*!< USB_EP DIEPINT: BNAIntr (Bit 9) */ 9464 #define USB_EP_DIEPINT_BNAIntr_Msk (0x200UL) /*!< USB_EP DIEPINT: BNAIntr (Bitfield-Mask: 0x01) */ 9465 9466 /* ------------------------------- USB_EP_DIEPTSIZ ------------------------------ */ 9467 #define USB_EP_DIEPTSIZ_XferSize_Pos (0UL) /*!< USB_EP DIEPTSIZ: XferSize (Bit 0) */ 9468 #define USB_EP_DIEPTSIZ_XferSize_Msk (0x7ffffUL) /*!< USB_EP DIEPTSIZ: XferSize (Bitfield-Mask: 0x7ffff) */ 9469 #define USB_EP_DIEPTSIZ_PktCnt_Pos (19UL) /*!< USB_EP DIEPTSIZ: PktCnt (Bit 19) */ 9470 #define USB_EP_DIEPTSIZ_PktCnt_Msk (0x1ff80000UL) /*!< USB_EP DIEPTSIZ: PktCnt (Bitfield-Mask: 0x3ff) */ 9471 9472 /* ------------------------------- USB_EP_DIEPDMA ------------------------------- */ 9473 #define USB_EP_DIEPDMA_DMAAddr_Pos (0UL) /*!< USB_EP DIEPDMA: DMAAddr (Bit 0) */ 9474 #define USB_EP_DIEPDMA_DMAAddr_Msk (0xffffffffUL) /*!< USB_EP DIEPDMA: DMAAddr (Bitfield-Mask: 0xffffffff) */ 9475 9476 /* ------------------------------- USB_EP_DTXFSTS ------------------------------- */ 9477 #define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos (0UL) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail (Bit 0) */ 9478 #define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk (0xffffUL) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail (Bitfield-Mask: 0xffff) */ 9479 9480 /* ------------------------------- USB_EP_DIEPDMAB ------------------------------ */ 9481 #define USB_EP_DIEPDMAB_DMABufferAddr_Pos (0UL) /*!< USB_EP DIEPDMAB: DMABufferAddr (Bit 0) */ 9482 #define USB_EP_DIEPDMAB_DMABufferAddr_Msk (0xffffffffUL) /*!< USB_EP DIEPDMAB: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ 9483 9484 /* --------------------------- USB_EP_DOEPCTL_ISOCONT --------------------------- */ 9485 #define USB_EP_DOEPCTL_ISOCONT_MPS_Pos (0UL) /*!< USB_EP DOEPCTL_ISOCONT: MPS (Bit 0) */ 9486 #define USB_EP_DOEPCTL_ISOCONT_MPS_Msk (0x7ffUL) /*!< USB_EP DOEPCTL_ISOCONT: MPS (Bitfield-Mask: 0x7ff) */ 9487 #define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos (15UL) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP (Bit 15) */ 9488 #define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk (0x8000UL) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP (Bitfield-Mask: 0x01) */ 9489 #define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos (16UL) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum (Bit 16) */ 9490 #define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk (0x10000UL) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum (Bitfield-Mask: 0x01) */ 9491 #define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos (17UL) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts (Bit 17) */ 9492 #define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk (0x20000UL) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts (Bitfield-Mask: 0x01) */ 9493 #define USB_EP_DOEPCTL_ISOCONT_EPType_Pos (18UL) /*!< USB_EP DOEPCTL_ISOCONT: EPType (Bit 18) */ 9494 #define USB_EP_DOEPCTL_ISOCONT_EPType_Msk (0xc0000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPType (Bitfield-Mask: 0x03) */ 9495 #define USB_EP_DOEPCTL_ISOCONT_Snp_Pos (20UL) /*!< USB_EP DOEPCTL_ISOCONT: Snp (Bit 20) */ 9496 #define USB_EP_DOEPCTL_ISOCONT_Snp_Msk (0x100000UL) /*!< USB_EP DOEPCTL_ISOCONT: Snp (Bitfield-Mask: 0x01) */ 9497 #define USB_EP_DOEPCTL_ISOCONT_Stall_Pos (21UL) /*!< USB_EP DOEPCTL_ISOCONT: Stall (Bit 21) */ 9498 #define USB_EP_DOEPCTL_ISOCONT_Stall_Msk (0x200000UL) /*!< USB_EP DOEPCTL_ISOCONT: Stall (Bitfield-Mask: 0x01) */ 9499 #define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos (22UL) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum (Bit 22) */ 9500 #define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk (0x3c00000UL) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum (Bitfield-Mask: 0x0f) */ 9501 #define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos (26UL) /*!< USB_EP DOEPCTL_ISOCONT: CNAK (Bit 26) */ 9502 #define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk (0x4000000UL) /*!< USB_EP DOEPCTL_ISOCONT: CNAK (Bitfield-Mask: 0x01) */ 9503 #define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos (27UL) /*!< USB_EP DOEPCTL_ISOCONT: SNAK (Bit 27) */ 9504 #define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk (0x8000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SNAK (Bitfield-Mask: 0x01) */ 9505 #define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos (28UL) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr (Bit 28) */ 9506 #define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk (0x10000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr (Bitfield-Mask: 0x01) */ 9507 #define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos (29UL) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr (Bit 29) */ 9508 #define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk (0x20000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr (Bitfield-Mask: 0x01) */ 9509 #define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos (30UL) /*!< USB_EP DOEPCTL_ISOCONT: EPDis (Bit 30) */ 9510 #define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk (0x40000000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPDis (Bitfield-Mask: 0x01) */ 9511 #define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos (31UL) /*!< USB_EP DOEPCTL_ISOCONT: EPEna (Bit 31) */ 9512 #define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk (0x80000000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPEna (Bitfield-Mask: 0x01) */ 9513 9514 /* --------------------------- USB_EP_DOEPCTL_INTBULK --------------------------- */ 9515 #define USB_EP_DOEPCTL_INTBULK_MPS_Pos (0UL) /*!< USB_EP DOEPCTL_INTBULK: MPS (Bit 0) */ 9516 #define USB_EP_DOEPCTL_INTBULK_MPS_Msk (0x7ffUL) /*!< USB_EP DOEPCTL_INTBULK: MPS (Bitfield-Mask: 0x7ff) */ 9517 #define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos (15UL) /*!< USB_EP DOEPCTL_INTBULK: USBActEP (Bit 15) */ 9518 #define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk (0x8000UL) /*!< USB_EP DOEPCTL_INTBULK: USBActEP (Bitfield-Mask: 0x01) */ 9519 #define USB_EP_DOEPCTL_INTBULK_DPID_Pos (16UL) /*!< USB_EP DOEPCTL_INTBULK: DPID (Bit 16) */ 9520 #define USB_EP_DOEPCTL_INTBULK_DPID_Msk (0x10000UL) /*!< USB_EP DOEPCTL_INTBULK: DPID (Bitfield-Mask: 0x01) */ 9521 #define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos (17UL) /*!< USB_EP DOEPCTL_INTBULK: NAKSts (Bit 17) */ 9522 #define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk (0x20000UL) /*!< USB_EP DOEPCTL_INTBULK: NAKSts (Bitfield-Mask: 0x01) */ 9523 #define USB_EP_DOEPCTL_INTBULK_EPType_Pos (18UL) /*!< USB_EP DOEPCTL_INTBULK: EPType (Bit 18) */ 9524 #define USB_EP_DOEPCTL_INTBULK_EPType_Msk (0xc0000UL) /*!< USB_EP DOEPCTL_INTBULK: EPType (Bitfield-Mask: 0x03) */ 9525 #define USB_EP_DOEPCTL_INTBULK_Snp_Pos (20UL) /*!< USB_EP DOEPCTL_INTBULK: Snp (Bit 20) */ 9526 #define USB_EP_DOEPCTL_INTBULK_Snp_Msk (0x100000UL) /*!< USB_EP DOEPCTL_INTBULK: Snp (Bitfield-Mask: 0x01) */ 9527 #define USB_EP_DOEPCTL_INTBULK_Stall_Pos (21UL) /*!< USB_EP DOEPCTL_INTBULK: Stall (Bit 21) */ 9528 #define USB_EP_DOEPCTL_INTBULK_Stall_Msk (0x200000UL) /*!< USB_EP DOEPCTL_INTBULK: Stall (Bitfield-Mask: 0x01) */ 9529 #define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos (22UL) /*!< USB_EP DOEPCTL_INTBULK: TxFNum (Bit 22) */ 9530 #define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk (0x3c00000UL) /*!< USB_EP DOEPCTL_INTBULK: TxFNum (Bitfield-Mask: 0x0f) */ 9531 #define USB_EP_DOEPCTL_INTBULK_CNAK_Pos (26UL) /*!< USB_EP DOEPCTL_INTBULK: CNAK (Bit 26) */ 9532 #define USB_EP_DOEPCTL_INTBULK_CNAK_Msk (0x4000000UL) /*!< USB_EP DOEPCTL_INTBULK: CNAK (Bitfield-Mask: 0x01) */ 9533 #define USB_EP_DOEPCTL_INTBULK_SNAK_Pos (27UL) /*!< USB_EP DOEPCTL_INTBULK: SNAK (Bit 27) */ 9534 #define USB_EP_DOEPCTL_INTBULK_SNAK_Msk (0x8000000UL) /*!< USB_EP DOEPCTL_INTBULK: SNAK (Bitfield-Mask: 0x01) */ 9535 #define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos (28UL) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID (Bit 28) */ 9536 #define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk (0x10000000UL) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID (Bitfield-Mask: 0x01) */ 9537 #define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos (29UL) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID (Bit 29) */ 9538 #define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk (0x20000000UL) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID (Bitfield-Mask: 0x01) */ 9539 #define USB_EP_DOEPCTL_INTBULK_EPDis_Pos (30UL) /*!< USB_EP DOEPCTL_INTBULK: EPDis (Bit 30) */ 9540 #define USB_EP_DOEPCTL_INTBULK_EPDis_Msk (0x40000000UL) /*!< USB_EP DOEPCTL_INTBULK: EPDis (Bitfield-Mask: 0x01) */ 9541 #define USB_EP_DOEPCTL_INTBULK_EPEna_Pos (31UL) /*!< USB_EP DOEPCTL_INTBULK: EPEna (Bit 31) */ 9542 #define USB_EP_DOEPCTL_INTBULK_EPEna_Msk (0x80000000UL) /*!< USB_EP DOEPCTL_INTBULK: EPEna (Bitfield-Mask: 0x01) */ 9543 9544 /* ------------------------------- USB_EP_DOEPINT ------------------------------- */ 9545 #define USB_EP_DOEPINT_XferCompl_Pos (0UL) /*!< USB_EP DOEPINT: XferCompl (Bit 0) */ 9546 #define USB_EP_DOEPINT_XferCompl_Msk (0x1UL) /*!< USB_EP DOEPINT: XferCompl (Bitfield-Mask: 0x01) */ 9547 #define USB_EP_DOEPINT_EPDisbld_Pos (1UL) /*!< USB_EP DOEPINT: EPDisbld (Bit 1) */ 9548 #define USB_EP_DOEPINT_EPDisbld_Msk (0x2UL) /*!< USB_EP DOEPINT: EPDisbld (Bitfield-Mask: 0x01) */ 9549 #define USB_EP_DOEPINT_AHBErr_Pos (2UL) /*!< USB_EP DOEPINT: AHBErr (Bit 2) */ 9550 #define USB_EP_DOEPINT_AHBErr_Msk (0x4UL) /*!< USB_EP DOEPINT: AHBErr (Bitfield-Mask: 0x01) */ 9551 #define USB_EP_DOEPINT_SetUp_Pos (3UL) /*!< USB_EP DOEPINT: SetUp (Bit 3) */ 9552 #define USB_EP_DOEPINT_SetUp_Msk (0x8UL) /*!< USB_EP DOEPINT: SetUp (Bitfield-Mask: 0x01) */ 9553 #define USB_EP_DOEPINT_OUTTknEPdis_Pos (4UL) /*!< USB_EP DOEPINT: OUTTknEPdis (Bit 4) */ 9554 #define USB_EP_DOEPINT_OUTTknEPdis_Msk (0x10UL) /*!< USB_EP DOEPINT: OUTTknEPdis (Bitfield-Mask: 0x01) */ 9555 #define USB_EP_DOEPINT_StsPhseRcvd_Pos (5UL) /*!< USB_EP DOEPINT: StsPhseRcvd (Bit 5) */ 9556 #define USB_EP_DOEPINT_StsPhseRcvd_Msk (0x20UL) /*!< USB_EP DOEPINT: StsPhseRcvd (Bitfield-Mask: 0x01) */ 9557 #define USB_EP_DOEPINT_Back2BackSETup_Pos (6UL) /*!< USB_EP DOEPINT: Back2BackSETup (Bit 6) */ 9558 #define USB_EP_DOEPINT_Back2BackSETup_Msk (0x40UL) /*!< USB_EP DOEPINT: Back2BackSETup (Bitfield-Mask: 0x01) */ 9559 #define USB_EP_DOEPINT_BNAIntr_Pos (9UL) /*!< USB_EP DOEPINT: BNAIntr (Bit 9) */ 9560 #define USB_EP_DOEPINT_BNAIntr_Msk (0x200UL) /*!< USB_EP DOEPINT: BNAIntr (Bitfield-Mask: 0x01) */ 9561 #define USB_EP_DOEPINT_PktDrpSts_Pos (11UL) /*!< USB_EP DOEPINT: PktDrpSts (Bit 11) */ 9562 #define USB_EP_DOEPINT_PktDrpSts_Msk (0x800UL) /*!< USB_EP DOEPINT: PktDrpSts (Bitfield-Mask: 0x01) */ 9563 #define USB_EP_DOEPINT_BbleErrIntrpt_Pos (12UL) /*!< USB_EP DOEPINT: BbleErrIntrpt (Bit 12) */ 9564 #define USB_EP_DOEPINT_BbleErrIntrpt_Msk (0x1000UL) /*!< USB_EP DOEPINT: BbleErrIntrpt (Bitfield-Mask: 0x01) */ 9565 #define USB_EP_DOEPINT_NAKIntrpt_Pos (13UL) /*!< USB_EP DOEPINT: NAKIntrpt (Bit 13) */ 9566 #define USB_EP_DOEPINT_NAKIntrpt_Msk (0x2000UL) /*!< USB_EP DOEPINT: NAKIntrpt (Bitfield-Mask: 0x01) */ 9567 #define USB_EP_DOEPINT_NYETIntrpt_Pos (14UL) /*!< USB_EP DOEPINT: NYETIntrpt (Bit 14) */ 9568 #define USB_EP_DOEPINT_NYETIntrpt_Msk (0x4000UL) /*!< USB_EP DOEPINT: NYETIntrpt (Bitfield-Mask: 0x01) */ 9569 9570 /* ----------------------------- USB_EP_DOEPTSIZ_ISO ---------------------------- */ 9571 #define USB_EP_DOEPTSIZ_ISO_XferSize_Pos (0UL) /*!< USB_EP DOEPTSIZ_ISO: XferSize (Bit 0) */ 9572 #define USB_EP_DOEPTSIZ_ISO_XferSize_Msk (0x7ffffUL) /*!< USB_EP DOEPTSIZ_ISO: XferSize (Bitfield-Mask: 0x7ffff) */ 9573 #define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos (19UL) /*!< USB_EP DOEPTSIZ_ISO: PktCnt (Bit 19) */ 9574 #define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk (0x1ff80000UL) /*!< USB_EP DOEPTSIZ_ISO: PktCnt (Bitfield-Mask: 0x3ff) */ 9575 #define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos (29UL) /*!< USB_EP DOEPTSIZ_ISO: RxDPID (Bit 29) */ 9576 #define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk (0x60000000UL) /*!< USB_EP DOEPTSIZ_ISO: RxDPID (Bitfield-Mask: 0x03) */ 9577 9578 /* --------------------------- USB_EP_DOEPTSIZ_CONTROL -------------------------- */ 9579 #define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos (0UL) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize (Bit 0) */ 9580 #define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk (0x7ffffUL) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize (Bitfield-Mask: 0x7ffff) */ 9581 #define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos (19UL) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt (Bit 19) */ 9582 #define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk (0x1ff80000UL) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt (Bitfield-Mask: 0x3ff) */ 9583 #define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos (29UL) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt (Bit 29) */ 9584 #define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk (0x60000000UL) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt (Bitfield-Mask: 0x03) */ 9585 9586 /* ------------------------------- USB_EP_DOEPDMA ------------------------------- */ 9587 #define USB_EP_DOEPDMA_DMAAddr_Pos (0UL) /*!< USB_EP DOEPDMA: DMAAddr (Bit 0) */ 9588 #define USB_EP_DOEPDMA_DMAAddr_Msk (0xffffffffUL) /*!< USB_EP DOEPDMA: DMAAddr (Bitfield-Mask: 0xffffffff) */ 9589 9590 /* ------------------------------- USB_EP_DOEPDMAB ------------------------------ */ 9591 #define USB_EP_DOEPDMAB_DMABufferAddr_Pos (0UL) /*!< USB_EP DOEPDMAB: DMABufferAddr (Bit 0) */ 9592 #define USB_EP_DOEPDMAB_DMABufferAddr_Msk (0xffffffffUL) /*!< USB_EP DOEPDMAB: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ 9593 9594 9595 /* ================================================================================ */ 9596 /* ================ Group 'USB_CH' Position & Mask ================ */ 9597 /* ================================================================================ */ 9598 9599 9600 /* -------------------------------- USB_CH_HCCHAR ------------------------------- */ 9601 #define USB_CH_HCCHAR_MPS_Pos (0UL) /*!< USB_CH HCCHAR: MPS (Bit 0) */ 9602 #define USB_CH_HCCHAR_MPS_Msk (0x7ffUL) /*!< USB_CH HCCHAR: MPS (Bitfield-Mask: 0x7ff) */ 9603 #define USB_CH_HCCHAR_EPNum_Pos (11UL) /*!< USB_CH HCCHAR: EPNum (Bit 11) */ 9604 #define USB_CH_HCCHAR_EPNum_Msk (0x7800UL) /*!< USB_CH HCCHAR: EPNum (Bitfield-Mask: 0x0f) */ 9605 #define USB_CH_HCCHAR_EPDir_Pos (15UL) /*!< USB_CH HCCHAR: EPDir (Bit 15) */ 9606 #define USB_CH_HCCHAR_EPDir_Msk (0x8000UL) /*!< USB_CH HCCHAR: EPDir (Bitfield-Mask: 0x01) */ 9607 #define USB_CH_HCCHAR_EPType_Pos (18UL) /*!< USB_CH HCCHAR: EPType (Bit 18) */ 9608 #define USB_CH_HCCHAR_EPType_Msk (0xc0000UL) /*!< USB_CH HCCHAR: EPType (Bitfield-Mask: 0x03) */ 9609 #define USB_CH_HCCHAR_MC_EC_Pos (20UL) /*!< USB_CH HCCHAR: MC_EC (Bit 20) */ 9610 #define USB_CH_HCCHAR_MC_EC_Msk (0x300000UL) /*!< USB_CH HCCHAR: MC_EC (Bitfield-Mask: 0x03) */ 9611 #define USB_CH_HCCHAR_DevAddr_Pos (22UL) /*!< USB_CH HCCHAR: DevAddr (Bit 22) */ 9612 #define USB_CH_HCCHAR_DevAddr_Msk (0x1fc00000UL) /*!< USB_CH HCCHAR: DevAddr (Bitfield-Mask: 0x7f) */ 9613 #define USB_CH_HCCHAR_OddFrm_Pos (29UL) /*!< USB_CH HCCHAR: OddFrm (Bit 29) */ 9614 #define USB_CH_HCCHAR_OddFrm_Msk (0x20000000UL) /*!< USB_CH HCCHAR: OddFrm (Bitfield-Mask: 0x01) */ 9615 #define USB_CH_HCCHAR_ChDis_Pos (30UL) /*!< USB_CH HCCHAR: ChDis (Bit 30) */ 9616 #define USB_CH_HCCHAR_ChDis_Msk (0x40000000UL) /*!< USB_CH HCCHAR: ChDis (Bitfield-Mask: 0x01) */ 9617 #define USB_CH_HCCHAR_ChEna_Pos (31UL) /*!< USB_CH HCCHAR: ChEna (Bit 31) */ 9618 #define USB_CH_HCCHAR_ChEna_Msk (0x80000000UL) /*!< USB_CH HCCHAR: ChEna (Bitfield-Mask: 0x01) */ 9619 9620 /* -------------------------------- USB_CH_HCINT -------------------------------- */ 9621 #define USB_CH_HCINT_XferCompl_Pos (0UL) /*!< USB_CH HCINT: XferCompl (Bit 0) */ 9622 #define USB_CH_HCINT_XferCompl_Msk (0x1UL) /*!< USB_CH HCINT: XferCompl (Bitfield-Mask: 0x01) */ 9623 #define USB_CH_HCINT_ChHltd_Pos (1UL) /*!< USB_CH HCINT: ChHltd (Bit 1) */ 9624 #define USB_CH_HCINT_ChHltd_Msk (0x2UL) /*!< USB_CH HCINT: ChHltd (Bitfield-Mask: 0x01) */ 9625 #define USB_CH_HCINT_AHBErr_Pos (2UL) /*!< USB_CH HCINT: AHBErr (Bit 2) */ 9626 #define USB_CH_HCINT_AHBErr_Msk (0x4UL) /*!< USB_CH HCINT: AHBErr (Bitfield-Mask: 0x01) */ 9627 #define USB_CH_HCINT_STALL_Pos (3UL) /*!< USB_CH HCINT: STALL (Bit 3) */ 9628 #define USB_CH_HCINT_STALL_Msk (0x8UL) /*!< USB_CH HCINT: STALL (Bitfield-Mask: 0x01) */ 9629 #define USB_CH_HCINT_NAK_Pos (4UL) /*!< USB_CH HCINT: NAK (Bit 4) */ 9630 #define USB_CH_HCINT_NAK_Msk (0x10UL) /*!< USB_CH HCINT: NAK (Bitfield-Mask: 0x01) */ 9631 #define USB_CH_HCINT_ACK_Pos (5UL) /*!< USB_CH HCINT: ACK (Bit 5) */ 9632 #define USB_CH_HCINT_ACK_Msk (0x20UL) /*!< USB_CH HCINT: ACK (Bitfield-Mask: 0x01) */ 9633 #define USB_CH_HCINT_NYET_Pos (6UL) /*!< USB_CH HCINT: NYET (Bit 6) */ 9634 #define USB_CH_HCINT_NYET_Msk (0x40UL) /*!< USB_CH HCINT: NYET (Bitfield-Mask: 0x01) */ 9635 #define USB_CH_HCINT_XactErr_Pos (7UL) /*!< USB_CH HCINT: XactErr (Bit 7) */ 9636 #define USB_CH_HCINT_XactErr_Msk (0x80UL) /*!< USB_CH HCINT: XactErr (Bitfield-Mask: 0x01) */ 9637 #define USB_CH_HCINT_BblErr_Pos (8UL) /*!< USB_CH HCINT: BblErr (Bit 8) */ 9638 #define USB_CH_HCINT_BblErr_Msk (0x100UL) /*!< USB_CH HCINT: BblErr (Bitfield-Mask: 0x01) */ 9639 #define USB_CH_HCINT_FrmOvrun_Pos (9UL) /*!< USB_CH HCINT: FrmOvrun (Bit 9) */ 9640 #define USB_CH_HCINT_FrmOvrun_Msk (0x200UL) /*!< USB_CH HCINT: FrmOvrun (Bitfield-Mask: 0x01) */ 9641 #define USB_CH_HCINT_DataTglErr_Pos (10UL) /*!< USB_CH HCINT: DataTglErr (Bit 10) */ 9642 #define USB_CH_HCINT_DataTglErr_Msk (0x400UL) /*!< USB_CH HCINT: DataTglErr (Bitfield-Mask: 0x01) */ 9643 #define USB_CH_HCINT_BNAIntr_Pos (11UL) /*!< USB_CH HCINT: BNAIntr (Bit 11) */ 9644 #define USB_CH_HCINT_BNAIntr_Msk (0x800UL) /*!< USB_CH HCINT: BNAIntr (Bitfield-Mask: 0x01) */ 9645 #define USB_CH_HCINT_XCS_XACT_ERR_Pos (12UL) /*!< USB_CH HCINT: XCS_XACT_ERR (Bit 12) */ 9646 #define USB_CH_HCINT_XCS_XACT_ERR_Msk (0x1000UL) /*!< USB_CH HCINT: XCS_XACT_ERR (Bitfield-Mask: 0x01) */ 9647 #define USB_CH_HCINT_DESC_LST_ROLLIntr_Pos (13UL) /*!< USB_CH HCINT: DESC_LST_ROLLIntr (Bit 13) */ 9648 #define USB_CH_HCINT_DESC_LST_ROLLIntr_Msk (0x2000UL) /*!< USB_CH HCINT: DESC_LST_ROLLIntr (Bitfield-Mask: 0x01) */ 9649 9650 /* ------------------------------- USB_CH_HCINTMSK ------------------------------ */ 9651 #define USB_CH_HCINTMSK_XferComplMsk_Pos (0UL) /*!< USB_CH HCINTMSK: XferComplMsk (Bit 0) */ 9652 #define USB_CH_HCINTMSK_XferComplMsk_Msk (0x1UL) /*!< USB_CH HCINTMSK: XferComplMsk (Bitfield-Mask: 0x01) */ 9653 #define USB_CH_HCINTMSK_ChHltdMsk_Pos (1UL) /*!< USB_CH HCINTMSK: ChHltdMsk (Bit 1) */ 9654 #define USB_CH_HCINTMSK_ChHltdMsk_Msk (0x2UL) /*!< USB_CH HCINTMSK: ChHltdMsk (Bitfield-Mask: 0x01) */ 9655 #define USB_CH_HCINTMSK_AHBErrMsk_Pos (2UL) /*!< USB_CH HCINTMSK: AHBErrMsk (Bit 2) */ 9656 #define USB_CH_HCINTMSK_AHBErrMsk_Msk (0x4UL) /*!< USB_CH HCINTMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ 9657 #define USB_CH_HCINTMSK_StallMsk_Pos (3UL) /*!< USB_CH HCINTMSK: StallMsk (Bit 3) */ 9658 #define USB_CH_HCINTMSK_StallMsk_Msk (0x8UL) /*!< USB_CH HCINTMSK: StallMsk (Bitfield-Mask: 0x01) */ 9659 #define USB_CH_HCINTMSK_NakMsk_Pos (4UL) /*!< USB_CH HCINTMSK: NakMsk (Bit 4) */ 9660 #define USB_CH_HCINTMSK_NakMsk_Msk (0x10UL) /*!< USB_CH HCINTMSK: NakMsk (Bitfield-Mask: 0x01) */ 9661 #define USB_CH_HCINTMSK_AckMsk_Pos (5UL) /*!< USB_CH HCINTMSK: AckMsk (Bit 5) */ 9662 #define USB_CH_HCINTMSK_AckMsk_Msk (0x20UL) /*!< USB_CH HCINTMSK: AckMsk (Bitfield-Mask: 0x01) */ 9663 #define USB_CH_HCINTMSK_NyetMsk_Pos (6UL) /*!< USB_CH HCINTMSK: NyetMsk (Bit 6) */ 9664 #define USB_CH_HCINTMSK_NyetMsk_Msk (0x40UL) /*!< USB_CH HCINTMSK: NyetMsk (Bitfield-Mask: 0x01) */ 9665 #define USB_CH_HCINTMSK_XactErrMsk_Pos (7UL) /*!< USB_CH HCINTMSK: XactErrMsk (Bit 7) */ 9666 #define USB_CH_HCINTMSK_XactErrMsk_Msk (0x80UL) /*!< USB_CH HCINTMSK: XactErrMsk (Bitfield-Mask: 0x01) */ 9667 #define USB_CH_HCINTMSK_BblErrMsk_Pos (8UL) /*!< USB_CH HCINTMSK: BblErrMsk (Bit 8) */ 9668 #define USB_CH_HCINTMSK_BblErrMsk_Msk (0x100UL) /*!< USB_CH HCINTMSK: BblErrMsk (Bitfield-Mask: 0x01) */ 9669 #define USB_CH_HCINTMSK_FrmOvrunMsk_Pos (9UL) /*!< USB_CH HCINTMSK: FrmOvrunMsk (Bit 9) */ 9670 #define USB_CH_HCINTMSK_FrmOvrunMsk_Msk (0x200UL) /*!< USB_CH HCINTMSK: FrmOvrunMsk (Bitfield-Mask: 0x01) */ 9671 #define USB_CH_HCINTMSK_DataTglErrMsk_Pos (10UL) /*!< USB_CH HCINTMSK: DataTglErrMsk (Bit 10) */ 9672 #define USB_CH_HCINTMSK_DataTglErrMsk_Msk (0x400UL) /*!< USB_CH HCINTMSK: DataTglErrMsk (Bitfield-Mask: 0x01) */ 9673 #define USB_CH_HCINTMSK_BNAIntrMsk_Pos (11UL) /*!< USB_CH HCINTMSK: BNAIntrMsk (Bit 11) */ 9674 #define USB_CH_HCINTMSK_BNAIntrMsk_Msk (0x800UL) /*!< USB_CH HCINTMSK: BNAIntrMsk (Bitfield-Mask: 0x01) */ 9675 #define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos (13UL) /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk (Bit 13) */ 9676 #define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk (0x2000UL) /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk (Bitfield-Mask: 0x01) */ 9677 9678 /* -------------------------- USB_CH_HCTSIZ_BUFFERMODE -------------------------- */ 9679 #define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos (0UL) /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize (Bit 0) */ 9680 #define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk (0x7ffffUL) /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize (Bitfield-Mask: 0x7ffff) */ 9681 #define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos (19UL) /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt (Bit 19) */ 9682 #define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk (0x1ff80000UL) /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt (Bitfield-Mask: 0x3ff) */ 9683 #define USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos (29UL) /*!< USB_CH HCTSIZ_BUFFERMODE: Pid (Bit 29) */ 9684 #define USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk (0x60000000UL) /*!< USB_CH HCTSIZ_BUFFERMODE: Pid (Bitfield-Mask: 0x03) */ 9685 9686 /* -------------------------- USB_CH_HCTSIZ_SCATGATHER -------------------------- */ 9687 #define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos (0UL) /*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO (Bit 0) */ 9688 #define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk (0xffUL) /*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO (Bitfield-Mask: 0xff) */ 9689 #define USB_CH_HCTSIZ_SCATGATHER_NTD_Pos (8UL) /*!< USB_CH HCTSIZ_SCATGATHER: NTD (Bit 8) */ 9690 #define USB_CH_HCTSIZ_SCATGATHER_NTD_Msk (0xff00UL) /*!< USB_CH HCTSIZ_SCATGATHER: NTD (Bitfield-Mask: 0xff) */ 9691 #define USB_CH_HCTSIZ_SCATGATHER_Pid_Pos (29UL) /*!< USB_CH HCTSIZ_SCATGATHER: Pid (Bit 29) */ 9692 #define USB_CH_HCTSIZ_SCATGATHER_Pid_Msk (0x60000000UL) /*!< USB_CH HCTSIZ_SCATGATHER: Pid (Bitfield-Mask: 0x03) */ 9693 9694 /* --------------------------- USB_CH_HCDMA_BUFFERMODE -------------------------- */ 9695 #define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos (0UL) /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr (Bit 0) */ 9696 #define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk (0xffffffffUL) /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr (Bitfield-Mask: 0xffffffff) */ 9697 9698 /* --------------------------- USB_CH_HCDMA_SCATGATHER -------------------------- */ 9699 #define USB_CH_HCDMA_SCATGATHER_CTD_Pos (3UL) /*!< USB_CH HCDMA_SCATGATHER: CTD (Bit 3) */ 9700 #define USB_CH_HCDMA_SCATGATHER_CTD_Msk (0x1f8UL) /*!< USB_CH HCDMA_SCATGATHER: CTD (Bitfield-Mask: 0x3f) */ 9701 #define USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos (9UL) /*!< USB_CH HCDMA_SCATGATHER: DMAAddr (Bit 9) */ 9702 #define USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk (0xfffffe00UL) /*!< USB_CH HCDMA_SCATGATHER: DMAAddr (Bitfield-Mask: 0x7fffff) */ 9703 9704 /* -------------------------------- USB_CH_HCDMAB ------------------------------- */ 9705 #define USB_CH_HCDMAB_Buffer_Address_Pos (0UL) /*!< USB_CH HCDMAB: Buffer_Address (Bit 0) */ 9706 #define USB_CH_HCDMAB_Buffer_Address_Msk (0xffffffffUL) /*!< USB_CH HCDMAB: Buffer_Address (Bitfield-Mask: 0xffffffff) */ 9707 9708 9709 /* ================================================================================ */ 9710 /* ================ Group 'USIC' Position & Mask ================ */ 9711 /* ================================================================================ */ 9712 9713 9714 /* ----------------------------------- USIC_ID ---------------------------------- */ 9715 #define USIC_ID_MOD_REV_Pos (0UL) /*!< USIC ID: MOD_REV (Bit 0) */ 9716 #define USIC_ID_MOD_REV_Msk (0xffUL) /*!< USIC ID: MOD_REV (Bitfield-Mask: 0xff) */ 9717 #define USIC_ID_MOD_TYPE_Pos (8UL) /*!< USIC ID: MOD_TYPE (Bit 8) */ 9718 #define USIC_ID_MOD_TYPE_Msk (0xff00UL) /*!< USIC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 9719 #define USIC_ID_MOD_NUMBER_Pos (16UL) /*!< USIC ID: MOD_NUMBER (Bit 16) */ 9720 #define USIC_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< USIC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 9721 9722 9723 /* ================================================================================ */ 9724 /* ================ Group 'USIC_CH' Position & Mask ================ */ 9725 /* ================================================================================ */ 9726 9727 9728 /* -------------------------------- USIC_CH_CCFG -------------------------------- */ 9729 #define USIC_CH_CCFG_SSC_Pos (0UL) /*!< USIC_CH CCFG: SSC (Bit 0) */ 9730 #define USIC_CH_CCFG_SSC_Msk (0x1UL) /*!< USIC_CH CCFG: SSC (Bitfield-Mask: 0x01) */ 9731 #define USIC_CH_CCFG_ASC_Pos (1UL) /*!< USIC_CH CCFG: ASC (Bit 1) */ 9732 #define USIC_CH_CCFG_ASC_Msk (0x2UL) /*!< USIC_CH CCFG: ASC (Bitfield-Mask: 0x01) */ 9733 #define USIC_CH_CCFG_IIC_Pos (2UL) /*!< USIC_CH CCFG: IIC (Bit 2) */ 9734 #define USIC_CH_CCFG_IIC_Msk (0x4UL) /*!< USIC_CH CCFG: IIC (Bitfield-Mask: 0x01) */ 9735 #define USIC_CH_CCFG_IIS_Pos (3UL) /*!< USIC_CH CCFG: IIS (Bit 3) */ 9736 #define USIC_CH_CCFG_IIS_Msk (0x8UL) /*!< USIC_CH CCFG: IIS (Bitfield-Mask: 0x01) */ 9737 #define USIC_CH_CCFG_RB_Pos (6UL) /*!< USIC_CH CCFG: RB (Bit 6) */ 9738 #define USIC_CH_CCFG_RB_Msk (0x40UL) /*!< USIC_CH CCFG: RB (Bitfield-Mask: 0x01) */ 9739 #define USIC_CH_CCFG_TB_Pos (7UL) /*!< USIC_CH CCFG: TB (Bit 7) */ 9740 #define USIC_CH_CCFG_TB_Msk (0x80UL) /*!< USIC_CH CCFG: TB (Bitfield-Mask: 0x01) */ 9741 9742 /* -------------------------------- USIC_CH_KSCFG ------------------------------- */ 9743 #define USIC_CH_KSCFG_MODEN_Pos (0UL) /*!< USIC_CH KSCFG: MODEN (Bit 0) */ 9744 #define USIC_CH_KSCFG_MODEN_Msk (0x1UL) /*!< USIC_CH KSCFG: MODEN (Bitfield-Mask: 0x01) */ 9745 #define USIC_CH_KSCFG_BPMODEN_Pos (1UL) /*!< USIC_CH KSCFG: BPMODEN (Bit 1) */ 9746 #define USIC_CH_KSCFG_BPMODEN_Msk (0x2UL) /*!< USIC_CH KSCFG: BPMODEN (Bitfield-Mask: 0x01) */ 9747 #define USIC_CH_KSCFG_NOMCFG_Pos (4UL) /*!< USIC_CH KSCFG: NOMCFG (Bit 4) */ 9748 #define USIC_CH_KSCFG_NOMCFG_Msk (0x30UL) /*!< USIC_CH KSCFG: NOMCFG (Bitfield-Mask: 0x03) */ 9749 #define USIC_CH_KSCFG_BPNOM_Pos (7UL) /*!< USIC_CH KSCFG: BPNOM (Bit 7) */ 9750 #define USIC_CH_KSCFG_BPNOM_Msk (0x80UL) /*!< USIC_CH KSCFG: BPNOM (Bitfield-Mask: 0x01) */ 9751 #define USIC_CH_KSCFG_SUMCFG_Pos (8UL) /*!< USIC_CH KSCFG: SUMCFG (Bit 8) */ 9752 #define USIC_CH_KSCFG_SUMCFG_Msk (0x300UL) /*!< USIC_CH KSCFG: SUMCFG (Bitfield-Mask: 0x03) */ 9753 #define USIC_CH_KSCFG_BPSUM_Pos (11UL) /*!< USIC_CH KSCFG: BPSUM (Bit 11) */ 9754 #define USIC_CH_KSCFG_BPSUM_Msk (0x800UL) /*!< USIC_CH KSCFG: BPSUM (Bitfield-Mask: 0x01) */ 9755 9756 /* --------------------------------- USIC_CH_FDR -------------------------------- */ 9757 #define USIC_CH_FDR_STEP_Pos (0UL) /*!< USIC_CH FDR: STEP (Bit 0) */ 9758 #define USIC_CH_FDR_STEP_Msk (0x3ffUL) /*!< USIC_CH FDR: STEP (Bitfield-Mask: 0x3ff) */ 9759 #define USIC_CH_FDR_DM_Pos (14UL) /*!< USIC_CH FDR: DM (Bit 14) */ 9760 #define USIC_CH_FDR_DM_Msk (0xc000UL) /*!< USIC_CH FDR: DM (Bitfield-Mask: 0x03) */ 9761 #define USIC_CH_FDR_RESULT_Pos (16UL) /*!< USIC_CH FDR: RESULT (Bit 16) */ 9762 #define USIC_CH_FDR_RESULT_Msk (0x3ff0000UL) /*!< USIC_CH FDR: RESULT (Bitfield-Mask: 0x3ff) */ 9763 9764 /* --------------------------------- USIC_CH_BRG -------------------------------- */ 9765 #define USIC_CH_BRG_CLKSEL_Pos (0UL) /*!< USIC_CH BRG: CLKSEL (Bit 0) */ 9766 #define USIC_CH_BRG_CLKSEL_Msk (0x3UL) /*!< USIC_CH BRG: CLKSEL (Bitfield-Mask: 0x03) */ 9767 #define USIC_CH_BRG_TMEN_Pos (3UL) /*!< USIC_CH BRG: TMEN (Bit 3) */ 9768 #define USIC_CH_BRG_TMEN_Msk (0x8UL) /*!< USIC_CH BRG: TMEN (Bitfield-Mask: 0x01) */ 9769 #define USIC_CH_BRG_PPPEN_Pos (4UL) /*!< USIC_CH BRG: PPPEN (Bit 4) */ 9770 #define USIC_CH_BRG_PPPEN_Msk (0x10UL) /*!< USIC_CH BRG: PPPEN (Bitfield-Mask: 0x01) */ 9771 #define USIC_CH_BRG_CTQSEL_Pos (6UL) /*!< USIC_CH BRG: CTQSEL (Bit 6) */ 9772 #define USIC_CH_BRG_CTQSEL_Msk (0xc0UL) /*!< USIC_CH BRG: CTQSEL (Bitfield-Mask: 0x03) */ 9773 #define USIC_CH_BRG_PCTQ_Pos (8UL) /*!< USIC_CH BRG: PCTQ (Bit 8) */ 9774 #define USIC_CH_BRG_PCTQ_Msk (0x300UL) /*!< USIC_CH BRG: PCTQ (Bitfield-Mask: 0x03) */ 9775 #define USIC_CH_BRG_DCTQ_Pos (10UL) /*!< USIC_CH BRG: DCTQ (Bit 10) */ 9776 #define USIC_CH_BRG_DCTQ_Msk (0x7c00UL) /*!< USIC_CH BRG: DCTQ (Bitfield-Mask: 0x1f) */ 9777 #define USIC_CH_BRG_PDIV_Pos (16UL) /*!< USIC_CH BRG: PDIV (Bit 16) */ 9778 #define USIC_CH_BRG_PDIV_Msk (0x3ff0000UL) /*!< USIC_CH BRG: PDIV (Bitfield-Mask: 0x3ff) */ 9779 #define USIC_CH_BRG_SCLKOSEL_Pos (28UL) /*!< USIC_CH BRG: SCLKOSEL (Bit 28) */ 9780 #define USIC_CH_BRG_SCLKOSEL_Msk (0x10000000UL) /*!< USIC_CH BRG: SCLKOSEL (Bitfield-Mask: 0x01) */ 9781 #define USIC_CH_BRG_MCLKCFG_Pos (29UL) /*!< USIC_CH BRG: MCLKCFG (Bit 29) */ 9782 #define USIC_CH_BRG_MCLKCFG_Msk (0x20000000UL) /*!< USIC_CH BRG: MCLKCFG (Bitfield-Mask: 0x01) */ 9783 #define USIC_CH_BRG_SCLKCFG_Pos (30UL) /*!< USIC_CH BRG: SCLKCFG (Bit 30) */ 9784 #define USIC_CH_BRG_SCLKCFG_Msk (0xc0000000UL) /*!< USIC_CH BRG: SCLKCFG (Bitfield-Mask: 0x03) */ 9785 9786 /* -------------------------------- USIC_CH_INPR -------------------------------- */ 9787 #define USIC_CH_INPR_TSINP_Pos (0UL) /*!< USIC_CH INPR: TSINP (Bit 0) */ 9788 #define USIC_CH_INPR_TSINP_Msk (0x7UL) /*!< USIC_CH INPR: TSINP (Bitfield-Mask: 0x07) */ 9789 #define USIC_CH_INPR_TBINP_Pos (4UL) /*!< USIC_CH INPR: TBINP (Bit 4) */ 9790 #define USIC_CH_INPR_TBINP_Msk (0x70UL) /*!< USIC_CH INPR: TBINP (Bitfield-Mask: 0x07) */ 9791 #define USIC_CH_INPR_RINP_Pos (8UL) /*!< USIC_CH INPR: RINP (Bit 8) */ 9792 #define USIC_CH_INPR_RINP_Msk (0x700UL) /*!< USIC_CH INPR: RINP (Bitfield-Mask: 0x07) */ 9793 #define USIC_CH_INPR_AINP_Pos (12UL) /*!< USIC_CH INPR: AINP (Bit 12) */ 9794 #define USIC_CH_INPR_AINP_Msk (0x7000UL) /*!< USIC_CH INPR: AINP (Bitfield-Mask: 0x07) */ 9795 #define USIC_CH_INPR_PINP_Pos (16UL) /*!< USIC_CH INPR: PINP (Bit 16) */ 9796 #define USIC_CH_INPR_PINP_Msk (0x70000UL) /*!< USIC_CH INPR: PINP (Bitfield-Mask: 0x07) */ 9797 9798 /* -------------------------------- USIC_CH_DX0CR ------------------------------- */ 9799 #define USIC_CH_DX0CR_DSEL_Pos (0UL) /*!< USIC_CH DX0CR: DSEL (Bit 0) */ 9800 #define USIC_CH_DX0CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX0CR: DSEL (Bitfield-Mask: 0x07) */ 9801 #define USIC_CH_DX0CR_INSW_Pos (4UL) /*!< USIC_CH DX0CR: INSW (Bit 4) */ 9802 #define USIC_CH_DX0CR_INSW_Msk (0x10UL) /*!< USIC_CH DX0CR: INSW (Bitfield-Mask: 0x01) */ 9803 #define USIC_CH_DX0CR_DFEN_Pos (5UL) /*!< USIC_CH DX0CR: DFEN (Bit 5) */ 9804 #define USIC_CH_DX0CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX0CR: DFEN (Bitfield-Mask: 0x01) */ 9805 #define USIC_CH_DX0CR_DSEN_Pos (6UL) /*!< USIC_CH DX0CR: DSEN (Bit 6) */ 9806 #define USIC_CH_DX0CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX0CR: DSEN (Bitfield-Mask: 0x01) */ 9807 #define USIC_CH_DX0CR_DPOL_Pos (8UL) /*!< USIC_CH DX0CR: DPOL (Bit 8) */ 9808 #define USIC_CH_DX0CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX0CR: DPOL (Bitfield-Mask: 0x01) */ 9809 #define USIC_CH_DX0CR_SFSEL_Pos (9UL) /*!< USIC_CH DX0CR: SFSEL (Bit 9) */ 9810 #define USIC_CH_DX0CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX0CR: SFSEL (Bitfield-Mask: 0x01) */ 9811 #define USIC_CH_DX0CR_CM_Pos (10UL) /*!< USIC_CH DX0CR: CM (Bit 10) */ 9812 #define USIC_CH_DX0CR_CM_Msk (0xc00UL) /*!< USIC_CH DX0CR: CM (Bitfield-Mask: 0x03) */ 9813 #define USIC_CH_DX0CR_DXS_Pos (15UL) /*!< USIC_CH DX0CR: DXS (Bit 15) */ 9814 #define USIC_CH_DX0CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX0CR: DXS (Bitfield-Mask: 0x01) */ 9815 9816 /* -------------------------------- USIC_CH_DX1CR ------------------------------- */ 9817 #define USIC_CH_DX1CR_DSEL_Pos (0UL) /*!< USIC_CH DX1CR: DSEL (Bit 0) */ 9818 #define USIC_CH_DX1CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX1CR: DSEL (Bitfield-Mask: 0x07) */ 9819 #define USIC_CH_DX1CR_DCEN_Pos (3UL) /*!< USIC_CH DX1CR: DCEN (Bit 3) */ 9820 #define USIC_CH_DX1CR_DCEN_Msk (0x8UL) /*!< USIC_CH DX1CR: DCEN (Bitfield-Mask: 0x01) */ 9821 #define USIC_CH_DX1CR_INSW_Pos (4UL) /*!< USIC_CH DX1CR: INSW (Bit 4) */ 9822 #define USIC_CH_DX1CR_INSW_Msk (0x10UL) /*!< USIC_CH DX1CR: INSW (Bitfield-Mask: 0x01) */ 9823 #define USIC_CH_DX1CR_DFEN_Pos (5UL) /*!< USIC_CH DX1CR: DFEN (Bit 5) */ 9824 #define USIC_CH_DX1CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX1CR: DFEN (Bitfield-Mask: 0x01) */ 9825 #define USIC_CH_DX1CR_DSEN_Pos (6UL) /*!< USIC_CH DX1CR: DSEN (Bit 6) */ 9826 #define USIC_CH_DX1CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX1CR: DSEN (Bitfield-Mask: 0x01) */ 9827 #define USIC_CH_DX1CR_DPOL_Pos (8UL) /*!< USIC_CH DX1CR: DPOL (Bit 8) */ 9828 #define USIC_CH_DX1CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX1CR: DPOL (Bitfield-Mask: 0x01) */ 9829 #define USIC_CH_DX1CR_SFSEL_Pos (9UL) /*!< USIC_CH DX1CR: SFSEL (Bit 9) */ 9830 #define USIC_CH_DX1CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX1CR: SFSEL (Bitfield-Mask: 0x01) */ 9831 #define USIC_CH_DX1CR_CM_Pos (10UL) /*!< USIC_CH DX1CR: CM (Bit 10) */ 9832 #define USIC_CH_DX1CR_CM_Msk (0xc00UL) /*!< USIC_CH DX1CR: CM (Bitfield-Mask: 0x03) */ 9833 #define USIC_CH_DX1CR_DXS_Pos (15UL) /*!< USIC_CH DX1CR: DXS (Bit 15) */ 9834 #define USIC_CH_DX1CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX1CR: DXS (Bitfield-Mask: 0x01) */ 9835 9836 /* -------------------------------- USIC_CH_DX2CR ------------------------------- */ 9837 #define USIC_CH_DX2CR_DSEL_Pos (0UL) /*!< USIC_CH DX2CR: DSEL (Bit 0) */ 9838 #define USIC_CH_DX2CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX2CR: DSEL (Bitfield-Mask: 0x07) */ 9839 #define USIC_CH_DX2CR_INSW_Pos (4UL) /*!< USIC_CH DX2CR: INSW (Bit 4) */ 9840 #define USIC_CH_DX2CR_INSW_Msk (0x10UL) /*!< USIC_CH DX2CR: INSW (Bitfield-Mask: 0x01) */ 9841 #define USIC_CH_DX2CR_DFEN_Pos (5UL) /*!< USIC_CH DX2CR: DFEN (Bit 5) */ 9842 #define USIC_CH_DX2CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX2CR: DFEN (Bitfield-Mask: 0x01) */ 9843 #define USIC_CH_DX2CR_DSEN_Pos (6UL) /*!< USIC_CH DX2CR: DSEN (Bit 6) */ 9844 #define USIC_CH_DX2CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX2CR: DSEN (Bitfield-Mask: 0x01) */ 9845 #define USIC_CH_DX2CR_DPOL_Pos (8UL) /*!< USIC_CH DX2CR: DPOL (Bit 8) */ 9846 #define USIC_CH_DX2CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX2CR: DPOL (Bitfield-Mask: 0x01) */ 9847 #define USIC_CH_DX2CR_SFSEL_Pos (9UL) /*!< USIC_CH DX2CR: SFSEL (Bit 9) */ 9848 #define USIC_CH_DX2CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX2CR: SFSEL (Bitfield-Mask: 0x01) */ 9849 #define USIC_CH_DX2CR_CM_Pos (10UL) /*!< USIC_CH DX2CR: CM (Bit 10) */ 9850 #define USIC_CH_DX2CR_CM_Msk (0xc00UL) /*!< USIC_CH DX2CR: CM (Bitfield-Mask: 0x03) */ 9851 #define USIC_CH_DX2CR_DXS_Pos (15UL) /*!< USIC_CH DX2CR: DXS (Bit 15) */ 9852 #define USIC_CH_DX2CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX2CR: DXS (Bitfield-Mask: 0x01) */ 9853 9854 /* -------------------------------- USIC_CH_DX3CR ------------------------------- */ 9855 #define USIC_CH_DX3CR_DSEL_Pos (0UL) /*!< USIC_CH DX3CR: DSEL (Bit 0) */ 9856 #define USIC_CH_DX3CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX3CR: DSEL (Bitfield-Mask: 0x07) */ 9857 #define USIC_CH_DX3CR_INSW_Pos (4UL) /*!< USIC_CH DX3CR: INSW (Bit 4) */ 9858 #define USIC_CH_DX3CR_INSW_Msk (0x10UL) /*!< USIC_CH DX3CR: INSW (Bitfield-Mask: 0x01) */ 9859 #define USIC_CH_DX3CR_DFEN_Pos (5UL) /*!< USIC_CH DX3CR: DFEN (Bit 5) */ 9860 #define USIC_CH_DX3CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX3CR: DFEN (Bitfield-Mask: 0x01) */ 9861 #define USIC_CH_DX3CR_DSEN_Pos (6UL) /*!< USIC_CH DX3CR: DSEN (Bit 6) */ 9862 #define USIC_CH_DX3CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX3CR: DSEN (Bitfield-Mask: 0x01) */ 9863 #define USIC_CH_DX3CR_DPOL_Pos (8UL) /*!< USIC_CH DX3CR: DPOL (Bit 8) */ 9864 #define USIC_CH_DX3CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX3CR: DPOL (Bitfield-Mask: 0x01) */ 9865 #define USIC_CH_DX3CR_SFSEL_Pos (9UL) /*!< USIC_CH DX3CR: SFSEL (Bit 9) */ 9866 #define USIC_CH_DX3CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX3CR: SFSEL (Bitfield-Mask: 0x01) */ 9867 #define USIC_CH_DX3CR_CM_Pos (10UL) /*!< USIC_CH DX3CR: CM (Bit 10) */ 9868 #define USIC_CH_DX3CR_CM_Msk (0xc00UL) /*!< USIC_CH DX3CR: CM (Bitfield-Mask: 0x03) */ 9869 #define USIC_CH_DX3CR_DXS_Pos (15UL) /*!< USIC_CH DX3CR: DXS (Bit 15) */ 9870 #define USIC_CH_DX3CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX3CR: DXS (Bitfield-Mask: 0x01) */ 9871 9872 /* -------------------------------- USIC_CH_DX4CR ------------------------------- */ 9873 #define USIC_CH_DX4CR_DSEL_Pos (0UL) /*!< USIC_CH DX4CR: DSEL (Bit 0) */ 9874 #define USIC_CH_DX4CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX4CR: DSEL (Bitfield-Mask: 0x07) */ 9875 #define USIC_CH_DX4CR_INSW_Pos (4UL) /*!< USIC_CH DX4CR: INSW (Bit 4) */ 9876 #define USIC_CH_DX4CR_INSW_Msk (0x10UL) /*!< USIC_CH DX4CR: INSW (Bitfield-Mask: 0x01) */ 9877 #define USIC_CH_DX4CR_DFEN_Pos (5UL) /*!< USIC_CH DX4CR: DFEN (Bit 5) */ 9878 #define USIC_CH_DX4CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX4CR: DFEN (Bitfield-Mask: 0x01) */ 9879 #define USIC_CH_DX4CR_DSEN_Pos (6UL) /*!< USIC_CH DX4CR: DSEN (Bit 6) */ 9880 #define USIC_CH_DX4CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX4CR: DSEN (Bitfield-Mask: 0x01) */ 9881 #define USIC_CH_DX4CR_DPOL_Pos (8UL) /*!< USIC_CH DX4CR: DPOL (Bit 8) */ 9882 #define USIC_CH_DX4CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX4CR: DPOL (Bitfield-Mask: 0x01) */ 9883 #define USIC_CH_DX4CR_SFSEL_Pos (9UL) /*!< USIC_CH DX4CR: SFSEL (Bit 9) */ 9884 #define USIC_CH_DX4CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX4CR: SFSEL (Bitfield-Mask: 0x01) */ 9885 #define USIC_CH_DX4CR_CM_Pos (10UL) /*!< USIC_CH DX4CR: CM (Bit 10) */ 9886 #define USIC_CH_DX4CR_CM_Msk (0xc00UL) /*!< USIC_CH DX4CR: CM (Bitfield-Mask: 0x03) */ 9887 #define USIC_CH_DX4CR_DXS_Pos (15UL) /*!< USIC_CH DX4CR: DXS (Bit 15) */ 9888 #define USIC_CH_DX4CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX4CR: DXS (Bitfield-Mask: 0x01) */ 9889 9890 /* -------------------------------- USIC_CH_DX5CR ------------------------------- */ 9891 #define USIC_CH_DX5CR_DSEL_Pos (0UL) /*!< USIC_CH DX5CR: DSEL (Bit 0) */ 9892 #define USIC_CH_DX5CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX5CR: DSEL (Bitfield-Mask: 0x07) */ 9893 #define USIC_CH_DX5CR_INSW_Pos (4UL) /*!< USIC_CH DX5CR: INSW (Bit 4) */ 9894 #define USIC_CH_DX5CR_INSW_Msk (0x10UL) /*!< USIC_CH DX5CR: INSW (Bitfield-Mask: 0x01) */ 9895 #define USIC_CH_DX5CR_DFEN_Pos (5UL) /*!< USIC_CH DX5CR: DFEN (Bit 5) */ 9896 #define USIC_CH_DX5CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX5CR: DFEN (Bitfield-Mask: 0x01) */ 9897 #define USIC_CH_DX5CR_DSEN_Pos (6UL) /*!< USIC_CH DX5CR: DSEN (Bit 6) */ 9898 #define USIC_CH_DX5CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX5CR: DSEN (Bitfield-Mask: 0x01) */ 9899 #define USIC_CH_DX5CR_DPOL_Pos (8UL) /*!< USIC_CH DX5CR: DPOL (Bit 8) */ 9900 #define USIC_CH_DX5CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX5CR: DPOL (Bitfield-Mask: 0x01) */ 9901 #define USIC_CH_DX5CR_SFSEL_Pos (9UL) /*!< USIC_CH DX5CR: SFSEL (Bit 9) */ 9902 #define USIC_CH_DX5CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX5CR: SFSEL (Bitfield-Mask: 0x01) */ 9903 #define USIC_CH_DX5CR_CM_Pos (10UL) /*!< USIC_CH DX5CR: CM (Bit 10) */ 9904 #define USIC_CH_DX5CR_CM_Msk (0xc00UL) /*!< USIC_CH DX5CR: CM (Bitfield-Mask: 0x03) */ 9905 #define USIC_CH_DX5CR_DXS_Pos (15UL) /*!< USIC_CH DX5CR: DXS (Bit 15) */ 9906 #define USIC_CH_DX5CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX5CR: DXS (Bitfield-Mask: 0x01) */ 9907 9908 /* -------------------------------- USIC_CH_SCTR -------------------------------- */ 9909 #define USIC_CH_SCTR_SDIR_Pos (0UL) /*!< USIC_CH SCTR: SDIR (Bit 0) */ 9910 #define USIC_CH_SCTR_SDIR_Msk (0x1UL) /*!< USIC_CH SCTR: SDIR (Bitfield-Mask: 0x01) */ 9911 #define USIC_CH_SCTR_PDL_Pos (1UL) /*!< USIC_CH SCTR: PDL (Bit 1) */ 9912 #define USIC_CH_SCTR_PDL_Msk (0x2UL) /*!< USIC_CH SCTR: PDL (Bitfield-Mask: 0x01) */ 9913 #define USIC_CH_SCTR_DSM_Pos (2UL) /*!< USIC_CH SCTR: DSM (Bit 2) */ 9914 #define USIC_CH_SCTR_DSM_Msk (0xcUL) /*!< USIC_CH SCTR: DSM (Bitfield-Mask: 0x03) */ 9915 #define USIC_CH_SCTR_HPCDIR_Pos (4UL) /*!< USIC_CH SCTR: HPCDIR (Bit 4) */ 9916 #define USIC_CH_SCTR_HPCDIR_Msk (0x10UL) /*!< USIC_CH SCTR: HPCDIR (Bitfield-Mask: 0x01) */ 9917 #define USIC_CH_SCTR_DOCFG_Pos (6UL) /*!< USIC_CH SCTR: DOCFG (Bit 6) */ 9918 #define USIC_CH_SCTR_DOCFG_Msk (0xc0UL) /*!< USIC_CH SCTR: DOCFG (Bitfield-Mask: 0x03) */ 9919 #define USIC_CH_SCTR_TRM_Pos (8UL) /*!< USIC_CH SCTR: TRM (Bit 8) */ 9920 #define USIC_CH_SCTR_TRM_Msk (0x300UL) /*!< USIC_CH SCTR: TRM (Bitfield-Mask: 0x03) */ 9921 #define USIC_CH_SCTR_FLE_Pos (16UL) /*!< USIC_CH SCTR: FLE (Bit 16) */ 9922 #define USIC_CH_SCTR_FLE_Msk (0x3f0000UL) /*!< USIC_CH SCTR: FLE (Bitfield-Mask: 0x3f) */ 9923 #define USIC_CH_SCTR_WLE_Pos (24UL) /*!< USIC_CH SCTR: WLE (Bit 24) */ 9924 #define USIC_CH_SCTR_WLE_Msk (0xf000000UL) /*!< USIC_CH SCTR: WLE (Bitfield-Mask: 0x0f) */ 9925 9926 /* -------------------------------- USIC_CH_TCSR -------------------------------- */ 9927 #define USIC_CH_TCSR_WLEMD_Pos (0UL) /*!< USIC_CH TCSR: WLEMD (Bit 0) */ 9928 #define USIC_CH_TCSR_WLEMD_Msk (0x1UL) /*!< USIC_CH TCSR: WLEMD (Bitfield-Mask: 0x01) */ 9929 #define USIC_CH_TCSR_SELMD_Pos (1UL) /*!< USIC_CH TCSR: SELMD (Bit 1) */ 9930 #define USIC_CH_TCSR_SELMD_Msk (0x2UL) /*!< USIC_CH TCSR: SELMD (Bitfield-Mask: 0x01) */ 9931 #define USIC_CH_TCSR_FLEMD_Pos (2UL) /*!< USIC_CH TCSR: FLEMD (Bit 2) */ 9932 #define USIC_CH_TCSR_FLEMD_Msk (0x4UL) /*!< USIC_CH TCSR: FLEMD (Bitfield-Mask: 0x01) */ 9933 #define USIC_CH_TCSR_WAMD_Pos (3UL) /*!< USIC_CH TCSR: WAMD (Bit 3) */ 9934 #define USIC_CH_TCSR_WAMD_Msk (0x8UL) /*!< USIC_CH TCSR: WAMD (Bitfield-Mask: 0x01) */ 9935 #define USIC_CH_TCSR_HPCMD_Pos (4UL) /*!< USIC_CH TCSR: HPCMD (Bit 4) */ 9936 #define USIC_CH_TCSR_HPCMD_Msk (0x10UL) /*!< USIC_CH TCSR: HPCMD (Bitfield-Mask: 0x01) */ 9937 #define USIC_CH_TCSR_SOF_Pos (5UL) /*!< USIC_CH TCSR: SOF (Bit 5) */ 9938 #define USIC_CH_TCSR_SOF_Msk (0x20UL) /*!< USIC_CH TCSR: SOF (Bitfield-Mask: 0x01) */ 9939 #define USIC_CH_TCSR_EOF_Pos (6UL) /*!< USIC_CH TCSR: EOF (Bit 6) */ 9940 #define USIC_CH_TCSR_EOF_Msk (0x40UL) /*!< USIC_CH TCSR: EOF (Bitfield-Mask: 0x01) */ 9941 #define USIC_CH_TCSR_TDV_Pos (7UL) /*!< USIC_CH TCSR: TDV (Bit 7) */ 9942 #define USIC_CH_TCSR_TDV_Msk (0x80UL) /*!< USIC_CH TCSR: TDV (Bitfield-Mask: 0x01) */ 9943 #define USIC_CH_TCSR_TDSSM_Pos (8UL) /*!< USIC_CH TCSR: TDSSM (Bit 8) */ 9944 #define USIC_CH_TCSR_TDSSM_Msk (0x100UL) /*!< USIC_CH TCSR: TDSSM (Bitfield-Mask: 0x01) */ 9945 #define USIC_CH_TCSR_TDEN_Pos (10UL) /*!< USIC_CH TCSR: TDEN (Bit 10) */ 9946 #define USIC_CH_TCSR_TDEN_Msk (0xc00UL) /*!< USIC_CH TCSR: TDEN (Bitfield-Mask: 0x03) */ 9947 #define USIC_CH_TCSR_TDVTR_Pos (12UL) /*!< USIC_CH TCSR: TDVTR (Bit 12) */ 9948 #define USIC_CH_TCSR_TDVTR_Msk (0x1000UL) /*!< USIC_CH TCSR: TDVTR (Bitfield-Mask: 0x01) */ 9949 #define USIC_CH_TCSR_WA_Pos (13UL) /*!< USIC_CH TCSR: WA (Bit 13) */ 9950 #define USIC_CH_TCSR_WA_Msk (0x2000UL) /*!< USIC_CH TCSR: WA (Bitfield-Mask: 0x01) */ 9951 #define USIC_CH_TCSR_TSOF_Pos (24UL) /*!< USIC_CH TCSR: TSOF (Bit 24) */ 9952 #define USIC_CH_TCSR_TSOF_Msk (0x1000000UL) /*!< USIC_CH TCSR: TSOF (Bitfield-Mask: 0x01) */ 9953 #define USIC_CH_TCSR_TV_Pos (26UL) /*!< USIC_CH TCSR: TV (Bit 26) */ 9954 #define USIC_CH_TCSR_TV_Msk (0x4000000UL) /*!< USIC_CH TCSR: TV (Bitfield-Mask: 0x01) */ 9955 #define USIC_CH_TCSR_TVC_Pos (27UL) /*!< USIC_CH TCSR: TVC (Bit 27) */ 9956 #define USIC_CH_TCSR_TVC_Msk (0x8000000UL) /*!< USIC_CH TCSR: TVC (Bitfield-Mask: 0x01) */ 9957 #define USIC_CH_TCSR_TE_Pos (28UL) /*!< USIC_CH TCSR: TE (Bit 28) */ 9958 #define USIC_CH_TCSR_TE_Msk (0x10000000UL) /*!< USIC_CH TCSR: TE (Bitfield-Mask: 0x01) */ 9959 9960 /* --------------------------------- USIC_CH_PCR -------------------------------- */ 9961 #define USIC_CH_PCR_CTR0_Pos (0UL) /*!< USIC_CH PCR: CTR0 (Bit 0) */ 9962 #define USIC_CH_PCR_CTR0_Msk (0x1UL) /*!< USIC_CH PCR: CTR0 (Bitfield-Mask: 0x01) */ 9963 #define USIC_CH_PCR_CTR1_Pos (1UL) /*!< USIC_CH PCR: CTR1 (Bit 1) */ 9964 #define USIC_CH_PCR_CTR1_Msk (0x2UL) /*!< USIC_CH PCR: CTR1 (Bitfield-Mask: 0x01) */ 9965 #define USIC_CH_PCR_CTR2_Pos (2UL) /*!< USIC_CH PCR: CTR2 (Bit 2) */ 9966 #define USIC_CH_PCR_CTR2_Msk (0x4UL) /*!< USIC_CH PCR: CTR2 (Bitfield-Mask: 0x01) */ 9967 #define USIC_CH_PCR_CTR3_Pos (3UL) /*!< USIC_CH PCR: CTR3 (Bit 3) */ 9968 #define USIC_CH_PCR_CTR3_Msk (0x8UL) /*!< USIC_CH PCR: CTR3 (Bitfield-Mask: 0x01) */ 9969 #define USIC_CH_PCR_CTR4_Pos (4UL) /*!< USIC_CH PCR: CTR4 (Bit 4) */ 9970 #define USIC_CH_PCR_CTR4_Msk (0x10UL) /*!< USIC_CH PCR: CTR4 (Bitfield-Mask: 0x01) */ 9971 #define USIC_CH_PCR_CTR5_Pos (5UL) /*!< USIC_CH PCR: CTR5 (Bit 5) */ 9972 #define USIC_CH_PCR_CTR5_Msk (0x20UL) /*!< USIC_CH PCR: CTR5 (Bitfield-Mask: 0x01) */ 9973 #define USIC_CH_PCR_CTR6_Pos (6UL) /*!< USIC_CH PCR: CTR6 (Bit 6) */ 9974 #define USIC_CH_PCR_CTR6_Msk (0x40UL) /*!< USIC_CH PCR: CTR6 (Bitfield-Mask: 0x01) */ 9975 #define USIC_CH_PCR_CTR7_Pos (7UL) /*!< USIC_CH PCR: CTR7 (Bit 7) */ 9976 #define USIC_CH_PCR_CTR7_Msk (0x80UL) /*!< USIC_CH PCR: CTR7 (Bitfield-Mask: 0x01) */ 9977 #define USIC_CH_PCR_CTR8_Pos (8UL) /*!< USIC_CH PCR: CTR8 (Bit 8) */ 9978 #define USIC_CH_PCR_CTR8_Msk (0x100UL) /*!< USIC_CH PCR: CTR8 (Bitfield-Mask: 0x01) */ 9979 #define USIC_CH_PCR_CTR9_Pos (9UL) /*!< USIC_CH PCR: CTR9 (Bit 9) */ 9980 #define USIC_CH_PCR_CTR9_Msk (0x200UL) /*!< USIC_CH PCR: CTR9 (Bitfield-Mask: 0x01) */ 9981 #define USIC_CH_PCR_CTR10_Pos (10UL) /*!< USIC_CH PCR: CTR10 (Bit 10) */ 9982 #define USIC_CH_PCR_CTR10_Msk (0x400UL) /*!< USIC_CH PCR: CTR10 (Bitfield-Mask: 0x01) */ 9983 #define USIC_CH_PCR_CTR11_Pos (11UL) /*!< USIC_CH PCR: CTR11 (Bit 11) */ 9984 #define USIC_CH_PCR_CTR11_Msk (0x800UL) /*!< USIC_CH PCR: CTR11 (Bitfield-Mask: 0x01) */ 9985 #define USIC_CH_PCR_CTR12_Pos (12UL) /*!< USIC_CH PCR: CTR12 (Bit 12) */ 9986 #define USIC_CH_PCR_CTR12_Msk (0x1000UL) /*!< USIC_CH PCR: CTR12 (Bitfield-Mask: 0x01) */ 9987 #define USIC_CH_PCR_CTR13_Pos (13UL) /*!< USIC_CH PCR: CTR13 (Bit 13) */ 9988 #define USIC_CH_PCR_CTR13_Msk (0x2000UL) /*!< USIC_CH PCR: CTR13 (Bitfield-Mask: 0x01) */ 9989 #define USIC_CH_PCR_CTR14_Pos (14UL) /*!< USIC_CH PCR: CTR14 (Bit 14) */ 9990 #define USIC_CH_PCR_CTR14_Msk (0x4000UL) /*!< USIC_CH PCR: CTR14 (Bitfield-Mask: 0x01) */ 9991 #define USIC_CH_PCR_CTR15_Pos (15UL) /*!< USIC_CH PCR: CTR15 (Bit 15) */ 9992 #define USIC_CH_PCR_CTR15_Msk (0x8000UL) /*!< USIC_CH PCR: CTR15 (Bitfield-Mask: 0x01) */ 9993 #define USIC_CH_PCR_CTR16_Pos (16UL) /*!< USIC_CH PCR: CTR16 (Bit 16) */ 9994 #define USIC_CH_PCR_CTR16_Msk (0x10000UL) /*!< USIC_CH PCR: CTR16 (Bitfield-Mask: 0x01) */ 9995 #define USIC_CH_PCR_CTR17_Pos (17UL) /*!< USIC_CH PCR: CTR17 (Bit 17) */ 9996 #define USIC_CH_PCR_CTR17_Msk (0x20000UL) /*!< USIC_CH PCR: CTR17 (Bitfield-Mask: 0x01) */ 9997 #define USIC_CH_PCR_CTR18_Pos (18UL) /*!< USIC_CH PCR: CTR18 (Bit 18) */ 9998 #define USIC_CH_PCR_CTR18_Msk (0x40000UL) /*!< USIC_CH PCR: CTR18 (Bitfield-Mask: 0x01) */ 9999 #define USIC_CH_PCR_CTR19_Pos (19UL) /*!< USIC_CH PCR: CTR19 (Bit 19) */ 10000 #define USIC_CH_PCR_CTR19_Msk (0x80000UL) /*!< USIC_CH PCR: CTR19 (Bitfield-Mask: 0x01) */ 10001 #define USIC_CH_PCR_CTR20_Pos (20UL) /*!< USIC_CH PCR: CTR20 (Bit 20) */ 10002 #define USIC_CH_PCR_CTR20_Msk (0x100000UL) /*!< USIC_CH PCR: CTR20 (Bitfield-Mask: 0x01) */ 10003 #define USIC_CH_PCR_CTR21_Pos (21UL) /*!< USIC_CH PCR: CTR21 (Bit 21) */ 10004 #define USIC_CH_PCR_CTR21_Msk (0x200000UL) /*!< USIC_CH PCR: CTR21 (Bitfield-Mask: 0x01) */ 10005 #define USIC_CH_PCR_CTR22_Pos (22UL) /*!< USIC_CH PCR: CTR22 (Bit 22) */ 10006 #define USIC_CH_PCR_CTR22_Msk (0x400000UL) /*!< USIC_CH PCR: CTR22 (Bitfield-Mask: 0x01) */ 10007 #define USIC_CH_PCR_CTR23_Pos (23UL) /*!< USIC_CH PCR: CTR23 (Bit 23) */ 10008 #define USIC_CH_PCR_CTR23_Msk (0x800000UL) /*!< USIC_CH PCR: CTR23 (Bitfield-Mask: 0x01) */ 10009 #define USIC_CH_PCR_CTR24_Pos (24UL) /*!< USIC_CH PCR: CTR24 (Bit 24) */ 10010 #define USIC_CH_PCR_CTR24_Msk (0x1000000UL) /*!< USIC_CH PCR: CTR24 (Bitfield-Mask: 0x01) */ 10011 #define USIC_CH_PCR_CTR25_Pos (25UL) /*!< USIC_CH PCR: CTR25 (Bit 25) */ 10012 #define USIC_CH_PCR_CTR25_Msk (0x2000000UL) /*!< USIC_CH PCR: CTR25 (Bitfield-Mask: 0x01) */ 10013 #define USIC_CH_PCR_CTR26_Pos (26UL) /*!< USIC_CH PCR: CTR26 (Bit 26) */ 10014 #define USIC_CH_PCR_CTR26_Msk (0x4000000UL) /*!< USIC_CH PCR: CTR26 (Bitfield-Mask: 0x01) */ 10015 #define USIC_CH_PCR_CTR27_Pos (27UL) /*!< USIC_CH PCR: CTR27 (Bit 27) */ 10016 #define USIC_CH_PCR_CTR27_Msk (0x8000000UL) /*!< USIC_CH PCR: CTR27 (Bitfield-Mask: 0x01) */ 10017 #define USIC_CH_PCR_CTR28_Pos (28UL) /*!< USIC_CH PCR: CTR28 (Bit 28) */ 10018 #define USIC_CH_PCR_CTR28_Msk (0x10000000UL) /*!< USIC_CH PCR: CTR28 (Bitfield-Mask: 0x01) */ 10019 #define USIC_CH_PCR_CTR29_Pos (29UL) /*!< USIC_CH PCR: CTR29 (Bit 29) */ 10020 #define USIC_CH_PCR_CTR29_Msk (0x20000000UL) /*!< USIC_CH PCR: CTR29 (Bitfield-Mask: 0x01) */ 10021 #define USIC_CH_PCR_CTR30_Pos (30UL) /*!< USIC_CH PCR: CTR30 (Bit 30) */ 10022 #define USIC_CH_PCR_CTR30_Msk (0x40000000UL) /*!< USIC_CH PCR: CTR30 (Bitfield-Mask: 0x01) */ 10023 #define USIC_CH_PCR_CTR31_Pos (31UL) /*!< USIC_CH PCR: CTR31 (Bit 31) */ 10024 #define USIC_CH_PCR_CTR31_Msk (0x80000000UL) /*!< USIC_CH PCR: CTR31 (Bitfield-Mask: 0x01) */ 10025 10026 /* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */ 10027 #define USIC_CH_PCR_ASCMode_SMD_Pos (0UL) /*!< USIC_CH PCR_ASCMode: SMD (Bit 0) */ 10028 #define USIC_CH_PCR_ASCMode_SMD_Msk (0x1UL) /*!< USIC_CH PCR_ASCMode: SMD (Bitfield-Mask: 0x01) */ 10029 #define USIC_CH_PCR_ASCMode_STPB_Pos (1UL) /*!< USIC_CH PCR_ASCMode: STPB (Bit 1) */ 10030 #define USIC_CH_PCR_ASCMode_STPB_Msk (0x2UL) /*!< USIC_CH PCR_ASCMode: STPB (Bitfield-Mask: 0x01) */ 10031 #define USIC_CH_PCR_ASCMode_IDM_Pos (2UL) /*!< USIC_CH PCR_ASCMode: IDM (Bit 2) */ 10032 #define USIC_CH_PCR_ASCMode_IDM_Msk (0x4UL) /*!< USIC_CH PCR_ASCMode: IDM (Bitfield-Mask: 0x01) */ 10033 #define USIC_CH_PCR_ASCMode_SBIEN_Pos (3UL) /*!< USIC_CH PCR_ASCMode: SBIEN (Bit 3) */ 10034 #define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x8UL) /*!< USIC_CH PCR_ASCMode: SBIEN (Bitfield-Mask: 0x01) */ 10035 #define USIC_CH_PCR_ASCMode_CDEN_Pos (4UL) /*!< USIC_CH PCR_ASCMode: CDEN (Bit 4) */ 10036 #define USIC_CH_PCR_ASCMode_CDEN_Msk (0x10UL) /*!< USIC_CH PCR_ASCMode: CDEN (Bitfield-Mask: 0x01) */ 10037 #define USIC_CH_PCR_ASCMode_RNIEN_Pos (5UL) /*!< USIC_CH PCR_ASCMode: RNIEN (Bit 5) */ 10038 #define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x20UL) /*!< USIC_CH PCR_ASCMode: RNIEN (Bitfield-Mask: 0x01) */ 10039 #define USIC_CH_PCR_ASCMode_FEIEN_Pos (6UL) /*!< USIC_CH PCR_ASCMode: FEIEN (Bit 6) */ 10040 #define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x40UL) /*!< USIC_CH PCR_ASCMode: FEIEN (Bitfield-Mask: 0x01) */ 10041 #define USIC_CH_PCR_ASCMode_FFIEN_Pos (7UL) /*!< USIC_CH PCR_ASCMode: FFIEN (Bit 7) */ 10042 #define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x80UL) /*!< USIC_CH PCR_ASCMode: FFIEN (Bitfield-Mask: 0x01) */ 10043 #define USIC_CH_PCR_ASCMode_SP_Pos (8UL) /*!< USIC_CH PCR_ASCMode: SP (Bit 8) */ 10044 #define USIC_CH_PCR_ASCMode_SP_Msk (0x1f00UL) /*!< USIC_CH PCR_ASCMode: SP (Bitfield-Mask: 0x1f) */ 10045 #define USIC_CH_PCR_ASCMode_PL_Pos (13UL) /*!< USIC_CH PCR_ASCMode: PL (Bit 13) */ 10046 #define USIC_CH_PCR_ASCMode_PL_Msk (0xe000UL) /*!< USIC_CH PCR_ASCMode: PL (Bitfield-Mask: 0x07) */ 10047 #define USIC_CH_PCR_ASCMode_RSTEN_Pos (16UL) /*!< USIC_CH PCR_ASCMode: RSTEN (Bit 16) */ 10048 #define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x10000UL) /*!< USIC_CH PCR_ASCMode: RSTEN (Bitfield-Mask: 0x01) */ 10049 #define USIC_CH_PCR_ASCMode_TSTEN_Pos (17UL) /*!< USIC_CH PCR_ASCMode: TSTEN (Bit 17) */ 10050 #define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x20000UL) /*!< USIC_CH PCR_ASCMode: TSTEN (Bitfield-Mask: 0x01) */ 10051 #define USIC_CH_PCR_ASCMode_MCLK_Pos (31UL) /*!< USIC_CH PCR_ASCMode: MCLK (Bit 31) */ 10052 #define USIC_CH_PCR_ASCMode_MCLK_Msk (0x80000000UL) /*!< USIC_CH PCR_ASCMode: MCLK (Bitfield-Mask: 0x01) */ 10053 10054 /* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */ 10055 #define USIC_CH_PCR_SSCMode_MSLSEN_Pos (0UL) /*!< USIC_CH PCR_SSCMode: MSLSEN (Bit 0) */ 10056 #define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x1UL) /*!< USIC_CH PCR_SSCMode: MSLSEN (Bitfield-Mask: 0x01) */ 10057 #define USIC_CH_PCR_SSCMode_SELCTR_Pos (1UL) /*!< USIC_CH PCR_SSCMode: SELCTR (Bit 1) */ 10058 #define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x2UL) /*!< USIC_CH PCR_SSCMode: SELCTR (Bitfield-Mask: 0x01) */ 10059 #define USIC_CH_PCR_SSCMode_SELINV_Pos (2UL) /*!< USIC_CH PCR_SSCMode: SELINV (Bit 2) */ 10060 #define USIC_CH_PCR_SSCMode_SELINV_Msk (0x4UL) /*!< USIC_CH PCR_SSCMode: SELINV (Bitfield-Mask: 0x01) */ 10061 #define USIC_CH_PCR_SSCMode_FEM_Pos (3UL) /*!< USIC_CH PCR_SSCMode: FEM (Bit 3) */ 10062 #define USIC_CH_PCR_SSCMode_FEM_Msk (0x8UL) /*!< USIC_CH PCR_SSCMode: FEM (Bitfield-Mask: 0x01) */ 10063 #define USIC_CH_PCR_SSCMode_CTQSEL1_Pos (4UL) /*!< USIC_CH PCR_SSCMode: CTQSEL1 (Bit 4) */ 10064 #define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x30UL) /*!< USIC_CH PCR_SSCMode: CTQSEL1 (Bitfield-Mask: 0x03) */ 10065 #define USIC_CH_PCR_SSCMode_PCTQ1_Pos (6UL) /*!< USIC_CH PCR_SSCMode: PCTQ1 (Bit 6) */ 10066 #define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0xc0UL) /*!< USIC_CH PCR_SSCMode: PCTQ1 (Bitfield-Mask: 0x03) */ 10067 #define USIC_CH_PCR_SSCMode_DCTQ1_Pos (8UL) /*!< USIC_CH PCR_SSCMode: DCTQ1 (Bit 8) */ 10068 #define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1f00UL) /*!< USIC_CH PCR_SSCMode: DCTQ1 (Bitfield-Mask: 0x1f) */ 10069 #define USIC_CH_PCR_SSCMode_PARIEN_Pos (13UL) /*!< USIC_CH PCR_SSCMode: PARIEN (Bit 13) */ 10070 #define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x2000UL) /*!< USIC_CH PCR_SSCMode: PARIEN (Bitfield-Mask: 0x01) */ 10071 #define USIC_CH_PCR_SSCMode_MSLSIEN_Pos (14UL) /*!< USIC_CH PCR_SSCMode: MSLSIEN (Bit 14) */ 10072 #define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x4000UL) /*!< USIC_CH PCR_SSCMode: MSLSIEN (Bitfield-Mask: 0x01) */ 10073 #define USIC_CH_PCR_SSCMode_DX2TIEN_Pos (15UL) /*!< USIC_CH PCR_SSCMode: DX2TIEN (Bit 15) */ 10074 #define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x8000UL) /*!< USIC_CH PCR_SSCMode: DX2TIEN (Bitfield-Mask: 0x01) */ 10075 #define USIC_CH_PCR_SSCMode_SELO_Pos (16UL) /*!< USIC_CH PCR_SSCMode: SELO (Bit 16) */ 10076 #define USIC_CH_PCR_SSCMode_SELO_Msk (0xff0000UL) /*!< USIC_CH PCR_SSCMode: SELO (Bitfield-Mask: 0xff) */ 10077 #define USIC_CH_PCR_SSCMode_TIWEN_Pos (24UL) /*!< USIC_CH PCR_SSCMode: TIWEN (Bit 24) */ 10078 #define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x1000000UL) /*!< USIC_CH PCR_SSCMode: TIWEN (Bitfield-Mask: 0x01) */ 10079 #define USIC_CH_PCR_SSCMode_MCLK_Pos (31UL) /*!< USIC_CH PCR_SSCMode: MCLK (Bit 31) */ 10080 #define USIC_CH_PCR_SSCMode_MCLK_Msk (0x80000000UL) /*!< USIC_CH PCR_SSCMode: MCLK (Bitfield-Mask: 0x01) */ 10081 10082 /* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */ 10083 #define USIC_CH_PCR_IICMode_SLAD_Pos (0UL) /*!< USIC_CH PCR_IICMode: SLAD (Bit 0) */ 10084 #define USIC_CH_PCR_IICMode_SLAD_Msk (0xffffUL) /*!< USIC_CH PCR_IICMode: SLAD (Bitfield-Mask: 0xffff) */ 10085 #define USIC_CH_PCR_IICMode_ACK00_Pos (16UL) /*!< USIC_CH PCR_IICMode: ACK00 (Bit 16) */ 10086 #define USIC_CH_PCR_IICMode_ACK00_Msk (0x10000UL) /*!< USIC_CH PCR_IICMode: ACK00 (Bitfield-Mask: 0x01) */ 10087 #define USIC_CH_PCR_IICMode_STIM_Pos (17UL) /*!< USIC_CH PCR_IICMode: STIM (Bit 17) */ 10088 #define USIC_CH_PCR_IICMode_STIM_Msk (0x20000UL) /*!< USIC_CH PCR_IICMode: STIM (Bitfield-Mask: 0x01) */ 10089 #define USIC_CH_PCR_IICMode_SCRIEN_Pos (18UL) /*!< USIC_CH PCR_IICMode: SCRIEN (Bit 18) */ 10090 #define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x40000UL) /*!< USIC_CH PCR_IICMode: SCRIEN (Bitfield-Mask: 0x01) */ 10091 #define USIC_CH_PCR_IICMode_RSCRIEN_Pos (19UL) /*!< USIC_CH PCR_IICMode: RSCRIEN (Bit 19) */ 10092 #define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x80000UL) /*!< USIC_CH PCR_IICMode: RSCRIEN (Bitfield-Mask: 0x01) */ 10093 #define USIC_CH_PCR_IICMode_PCRIEN_Pos (20UL) /*!< USIC_CH PCR_IICMode: PCRIEN (Bit 20) */ 10094 #define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x100000UL) /*!< USIC_CH PCR_IICMode: PCRIEN (Bitfield-Mask: 0x01) */ 10095 #define USIC_CH_PCR_IICMode_NACKIEN_Pos (21UL) /*!< USIC_CH PCR_IICMode: NACKIEN (Bit 21) */ 10096 #define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x200000UL) /*!< USIC_CH PCR_IICMode: NACKIEN (Bitfield-Mask: 0x01) */ 10097 #define USIC_CH_PCR_IICMode_ARLIEN_Pos (22UL) /*!< USIC_CH PCR_IICMode: ARLIEN (Bit 22) */ 10098 #define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x400000UL) /*!< USIC_CH PCR_IICMode: ARLIEN (Bitfield-Mask: 0x01) */ 10099 #define USIC_CH_PCR_IICMode_SRRIEN_Pos (23UL) /*!< USIC_CH PCR_IICMode: SRRIEN (Bit 23) */ 10100 #define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x800000UL) /*!< USIC_CH PCR_IICMode: SRRIEN (Bitfield-Mask: 0x01) */ 10101 #define USIC_CH_PCR_IICMode_ERRIEN_Pos (24UL) /*!< USIC_CH PCR_IICMode: ERRIEN (Bit 24) */ 10102 #define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x1000000UL) /*!< USIC_CH PCR_IICMode: ERRIEN (Bitfield-Mask: 0x01) */ 10103 #define USIC_CH_PCR_IICMode_SACKDIS_Pos (25UL) /*!< USIC_CH PCR_IICMode: SACKDIS (Bit 25) */ 10104 #define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x2000000UL) /*!< USIC_CH PCR_IICMode: SACKDIS (Bitfield-Mask: 0x01) */ 10105 #define USIC_CH_PCR_IICMode_HDEL_Pos (26UL) /*!< USIC_CH PCR_IICMode: HDEL (Bit 26) */ 10106 #define USIC_CH_PCR_IICMode_HDEL_Msk (0x3c000000UL) /*!< USIC_CH PCR_IICMode: HDEL (Bitfield-Mask: 0x0f) */ 10107 #define USIC_CH_PCR_IICMode_ACKIEN_Pos (30UL) /*!< USIC_CH PCR_IICMode: ACKIEN (Bit 30) */ 10108 #define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x40000000UL) /*!< USIC_CH PCR_IICMode: ACKIEN (Bitfield-Mask: 0x01) */ 10109 #define USIC_CH_PCR_IICMode_MCLK_Pos (31UL) /*!< USIC_CH PCR_IICMode: MCLK (Bit 31) */ 10110 #define USIC_CH_PCR_IICMode_MCLK_Msk (0x80000000UL) /*!< USIC_CH PCR_IICMode: MCLK (Bitfield-Mask: 0x01) */ 10111 10112 /* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */ 10113 #define USIC_CH_PCR_IISMode_WAGEN_Pos (0UL) /*!< USIC_CH PCR_IISMode: WAGEN (Bit 0) */ 10114 #define USIC_CH_PCR_IISMode_WAGEN_Msk (0x1UL) /*!< USIC_CH PCR_IISMode: WAGEN (Bitfield-Mask: 0x01) */ 10115 #define USIC_CH_PCR_IISMode_DTEN_Pos (1UL) /*!< USIC_CH PCR_IISMode: DTEN (Bit 1) */ 10116 #define USIC_CH_PCR_IISMode_DTEN_Msk (0x2UL) /*!< USIC_CH PCR_IISMode: DTEN (Bitfield-Mask: 0x01) */ 10117 #define USIC_CH_PCR_IISMode_SELINV_Pos (2UL) /*!< USIC_CH PCR_IISMode: SELINV (Bit 2) */ 10118 #define USIC_CH_PCR_IISMode_SELINV_Msk (0x4UL) /*!< USIC_CH PCR_IISMode: SELINV (Bitfield-Mask: 0x01) */ 10119 #define USIC_CH_PCR_IISMode_WAFEIEN_Pos (4UL) /*!< USIC_CH PCR_IISMode: WAFEIEN (Bit 4) */ 10120 #define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x10UL) /*!< USIC_CH PCR_IISMode: WAFEIEN (Bitfield-Mask: 0x01) */ 10121 #define USIC_CH_PCR_IISMode_WAREIEN_Pos (5UL) /*!< USIC_CH PCR_IISMode: WAREIEN (Bit 5) */ 10122 #define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x20UL) /*!< USIC_CH PCR_IISMode: WAREIEN (Bitfield-Mask: 0x01) */ 10123 #define USIC_CH_PCR_IISMode_ENDIEN_Pos (6UL) /*!< USIC_CH PCR_IISMode: ENDIEN (Bit 6) */ 10124 #define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x40UL) /*!< USIC_CH PCR_IISMode: ENDIEN (Bitfield-Mask: 0x01) */ 10125 #define USIC_CH_PCR_IISMode_DX2TIEN_Pos (15UL) /*!< USIC_CH PCR_IISMode: DX2TIEN (Bit 15) */ 10126 #define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x8000UL) /*!< USIC_CH PCR_IISMode: DX2TIEN (Bitfield-Mask: 0x01) */ 10127 #define USIC_CH_PCR_IISMode_TDEL_Pos (16UL) /*!< USIC_CH PCR_IISMode: TDEL (Bit 16) */ 10128 #define USIC_CH_PCR_IISMode_TDEL_Msk (0x3f0000UL) /*!< USIC_CH PCR_IISMode: TDEL (Bitfield-Mask: 0x3f) */ 10129 #define USIC_CH_PCR_IISMode_MCLK_Pos (31UL) /*!< USIC_CH PCR_IISMode: MCLK (Bit 31) */ 10130 #define USIC_CH_PCR_IISMode_MCLK_Msk (0x80000000UL) /*!< USIC_CH PCR_IISMode: MCLK (Bitfield-Mask: 0x01) */ 10131 10132 /* --------------------------------- USIC_CH_CCR -------------------------------- */ 10133 #define USIC_CH_CCR_MODE_Pos (0UL) /*!< USIC_CH CCR: MODE (Bit 0) */ 10134 #define USIC_CH_CCR_MODE_Msk (0xfUL) /*!< USIC_CH CCR: MODE (Bitfield-Mask: 0x0f) */ 10135 #define USIC_CH_CCR_HPCEN_Pos (6UL) /*!< USIC_CH CCR: HPCEN (Bit 6) */ 10136 #define USIC_CH_CCR_HPCEN_Msk (0xc0UL) /*!< USIC_CH CCR: HPCEN (Bitfield-Mask: 0x03) */ 10137 #define USIC_CH_CCR_PM_Pos (8UL) /*!< USIC_CH CCR: PM (Bit 8) */ 10138 #define USIC_CH_CCR_PM_Msk (0x300UL) /*!< USIC_CH CCR: PM (Bitfield-Mask: 0x03) */ 10139 #define USIC_CH_CCR_RSIEN_Pos (10UL) /*!< USIC_CH CCR: RSIEN (Bit 10) */ 10140 #define USIC_CH_CCR_RSIEN_Msk (0x400UL) /*!< USIC_CH CCR: RSIEN (Bitfield-Mask: 0x01) */ 10141 #define USIC_CH_CCR_DLIEN_Pos (11UL) /*!< USIC_CH CCR: DLIEN (Bit 11) */ 10142 #define USIC_CH_CCR_DLIEN_Msk (0x800UL) /*!< USIC_CH CCR: DLIEN (Bitfield-Mask: 0x01) */ 10143 #define USIC_CH_CCR_TSIEN_Pos (12UL) /*!< USIC_CH CCR: TSIEN (Bit 12) */ 10144 #define USIC_CH_CCR_TSIEN_Msk (0x1000UL) /*!< USIC_CH CCR: TSIEN (Bitfield-Mask: 0x01) */ 10145 #define USIC_CH_CCR_TBIEN_Pos (13UL) /*!< USIC_CH CCR: TBIEN (Bit 13) */ 10146 #define USIC_CH_CCR_TBIEN_Msk (0x2000UL) /*!< USIC_CH CCR: TBIEN (Bitfield-Mask: 0x01) */ 10147 #define USIC_CH_CCR_RIEN_Pos (14UL) /*!< USIC_CH CCR: RIEN (Bit 14) */ 10148 #define USIC_CH_CCR_RIEN_Msk (0x4000UL) /*!< USIC_CH CCR: RIEN (Bitfield-Mask: 0x01) */ 10149 #define USIC_CH_CCR_AIEN_Pos (15UL) /*!< USIC_CH CCR: AIEN (Bit 15) */ 10150 #define USIC_CH_CCR_AIEN_Msk (0x8000UL) /*!< USIC_CH CCR: AIEN (Bitfield-Mask: 0x01) */ 10151 #define USIC_CH_CCR_BRGIEN_Pos (16UL) /*!< USIC_CH CCR: BRGIEN (Bit 16) */ 10152 #define USIC_CH_CCR_BRGIEN_Msk (0x10000UL) /*!< USIC_CH CCR: BRGIEN (Bitfield-Mask: 0x01) */ 10153 10154 /* -------------------------------- USIC_CH_CMTR -------------------------------- */ 10155 #define USIC_CH_CMTR_CTV_Pos (0UL) /*!< USIC_CH CMTR: CTV (Bit 0) */ 10156 #define USIC_CH_CMTR_CTV_Msk (0x3ffUL) /*!< USIC_CH CMTR: CTV (Bitfield-Mask: 0x3ff) */ 10157 10158 /* --------------------------------- USIC_CH_PSR -------------------------------- */ 10159 #define USIC_CH_PSR_ST0_Pos (0UL) /*!< USIC_CH PSR: ST0 (Bit 0) */ 10160 #define USIC_CH_PSR_ST0_Msk (0x1UL) /*!< USIC_CH PSR: ST0 (Bitfield-Mask: 0x01) */ 10161 #define USIC_CH_PSR_ST1_Pos (1UL) /*!< USIC_CH PSR: ST1 (Bit 1) */ 10162 #define USIC_CH_PSR_ST1_Msk (0x2UL) /*!< USIC_CH PSR: ST1 (Bitfield-Mask: 0x01) */ 10163 #define USIC_CH_PSR_ST2_Pos (2UL) /*!< USIC_CH PSR: ST2 (Bit 2) */ 10164 #define USIC_CH_PSR_ST2_Msk (0x4UL) /*!< USIC_CH PSR: ST2 (Bitfield-Mask: 0x01) */ 10165 #define USIC_CH_PSR_ST3_Pos (3UL) /*!< USIC_CH PSR: ST3 (Bit 3) */ 10166 #define USIC_CH_PSR_ST3_Msk (0x8UL) /*!< USIC_CH PSR: ST3 (Bitfield-Mask: 0x01) */ 10167 #define USIC_CH_PSR_ST4_Pos (4UL) /*!< USIC_CH PSR: ST4 (Bit 4) */ 10168 #define USIC_CH_PSR_ST4_Msk (0x10UL) /*!< USIC_CH PSR: ST4 (Bitfield-Mask: 0x01) */ 10169 #define USIC_CH_PSR_ST5_Pos (5UL) /*!< USIC_CH PSR: ST5 (Bit 5) */ 10170 #define USIC_CH_PSR_ST5_Msk (0x20UL) /*!< USIC_CH PSR: ST5 (Bitfield-Mask: 0x01) */ 10171 #define USIC_CH_PSR_ST6_Pos (6UL) /*!< USIC_CH PSR: ST6 (Bit 6) */ 10172 #define USIC_CH_PSR_ST6_Msk (0x40UL) /*!< USIC_CH PSR: ST6 (Bitfield-Mask: 0x01) */ 10173 #define USIC_CH_PSR_ST7_Pos (7UL) /*!< USIC_CH PSR: ST7 (Bit 7) */ 10174 #define USIC_CH_PSR_ST7_Msk (0x80UL) /*!< USIC_CH PSR: ST7 (Bitfield-Mask: 0x01) */ 10175 #define USIC_CH_PSR_ST8_Pos (8UL) /*!< USIC_CH PSR: ST8 (Bit 8) */ 10176 #define USIC_CH_PSR_ST8_Msk (0x100UL) /*!< USIC_CH PSR: ST8 (Bitfield-Mask: 0x01) */ 10177 #define USIC_CH_PSR_ST9_Pos (9UL) /*!< USIC_CH PSR: ST9 (Bit 9) */ 10178 #define USIC_CH_PSR_ST9_Msk (0x200UL) /*!< USIC_CH PSR: ST9 (Bitfield-Mask: 0x01) */ 10179 #define USIC_CH_PSR_RSIF_Pos (10UL) /*!< USIC_CH PSR: RSIF (Bit 10) */ 10180 #define USIC_CH_PSR_RSIF_Msk (0x400UL) /*!< USIC_CH PSR: RSIF (Bitfield-Mask: 0x01) */ 10181 #define USIC_CH_PSR_DLIF_Pos (11UL) /*!< USIC_CH PSR: DLIF (Bit 11) */ 10182 #define USIC_CH_PSR_DLIF_Msk (0x800UL) /*!< USIC_CH PSR: DLIF (Bitfield-Mask: 0x01) */ 10183 #define USIC_CH_PSR_TSIF_Pos (12UL) /*!< USIC_CH PSR: TSIF (Bit 12) */ 10184 #define USIC_CH_PSR_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR: TSIF (Bitfield-Mask: 0x01) */ 10185 #define USIC_CH_PSR_TBIF_Pos (13UL) /*!< USIC_CH PSR: TBIF (Bit 13) */ 10186 #define USIC_CH_PSR_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR: TBIF (Bitfield-Mask: 0x01) */ 10187 #define USIC_CH_PSR_RIF_Pos (14UL) /*!< USIC_CH PSR: RIF (Bit 14) */ 10188 #define USIC_CH_PSR_RIF_Msk (0x4000UL) /*!< USIC_CH PSR: RIF (Bitfield-Mask: 0x01) */ 10189 #define USIC_CH_PSR_AIF_Pos (15UL) /*!< USIC_CH PSR: AIF (Bit 15) */ 10190 #define USIC_CH_PSR_AIF_Msk (0x8000UL) /*!< USIC_CH PSR: AIF (Bitfield-Mask: 0x01) */ 10191 #define USIC_CH_PSR_BRGIF_Pos (16UL) /*!< USIC_CH PSR: BRGIF (Bit 16) */ 10192 #define USIC_CH_PSR_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR: BRGIF (Bitfield-Mask: 0x01) */ 10193 10194 /* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */ 10195 #define USIC_CH_PSR_ASCMode_TXIDLE_Pos (0UL) /*!< USIC_CH PSR_ASCMode: TXIDLE (Bit 0) */ 10196 #define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x1UL) /*!< USIC_CH PSR_ASCMode: TXIDLE (Bitfield-Mask: 0x01) */ 10197 #define USIC_CH_PSR_ASCMode_RXIDLE_Pos (1UL) /*!< USIC_CH PSR_ASCMode: RXIDLE (Bit 1) */ 10198 #define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x2UL) /*!< USIC_CH PSR_ASCMode: RXIDLE (Bitfield-Mask: 0x01) */ 10199 #define USIC_CH_PSR_ASCMode_SBD_Pos (2UL) /*!< USIC_CH PSR_ASCMode: SBD (Bit 2) */ 10200 #define USIC_CH_PSR_ASCMode_SBD_Msk (0x4UL) /*!< USIC_CH PSR_ASCMode: SBD (Bitfield-Mask: 0x01) */ 10201 #define USIC_CH_PSR_ASCMode_COL_Pos (3UL) /*!< USIC_CH PSR_ASCMode: COL (Bit 3) */ 10202 #define USIC_CH_PSR_ASCMode_COL_Msk (0x8UL) /*!< USIC_CH PSR_ASCMode: COL (Bitfield-Mask: 0x01) */ 10203 #define USIC_CH_PSR_ASCMode_RNS_Pos (4UL) /*!< USIC_CH PSR_ASCMode: RNS (Bit 4) */ 10204 #define USIC_CH_PSR_ASCMode_RNS_Msk (0x10UL) /*!< USIC_CH PSR_ASCMode: RNS (Bitfield-Mask: 0x01) */ 10205 #define USIC_CH_PSR_ASCMode_FER0_Pos (5UL) /*!< USIC_CH PSR_ASCMode: FER0 (Bit 5) */ 10206 #define USIC_CH_PSR_ASCMode_FER0_Msk (0x20UL) /*!< USIC_CH PSR_ASCMode: FER0 (Bitfield-Mask: 0x01) */ 10207 #define USIC_CH_PSR_ASCMode_FER1_Pos (6UL) /*!< USIC_CH PSR_ASCMode: FER1 (Bit 6) */ 10208 #define USIC_CH_PSR_ASCMode_FER1_Msk (0x40UL) /*!< USIC_CH PSR_ASCMode: FER1 (Bitfield-Mask: 0x01) */ 10209 #define USIC_CH_PSR_ASCMode_RFF_Pos (7UL) /*!< USIC_CH PSR_ASCMode: RFF (Bit 7) */ 10210 #define USIC_CH_PSR_ASCMode_RFF_Msk (0x80UL) /*!< USIC_CH PSR_ASCMode: RFF (Bitfield-Mask: 0x01) */ 10211 #define USIC_CH_PSR_ASCMode_TFF_Pos (8UL) /*!< USIC_CH PSR_ASCMode: TFF (Bit 8) */ 10212 #define USIC_CH_PSR_ASCMode_TFF_Msk (0x100UL) /*!< USIC_CH PSR_ASCMode: TFF (Bitfield-Mask: 0x01) */ 10213 #define USIC_CH_PSR_ASCMode_BUSY_Pos (9UL) /*!< USIC_CH PSR_ASCMode: BUSY (Bit 9) */ 10214 #define USIC_CH_PSR_ASCMode_BUSY_Msk (0x200UL) /*!< USIC_CH PSR_ASCMode: BUSY (Bitfield-Mask: 0x01) */ 10215 #define USIC_CH_PSR_ASCMode_RSIF_Pos (10UL) /*!< USIC_CH PSR_ASCMode: RSIF (Bit 10) */ 10216 #define USIC_CH_PSR_ASCMode_RSIF_Msk (0x400UL) /*!< USIC_CH PSR_ASCMode: RSIF (Bitfield-Mask: 0x01) */ 10217 #define USIC_CH_PSR_ASCMode_DLIF_Pos (11UL) /*!< USIC_CH PSR_ASCMode: DLIF (Bit 11) */ 10218 #define USIC_CH_PSR_ASCMode_DLIF_Msk (0x800UL) /*!< USIC_CH PSR_ASCMode: DLIF (Bitfield-Mask: 0x01) */ 10219 #define USIC_CH_PSR_ASCMode_TSIF_Pos (12UL) /*!< USIC_CH PSR_ASCMode: TSIF (Bit 12) */ 10220 #define USIC_CH_PSR_ASCMode_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR_ASCMode: TSIF (Bitfield-Mask: 0x01) */ 10221 #define USIC_CH_PSR_ASCMode_TBIF_Pos (13UL) /*!< USIC_CH PSR_ASCMode: TBIF (Bit 13) */ 10222 #define USIC_CH_PSR_ASCMode_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR_ASCMode: TBIF (Bitfield-Mask: 0x01) */ 10223 #define USIC_CH_PSR_ASCMode_RIF_Pos (14UL) /*!< USIC_CH PSR_ASCMode: RIF (Bit 14) */ 10224 #define USIC_CH_PSR_ASCMode_RIF_Msk (0x4000UL) /*!< USIC_CH PSR_ASCMode: RIF (Bitfield-Mask: 0x01) */ 10225 #define USIC_CH_PSR_ASCMode_AIF_Pos (15UL) /*!< USIC_CH PSR_ASCMode: AIF (Bit 15) */ 10226 #define USIC_CH_PSR_ASCMode_AIF_Msk (0x8000UL) /*!< USIC_CH PSR_ASCMode: AIF (Bitfield-Mask: 0x01) */ 10227 #define USIC_CH_PSR_ASCMode_BRGIF_Pos (16UL) /*!< USIC_CH PSR_ASCMode: BRGIF (Bit 16) */ 10228 #define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR_ASCMode: BRGIF (Bitfield-Mask: 0x01) */ 10229 10230 /* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */ 10231 #define USIC_CH_PSR_SSCMode_MSLS_Pos (0UL) /*!< USIC_CH PSR_SSCMode: MSLS (Bit 0) */ 10232 #define USIC_CH_PSR_SSCMode_MSLS_Msk (0x1UL) /*!< USIC_CH PSR_SSCMode: MSLS (Bitfield-Mask: 0x01) */ 10233 #define USIC_CH_PSR_SSCMode_DX2S_Pos (1UL) /*!< USIC_CH PSR_SSCMode: DX2S (Bit 1) */ 10234 #define USIC_CH_PSR_SSCMode_DX2S_Msk (0x2UL) /*!< USIC_CH PSR_SSCMode: DX2S (Bitfield-Mask: 0x01) */ 10235 #define USIC_CH_PSR_SSCMode_MSLSEV_Pos (2UL) /*!< USIC_CH PSR_SSCMode: MSLSEV (Bit 2) */ 10236 #define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x4UL) /*!< USIC_CH PSR_SSCMode: MSLSEV (Bitfield-Mask: 0x01) */ 10237 #define USIC_CH_PSR_SSCMode_DX2TEV_Pos (3UL) /*!< USIC_CH PSR_SSCMode: DX2TEV (Bit 3) */ 10238 #define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x8UL) /*!< USIC_CH PSR_SSCMode: DX2TEV (Bitfield-Mask: 0x01) */ 10239 #define USIC_CH_PSR_SSCMode_PARERR_Pos (4UL) /*!< USIC_CH PSR_SSCMode: PARERR (Bit 4) */ 10240 #define USIC_CH_PSR_SSCMode_PARERR_Msk (0x10UL) /*!< USIC_CH PSR_SSCMode: PARERR (Bitfield-Mask: 0x01) */ 10241 #define USIC_CH_PSR_SSCMode_RSIF_Pos (10UL) /*!< USIC_CH PSR_SSCMode: RSIF (Bit 10) */ 10242 #define USIC_CH_PSR_SSCMode_RSIF_Msk (0x400UL) /*!< USIC_CH PSR_SSCMode: RSIF (Bitfield-Mask: 0x01) */ 10243 #define USIC_CH_PSR_SSCMode_DLIF_Pos (11UL) /*!< USIC_CH PSR_SSCMode: DLIF (Bit 11) */ 10244 #define USIC_CH_PSR_SSCMode_DLIF_Msk (0x800UL) /*!< USIC_CH PSR_SSCMode: DLIF (Bitfield-Mask: 0x01) */ 10245 #define USIC_CH_PSR_SSCMode_TSIF_Pos (12UL) /*!< USIC_CH PSR_SSCMode: TSIF (Bit 12) */ 10246 #define USIC_CH_PSR_SSCMode_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR_SSCMode: TSIF (Bitfield-Mask: 0x01) */ 10247 #define USIC_CH_PSR_SSCMode_TBIF_Pos (13UL) /*!< USIC_CH PSR_SSCMode: TBIF (Bit 13) */ 10248 #define USIC_CH_PSR_SSCMode_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR_SSCMode: TBIF (Bitfield-Mask: 0x01) */ 10249 #define USIC_CH_PSR_SSCMode_RIF_Pos (14UL) /*!< USIC_CH PSR_SSCMode: RIF (Bit 14) */ 10250 #define USIC_CH_PSR_SSCMode_RIF_Msk (0x4000UL) /*!< USIC_CH PSR_SSCMode: RIF (Bitfield-Mask: 0x01) */ 10251 #define USIC_CH_PSR_SSCMode_AIF_Pos (15UL) /*!< USIC_CH PSR_SSCMode: AIF (Bit 15) */ 10252 #define USIC_CH_PSR_SSCMode_AIF_Msk (0x8000UL) /*!< USIC_CH PSR_SSCMode: AIF (Bitfield-Mask: 0x01) */ 10253 #define USIC_CH_PSR_SSCMode_BRGIF_Pos (16UL) /*!< USIC_CH PSR_SSCMode: BRGIF (Bit 16) */ 10254 #define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR_SSCMode: BRGIF (Bitfield-Mask: 0x01) */ 10255 10256 /* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */ 10257 #define USIC_CH_PSR_IICMode_SLSEL_Pos (0UL) /*!< USIC_CH PSR_IICMode: SLSEL (Bit 0) */ 10258 #define USIC_CH_PSR_IICMode_SLSEL_Msk (0x1UL) /*!< USIC_CH PSR_IICMode: SLSEL (Bitfield-Mask: 0x01) */ 10259 #define USIC_CH_PSR_IICMode_WTDF_Pos (1UL) /*!< USIC_CH PSR_IICMode: WTDF (Bit 1) */ 10260 #define USIC_CH_PSR_IICMode_WTDF_Msk (0x2UL) /*!< USIC_CH PSR_IICMode: WTDF (Bitfield-Mask: 0x01) */ 10261 #define USIC_CH_PSR_IICMode_SCR_Pos (2UL) /*!< USIC_CH PSR_IICMode: SCR (Bit 2) */ 10262 #define USIC_CH_PSR_IICMode_SCR_Msk (0x4UL) /*!< USIC_CH PSR_IICMode: SCR (Bitfield-Mask: 0x01) */ 10263 #define USIC_CH_PSR_IICMode_RSCR_Pos (3UL) /*!< USIC_CH PSR_IICMode: RSCR (Bit 3) */ 10264 #define USIC_CH_PSR_IICMode_RSCR_Msk (0x8UL) /*!< USIC_CH PSR_IICMode: RSCR (Bitfield-Mask: 0x01) */ 10265 #define USIC_CH_PSR_IICMode_PCR_Pos (4UL) /*!< USIC_CH PSR_IICMode: PCR (Bit 4) */ 10266 #define USIC_CH_PSR_IICMode_PCR_Msk (0x10UL) /*!< USIC_CH PSR_IICMode: PCR (Bitfield-Mask: 0x01) */ 10267 #define USIC_CH_PSR_IICMode_NACK_Pos (5UL) /*!< USIC_CH PSR_IICMode: NACK (Bit 5) */ 10268 #define USIC_CH_PSR_IICMode_NACK_Msk (0x20UL) /*!< USIC_CH PSR_IICMode: NACK (Bitfield-Mask: 0x01) */ 10269 #define USIC_CH_PSR_IICMode_ARL_Pos (6UL) /*!< USIC_CH PSR_IICMode: ARL (Bit 6) */ 10270 #define USIC_CH_PSR_IICMode_ARL_Msk (0x40UL) /*!< USIC_CH PSR_IICMode: ARL (Bitfield-Mask: 0x01) */ 10271 #define USIC_CH_PSR_IICMode_SRR_Pos (7UL) /*!< USIC_CH PSR_IICMode: SRR (Bit 7) */ 10272 #define USIC_CH_PSR_IICMode_SRR_Msk (0x80UL) /*!< USIC_CH PSR_IICMode: SRR (Bitfield-Mask: 0x01) */ 10273 #define USIC_CH_PSR_IICMode_ERR_Pos (8UL) /*!< USIC_CH PSR_IICMode: ERR (Bit 8) */ 10274 #define USIC_CH_PSR_IICMode_ERR_Msk (0x100UL) /*!< USIC_CH PSR_IICMode: ERR (Bitfield-Mask: 0x01) */ 10275 #define USIC_CH_PSR_IICMode_ACK_Pos (9UL) /*!< USIC_CH PSR_IICMode: ACK (Bit 9) */ 10276 #define USIC_CH_PSR_IICMode_ACK_Msk (0x200UL) /*!< USIC_CH PSR_IICMode: ACK (Bitfield-Mask: 0x01) */ 10277 #define USIC_CH_PSR_IICMode_RSIF_Pos (10UL) /*!< USIC_CH PSR_IICMode: RSIF (Bit 10) */ 10278 #define USIC_CH_PSR_IICMode_RSIF_Msk (0x400UL) /*!< USIC_CH PSR_IICMode: RSIF (Bitfield-Mask: 0x01) */ 10279 #define USIC_CH_PSR_IICMode_DLIF_Pos (11UL) /*!< USIC_CH PSR_IICMode: DLIF (Bit 11) */ 10280 #define USIC_CH_PSR_IICMode_DLIF_Msk (0x800UL) /*!< USIC_CH PSR_IICMode: DLIF (Bitfield-Mask: 0x01) */ 10281 #define USIC_CH_PSR_IICMode_TSIF_Pos (12UL) /*!< USIC_CH PSR_IICMode: TSIF (Bit 12) */ 10282 #define USIC_CH_PSR_IICMode_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR_IICMode: TSIF (Bitfield-Mask: 0x01) */ 10283 #define USIC_CH_PSR_IICMode_TBIF_Pos (13UL) /*!< USIC_CH PSR_IICMode: TBIF (Bit 13) */ 10284 #define USIC_CH_PSR_IICMode_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR_IICMode: TBIF (Bitfield-Mask: 0x01) */ 10285 #define USIC_CH_PSR_IICMode_RIF_Pos (14UL) /*!< USIC_CH PSR_IICMode: RIF (Bit 14) */ 10286 #define USIC_CH_PSR_IICMode_RIF_Msk (0x4000UL) /*!< USIC_CH PSR_IICMode: RIF (Bitfield-Mask: 0x01) */ 10287 #define USIC_CH_PSR_IICMode_AIF_Pos (15UL) /*!< USIC_CH PSR_IICMode: AIF (Bit 15) */ 10288 #define USIC_CH_PSR_IICMode_AIF_Msk (0x8000UL) /*!< USIC_CH PSR_IICMode: AIF (Bitfield-Mask: 0x01) */ 10289 #define USIC_CH_PSR_IICMode_BRGIF_Pos (16UL) /*!< USIC_CH PSR_IICMode: BRGIF (Bit 16) */ 10290 #define USIC_CH_PSR_IICMode_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR_IICMode: BRGIF (Bitfield-Mask: 0x01) */ 10291 10292 /* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */ 10293 #define USIC_CH_PSR_IISMode_WA_Pos (0UL) /*!< USIC_CH PSR_IISMode: WA (Bit 0) */ 10294 #define USIC_CH_PSR_IISMode_WA_Msk (0x1UL) /*!< USIC_CH PSR_IISMode: WA (Bitfield-Mask: 0x01) */ 10295 #define USIC_CH_PSR_IISMode_DX2S_Pos (1UL) /*!< USIC_CH PSR_IISMode: DX2S (Bit 1) */ 10296 #define USIC_CH_PSR_IISMode_DX2S_Msk (0x2UL) /*!< USIC_CH PSR_IISMode: DX2S (Bitfield-Mask: 0x01) */ 10297 #define USIC_CH_PSR_IISMode_DX2TEV_Pos (3UL) /*!< USIC_CH PSR_IISMode: DX2TEV (Bit 3) */ 10298 #define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x8UL) /*!< USIC_CH PSR_IISMode: DX2TEV (Bitfield-Mask: 0x01) */ 10299 #define USIC_CH_PSR_IISMode_WAFE_Pos (4UL) /*!< USIC_CH PSR_IISMode: WAFE (Bit 4) */ 10300 #define USIC_CH_PSR_IISMode_WAFE_Msk (0x10UL) /*!< USIC_CH PSR_IISMode: WAFE (Bitfield-Mask: 0x01) */ 10301 #define USIC_CH_PSR_IISMode_WARE_Pos (5UL) /*!< USIC_CH PSR_IISMode: WARE (Bit 5) */ 10302 #define USIC_CH_PSR_IISMode_WARE_Msk (0x20UL) /*!< USIC_CH PSR_IISMode: WARE (Bitfield-Mask: 0x01) */ 10303 #define USIC_CH_PSR_IISMode_END_Pos (6UL) /*!< USIC_CH PSR_IISMode: END (Bit 6) */ 10304 #define USIC_CH_PSR_IISMode_END_Msk (0x40UL) /*!< USIC_CH PSR_IISMode: END (Bitfield-Mask: 0x01) */ 10305 #define USIC_CH_PSR_IISMode_RSIF_Pos (10UL) /*!< USIC_CH PSR_IISMode: RSIF (Bit 10) */ 10306 #define USIC_CH_PSR_IISMode_RSIF_Msk (0x400UL) /*!< USIC_CH PSR_IISMode: RSIF (Bitfield-Mask: 0x01) */ 10307 #define USIC_CH_PSR_IISMode_DLIF_Pos (11UL) /*!< USIC_CH PSR_IISMode: DLIF (Bit 11) */ 10308 #define USIC_CH_PSR_IISMode_DLIF_Msk (0x800UL) /*!< USIC_CH PSR_IISMode: DLIF (Bitfield-Mask: 0x01) */ 10309 #define USIC_CH_PSR_IISMode_TSIF_Pos (12UL) /*!< USIC_CH PSR_IISMode: TSIF (Bit 12) */ 10310 #define USIC_CH_PSR_IISMode_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR_IISMode: TSIF (Bitfield-Mask: 0x01) */ 10311 #define USIC_CH_PSR_IISMode_TBIF_Pos (13UL) /*!< USIC_CH PSR_IISMode: TBIF (Bit 13) */ 10312 #define USIC_CH_PSR_IISMode_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR_IISMode: TBIF (Bitfield-Mask: 0x01) */ 10313 #define USIC_CH_PSR_IISMode_RIF_Pos (14UL) /*!< USIC_CH PSR_IISMode: RIF (Bit 14) */ 10314 #define USIC_CH_PSR_IISMode_RIF_Msk (0x4000UL) /*!< USIC_CH PSR_IISMode: RIF (Bitfield-Mask: 0x01) */ 10315 #define USIC_CH_PSR_IISMode_AIF_Pos (15UL) /*!< USIC_CH PSR_IISMode: AIF (Bit 15) */ 10316 #define USIC_CH_PSR_IISMode_AIF_Msk (0x8000UL) /*!< USIC_CH PSR_IISMode: AIF (Bitfield-Mask: 0x01) */ 10317 #define USIC_CH_PSR_IISMode_BRGIF_Pos (16UL) /*!< USIC_CH PSR_IISMode: BRGIF (Bit 16) */ 10318 #define USIC_CH_PSR_IISMode_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR_IISMode: BRGIF (Bitfield-Mask: 0x01) */ 10319 10320 /* -------------------------------- USIC_CH_PSCR -------------------------------- */ 10321 #define USIC_CH_PSCR_CST0_Pos (0UL) /*!< USIC_CH PSCR: CST0 (Bit 0) */ 10322 #define USIC_CH_PSCR_CST0_Msk (0x1UL) /*!< USIC_CH PSCR: CST0 (Bitfield-Mask: 0x01) */ 10323 #define USIC_CH_PSCR_CST1_Pos (1UL) /*!< USIC_CH PSCR: CST1 (Bit 1) */ 10324 #define USIC_CH_PSCR_CST1_Msk (0x2UL) /*!< USIC_CH PSCR: CST1 (Bitfield-Mask: 0x01) */ 10325 #define USIC_CH_PSCR_CST2_Pos (2UL) /*!< USIC_CH PSCR: CST2 (Bit 2) */ 10326 #define USIC_CH_PSCR_CST2_Msk (0x4UL) /*!< USIC_CH PSCR: CST2 (Bitfield-Mask: 0x01) */ 10327 #define USIC_CH_PSCR_CST3_Pos (3UL) /*!< USIC_CH PSCR: CST3 (Bit 3) */ 10328 #define USIC_CH_PSCR_CST3_Msk (0x8UL) /*!< USIC_CH PSCR: CST3 (Bitfield-Mask: 0x01) */ 10329 #define USIC_CH_PSCR_CST4_Pos (4UL) /*!< USIC_CH PSCR: CST4 (Bit 4) */ 10330 #define USIC_CH_PSCR_CST4_Msk (0x10UL) /*!< USIC_CH PSCR: CST4 (Bitfield-Mask: 0x01) */ 10331 #define USIC_CH_PSCR_CST5_Pos (5UL) /*!< USIC_CH PSCR: CST5 (Bit 5) */ 10332 #define USIC_CH_PSCR_CST5_Msk (0x20UL) /*!< USIC_CH PSCR: CST5 (Bitfield-Mask: 0x01) */ 10333 #define USIC_CH_PSCR_CST6_Pos (6UL) /*!< USIC_CH PSCR: CST6 (Bit 6) */ 10334 #define USIC_CH_PSCR_CST6_Msk (0x40UL) /*!< USIC_CH PSCR: CST6 (Bitfield-Mask: 0x01) */ 10335 #define USIC_CH_PSCR_CST7_Pos (7UL) /*!< USIC_CH PSCR: CST7 (Bit 7) */ 10336 #define USIC_CH_PSCR_CST7_Msk (0x80UL) /*!< USIC_CH PSCR: CST7 (Bitfield-Mask: 0x01) */ 10337 #define USIC_CH_PSCR_CST8_Pos (8UL) /*!< USIC_CH PSCR: CST8 (Bit 8) */ 10338 #define USIC_CH_PSCR_CST8_Msk (0x100UL) /*!< USIC_CH PSCR: CST8 (Bitfield-Mask: 0x01) */ 10339 #define USIC_CH_PSCR_CST9_Pos (9UL) /*!< USIC_CH PSCR: CST9 (Bit 9) */ 10340 #define USIC_CH_PSCR_CST9_Msk (0x200UL) /*!< USIC_CH PSCR: CST9 (Bitfield-Mask: 0x01) */ 10341 #define USIC_CH_PSCR_CRSIF_Pos (10UL) /*!< USIC_CH PSCR: CRSIF (Bit 10) */ 10342 #define USIC_CH_PSCR_CRSIF_Msk (0x400UL) /*!< USIC_CH PSCR: CRSIF (Bitfield-Mask: 0x01) */ 10343 #define USIC_CH_PSCR_CDLIF_Pos (11UL) /*!< USIC_CH PSCR: CDLIF (Bit 11) */ 10344 #define USIC_CH_PSCR_CDLIF_Msk (0x800UL) /*!< USIC_CH PSCR: CDLIF (Bitfield-Mask: 0x01) */ 10345 #define USIC_CH_PSCR_CTSIF_Pos (12UL) /*!< USIC_CH PSCR: CTSIF (Bit 12) */ 10346 #define USIC_CH_PSCR_CTSIF_Msk (0x1000UL) /*!< USIC_CH PSCR: CTSIF (Bitfield-Mask: 0x01) */ 10347 #define USIC_CH_PSCR_CTBIF_Pos (13UL) /*!< USIC_CH PSCR: CTBIF (Bit 13) */ 10348 #define USIC_CH_PSCR_CTBIF_Msk (0x2000UL) /*!< USIC_CH PSCR: CTBIF (Bitfield-Mask: 0x01) */ 10349 #define USIC_CH_PSCR_CRIF_Pos (14UL) /*!< USIC_CH PSCR: CRIF (Bit 14) */ 10350 #define USIC_CH_PSCR_CRIF_Msk (0x4000UL) /*!< USIC_CH PSCR: CRIF (Bitfield-Mask: 0x01) */ 10351 #define USIC_CH_PSCR_CAIF_Pos (15UL) /*!< USIC_CH PSCR: CAIF (Bit 15) */ 10352 #define USIC_CH_PSCR_CAIF_Msk (0x8000UL) /*!< USIC_CH PSCR: CAIF (Bitfield-Mask: 0x01) */ 10353 #define USIC_CH_PSCR_CBRGIF_Pos (16UL) /*!< USIC_CH PSCR: CBRGIF (Bit 16) */ 10354 #define USIC_CH_PSCR_CBRGIF_Msk (0x10000UL) /*!< USIC_CH PSCR: CBRGIF (Bitfield-Mask: 0x01) */ 10355 10356 /* ------------------------------- USIC_CH_RBUFSR ------------------------------- */ 10357 #define USIC_CH_RBUFSR_WLEN_Pos (0UL) /*!< USIC_CH RBUFSR: WLEN (Bit 0) */ 10358 #define USIC_CH_RBUFSR_WLEN_Msk (0xfUL) /*!< USIC_CH RBUFSR: WLEN (Bitfield-Mask: 0x0f) */ 10359 #define USIC_CH_RBUFSR_SOF_Pos (6UL) /*!< USIC_CH RBUFSR: SOF (Bit 6) */ 10360 #define USIC_CH_RBUFSR_SOF_Msk (0x40UL) /*!< USIC_CH RBUFSR: SOF (Bitfield-Mask: 0x01) */ 10361 #define USIC_CH_RBUFSR_PAR_Pos (8UL) /*!< USIC_CH RBUFSR: PAR (Bit 8) */ 10362 #define USIC_CH_RBUFSR_PAR_Msk (0x100UL) /*!< USIC_CH RBUFSR: PAR (Bitfield-Mask: 0x01) */ 10363 #define USIC_CH_RBUFSR_PERR_Pos (9UL) /*!< USIC_CH RBUFSR: PERR (Bit 9) */ 10364 #define USIC_CH_RBUFSR_PERR_Msk (0x200UL) /*!< USIC_CH RBUFSR: PERR (Bitfield-Mask: 0x01) */ 10365 #define USIC_CH_RBUFSR_RDV0_Pos (13UL) /*!< USIC_CH RBUFSR: RDV0 (Bit 13) */ 10366 #define USIC_CH_RBUFSR_RDV0_Msk (0x2000UL) /*!< USIC_CH RBUFSR: RDV0 (Bitfield-Mask: 0x01) */ 10367 #define USIC_CH_RBUFSR_RDV1_Pos (14UL) /*!< USIC_CH RBUFSR: RDV1 (Bit 14) */ 10368 #define USIC_CH_RBUFSR_RDV1_Msk (0x4000UL) /*!< USIC_CH RBUFSR: RDV1 (Bitfield-Mask: 0x01) */ 10369 #define USIC_CH_RBUFSR_DS_Pos (15UL) /*!< USIC_CH RBUFSR: DS (Bit 15) */ 10370 #define USIC_CH_RBUFSR_DS_Msk (0x8000UL) /*!< USIC_CH RBUFSR: DS (Bitfield-Mask: 0x01) */ 10371 10372 /* -------------------------------- USIC_CH_RBUF -------------------------------- */ 10373 #define USIC_CH_RBUF_DSR_Pos (0UL) /*!< USIC_CH RBUF: DSR (Bit 0) */ 10374 #define USIC_CH_RBUF_DSR_Msk (0xffffUL) /*!< USIC_CH RBUF: DSR (Bitfield-Mask: 0xffff) */ 10375 10376 /* -------------------------------- USIC_CH_RBUFD ------------------------------- */ 10377 #define USIC_CH_RBUFD_DSR_Pos (0UL) /*!< USIC_CH RBUFD: DSR (Bit 0) */ 10378 #define USIC_CH_RBUFD_DSR_Msk (0xffffUL) /*!< USIC_CH RBUFD: DSR (Bitfield-Mask: 0xffff) */ 10379 10380 /* -------------------------------- USIC_CH_RBUF0 ------------------------------- */ 10381 #define USIC_CH_RBUF0_DSR0_Pos (0UL) /*!< USIC_CH RBUF0: DSR0 (Bit 0) */ 10382 #define USIC_CH_RBUF0_DSR0_Msk (0xffffUL) /*!< USIC_CH RBUF0: DSR0 (Bitfield-Mask: 0xffff) */ 10383 10384 /* -------------------------------- USIC_CH_RBUF1 ------------------------------- */ 10385 #define USIC_CH_RBUF1_DSR1_Pos (0UL) /*!< USIC_CH RBUF1: DSR1 (Bit 0) */ 10386 #define USIC_CH_RBUF1_DSR1_Msk (0xffffUL) /*!< USIC_CH RBUF1: DSR1 (Bitfield-Mask: 0xffff) */ 10387 10388 /* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */ 10389 #define USIC_CH_RBUF01SR_WLEN0_Pos (0UL) /*!< USIC_CH RBUF01SR: WLEN0 (Bit 0) */ 10390 #define USIC_CH_RBUF01SR_WLEN0_Msk (0xfUL) /*!< USIC_CH RBUF01SR: WLEN0 (Bitfield-Mask: 0x0f) */ 10391 #define USIC_CH_RBUF01SR_SOF0_Pos (6UL) /*!< USIC_CH RBUF01SR: SOF0 (Bit 6) */ 10392 #define USIC_CH_RBUF01SR_SOF0_Msk (0x40UL) /*!< USIC_CH RBUF01SR: SOF0 (Bitfield-Mask: 0x01) */ 10393 #define USIC_CH_RBUF01SR_PAR0_Pos (8UL) /*!< USIC_CH RBUF01SR: PAR0 (Bit 8) */ 10394 #define USIC_CH_RBUF01SR_PAR0_Msk (0x100UL) /*!< USIC_CH RBUF01SR: PAR0 (Bitfield-Mask: 0x01) */ 10395 #define USIC_CH_RBUF01SR_PERR0_Pos (9UL) /*!< USIC_CH RBUF01SR: PERR0 (Bit 9) */ 10396 #define USIC_CH_RBUF01SR_PERR0_Msk (0x200UL) /*!< USIC_CH RBUF01SR: PERR0 (Bitfield-Mask: 0x01) */ 10397 #define USIC_CH_RBUF01SR_RDV00_Pos (13UL) /*!< USIC_CH RBUF01SR: RDV00 (Bit 13) */ 10398 #define USIC_CH_RBUF01SR_RDV00_Msk (0x2000UL) /*!< USIC_CH RBUF01SR: RDV00 (Bitfield-Mask: 0x01) */ 10399 #define USIC_CH_RBUF01SR_RDV01_Pos (14UL) /*!< USIC_CH RBUF01SR: RDV01 (Bit 14) */ 10400 #define USIC_CH_RBUF01SR_RDV01_Msk (0x4000UL) /*!< USIC_CH RBUF01SR: RDV01 (Bitfield-Mask: 0x01) */ 10401 #define USIC_CH_RBUF01SR_DS0_Pos (15UL) /*!< USIC_CH RBUF01SR: DS0 (Bit 15) */ 10402 #define USIC_CH_RBUF01SR_DS0_Msk (0x8000UL) /*!< USIC_CH RBUF01SR: DS0 (Bitfield-Mask: 0x01) */ 10403 #define USIC_CH_RBUF01SR_WLEN1_Pos (16UL) /*!< USIC_CH RBUF01SR: WLEN1 (Bit 16) */ 10404 #define USIC_CH_RBUF01SR_WLEN1_Msk (0xf0000UL) /*!< USIC_CH RBUF01SR: WLEN1 (Bitfield-Mask: 0x0f) */ 10405 #define USIC_CH_RBUF01SR_SOF1_Pos (22UL) /*!< USIC_CH RBUF01SR: SOF1 (Bit 22) */ 10406 #define USIC_CH_RBUF01SR_SOF1_Msk (0x400000UL) /*!< USIC_CH RBUF01SR: SOF1 (Bitfield-Mask: 0x01) */ 10407 #define USIC_CH_RBUF01SR_PAR1_Pos (24UL) /*!< USIC_CH RBUF01SR: PAR1 (Bit 24) */ 10408 #define USIC_CH_RBUF01SR_PAR1_Msk (0x1000000UL) /*!< USIC_CH RBUF01SR: PAR1 (Bitfield-Mask: 0x01) */ 10409 #define USIC_CH_RBUF01SR_PERR1_Pos (25UL) /*!< USIC_CH RBUF01SR: PERR1 (Bit 25) */ 10410 #define USIC_CH_RBUF01SR_PERR1_Msk (0x2000000UL) /*!< USIC_CH RBUF01SR: PERR1 (Bitfield-Mask: 0x01) */ 10411 #define USIC_CH_RBUF01SR_RDV10_Pos (29UL) /*!< USIC_CH RBUF01SR: RDV10 (Bit 29) */ 10412 #define USIC_CH_RBUF01SR_RDV10_Msk (0x20000000UL) /*!< USIC_CH RBUF01SR: RDV10 (Bitfield-Mask: 0x01) */ 10413 #define USIC_CH_RBUF01SR_RDV11_Pos (30UL) /*!< USIC_CH RBUF01SR: RDV11 (Bit 30) */ 10414 #define USIC_CH_RBUF01SR_RDV11_Msk (0x40000000UL) /*!< USIC_CH RBUF01SR: RDV11 (Bitfield-Mask: 0x01) */ 10415 #define USIC_CH_RBUF01SR_DS1_Pos (31UL) /*!< USIC_CH RBUF01SR: DS1 (Bit 31) */ 10416 #define USIC_CH_RBUF01SR_DS1_Msk (0x80000000UL) /*!< USIC_CH RBUF01SR: DS1 (Bitfield-Mask: 0x01) */ 10417 10418 /* --------------------------------- USIC_CH_FMR -------------------------------- */ 10419 #define USIC_CH_FMR_MTDV_Pos (0UL) /*!< USIC_CH FMR: MTDV (Bit 0) */ 10420 #define USIC_CH_FMR_MTDV_Msk (0x3UL) /*!< USIC_CH FMR: MTDV (Bitfield-Mask: 0x03) */ 10421 #define USIC_CH_FMR_ATVC_Pos (4UL) /*!< USIC_CH FMR: ATVC (Bit 4) */ 10422 #define USIC_CH_FMR_ATVC_Msk (0x10UL) /*!< USIC_CH FMR: ATVC (Bitfield-Mask: 0x01) */ 10423 #define USIC_CH_FMR_CRDV0_Pos (14UL) /*!< USIC_CH FMR: CRDV0 (Bit 14) */ 10424 #define USIC_CH_FMR_CRDV0_Msk (0x4000UL) /*!< USIC_CH FMR: CRDV0 (Bitfield-Mask: 0x01) */ 10425 #define USIC_CH_FMR_CRDV1_Pos (15UL) /*!< USIC_CH FMR: CRDV1 (Bit 15) */ 10426 #define USIC_CH_FMR_CRDV1_Msk (0x8000UL) /*!< USIC_CH FMR: CRDV1 (Bitfield-Mask: 0x01) */ 10427 #define USIC_CH_FMR_SIO0_Pos (16UL) /*!< USIC_CH FMR: SIO0 (Bit 16) */ 10428 #define USIC_CH_FMR_SIO0_Msk (0x10000UL) /*!< USIC_CH FMR: SIO0 (Bitfield-Mask: 0x01) */ 10429 #define USIC_CH_FMR_SIO1_Pos (17UL) /*!< USIC_CH FMR: SIO1 (Bit 17) */ 10430 #define USIC_CH_FMR_SIO1_Msk (0x20000UL) /*!< USIC_CH FMR: SIO1 (Bitfield-Mask: 0x01) */ 10431 #define USIC_CH_FMR_SIO2_Pos (18UL) /*!< USIC_CH FMR: SIO2 (Bit 18) */ 10432 #define USIC_CH_FMR_SIO2_Msk (0x40000UL) /*!< USIC_CH FMR: SIO2 (Bitfield-Mask: 0x01) */ 10433 #define USIC_CH_FMR_SIO3_Pos (19UL) /*!< USIC_CH FMR: SIO3 (Bit 19) */ 10434 #define USIC_CH_FMR_SIO3_Msk (0x80000UL) /*!< USIC_CH FMR: SIO3 (Bitfield-Mask: 0x01) */ 10435 #define USIC_CH_FMR_SIO4_Pos (20UL) /*!< USIC_CH FMR: SIO4 (Bit 20) */ 10436 #define USIC_CH_FMR_SIO4_Msk (0x100000UL) /*!< USIC_CH FMR: SIO4 (Bitfield-Mask: 0x01) */ 10437 #define USIC_CH_FMR_SIO5_Pos (21UL) /*!< USIC_CH FMR: SIO5 (Bit 21) */ 10438 #define USIC_CH_FMR_SIO5_Msk (0x200000UL) /*!< USIC_CH FMR: SIO5 (Bitfield-Mask: 0x01) */ 10439 10440 /* -------------------------------- USIC_CH_TBUF -------------------------------- */ 10441 #define USIC_CH_TBUF_TDATA_Pos (0UL) /*!< USIC_CH TBUF: TDATA (Bit 0) */ 10442 #define USIC_CH_TBUF_TDATA_Msk (0xffffUL) /*!< USIC_CH TBUF: TDATA (Bitfield-Mask: 0xffff) */ 10443 10444 /* --------------------------------- USIC_CH_BYP -------------------------------- */ 10445 #define USIC_CH_BYP_BDATA_Pos (0UL) /*!< USIC_CH BYP: BDATA (Bit 0) */ 10446 #define USIC_CH_BYP_BDATA_Msk (0xffffUL) /*!< USIC_CH BYP: BDATA (Bitfield-Mask: 0xffff) */ 10447 10448 /* -------------------------------- USIC_CH_BYPCR ------------------------------- */ 10449 #define USIC_CH_BYPCR_BWLE_Pos (0UL) /*!< USIC_CH BYPCR: BWLE (Bit 0) */ 10450 #define USIC_CH_BYPCR_BWLE_Msk (0xfUL) /*!< USIC_CH BYPCR: BWLE (Bitfield-Mask: 0x0f) */ 10451 #define USIC_CH_BYPCR_BDSSM_Pos (8UL) /*!< USIC_CH BYPCR: BDSSM (Bit 8) */ 10452 #define USIC_CH_BYPCR_BDSSM_Msk (0x100UL) /*!< USIC_CH BYPCR: BDSSM (Bitfield-Mask: 0x01) */ 10453 #define USIC_CH_BYPCR_BDEN_Pos (10UL) /*!< USIC_CH BYPCR: BDEN (Bit 10) */ 10454 #define USIC_CH_BYPCR_BDEN_Msk (0xc00UL) /*!< USIC_CH BYPCR: BDEN (Bitfield-Mask: 0x03) */ 10455 #define USIC_CH_BYPCR_BDVTR_Pos (12UL) /*!< USIC_CH BYPCR: BDVTR (Bit 12) */ 10456 #define USIC_CH_BYPCR_BDVTR_Msk (0x1000UL) /*!< USIC_CH BYPCR: BDVTR (Bitfield-Mask: 0x01) */ 10457 #define USIC_CH_BYPCR_BPRIO_Pos (13UL) /*!< USIC_CH BYPCR: BPRIO (Bit 13) */ 10458 #define USIC_CH_BYPCR_BPRIO_Msk (0x2000UL) /*!< USIC_CH BYPCR: BPRIO (Bitfield-Mask: 0x01) */ 10459 #define USIC_CH_BYPCR_BDV_Pos (15UL) /*!< USIC_CH BYPCR: BDV (Bit 15) */ 10460 #define USIC_CH_BYPCR_BDV_Msk (0x8000UL) /*!< USIC_CH BYPCR: BDV (Bitfield-Mask: 0x01) */ 10461 #define USIC_CH_BYPCR_BSELO_Pos (16UL) /*!< USIC_CH BYPCR: BSELO (Bit 16) */ 10462 #define USIC_CH_BYPCR_BSELO_Msk (0x1f0000UL) /*!< USIC_CH BYPCR: BSELO (Bitfield-Mask: 0x1f) */ 10463 #define USIC_CH_BYPCR_BHPC_Pos (21UL) /*!< USIC_CH BYPCR: BHPC (Bit 21) */ 10464 #define USIC_CH_BYPCR_BHPC_Msk (0xe00000UL) /*!< USIC_CH BYPCR: BHPC (Bitfield-Mask: 0x07) */ 10465 10466 /* -------------------------------- USIC_CH_TBCTR ------------------------------- */ 10467 #define USIC_CH_TBCTR_DPTR_Pos (0UL) /*!< USIC_CH TBCTR: DPTR (Bit 0) */ 10468 #define USIC_CH_TBCTR_DPTR_Msk (0x3fUL) /*!< USIC_CH TBCTR: DPTR (Bitfield-Mask: 0x3f) */ 10469 #define USIC_CH_TBCTR_LIMIT_Pos (8UL) /*!< USIC_CH TBCTR: LIMIT (Bit 8) */ 10470 #define USIC_CH_TBCTR_LIMIT_Msk (0x3f00UL) /*!< USIC_CH TBCTR: LIMIT (Bitfield-Mask: 0x3f) */ 10471 #define USIC_CH_TBCTR_STBTM_Pos (14UL) /*!< USIC_CH TBCTR: STBTM (Bit 14) */ 10472 #define USIC_CH_TBCTR_STBTM_Msk (0x4000UL) /*!< USIC_CH TBCTR: STBTM (Bitfield-Mask: 0x01) */ 10473 #define USIC_CH_TBCTR_STBTEN_Pos (15UL) /*!< USIC_CH TBCTR: STBTEN (Bit 15) */ 10474 #define USIC_CH_TBCTR_STBTEN_Msk (0x8000UL) /*!< USIC_CH TBCTR: STBTEN (Bitfield-Mask: 0x01) */ 10475 #define USIC_CH_TBCTR_STBINP_Pos (16UL) /*!< USIC_CH TBCTR: STBINP (Bit 16) */ 10476 #define USIC_CH_TBCTR_STBINP_Msk (0x70000UL) /*!< USIC_CH TBCTR: STBINP (Bitfield-Mask: 0x07) */ 10477 #define USIC_CH_TBCTR_ATBINP_Pos (19UL) /*!< USIC_CH TBCTR: ATBINP (Bit 19) */ 10478 #define USIC_CH_TBCTR_ATBINP_Msk (0x380000UL) /*!< USIC_CH TBCTR: ATBINP (Bitfield-Mask: 0x07) */ 10479 #define USIC_CH_TBCTR_SIZE_Pos (24UL) /*!< USIC_CH TBCTR: SIZE (Bit 24) */ 10480 #define USIC_CH_TBCTR_SIZE_Msk (0x7000000UL) /*!< USIC_CH TBCTR: SIZE (Bitfield-Mask: 0x07) */ 10481 #define USIC_CH_TBCTR_LOF_Pos (28UL) /*!< USIC_CH TBCTR: LOF (Bit 28) */ 10482 #define USIC_CH_TBCTR_LOF_Msk (0x10000000UL) /*!< USIC_CH TBCTR: LOF (Bitfield-Mask: 0x01) */ 10483 #define USIC_CH_TBCTR_STBIEN_Pos (30UL) /*!< USIC_CH TBCTR: STBIEN (Bit 30) */ 10484 #define USIC_CH_TBCTR_STBIEN_Msk (0x40000000UL) /*!< USIC_CH TBCTR: STBIEN (Bitfield-Mask: 0x01) */ 10485 #define USIC_CH_TBCTR_TBERIEN_Pos (31UL) /*!< USIC_CH TBCTR: TBERIEN (Bit 31) */ 10486 #define USIC_CH_TBCTR_TBERIEN_Msk (0x80000000UL) /*!< USIC_CH TBCTR: TBERIEN (Bitfield-Mask: 0x01) */ 10487 10488 /* -------------------------------- USIC_CH_RBCTR ------------------------------- */ 10489 #define USIC_CH_RBCTR_DPTR_Pos (0UL) /*!< USIC_CH RBCTR: DPTR (Bit 0) */ 10490 #define USIC_CH_RBCTR_DPTR_Msk (0x3fUL) /*!< USIC_CH RBCTR: DPTR (Bitfield-Mask: 0x3f) */ 10491 #define USIC_CH_RBCTR_LIMIT_Pos (8UL) /*!< USIC_CH RBCTR: LIMIT (Bit 8) */ 10492 #define USIC_CH_RBCTR_LIMIT_Msk (0x3f00UL) /*!< USIC_CH RBCTR: LIMIT (Bitfield-Mask: 0x3f) */ 10493 #define USIC_CH_RBCTR_SRBTM_Pos (14UL) /*!< USIC_CH RBCTR: SRBTM (Bit 14) */ 10494 #define USIC_CH_RBCTR_SRBTM_Msk (0x4000UL) /*!< USIC_CH RBCTR: SRBTM (Bitfield-Mask: 0x01) */ 10495 #define USIC_CH_RBCTR_SRBTEN_Pos (15UL) /*!< USIC_CH RBCTR: SRBTEN (Bit 15) */ 10496 #define USIC_CH_RBCTR_SRBTEN_Msk (0x8000UL) /*!< USIC_CH RBCTR: SRBTEN (Bitfield-Mask: 0x01) */ 10497 #define USIC_CH_RBCTR_SRBINP_Pos (16UL) /*!< USIC_CH RBCTR: SRBINP (Bit 16) */ 10498 #define USIC_CH_RBCTR_SRBINP_Msk (0x70000UL) /*!< USIC_CH RBCTR: SRBINP (Bitfield-Mask: 0x07) */ 10499 #define USIC_CH_RBCTR_ARBINP_Pos (19UL) /*!< USIC_CH RBCTR: ARBINP (Bit 19) */ 10500 #define USIC_CH_RBCTR_ARBINP_Msk (0x380000UL) /*!< USIC_CH RBCTR: ARBINP (Bitfield-Mask: 0x07) */ 10501 #define USIC_CH_RBCTR_RCIM_Pos (22UL) /*!< USIC_CH RBCTR: RCIM (Bit 22) */ 10502 #define USIC_CH_RBCTR_RCIM_Msk (0xc00000UL) /*!< USIC_CH RBCTR: RCIM (Bitfield-Mask: 0x03) */ 10503 #define USIC_CH_RBCTR_SIZE_Pos (24UL) /*!< USIC_CH RBCTR: SIZE (Bit 24) */ 10504 #define USIC_CH_RBCTR_SIZE_Msk (0x7000000UL) /*!< USIC_CH RBCTR: SIZE (Bitfield-Mask: 0x07) */ 10505 #define USIC_CH_RBCTR_RNM_Pos (27UL) /*!< USIC_CH RBCTR: RNM (Bit 27) */ 10506 #define USIC_CH_RBCTR_RNM_Msk (0x8000000UL) /*!< USIC_CH RBCTR: RNM (Bitfield-Mask: 0x01) */ 10507 #define USIC_CH_RBCTR_LOF_Pos (28UL) /*!< USIC_CH RBCTR: LOF (Bit 28) */ 10508 #define USIC_CH_RBCTR_LOF_Msk (0x10000000UL) /*!< USIC_CH RBCTR: LOF (Bitfield-Mask: 0x01) */ 10509 #define USIC_CH_RBCTR_ARBIEN_Pos (29UL) /*!< USIC_CH RBCTR: ARBIEN (Bit 29) */ 10510 #define USIC_CH_RBCTR_ARBIEN_Msk (0x20000000UL) /*!< USIC_CH RBCTR: ARBIEN (Bitfield-Mask: 0x01) */ 10511 #define USIC_CH_RBCTR_SRBIEN_Pos (30UL) /*!< USIC_CH RBCTR: SRBIEN (Bit 30) */ 10512 #define USIC_CH_RBCTR_SRBIEN_Msk (0x40000000UL) /*!< USIC_CH RBCTR: SRBIEN (Bitfield-Mask: 0x01) */ 10513 #define USIC_CH_RBCTR_RBERIEN_Pos (31UL) /*!< USIC_CH RBCTR: RBERIEN (Bit 31) */ 10514 #define USIC_CH_RBCTR_RBERIEN_Msk (0x80000000UL) /*!< USIC_CH RBCTR: RBERIEN (Bitfield-Mask: 0x01) */ 10515 10516 /* ------------------------------- USIC_CH_TRBPTR ------------------------------- */ 10517 #define USIC_CH_TRBPTR_TDIPTR_Pos (0UL) /*!< USIC_CH TRBPTR: TDIPTR (Bit 0) */ 10518 #define USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL) /*!< USIC_CH TRBPTR: TDIPTR (Bitfield-Mask: 0x3f) */ 10519 #define USIC_CH_TRBPTR_TDOPTR_Pos (8UL) /*!< USIC_CH TRBPTR: TDOPTR (Bit 8) */ 10520 #define USIC_CH_TRBPTR_TDOPTR_Msk (0x3f00UL) /*!< USIC_CH TRBPTR: TDOPTR (Bitfield-Mask: 0x3f) */ 10521 #define USIC_CH_TRBPTR_RDIPTR_Pos (16UL) /*!< USIC_CH TRBPTR: RDIPTR (Bit 16) */ 10522 #define USIC_CH_TRBPTR_RDIPTR_Msk (0x3f0000UL) /*!< USIC_CH TRBPTR: RDIPTR (Bitfield-Mask: 0x3f) */ 10523 #define USIC_CH_TRBPTR_RDOPTR_Pos (24UL) /*!< USIC_CH TRBPTR: RDOPTR (Bit 24) */ 10524 #define USIC_CH_TRBPTR_RDOPTR_Msk (0x3f000000UL) /*!< USIC_CH TRBPTR: RDOPTR (Bitfield-Mask: 0x3f) */ 10525 10526 /* -------------------------------- USIC_CH_TRBSR ------------------------------- */ 10527 #define USIC_CH_TRBSR_SRBI_Pos (0UL) /*!< USIC_CH TRBSR: SRBI (Bit 0) */ 10528 #define USIC_CH_TRBSR_SRBI_Msk (0x1UL) /*!< USIC_CH TRBSR: SRBI (Bitfield-Mask: 0x01) */ 10529 #define USIC_CH_TRBSR_RBERI_Pos (1UL) /*!< USIC_CH TRBSR: RBERI (Bit 1) */ 10530 #define USIC_CH_TRBSR_RBERI_Msk (0x2UL) /*!< USIC_CH TRBSR: RBERI (Bitfield-Mask: 0x01) */ 10531 #define USIC_CH_TRBSR_ARBI_Pos (2UL) /*!< USIC_CH TRBSR: ARBI (Bit 2) */ 10532 #define USIC_CH_TRBSR_ARBI_Msk (0x4UL) /*!< USIC_CH TRBSR: ARBI (Bitfield-Mask: 0x01) */ 10533 #define USIC_CH_TRBSR_REMPTY_Pos (3UL) /*!< USIC_CH TRBSR: REMPTY (Bit 3) */ 10534 #define USIC_CH_TRBSR_REMPTY_Msk (0x8UL) /*!< USIC_CH TRBSR: REMPTY (Bitfield-Mask: 0x01) */ 10535 #define USIC_CH_TRBSR_RFULL_Pos (4UL) /*!< USIC_CH TRBSR: RFULL (Bit 4) */ 10536 #define USIC_CH_TRBSR_RFULL_Msk (0x10UL) /*!< USIC_CH TRBSR: RFULL (Bitfield-Mask: 0x01) */ 10537 #define USIC_CH_TRBSR_RBUS_Pos (5UL) /*!< USIC_CH TRBSR: RBUS (Bit 5) */ 10538 #define USIC_CH_TRBSR_RBUS_Msk (0x20UL) /*!< USIC_CH TRBSR: RBUS (Bitfield-Mask: 0x01) */ 10539 #define USIC_CH_TRBSR_SRBT_Pos (6UL) /*!< USIC_CH TRBSR: SRBT (Bit 6) */ 10540 #define USIC_CH_TRBSR_SRBT_Msk (0x40UL) /*!< USIC_CH TRBSR: SRBT (Bitfield-Mask: 0x01) */ 10541 #define USIC_CH_TRBSR_STBI_Pos (8UL) /*!< USIC_CH TRBSR: STBI (Bit 8) */ 10542 #define USIC_CH_TRBSR_STBI_Msk (0x100UL) /*!< USIC_CH TRBSR: STBI (Bitfield-Mask: 0x01) */ 10543 #define USIC_CH_TRBSR_TBERI_Pos (9UL) /*!< USIC_CH TRBSR: TBERI (Bit 9) */ 10544 #define USIC_CH_TRBSR_TBERI_Msk (0x200UL) /*!< USIC_CH TRBSR: TBERI (Bitfield-Mask: 0x01) */ 10545 #define USIC_CH_TRBSR_TEMPTY_Pos (11UL) /*!< USIC_CH TRBSR: TEMPTY (Bit 11) */ 10546 #define USIC_CH_TRBSR_TEMPTY_Msk (0x800UL) /*!< USIC_CH TRBSR: TEMPTY (Bitfield-Mask: 0x01) */ 10547 #define USIC_CH_TRBSR_TFULL_Pos (12UL) /*!< USIC_CH TRBSR: TFULL (Bit 12) */ 10548 #define USIC_CH_TRBSR_TFULL_Msk (0x1000UL) /*!< USIC_CH TRBSR: TFULL (Bitfield-Mask: 0x01) */ 10549 #define USIC_CH_TRBSR_TBUS_Pos (13UL) /*!< USIC_CH TRBSR: TBUS (Bit 13) */ 10550 #define USIC_CH_TRBSR_TBUS_Msk (0x2000UL) /*!< USIC_CH TRBSR: TBUS (Bitfield-Mask: 0x01) */ 10551 #define USIC_CH_TRBSR_STBT_Pos (14UL) /*!< USIC_CH TRBSR: STBT (Bit 14) */ 10552 #define USIC_CH_TRBSR_STBT_Msk (0x4000UL) /*!< USIC_CH TRBSR: STBT (Bitfield-Mask: 0x01) */ 10553 #define USIC_CH_TRBSR_RBFLVL_Pos (16UL) /*!< USIC_CH TRBSR: RBFLVL (Bit 16) */ 10554 #define USIC_CH_TRBSR_RBFLVL_Msk (0x7f0000UL) /*!< USIC_CH TRBSR: RBFLVL (Bitfield-Mask: 0x7f) */ 10555 #define USIC_CH_TRBSR_TBFLVL_Pos (24UL) /*!< USIC_CH TRBSR: TBFLVL (Bit 24) */ 10556 #define USIC_CH_TRBSR_TBFLVL_Msk (0x7f000000UL) /*!< USIC_CH TRBSR: TBFLVL (Bitfield-Mask: 0x7f) */ 10557 10558 /* ------------------------------- USIC_CH_TRBSCR ------------------------------- */ 10559 #define USIC_CH_TRBSCR_CSRBI_Pos (0UL) /*!< USIC_CH TRBSCR: CSRBI (Bit 0) */ 10560 #define USIC_CH_TRBSCR_CSRBI_Msk (0x1UL) /*!< USIC_CH TRBSCR: CSRBI (Bitfield-Mask: 0x01) */ 10561 #define USIC_CH_TRBSCR_CRBERI_Pos (1UL) /*!< USIC_CH TRBSCR: CRBERI (Bit 1) */ 10562 #define USIC_CH_TRBSCR_CRBERI_Msk (0x2UL) /*!< USIC_CH TRBSCR: CRBERI (Bitfield-Mask: 0x01) */ 10563 #define USIC_CH_TRBSCR_CARBI_Pos (2UL) /*!< USIC_CH TRBSCR: CARBI (Bit 2) */ 10564 #define USIC_CH_TRBSCR_CARBI_Msk (0x4UL) /*!< USIC_CH TRBSCR: CARBI (Bitfield-Mask: 0x01) */ 10565 #define USIC_CH_TRBSCR_CSTBI_Pos (8UL) /*!< USIC_CH TRBSCR: CSTBI (Bit 8) */ 10566 #define USIC_CH_TRBSCR_CSTBI_Msk (0x100UL) /*!< USIC_CH TRBSCR: CSTBI (Bitfield-Mask: 0x01) */ 10567 #define USIC_CH_TRBSCR_CTBERI_Pos (9UL) /*!< USIC_CH TRBSCR: CTBERI (Bit 9) */ 10568 #define USIC_CH_TRBSCR_CTBERI_Msk (0x200UL) /*!< USIC_CH TRBSCR: CTBERI (Bitfield-Mask: 0x01) */ 10569 #define USIC_CH_TRBSCR_CBDV_Pos (10UL) /*!< USIC_CH TRBSCR: CBDV (Bit 10) */ 10570 #define USIC_CH_TRBSCR_CBDV_Msk (0x400UL) /*!< USIC_CH TRBSCR: CBDV (Bitfield-Mask: 0x01) */ 10571 #define USIC_CH_TRBSCR_FLUSHRB_Pos (14UL) /*!< USIC_CH TRBSCR: FLUSHRB (Bit 14) */ 10572 #define USIC_CH_TRBSCR_FLUSHRB_Msk (0x4000UL) /*!< USIC_CH TRBSCR: FLUSHRB (Bitfield-Mask: 0x01) */ 10573 #define USIC_CH_TRBSCR_FLUSHTB_Pos (15UL) /*!< USIC_CH TRBSCR: FLUSHTB (Bit 15) */ 10574 #define USIC_CH_TRBSCR_FLUSHTB_Msk (0x8000UL) /*!< USIC_CH TRBSCR: FLUSHTB (Bitfield-Mask: 0x01) */ 10575 10576 /* -------------------------------- USIC_CH_OUTR -------------------------------- */ 10577 #define USIC_CH_OUTR_DSR_Pos (0UL) /*!< USIC_CH OUTR: DSR (Bit 0) */ 10578 #define USIC_CH_OUTR_DSR_Msk (0xffffUL) /*!< USIC_CH OUTR: DSR (Bitfield-Mask: 0xffff) */ 10579 #define USIC_CH_OUTR_RCI_Pos (16UL) /*!< USIC_CH OUTR: RCI (Bit 16) */ 10580 #define USIC_CH_OUTR_RCI_Msk (0x1f0000UL) /*!< USIC_CH OUTR: RCI (Bitfield-Mask: 0x1f) */ 10581 10582 /* -------------------------------- USIC_CH_OUTDR ------------------------------- */ 10583 #define USIC_CH_OUTDR_DSR_Pos (0UL) /*!< USIC_CH OUTDR: DSR (Bit 0) */ 10584 #define USIC_CH_OUTDR_DSR_Msk (0xffffUL) /*!< USIC_CH OUTDR: DSR (Bitfield-Mask: 0xffff) */ 10585 #define USIC_CH_OUTDR_RCI_Pos (16UL) /*!< USIC_CH OUTDR: RCI (Bit 16) */ 10586 #define USIC_CH_OUTDR_RCI_Msk (0x1f0000UL) /*!< USIC_CH OUTDR: RCI (Bitfield-Mask: 0x1f) */ 10587 10588 /* --------------------------------- USIC_CH_IN --------------------------------- */ 10589 #define USIC_CH_IN_TDATA_Pos (0UL) /*!< USIC_CH IN: TDATA (Bit 0) */ 10590 #define USIC_CH_IN_TDATA_Msk (0xffffUL) /*!< USIC_CH IN: TDATA (Bitfield-Mask: 0xffff) */ 10591 10592 10593 /* ================================================================================ */ 10594 /* ================ struct 'CAN' Position & Mask ================ */ 10595 /* ================================================================================ */ 10596 10597 10598 /* ----------------------------------- CAN_CLC ---------------------------------- */ 10599 #define CAN_CLC_DISR_Pos (0UL) /*!< CAN CLC: DISR (Bit 0) */ 10600 #define CAN_CLC_DISR_Msk (0x1UL) /*!< CAN CLC: DISR (Bitfield-Mask: 0x01) */ 10601 #define CAN_CLC_DISS_Pos (1UL) /*!< CAN CLC: DISS (Bit 1) */ 10602 #define CAN_CLC_DISS_Msk (0x2UL) /*!< CAN CLC: DISS (Bitfield-Mask: 0x01) */ 10603 #define CAN_CLC_EDIS_Pos (3UL) /*!< CAN CLC: EDIS (Bit 3) */ 10604 #define CAN_CLC_EDIS_Msk (0x8UL) /*!< CAN CLC: EDIS (Bitfield-Mask: 0x01) */ 10605 #define CAN_CLC_SBWE_Pos (4UL) /*!< CAN CLC: SBWE (Bit 4) */ 10606 #define CAN_CLC_SBWE_Msk (0x10UL) /*!< CAN CLC: SBWE (Bitfield-Mask: 0x01) */ 10607 10608 /* ----------------------------------- CAN_ID ----------------------------------- */ 10609 #define CAN_ID_MOD_REV_Pos (0UL) /*!< CAN ID: MOD_REV (Bit 0) */ 10610 #define CAN_ID_MOD_REV_Msk (0xffUL) /*!< CAN ID: MOD_REV (Bitfield-Mask: 0xff) */ 10611 #define CAN_ID_MOD_TYPE_Pos (8UL) /*!< CAN ID: MOD_TYPE (Bit 8) */ 10612 #define CAN_ID_MOD_TYPE_Msk (0xff00UL) /*!< CAN ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 10613 #define CAN_ID_MOD_NUMBER_Pos (16UL) /*!< CAN ID: MOD_NUMBER (Bit 16) */ 10614 #define CAN_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< CAN ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 10615 10616 /* ----------------------------------- CAN_FDR ---------------------------------- */ 10617 #define CAN_FDR_STEP_Pos (0UL) /*!< CAN FDR: STEP (Bit 0) */ 10618 #define CAN_FDR_STEP_Msk (0x3ffUL) /*!< CAN FDR: STEP (Bitfield-Mask: 0x3ff) */ 10619 #define CAN_FDR_SM_Pos (11UL) /*!< CAN FDR: SM (Bit 11) */ 10620 #define CAN_FDR_SM_Msk (0x800UL) /*!< CAN FDR: SM (Bitfield-Mask: 0x01) */ 10621 #define CAN_FDR_SC_Pos (12UL) /*!< CAN FDR: SC (Bit 12) */ 10622 #define CAN_FDR_SC_Msk (0x3000UL) /*!< CAN FDR: SC (Bitfield-Mask: 0x03) */ 10623 #define CAN_FDR_DM_Pos (14UL) /*!< CAN FDR: DM (Bit 14) */ 10624 #define CAN_FDR_DM_Msk (0xc000UL) /*!< CAN FDR: DM (Bitfield-Mask: 0x03) */ 10625 #define CAN_FDR_RESULT_Pos (16UL) /*!< CAN FDR: RESULT (Bit 16) */ 10626 #define CAN_FDR_RESULT_Msk (0x3ff0000UL) /*!< CAN FDR: RESULT (Bitfield-Mask: 0x3ff) */ 10627 #define CAN_FDR_SUSACK_Pos (28UL) /*!< CAN FDR: SUSACK (Bit 28) */ 10628 #define CAN_FDR_SUSACK_Msk (0x10000000UL) /*!< CAN FDR: SUSACK (Bitfield-Mask: 0x01) */ 10629 #define CAN_FDR_SUSREQ_Pos (29UL) /*!< CAN FDR: SUSREQ (Bit 29) */ 10630 #define CAN_FDR_SUSREQ_Msk (0x20000000UL) /*!< CAN FDR: SUSREQ (Bitfield-Mask: 0x01) */ 10631 #define CAN_FDR_ENHW_Pos (30UL) /*!< CAN FDR: ENHW (Bit 30) */ 10632 #define CAN_FDR_ENHW_Msk (0x40000000UL) /*!< CAN FDR: ENHW (Bitfield-Mask: 0x01) */ 10633 #define CAN_FDR_DISCLK_Pos (31UL) /*!< CAN FDR: DISCLK (Bit 31) */ 10634 #define CAN_FDR_DISCLK_Msk (0x80000000UL) /*!< CAN FDR: DISCLK (Bitfield-Mask: 0x01) */ 10635 10636 /* ---------------------------------- CAN_LIST ---------------------------------- */ 10637 #define CAN_LIST_BEGIN_Pos (0UL) /*!< CAN LIST: BEGIN (Bit 0) */ 10638 #define CAN_LIST_BEGIN_Msk (0xffUL) /*!< CAN LIST: BEGIN (Bitfield-Mask: 0xff) */ 10639 #define CAN_LIST_END_Pos (8UL) /*!< CAN LIST: END (Bit 8) */ 10640 #define CAN_LIST_END_Msk (0xff00UL) /*!< CAN LIST: END (Bitfield-Mask: 0xff) */ 10641 #define CAN_LIST_SIZE_Pos (16UL) /*!< CAN LIST: SIZE (Bit 16) */ 10642 #define CAN_LIST_SIZE_Msk (0xff0000UL) /*!< CAN LIST: SIZE (Bitfield-Mask: 0xff) */ 10643 #define CAN_LIST_EMPTY_Pos (24UL) /*!< CAN LIST: EMPTY (Bit 24) */ 10644 #define CAN_LIST_EMPTY_Msk (0x1000000UL) /*!< CAN LIST: EMPTY (Bitfield-Mask: 0x01) */ 10645 10646 /* ---------------------------------- CAN_MSPND --------------------------------- */ 10647 #define CAN_MSPND_PND_Pos (0UL) /*!< CAN MSPND: PND (Bit 0) */ 10648 #define CAN_MSPND_PND_Msk (0xffffffffUL) /*!< CAN MSPND: PND (Bitfield-Mask: 0xffffffff) */ 10649 10650 /* ---------------------------------- CAN_MSID ---------------------------------- */ 10651 #define CAN_MSID_INDEX_Pos (0UL) /*!< CAN MSID: INDEX (Bit 0) */ 10652 #define CAN_MSID_INDEX_Msk (0x3fUL) /*!< CAN MSID: INDEX (Bitfield-Mask: 0x3f) */ 10653 10654 /* --------------------------------- CAN_MSIMASK -------------------------------- */ 10655 #define CAN_MSIMASK_IM_Pos (0UL) /*!< CAN MSIMASK: IM (Bit 0) */ 10656 #define CAN_MSIMASK_IM_Msk (0xffffffffUL) /*!< CAN MSIMASK: IM (Bitfield-Mask: 0xffffffff) */ 10657 10658 /* --------------------------------- CAN_PANCTR --------------------------------- */ 10659 #define CAN_PANCTR_PANCMD_Pos (0UL) /*!< CAN PANCTR: PANCMD (Bit 0) */ 10660 #define CAN_PANCTR_PANCMD_Msk (0xffUL) /*!< CAN PANCTR: PANCMD (Bitfield-Mask: 0xff) */ 10661 #define CAN_PANCTR_BUSY_Pos (8UL) /*!< CAN PANCTR: BUSY (Bit 8) */ 10662 #define CAN_PANCTR_BUSY_Msk (0x100UL) /*!< CAN PANCTR: BUSY (Bitfield-Mask: 0x01) */ 10663 #define CAN_PANCTR_RBUSY_Pos (9UL) /*!< CAN PANCTR: RBUSY (Bit 9) */ 10664 #define CAN_PANCTR_RBUSY_Msk (0x200UL) /*!< CAN PANCTR: RBUSY (Bitfield-Mask: 0x01) */ 10665 #define CAN_PANCTR_PANAR1_Pos (16UL) /*!< CAN PANCTR: PANAR1 (Bit 16) */ 10666 #define CAN_PANCTR_PANAR1_Msk (0xff0000UL) /*!< CAN PANCTR: PANAR1 (Bitfield-Mask: 0xff) */ 10667 #define CAN_PANCTR_PANAR2_Pos (24UL) /*!< CAN PANCTR: PANAR2 (Bit 24) */ 10668 #define CAN_PANCTR_PANAR2_Msk (0xff000000UL) /*!< CAN PANCTR: PANAR2 (Bitfield-Mask: 0xff) */ 10669 10670 /* ----------------------------------- CAN_MCR ---------------------------------- */ 10671 #define CAN_MCR_MPSEL_Pos (12UL) /*!< CAN MCR: MPSEL (Bit 12) */ 10672 #define CAN_MCR_MPSEL_Msk (0xf000UL) /*!< CAN MCR: MPSEL (Bitfield-Mask: 0x0f) */ 10673 10674 /* ---------------------------------- CAN_MITR ---------------------------------- */ 10675 #define CAN_MITR_IT_Pos (0UL) /*!< CAN MITR: IT (Bit 0) */ 10676 #define CAN_MITR_IT_Msk (0xffUL) /*!< CAN MITR: IT (Bitfield-Mask: 0xff) */ 10677 10678 10679 /* ================================================================================ */ 10680 /* ================ Group 'CAN_NODE' Position & Mask ================ */ 10681 /* ================================================================================ */ 10682 10683 10684 /* -------------------------------- CAN_NODE_NCR -------------------------------- */ 10685 #define CAN_NODE_NCR_INIT_Pos (0UL) /*!< CAN_NODE NCR: INIT (Bit 0) */ 10686 #define CAN_NODE_NCR_INIT_Msk (0x1UL) /*!< CAN_NODE NCR: INIT (Bitfield-Mask: 0x01) */ 10687 #define CAN_NODE_NCR_TRIE_Pos (1UL) /*!< CAN_NODE NCR: TRIE (Bit 1) */ 10688 #define CAN_NODE_NCR_TRIE_Msk (0x2UL) /*!< CAN_NODE NCR: TRIE (Bitfield-Mask: 0x01) */ 10689 #define CAN_NODE_NCR_LECIE_Pos (2UL) /*!< CAN_NODE NCR: LECIE (Bit 2) */ 10690 #define CAN_NODE_NCR_LECIE_Msk (0x4UL) /*!< CAN_NODE NCR: LECIE (Bitfield-Mask: 0x01) */ 10691 #define CAN_NODE_NCR_ALIE_Pos (3UL) /*!< CAN_NODE NCR: ALIE (Bit 3) */ 10692 #define CAN_NODE_NCR_ALIE_Msk (0x8UL) /*!< CAN_NODE NCR: ALIE (Bitfield-Mask: 0x01) */ 10693 #define CAN_NODE_NCR_CANDIS_Pos (4UL) /*!< CAN_NODE NCR: CANDIS (Bit 4) */ 10694 #define CAN_NODE_NCR_CANDIS_Msk (0x10UL) /*!< CAN_NODE NCR: CANDIS (Bitfield-Mask: 0x01) */ 10695 #define CAN_NODE_NCR_CCE_Pos (6UL) /*!< CAN_NODE NCR: CCE (Bit 6) */ 10696 #define CAN_NODE_NCR_CCE_Msk (0x40UL) /*!< CAN_NODE NCR: CCE (Bitfield-Mask: 0x01) */ 10697 #define CAN_NODE_NCR_CALM_Pos (7UL) /*!< CAN_NODE NCR: CALM (Bit 7) */ 10698 #define CAN_NODE_NCR_CALM_Msk (0x80UL) /*!< CAN_NODE NCR: CALM (Bitfield-Mask: 0x01) */ 10699 #define CAN_NODE_NCR_SUSEN_Pos (8UL) /*!< CAN_NODE NCR: SUSEN (Bit 8) */ 10700 #define CAN_NODE_NCR_SUSEN_Msk (0x100UL) /*!< CAN_NODE NCR: SUSEN (Bitfield-Mask: 0x01) */ 10701 10702 /* -------------------------------- CAN_NODE_NSR -------------------------------- */ 10703 #define CAN_NODE_NSR_LEC_Pos (0UL) /*!< CAN_NODE NSR: LEC (Bit 0) */ 10704 #define CAN_NODE_NSR_LEC_Msk (0x7UL) /*!< CAN_NODE NSR: LEC (Bitfield-Mask: 0x07) */ 10705 #define CAN_NODE_NSR_TXOK_Pos (3UL) /*!< CAN_NODE NSR: TXOK (Bit 3) */ 10706 #define CAN_NODE_NSR_TXOK_Msk (0x8UL) /*!< CAN_NODE NSR: TXOK (Bitfield-Mask: 0x01) */ 10707 #define CAN_NODE_NSR_RXOK_Pos (4UL) /*!< CAN_NODE NSR: RXOK (Bit 4) */ 10708 #define CAN_NODE_NSR_RXOK_Msk (0x10UL) /*!< CAN_NODE NSR: RXOK (Bitfield-Mask: 0x01) */ 10709 #define CAN_NODE_NSR_ALERT_Pos (5UL) /*!< CAN_NODE NSR: ALERT (Bit 5) */ 10710 #define CAN_NODE_NSR_ALERT_Msk (0x20UL) /*!< CAN_NODE NSR: ALERT (Bitfield-Mask: 0x01) */ 10711 #define CAN_NODE_NSR_EWRN_Pos (6UL) /*!< CAN_NODE NSR: EWRN (Bit 6) */ 10712 #define CAN_NODE_NSR_EWRN_Msk (0x40UL) /*!< CAN_NODE NSR: EWRN (Bitfield-Mask: 0x01) */ 10713 #define CAN_NODE_NSR_BOFF_Pos (7UL) /*!< CAN_NODE NSR: BOFF (Bit 7) */ 10714 #define CAN_NODE_NSR_BOFF_Msk (0x80UL) /*!< CAN_NODE NSR: BOFF (Bitfield-Mask: 0x01) */ 10715 #define CAN_NODE_NSR_LLE_Pos (8UL) /*!< CAN_NODE NSR: LLE (Bit 8) */ 10716 #define CAN_NODE_NSR_LLE_Msk (0x100UL) /*!< CAN_NODE NSR: LLE (Bitfield-Mask: 0x01) */ 10717 #define CAN_NODE_NSR_LOE_Pos (9UL) /*!< CAN_NODE NSR: LOE (Bit 9) */ 10718 #define CAN_NODE_NSR_LOE_Msk (0x200UL) /*!< CAN_NODE NSR: LOE (Bitfield-Mask: 0x01) */ 10719 #define CAN_NODE_NSR_SUSACK_Pos (10UL) /*!< CAN_NODE NSR: SUSACK (Bit 10) */ 10720 #define CAN_NODE_NSR_SUSACK_Msk (0x400UL) /*!< CAN_NODE NSR: SUSACK (Bitfield-Mask: 0x01) */ 10721 10722 /* -------------------------------- CAN_NODE_NIPR ------------------------------- */ 10723 #define CAN_NODE_NIPR_ALINP_Pos (0UL) /*!< CAN_NODE NIPR: ALINP (Bit 0) */ 10724 #define CAN_NODE_NIPR_ALINP_Msk (0x7UL) /*!< CAN_NODE NIPR: ALINP (Bitfield-Mask: 0x07) */ 10725 #define CAN_NODE_NIPR_LECINP_Pos (4UL) /*!< CAN_NODE NIPR: LECINP (Bit 4) */ 10726 #define CAN_NODE_NIPR_LECINP_Msk (0x70UL) /*!< CAN_NODE NIPR: LECINP (Bitfield-Mask: 0x07) */ 10727 #define CAN_NODE_NIPR_TRINP_Pos (8UL) /*!< CAN_NODE NIPR: TRINP (Bit 8) */ 10728 #define CAN_NODE_NIPR_TRINP_Msk (0x700UL) /*!< CAN_NODE NIPR: TRINP (Bitfield-Mask: 0x07) */ 10729 #define CAN_NODE_NIPR_CFCINP_Pos (12UL) /*!< CAN_NODE NIPR: CFCINP (Bit 12) */ 10730 #define CAN_NODE_NIPR_CFCINP_Msk (0x7000UL) /*!< CAN_NODE NIPR: CFCINP (Bitfield-Mask: 0x07) */ 10731 10732 /* -------------------------------- CAN_NODE_NPCR ------------------------------- */ 10733 #define CAN_NODE_NPCR_RXSEL_Pos (0UL) /*!< CAN_NODE NPCR: RXSEL (Bit 0) */ 10734 #define CAN_NODE_NPCR_RXSEL_Msk (0x7UL) /*!< CAN_NODE NPCR: RXSEL (Bitfield-Mask: 0x07) */ 10735 #define CAN_NODE_NPCR_LBM_Pos (8UL) /*!< CAN_NODE NPCR: LBM (Bit 8) */ 10736 #define CAN_NODE_NPCR_LBM_Msk (0x100UL) /*!< CAN_NODE NPCR: LBM (Bitfield-Mask: 0x01) */ 10737 10738 /* -------------------------------- CAN_NODE_NBTR ------------------------------- */ 10739 #define CAN_NODE_NBTR_BRP_Pos (0UL) /*!< CAN_NODE NBTR: BRP (Bit 0) */ 10740 #define CAN_NODE_NBTR_BRP_Msk (0x3fUL) /*!< CAN_NODE NBTR: BRP (Bitfield-Mask: 0x3f) */ 10741 #define CAN_NODE_NBTR_SJW_Pos (6UL) /*!< CAN_NODE NBTR: SJW (Bit 6) */ 10742 #define CAN_NODE_NBTR_SJW_Msk (0xc0UL) /*!< CAN_NODE NBTR: SJW (Bitfield-Mask: 0x03) */ 10743 #define CAN_NODE_NBTR_TSEG1_Pos (8UL) /*!< CAN_NODE NBTR: TSEG1 (Bit 8) */ 10744 #define CAN_NODE_NBTR_TSEG1_Msk (0xf00UL) /*!< CAN_NODE NBTR: TSEG1 (Bitfield-Mask: 0x0f) */ 10745 #define CAN_NODE_NBTR_TSEG2_Pos (12UL) /*!< CAN_NODE NBTR: TSEG2 (Bit 12) */ 10746 #define CAN_NODE_NBTR_TSEG2_Msk (0x7000UL) /*!< CAN_NODE NBTR: TSEG2 (Bitfield-Mask: 0x07) */ 10747 #define CAN_NODE_NBTR_DIV8_Pos (15UL) /*!< CAN_NODE NBTR: DIV8 (Bit 15) */ 10748 #define CAN_NODE_NBTR_DIV8_Msk (0x8000UL) /*!< CAN_NODE NBTR: DIV8 (Bitfield-Mask: 0x01) */ 10749 10750 /* ------------------------------- CAN_NODE_NECNT ------------------------------- */ 10751 #define CAN_NODE_NECNT_REC_Pos (0UL) /*!< CAN_NODE NECNT: REC (Bit 0) */ 10752 #define CAN_NODE_NECNT_REC_Msk (0xffUL) /*!< CAN_NODE NECNT: REC (Bitfield-Mask: 0xff) */ 10753 #define CAN_NODE_NECNT_TEC_Pos (8UL) /*!< CAN_NODE NECNT: TEC (Bit 8) */ 10754 #define CAN_NODE_NECNT_TEC_Msk (0xff00UL) /*!< CAN_NODE NECNT: TEC (Bitfield-Mask: 0xff) */ 10755 #define CAN_NODE_NECNT_EWRNLVL_Pos (16UL) /*!< CAN_NODE NECNT: EWRNLVL (Bit 16) */ 10756 #define CAN_NODE_NECNT_EWRNLVL_Msk (0xff0000UL) /*!< CAN_NODE NECNT: EWRNLVL (Bitfield-Mask: 0xff) */ 10757 #define CAN_NODE_NECNT_LETD_Pos (24UL) /*!< CAN_NODE NECNT: LETD (Bit 24) */ 10758 #define CAN_NODE_NECNT_LETD_Msk (0x1000000UL) /*!< CAN_NODE NECNT: LETD (Bitfield-Mask: 0x01) */ 10759 #define CAN_NODE_NECNT_LEINC_Pos (25UL) /*!< CAN_NODE NECNT: LEINC (Bit 25) */ 10760 #define CAN_NODE_NECNT_LEINC_Msk (0x2000000UL) /*!< CAN_NODE NECNT: LEINC (Bitfield-Mask: 0x01) */ 10761 10762 /* -------------------------------- CAN_NODE_NFCR ------------------------------- */ 10763 #define CAN_NODE_NFCR_CFC_Pos (0UL) /*!< CAN_NODE NFCR: CFC (Bit 0) */ 10764 #define CAN_NODE_NFCR_CFC_Msk (0xffffUL) /*!< CAN_NODE NFCR: CFC (Bitfield-Mask: 0xffff) */ 10765 #define CAN_NODE_NFCR_CFSEL_Pos (16UL) /*!< CAN_NODE NFCR: CFSEL (Bit 16) */ 10766 #define CAN_NODE_NFCR_CFSEL_Msk (0x70000UL) /*!< CAN_NODE NFCR: CFSEL (Bitfield-Mask: 0x07) */ 10767 #define CAN_NODE_NFCR_CFMOD_Pos (19UL) /*!< CAN_NODE NFCR: CFMOD (Bit 19) */ 10768 #define CAN_NODE_NFCR_CFMOD_Msk (0x180000UL) /*!< CAN_NODE NFCR: CFMOD (Bitfield-Mask: 0x03) */ 10769 #define CAN_NODE_NFCR_CFCIE_Pos (22UL) /*!< CAN_NODE NFCR: CFCIE (Bit 22) */ 10770 #define CAN_NODE_NFCR_CFCIE_Msk (0x400000UL) /*!< CAN_NODE NFCR: CFCIE (Bitfield-Mask: 0x01) */ 10771 #define CAN_NODE_NFCR_CFCOV_Pos (23UL) /*!< CAN_NODE NFCR: CFCOV (Bit 23) */ 10772 #define CAN_NODE_NFCR_CFCOV_Msk (0x800000UL) /*!< CAN_NODE NFCR: CFCOV (Bitfield-Mask: 0x01) */ 10773 10774 10775 /* ================================================================================ */ 10776 /* ================ Group 'CAN_MO' Position & Mask ================ */ 10777 /* ================================================================================ */ 10778 10779 10780 /* -------------------------------- CAN_MO_MOFCR -------------------------------- */ 10781 #define CAN_MO_MOFCR_MMC_Pos (0UL) /*!< CAN_MO MOFCR: MMC (Bit 0) */ 10782 #define CAN_MO_MOFCR_MMC_Msk (0xfUL) /*!< CAN_MO MOFCR: MMC (Bitfield-Mask: 0x0f) */ 10783 #define CAN_MO_MOFCR_GDFS_Pos (8UL) /*!< CAN_MO MOFCR: GDFS (Bit 8) */ 10784 #define CAN_MO_MOFCR_GDFS_Msk (0x100UL) /*!< CAN_MO MOFCR: GDFS (Bitfield-Mask: 0x01) */ 10785 #define CAN_MO_MOFCR_IDC_Pos (9UL) /*!< CAN_MO MOFCR: IDC (Bit 9) */ 10786 #define CAN_MO_MOFCR_IDC_Msk (0x200UL) /*!< CAN_MO MOFCR: IDC (Bitfield-Mask: 0x01) */ 10787 #define CAN_MO_MOFCR_DLCC_Pos (10UL) /*!< CAN_MO MOFCR: DLCC (Bit 10) */ 10788 #define CAN_MO_MOFCR_DLCC_Msk (0x400UL) /*!< CAN_MO MOFCR: DLCC (Bitfield-Mask: 0x01) */ 10789 #define CAN_MO_MOFCR_DATC_Pos (11UL) /*!< CAN_MO MOFCR: DATC (Bit 11) */ 10790 #define CAN_MO_MOFCR_DATC_Msk (0x800UL) /*!< CAN_MO MOFCR: DATC (Bitfield-Mask: 0x01) */ 10791 #define CAN_MO_MOFCR_RXIE_Pos (16UL) /*!< CAN_MO MOFCR: RXIE (Bit 16) */ 10792 #define CAN_MO_MOFCR_RXIE_Msk (0x10000UL) /*!< CAN_MO MOFCR: RXIE (Bitfield-Mask: 0x01) */ 10793 #define CAN_MO_MOFCR_TXIE_Pos (17UL) /*!< CAN_MO MOFCR: TXIE (Bit 17) */ 10794 #define CAN_MO_MOFCR_TXIE_Msk (0x20000UL) /*!< CAN_MO MOFCR: TXIE (Bitfield-Mask: 0x01) */ 10795 #define CAN_MO_MOFCR_OVIE_Pos (18UL) /*!< CAN_MO MOFCR: OVIE (Bit 18) */ 10796 #define CAN_MO_MOFCR_OVIE_Msk (0x40000UL) /*!< CAN_MO MOFCR: OVIE (Bitfield-Mask: 0x01) */ 10797 #define CAN_MO_MOFCR_FRREN_Pos (20UL) /*!< CAN_MO MOFCR: FRREN (Bit 20) */ 10798 #define CAN_MO_MOFCR_FRREN_Msk (0x100000UL) /*!< CAN_MO MOFCR: FRREN (Bitfield-Mask: 0x01) */ 10799 #define CAN_MO_MOFCR_RMM_Pos (21UL) /*!< CAN_MO MOFCR: RMM (Bit 21) */ 10800 #define CAN_MO_MOFCR_RMM_Msk (0x200000UL) /*!< CAN_MO MOFCR: RMM (Bitfield-Mask: 0x01) */ 10801 #define CAN_MO_MOFCR_SDT_Pos (22UL) /*!< CAN_MO MOFCR: SDT (Bit 22) */ 10802 #define CAN_MO_MOFCR_SDT_Msk (0x400000UL) /*!< CAN_MO MOFCR: SDT (Bitfield-Mask: 0x01) */ 10803 #define CAN_MO_MOFCR_STT_Pos (23UL) /*!< CAN_MO MOFCR: STT (Bit 23) */ 10804 #define CAN_MO_MOFCR_STT_Msk (0x800000UL) /*!< CAN_MO MOFCR: STT (Bitfield-Mask: 0x01) */ 10805 #define CAN_MO_MOFCR_DLC_Pos (24UL) /*!< CAN_MO MOFCR: DLC (Bit 24) */ 10806 #define CAN_MO_MOFCR_DLC_Msk (0xf000000UL) /*!< CAN_MO MOFCR: DLC (Bitfield-Mask: 0x0f) */ 10807 10808 /* -------------------------------- CAN_MO_MOFGPR ------------------------------- */ 10809 #define CAN_MO_MOFGPR_BOT_Pos (0UL) /*!< CAN_MO MOFGPR: BOT (Bit 0) */ 10810 #define CAN_MO_MOFGPR_BOT_Msk (0xffUL) /*!< CAN_MO MOFGPR: BOT (Bitfield-Mask: 0xff) */ 10811 #define CAN_MO_MOFGPR_TOP_Pos (8UL) /*!< CAN_MO MOFGPR: TOP (Bit 8) */ 10812 #define CAN_MO_MOFGPR_TOP_Msk (0xff00UL) /*!< CAN_MO MOFGPR: TOP (Bitfield-Mask: 0xff) */ 10813 #define CAN_MO_MOFGPR_CUR_Pos (16UL) /*!< CAN_MO MOFGPR: CUR (Bit 16) */ 10814 #define CAN_MO_MOFGPR_CUR_Msk (0xff0000UL) /*!< CAN_MO MOFGPR: CUR (Bitfield-Mask: 0xff) */ 10815 #define CAN_MO_MOFGPR_SEL_Pos (24UL) /*!< CAN_MO MOFGPR: SEL (Bit 24) */ 10816 #define CAN_MO_MOFGPR_SEL_Msk (0xff000000UL) /*!< CAN_MO MOFGPR: SEL (Bitfield-Mask: 0xff) */ 10817 10818 /* -------------------------------- CAN_MO_MOIPR -------------------------------- */ 10819 #define CAN_MO_MOIPR_RXINP_Pos (0UL) /*!< CAN_MO MOIPR: RXINP (Bit 0) */ 10820 #define CAN_MO_MOIPR_RXINP_Msk (0x7UL) /*!< CAN_MO MOIPR: RXINP (Bitfield-Mask: 0x07) */ 10821 #define CAN_MO_MOIPR_TXINP_Pos (4UL) /*!< CAN_MO MOIPR: TXINP (Bit 4) */ 10822 #define CAN_MO_MOIPR_TXINP_Msk (0x70UL) /*!< CAN_MO MOIPR: TXINP (Bitfield-Mask: 0x07) */ 10823 #define CAN_MO_MOIPR_MPN_Pos (8UL) /*!< CAN_MO MOIPR: MPN (Bit 8) */ 10824 #define CAN_MO_MOIPR_MPN_Msk (0xff00UL) /*!< CAN_MO MOIPR: MPN (Bitfield-Mask: 0xff) */ 10825 #define CAN_MO_MOIPR_CFCVAL_Pos (16UL) /*!< CAN_MO MOIPR: CFCVAL (Bit 16) */ 10826 #define CAN_MO_MOIPR_CFCVAL_Msk (0xffff0000UL) /*!< CAN_MO MOIPR: CFCVAL (Bitfield-Mask: 0xffff) */ 10827 10828 /* -------------------------------- CAN_MO_MOAMR -------------------------------- */ 10829 #define CAN_MO_MOAMR_AM_Pos (0UL) /*!< CAN_MO MOAMR: AM (Bit 0) */ 10830 #define CAN_MO_MOAMR_AM_Msk (0x1fffffffUL) /*!< CAN_MO MOAMR: AM (Bitfield-Mask: 0x1fffffff) */ 10831 #define CAN_MO_MOAMR_MIDE_Pos (29UL) /*!< CAN_MO MOAMR: MIDE (Bit 29) */ 10832 #define CAN_MO_MOAMR_MIDE_Msk (0x20000000UL) /*!< CAN_MO MOAMR: MIDE (Bitfield-Mask: 0x01) */ 10833 10834 /* ------------------------------- CAN_MO_MODATAL ------------------------------- */ 10835 #define CAN_MO_MODATAL_DB0_Pos (0UL) /*!< CAN_MO MODATAL: DB0 (Bit 0) */ 10836 #define CAN_MO_MODATAL_DB0_Msk (0xffUL) /*!< CAN_MO MODATAL: DB0 (Bitfield-Mask: 0xff) */ 10837 #define CAN_MO_MODATAL_DB1_Pos (8UL) /*!< CAN_MO MODATAL: DB1 (Bit 8) */ 10838 #define CAN_MO_MODATAL_DB1_Msk (0xff00UL) /*!< CAN_MO MODATAL: DB1 (Bitfield-Mask: 0xff) */ 10839 #define CAN_MO_MODATAL_DB2_Pos (16UL) /*!< CAN_MO MODATAL: DB2 (Bit 16) */ 10840 #define CAN_MO_MODATAL_DB2_Msk (0xff0000UL) /*!< CAN_MO MODATAL: DB2 (Bitfield-Mask: 0xff) */ 10841 #define CAN_MO_MODATAL_DB3_Pos (24UL) /*!< CAN_MO MODATAL: DB3 (Bit 24) */ 10842 #define CAN_MO_MODATAL_DB3_Msk (0xff000000UL) /*!< CAN_MO MODATAL: DB3 (Bitfield-Mask: 0xff) */ 10843 10844 /* ------------------------------- CAN_MO_MODATAH ------------------------------- */ 10845 #define CAN_MO_MODATAH_DB4_Pos (0UL) /*!< CAN_MO MODATAH: DB4 (Bit 0) */ 10846 #define CAN_MO_MODATAH_DB4_Msk (0xffUL) /*!< CAN_MO MODATAH: DB4 (Bitfield-Mask: 0xff) */ 10847 #define CAN_MO_MODATAH_DB5_Pos (8UL) /*!< CAN_MO MODATAH: DB5 (Bit 8) */ 10848 #define CAN_MO_MODATAH_DB5_Msk (0xff00UL) /*!< CAN_MO MODATAH: DB5 (Bitfield-Mask: 0xff) */ 10849 #define CAN_MO_MODATAH_DB6_Pos (16UL) /*!< CAN_MO MODATAH: DB6 (Bit 16) */ 10850 #define CAN_MO_MODATAH_DB6_Msk (0xff0000UL) /*!< CAN_MO MODATAH: DB6 (Bitfield-Mask: 0xff) */ 10851 #define CAN_MO_MODATAH_DB7_Pos (24UL) /*!< CAN_MO MODATAH: DB7 (Bit 24) */ 10852 #define CAN_MO_MODATAH_DB7_Msk (0xff000000UL) /*!< CAN_MO MODATAH: DB7 (Bitfield-Mask: 0xff) */ 10853 10854 /* --------------------------------- CAN_MO_MOAR -------------------------------- */ 10855 #define CAN_MO_MOAR_ID_Pos (0UL) /*!< CAN_MO MOAR: ID (Bit 0) */ 10856 #define CAN_MO_MOAR_ID_Msk (0x1fffffffUL) /*!< CAN_MO MOAR: ID (Bitfield-Mask: 0x1fffffff) */ 10857 #define CAN_MO_MOAR_IDE_Pos (29UL) /*!< CAN_MO MOAR: IDE (Bit 29) */ 10858 #define CAN_MO_MOAR_IDE_Msk (0x20000000UL) /*!< CAN_MO MOAR: IDE (Bitfield-Mask: 0x01) */ 10859 #define CAN_MO_MOAR_PRI_Pos (30UL) /*!< CAN_MO MOAR: PRI (Bit 30) */ 10860 #define CAN_MO_MOAR_PRI_Msk (0xc0000000UL) /*!< CAN_MO MOAR: PRI (Bitfield-Mask: 0x03) */ 10861 10862 /* -------------------------------- CAN_MO_MOCTR -------------------------------- */ 10863 #define CAN_MO_MOCTR_RESRXPND_Pos (0UL) /*!< CAN_MO MOCTR: RESRXPND (Bit 0) */ 10864 #define CAN_MO_MOCTR_RESRXPND_Msk (0x1UL) /*!< CAN_MO MOCTR: RESRXPND (Bitfield-Mask: 0x01) */ 10865 #define CAN_MO_MOCTR_RESTXPND_Pos (1UL) /*!< CAN_MO MOCTR: RESTXPND (Bit 1) */ 10866 #define CAN_MO_MOCTR_RESTXPND_Msk (0x2UL) /*!< CAN_MO MOCTR: RESTXPND (Bitfield-Mask: 0x01) */ 10867 #define CAN_MO_MOCTR_RESRXUPD_Pos (2UL) /*!< CAN_MO MOCTR: RESRXUPD (Bit 2) */ 10868 #define CAN_MO_MOCTR_RESRXUPD_Msk (0x4UL) /*!< CAN_MO MOCTR: RESRXUPD (Bitfield-Mask: 0x01) */ 10869 #define CAN_MO_MOCTR_RESNEWDAT_Pos (3UL) /*!< CAN_MO MOCTR: RESNEWDAT (Bit 3) */ 10870 #define CAN_MO_MOCTR_RESNEWDAT_Msk (0x8UL) /*!< CAN_MO MOCTR: RESNEWDAT (Bitfield-Mask: 0x01) */ 10871 #define CAN_MO_MOCTR_RESMSGLST_Pos (4UL) /*!< CAN_MO MOCTR: RESMSGLST (Bit 4) */ 10872 #define CAN_MO_MOCTR_RESMSGLST_Msk (0x10UL) /*!< CAN_MO MOCTR: RESMSGLST (Bitfield-Mask: 0x01) */ 10873 #define CAN_MO_MOCTR_RESMSGVAL_Pos (5UL) /*!< CAN_MO MOCTR: RESMSGVAL (Bit 5) */ 10874 #define CAN_MO_MOCTR_RESMSGVAL_Msk (0x20UL) /*!< CAN_MO MOCTR: RESMSGVAL (Bitfield-Mask: 0x01) */ 10875 #define CAN_MO_MOCTR_RESRTSEL_Pos (6UL) /*!< CAN_MO MOCTR: RESRTSEL (Bit 6) */ 10876 #define CAN_MO_MOCTR_RESRTSEL_Msk (0x40UL) /*!< CAN_MO MOCTR: RESRTSEL (Bitfield-Mask: 0x01) */ 10877 #define CAN_MO_MOCTR_RESRXEN_Pos (7UL) /*!< CAN_MO MOCTR: RESRXEN (Bit 7) */ 10878 #define CAN_MO_MOCTR_RESRXEN_Msk (0x80UL) /*!< CAN_MO MOCTR: RESRXEN (Bitfield-Mask: 0x01) */ 10879 #define CAN_MO_MOCTR_RESTXRQ_Pos (8UL) /*!< CAN_MO MOCTR: RESTXRQ (Bit 8) */ 10880 #define CAN_MO_MOCTR_RESTXRQ_Msk (0x100UL) /*!< CAN_MO MOCTR: RESTXRQ (Bitfield-Mask: 0x01) */ 10881 #define CAN_MO_MOCTR_RESTXEN0_Pos (9UL) /*!< CAN_MO MOCTR: RESTXEN0 (Bit 9) */ 10882 #define CAN_MO_MOCTR_RESTXEN0_Msk (0x200UL) /*!< CAN_MO MOCTR: RESTXEN0 (Bitfield-Mask: 0x01) */ 10883 #define CAN_MO_MOCTR_RESTXEN1_Pos (10UL) /*!< CAN_MO MOCTR: RESTXEN1 (Bit 10) */ 10884 #define CAN_MO_MOCTR_RESTXEN1_Msk (0x400UL) /*!< CAN_MO MOCTR: RESTXEN1 (Bitfield-Mask: 0x01) */ 10885 #define CAN_MO_MOCTR_RESDIR_Pos (11UL) /*!< CAN_MO MOCTR: RESDIR (Bit 11) */ 10886 #define CAN_MO_MOCTR_RESDIR_Msk (0x800UL) /*!< CAN_MO MOCTR: RESDIR (Bitfield-Mask: 0x01) */ 10887 #define CAN_MO_MOCTR_SETRXPND_Pos (16UL) /*!< CAN_MO MOCTR: SETRXPND (Bit 16) */ 10888 #define CAN_MO_MOCTR_SETRXPND_Msk (0x10000UL) /*!< CAN_MO MOCTR: SETRXPND (Bitfield-Mask: 0x01) */ 10889 #define CAN_MO_MOCTR_SETTXPND_Pos (17UL) /*!< CAN_MO MOCTR: SETTXPND (Bit 17) */ 10890 #define CAN_MO_MOCTR_SETTXPND_Msk (0x20000UL) /*!< CAN_MO MOCTR: SETTXPND (Bitfield-Mask: 0x01) */ 10891 #define CAN_MO_MOCTR_SETRXUPD_Pos (18UL) /*!< CAN_MO MOCTR: SETRXUPD (Bit 18) */ 10892 #define CAN_MO_MOCTR_SETRXUPD_Msk (0x40000UL) /*!< CAN_MO MOCTR: SETRXUPD (Bitfield-Mask: 0x01) */ 10893 #define CAN_MO_MOCTR_SETNEWDAT_Pos (19UL) /*!< CAN_MO MOCTR: SETNEWDAT (Bit 19) */ 10894 #define CAN_MO_MOCTR_SETNEWDAT_Msk (0x80000UL) /*!< CAN_MO MOCTR: SETNEWDAT (Bitfield-Mask: 0x01) */ 10895 #define CAN_MO_MOCTR_SETMSGLST_Pos (20UL) /*!< CAN_MO MOCTR: SETMSGLST (Bit 20) */ 10896 #define CAN_MO_MOCTR_SETMSGLST_Msk (0x100000UL) /*!< CAN_MO MOCTR: SETMSGLST (Bitfield-Mask: 0x01) */ 10897 #define CAN_MO_MOCTR_SETMSGVAL_Pos (21UL) /*!< CAN_MO MOCTR: SETMSGVAL (Bit 21) */ 10898 #define CAN_MO_MOCTR_SETMSGVAL_Msk (0x200000UL) /*!< CAN_MO MOCTR: SETMSGVAL (Bitfield-Mask: 0x01) */ 10899 #define CAN_MO_MOCTR_SETRTSEL_Pos (22UL) /*!< CAN_MO MOCTR: SETRTSEL (Bit 22) */ 10900 #define CAN_MO_MOCTR_SETRTSEL_Msk (0x400000UL) /*!< CAN_MO MOCTR: SETRTSEL (Bitfield-Mask: 0x01) */ 10901 #define CAN_MO_MOCTR_SETRXEN_Pos (23UL) /*!< CAN_MO MOCTR: SETRXEN (Bit 23) */ 10902 #define CAN_MO_MOCTR_SETRXEN_Msk (0x800000UL) /*!< CAN_MO MOCTR: SETRXEN (Bitfield-Mask: 0x01) */ 10903 #define CAN_MO_MOCTR_SETTXRQ_Pos (24UL) /*!< CAN_MO MOCTR: SETTXRQ (Bit 24) */ 10904 #define CAN_MO_MOCTR_SETTXRQ_Msk (0x1000000UL) /*!< CAN_MO MOCTR: SETTXRQ (Bitfield-Mask: 0x01) */ 10905 #define CAN_MO_MOCTR_SETTXEN0_Pos (25UL) /*!< CAN_MO MOCTR: SETTXEN0 (Bit 25) */ 10906 #define CAN_MO_MOCTR_SETTXEN0_Msk (0x2000000UL) /*!< CAN_MO MOCTR: SETTXEN0 (Bitfield-Mask: 0x01) */ 10907 #define CAN_MO_MOCTR_SETTXEN1_Pos (26UL) /*!< CAN_MO MOCTR: SETTXEN1 (Bit 26) */ 10908 #define CAN_MO_MOCTR_SETTXEN1_Msk (0x4000000UL) /*!< CAN_MO MOCTR: SETTXEN1 (Bitfield-Mask: 0x01) */ 10909 #define CAN_MO_MOCTR_SETDIR_Pos (27UL) /*!< CAN_MO MOCTR: SETDIR (Bit 27) */ 10910 #define CAN_MO_MOCTR_SETDIR_Msk (0x8000000UL) /*!< CAN_MO MOCTR: SETDIR (Bitfield-Mask: 0x01) */ 10911 10912 /* -------------------------------- CAN_MO_MOSTAT ------------------------------- */ 10913 #define CAN_MO_MOSTAT_RXPND_Pos (0UL) /*!< CAN_MO MOSTAT: RXPND (Bit 0) */ 10914 #define CAN_MO_MOSTAT_RXPND_Msk (0x1UL) /*!< CAN_MO MOSTAT: RXPND (Bitfield-Mask: 0x01) */ 10915 #define CAN_MO_MOSTAT_TXPND_Pos (1UL) /*!< CAN_MO MOSTAT: TXPND (Bit 1) */ 10916 #define CAN_MO_MOSTAT_TXPND_Msk (0x2UL) /*!< CAN_MO MOSTAT: TXPND (Bitfield-Mask: 0x01) */ 10917 #define CAN_MO_MOSTAT_RXUPD_Pos (2UL) /*!< CAN_MO MOSTAT: RXUPD (Bit 2) */ 10918 #define CAN_MO_MOSTAT_RXUPD_Msk (0x4UL) /*!< CAN_MO MOSTAT: RXUPD (Bitfield-Mask: 0x01) */ 10919 #define CAN_MO_MOSTAT_NEWDAT_Pos (3UL) /*!< CAN_MO MOSTAT: NEWDAT (Bit 3) */ 10920 #define CAN_MO_MOSTAT_NEWDAT_Msk (0x8UL) /*!< CAN_MO MOSTAT: NEWDAT (Bitfield-Mask: 0x01) */ 10921 #define CAN_MO_MOSTAT_MSGLST_Pos (4UL) /*!< CAN_MO MOSTAT: MSGLST (Bit 4) */ 10922 #define CAN_MO_MOSTAT_MSGLST_Msk (0x10UL) /*!< CAN_MO MOSTAT: MSGLST (Bitfield-Mask: 0x01) */ 10923 #define CAN_MO_MOSTAT_MSGVAL_Pos (5UL) /*!< CAN_MO MOSTAT: MSGVAL (Bit 5) */ 10924 #define CAN_MO_MOSTAT_MSGVAL_Msk (0x20UL) /*!< CAN_MO MOSTAT: MSGVAL (Bitfield-Mask: 0x01) */ 10925 #define CAN_MO_MOSTAT_RTSEL_Pos (6UL) /*!< CAN_MO MOSTAT: RTSEL (Bit 6) */ 10926 #define CAN_MO_MOSTAT_RTSEL_Msk (0x40UL) /*!< CAN_MO MOSTAT: RTSEL (Bitfield-Mask: 0x01) */ 10927 #define CAN_MO_MOSTAT_RXEN_Pos (7UL) /*!< CAN_MO MOSTAT: RXEN (Bit 7) */ 10928 #define CAN_MO_MOSTAT_RXEN_Msk (0x80UL) /*!< CAN_MO MOSTAT: RXEN (Bitfield-Mask: 0x01) */ 10929 #define CAN_MO_MOSTAT_TXRQ_Pos (8UL) /*!< CAN_MO MOSTAT: TXRQ (Bit 8) */ 10930 #define CAN_MO_MOSTAT_TXRQ_Msk (0x100UL) /*!< CAN_MO MOSTAT: TXRQ (Bitfield-Mask: 0x01) */ 10931 #define CAN_MO_MOSTAT_TXEN0_Pos (9UL) /*!< CAN_MO MOSTAT: TXEN0 (Bit 9) */ 10932 #define CAN_MO_MOSTAT_TXEN0_Msk (0x200UL) /*!< CAN_MO MOSTAT: TXEN0 (Bitfield-Mask: 0x01) */ 10933 #define CAN_MO_MOSTAT_TXEN1_Pos (10UL) /*!< CAN_MO MOSTAT: TXEN1 (Bit 10) */ 10934 #define CAN_MO_MOSTAT_TXEN1_Msk (0x400UL) /*!< CAN_MO MOSTAT: TXEN1 (Bitfield-Mask: 0x01) */ 10935 #define CAN_MO_MOSTAT_DIR_Pos (11UL) /*!< CAN_MO MOSTAT: DIR (Bit 11) */ 10936 #define CAN_MO_MOSTAT_DIR_Msk (0x800UL) /*!< CAN_MO MOSTAT: DIR (Bitfield-Mask: 0x01) */ 10937 #define CAN_MO_MOSTAT_LIST_Pos (12UL) /*!< CAN_MO MOSTAT: LIST (Bit 12) */ 10938 #define CAN_MO_MOSTAT_LIST_Msk (0xf000UL) /*!< CAN_MO MOSTAT: LIST (Bitfield-Mask: 0x0f) */ 10939 #define CAN_MO_MOSTAT_PPREV_Pos (16UL) /*!< CAN_MO MOSTAT: PPREV (Bit 16) */ 10940 #define CAN_MO_MOSTAT_PPREV_Msk (0xff0000UL) /*!< CAN_MO MOSTAT: PPREV (Bitfield-Mask: 0xff) */ 10941 #define CAN_MO_MOSTAT_PNEXT_Pos (24UL) /*!< CAN_MO MOSTAT: PNEXT (Bit 24) */ 10942 #define CAN_MO_MOSTAT_PNEXT_Msk (0xff000000UL) /*!< CAN_MO MOSTAT: PNEXT (Bitfield-Mask: 0xff) */ 10943 10944 10945 /* ================================================================================ */ 10946 /* ================ struct 'VADC' Position & Mask ================ */ 10947 /* ================================================================================ */ 10948 10949 10950 /* ---------------------------------- VADC_CLC ---------------------------------- */ 10951 #define VADC_CLC_DISR_Pos (0UL) /*!< VADC CLC: DISR (Bit 0) */ 10952 #define VADC_CLC_DISR_Msk (0x1UL) /*!< VADC CLC: DISR (Bitfield-Mask: 0x01) */ 10953 #define VADC_CLC_DISS_Pos (1UL) /*!< VADC CLC: DISS (Bit 1) */ 10954 #define VADC_CLC_DISS_Msk (0x2UL) /*!< VADC CLC: DISS (Bitfield-Mask: 0x01) */ 10955 #define VADC_CLC_EDIS_Pos (3UL) /*!< VADC CLC: EDIS (Bit 3) */ 10956 #define VADC_CLC_EDIS_Msk (0x8UL) /*!< VADC CLC: EDIS (Bitfield-Mask: 0x01) */ 10957 10958 /* ----------------------------------- VADC_ID ---------------------------------- */ 10959 #define VADC_ID_MOD_REV_Pos (0UL) /*!< VADC ID: MOD_REV (Bit 0) */ 10960 #define VADC_ID_MOD_REV_Msk (0xffUL) /*!< VADC ID: MOD_REV (Bitfield-Mask: 0xff) */ 10961 #define VADC_ID_MOD_TYPE_Pos (8UL) /*!< VADC ID: MOD_TYPE (Bit 8) */ 10962 #define VADC_ID_MOD_TYPE_Msk (0xff00UL) /*!< VADC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 10963 #define VADC_ID_MOD_NUMBER_Pos (16UL) /*!< VADC ID: MOD_NUMBER (Bit 16) */ 10964 #define VADC_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< VADC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 10965 10966 /* ---------------------------------- VADC_OCS ---------------------------------- */ 10967 #define VADC_OCS_TGS_Pos (0UL) /*!< VADC OCS: TGS (Bit 0) */ 10968 #define VADC_OCS_TGS_Msk (0x3UL) /*!< VADC OCS: TGS (Bitfield-Mask: 0x03) */ 10969 #define VADC_OCS_TGB_Pos (2UL) /*!< VADC OCS: TGB (Bit 2) */ 10970 #define VADC_OCS_TGB_Msk (0x4UL) /*!< VADC OCS: TGB (Bitfield-Mask: 0x01) */ 10971 #define VADC_OCS_TG_P_Pos (3UL) /*!< VADC OCS: TG_P (Bit 3) */ 10972 #define VADC_OCS_TG_P_Msk (0x8UL) /*!< VADC OCS: TG_P (Bitfield-Mask: 0x01) */ 10973 #define VADC_OCS_SUS_Pos (24UL) /*!< VADC OCS: SUS (Bit 24) */ 10974 #define VADC_OCS_SUS_Msk (0xf000000UL) /*!< VADC OCS: SUS (Bitfield-Mask: 0x0f) */ 10975 #define VADC_OCS_SUS_P_Pos (28UL) /*!< VADC OCS: SUS_P (Bit 28) */ 10976 #define VADC_OCS_SUS_P_Msk (0x10000000UL) /*!< VADC OCS: SUS_P (Bitfield-Mask: 0x01) */ 10977 #define VADC_OCS_SUSSTA_Pos (29UL) /*!< VADC OCS: SUSSTA (Bit 29) */ 10978 #define VADC_OCS_SUSSTA_Msk (0x20000000UL) /*!< VADC OCS: SUSSTA (Bitfield-Mask: 0x01) */ 10979 10980 /* -------------------------------- VADC_GLOBCFG -------------------------------- */ 10981 #define VADC_GLOBCFG_DIVA_Pos (0UL) /*!< VADC GLOBCFG: DIVA (Bit 0) */ 10982 #define VADC_GLOBCFG_DIVA_Msk (0x1fUL) /*!< VADC GLOBCFG: DIVA (Bitfield-Mask: 0x1f) */ 10983 #define VADC_GLOBCFG_DCMSB_Pos (7UL) /*!< VADC GLOBCFG: DCMSB (Bit 7) */ 10984 #define VADC_GLOBCFG_DCMSB_Msk (0x80UL) /*!< VADC GLOBCFG: DCMSB (Bitfield-Mask: 0x01) */ 10985 #define VADC_GLOBCFG_DIVD_Pos (8UL) /*!< VADC GLOBCFG: DIVD (Bit 8) */ 10986 #define VADC_GLOBCFG_DIVD_Msk (0x300UL) /*!< VADC GLOBCFG: DIVD (Bitfield-Mask: 0x03) */ 10987 #define VADC_GLOBCFG_DIVWC_Pos (15UL) /*!< VADC GLOBCFG: DIVWC (Bit 15) */ 10988 #define VADC_GLOBCFG_DIVWC_Msk (0x8000UL) /*!< VADC GLOBCFG: DIVWC (Bitfield-Mask: 0x01) */ 10989 #define VADC_GLOBCFG_DPCAL0_Pos (16UL) /*!< VADC GLOBCFG: DPCAL0 (Bit 16) */ 10990 #define VADC_GLOBCFG_DPCAL0_Msk (0x10000UL) /*!< VADC GLOBCFG: DPCAL0 (Bitfield-Mask: 0x01) */ 10991 #define VADC_GLOBCFG_DPCAL1_Pos (17UL) /*!< VADC GLOBCFG: DPCAL1 (Bit 17) */ 10992 #define VADC_GLOBCFG_DPCAL1_Msk (0x20000UL) /*!< VADC GLOBCFG: DPCAL1 (Bitfield-Mask: 0x01) */ 10993 #define VADC_GLOBCFG_DPCAL2_Pos (18UL) /*!< VADC GLOBCFG: DPCAL2 (Bit 18) */ 10994 #define VADC_GLOBCFG_DPCAL2_Msk (0x40000UL) /*!< VADC GLOBCFG: DPCAL2 (Bitfield-Mask: 0x01) */ 10995 #define VADC_GLOBCFG_DPCAL3_Pos (19UL) /*!< VADC GLOBCFG: DPCAL3 (Bit 19) */ 10996 #define VADC_GLOBCFG_DPCAL3_Msk (0x80000UL) /*!< VADC GLOBCFG: DPCAL3 (Bitfield-Mask: 0x01) */ 10997 #define VADC_GLOBCFG_SUCAL_Pos (31UL) /*!< VADC GLOBCFG: SUCAL (Bit 31) */ 10998 #define VADC_GLOBCFG_SUCAL_Msk (0x80000000UL) /*!< VADC GLOBCFG: SUCAL (Bitfield-Mask: 0x01) */ 10999 11000 /* ------------------------------- VADC_GLOBICLASS ------------------------------ */ 11001 #define VADC_GLOBICLASS_STCS_Pos (0UL) /*!< VADC GLOBICLASS: STCS (Bit 0) */ 11002 #define VADC_GLOBICLASS_STCS_Msk (0x1fUL) /*!< VADC GLOBICLASS: STCS (Bitfield-Mask: 0x1f) */ 11003 #define VADC_GLOBICLASS_CMS_Pos (8UL) /*!< VADC GLOBICLASS: CMS (Bit 8) */ 11004 #define VADC_GLOBICLASS_CMS_Msk (0x700UL) /*!< VADC GLOBICLASS: CMS (Bitfield-Mask: 0x07) */ 11005 #define VADC_GLOBICLASS_STCE_Pos (16UL) /*!< VADC GLOBICLASS: STCE (Bit 16) */ 11006 #define VADC_GLOBICLASS_STCE_Msk (0x1f0000UL) /*!< VADC GLOBICLASS: STCE (Bitfield-Mask: 0x1f) */ 11007 #define VADC_GLOBICLASS_CME_Pos (24UL) /*!< VADC GLOBICLASS: CME (Bit 24) */ 11008 #define VADC_GLOBICLASS_CME_Msk (0x7000000UL) /*!< VADC GLOBICLASS: CME (Bitfield-Mask: 0x07) */ 11009 11010 /* ------------------------------- VADC_GLOBBOUND ------------------------------- */ 11011 #define VADC_GLOBBOUND_BOUNDARY0_Pos (0UL) /*!< VADC GLOBBOUND: BOUNDARY0 (Bit 0) */ 11012 #define VADC_GLOBBOUND_BOUNDARY0_Msk (0xfffUL) /*!< VADC GLOBBOUND: BOUNDARY0 (Bitfield-Mask: 0xfff) */ 11013 #define VADC_GLOBBOUND_BOUNDARY1_Pos (16UL) /*!< VADC GLOBBOUND: BOUNDARY1 (Bit 16) */ 11014 #define VADC_GLOBBOUND_BOUNDARY1_Msk (0xfff0000UL) /*!< VADC GLOBBOUND: BOUNDARY1 (Bitfield-Mask: 0xfff) */ 11015 11016 /* ------------------------------- VADC_GLOBEFLAG ------------------------------- */ 11017 #define VADC_GLOBEFLAG_SEVGLB_Pos (0UL) /*!< VADC GLOBEFLAG: SEVGLB (Bit 0) */ 11018 #define VADC_GLOBEFLAG_SEVGLB_Msk (0x1UL) /*!< VADC GLOBEFLAG: SEVGLB (Bitfield-Mask: 0x01) */ 11019 #define VADC_GLOBEFLAG_REVGLB_Pos (8UL) /*!< VADC GLOBEFLAG: REVGLB (Bit 8) */ 11020 #define VADC_GLOBEFLAG_REVGLB_Msk (0x100UL) /*!< VADC GLOBEFLAG: REVGLB (Bitfield-Mask: 0x01) */ 11021 #define VADC_GLOBEFLAG_SEVGLBCLR_Pos (16UL) /*!< VADC GLOBEFLAG: SEVGLBCLR (Bit 16) */ 11022 #define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x10000UL) /*!< VADC GLOBEFLAG: SEVGLBCLR (Bitfield-Mask: 0x01) */ 11023 #define VADC_GLOBEFLAG_REVGLBCLR_Pos (24UL) /*!< VADC GLOBEFLAG: REVGLBCLR (Bit 24) */ 11024 #define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x1000000UL) /*!< VADC GLOBEFLAG: REVGLBCLR (Bitfield-Mask: 0x01) */ 11025 11026 /* -------------------------------- VADC_GLOBEVNP ------------------------------- */ 11027 #define VADC_GLOBEVNP_SEV0NP_Pos (0UL) /*!< VADC GLOBEVNP: SEV0NP (Bit 0) */ 11028 #define VADC_GLOBEVNP_SEV0NP_Msk (0xfUL) /*!< VADC GLOBEVNP: SEV0NP (Bitfield-Mask: 0x0f) */ 11029 #define VADC_GLOBEVNP_REV0NP_Pos (16UL) /*!< VADC GLOBEVNP: REV0NP (Bit 16) */ 11030 #define VADC_GLOBEVNP_REV0NP_Msk (0xf0000UL) /*!< VADC GLOBEVNP: REV0NP (Bitfield-Mask: 0x0f) */ 11031 11032 /* --------------------------------- VADC_GLOBTF -------------------------------- */ 11033 #define VADC_GLOBTF_CDGR_Pos (4UL) /*!< VADC GLOBTF: CDGR (Bit 4) */ 11034 #define VADC_GLOBTF_CDGR_Msk (0xf0UL) /*!< VADC GLOBTF: CDGR (Bitfield-Mask: 0x0f) */ 11035 #define VADC_GLOBTF_CDEN_Pos (8UL) /*!< VADC GLOBTF: CDEN (Bit 8) */ 11036 #define VADC_GLOBTF_CDEN_Msk (0x100UL) /*!< VADC GLOBTF: CDEN (Bitfield-Mask: 0x01) */ 11037 #define VADC_GLOBTF_CDSEL_Pos (9UL) /*!< VADC GLOBTF: CDSEL (Bit 9) */ 11038 #define VADC_GLOBTF_CDSEL_Msk (0x600UL) /*!< VADC GLOBTF: CDSEL (Bitfield-Mask: 0x03) */ 11039 #define VADC_GLOBTF_CDWC_Pos (15UL) /*!< VADC GLOBTF: CDWC (Bit 15) */ 11040 #define VADC_GLOBTF_CDWC_Msk (0x8000UL) /*!< VADC GLOBTF: CDWC (Bitfield-Mask: 0x01) */ 11041 #define VADC_GLOBTF_PDD_Pos (16UL) /*!< VADC GLOBTF: PDD (Bit 16) */ 11042 #define VADC_GLOBTF_PDD_Msk (0x10000UL) /*!< VADC GLOBTF: PDD (Bitfield-Mask: 0x01) */ 11043 #define VADC_GLOBTF_MDWC_Pos (23UL) /*!< VADC GLOBTF: MDWC (Bit 23) */ 11044 #define VADC_GLOBTF_MDWC_Msk (0x800000UL) /*!< VADC GLOBTF: MDWC (Bitfield-Mask: 0x01) */ 11045 11046 /* --------------------------------- VADC_BRSSEL -------------------------------- */ 11047 #define VADC_BRSSEL_CHSELG0_Pos (0UL) /*!< VADC BRSSEL: CHSELG0 (Bit 0) */ 11048 #define VADC_BRSSEL_CHSELG0_Msk (0x1UL) /*!< VADC BRSSEL: CHSELG0 (Bitfield-Mask: 0x01) */ 11049 #define VADC_BRSSEL_CHSELG1_Pos (1UL) /*!< VADC BRSSEL: CHSELG1 (Bit 1) */ 11050 #define VADC_BRSSEL_CHSELG1_Msk (0x2UL) /*!< VADC BRSSEL: CHSELG1 (Bitfield-Mask: 0x01) */ 11051 #define VADC_BRSSEL_CHSELG2_Pos (2UL) /*!< VADC BRSSEL: CHSELG2 (Bit 2) */ 11052 #define VADC_BRSSEL_CHSELG2_Msk (0x4UL) /*!< VADC BRSSEL: CHSELG2 (Bitfield-Mask: 0x01) */ 11053 #define VADC_BRSSEL_CHSELG3_Pos (3UL) /*!< VADC BRSSEL: CHSELG3 (Bit 3) */ 11054 #define VADC_BRSSEL_CHSELG3_Msk (0x8UL) /*!< VADC BRSSEL: CHSELG3 (Bitfield-Mask: 0x01) */ 11055 #define VADC_BRSSEL_CHSELG4_Pos (4UL) /*!< VADC BRSSEL: CHSELG4 (Bit 4) */ 11056 #define VADC_BRSSEL_CHSELG4_Msk (0x10UL) /*!< VADC BRSSEL: CHSELG4 (Bitfield-Mask: 0x01) */ 11057 #define VADC_BRSSEL_CHSELG5_Pos (5UL) /*!< VADC BRSSEL: CHSELG5 (Bit 5) */ 11058 #define VADC_BRSSEL_CHSELG5_Msk (0x20UL) /*!< VADC BRSSEL: CHSELG5 (Bitfield-Mask: 0x01) */ 11059 #define VADC_BRSSEL_CHSELG6_Pos (6UL) /*!< VADC BRSSEL: CHSELG6 (Bit 6) */ 11060 #define VADC_BRSSEL_CHSELG6_Msk (0x40UL) /*!< VADC BRSSEL: CHSELG6 (Bitfield-Mask: 0x01) */ 11061 #define VADC_BRSSEL_CHSELG7_Pos (7UL) /*!< VADC BRSSEL: CHSELG7 (Bit 7) */ 11062 #define VADC_BRSSEL_CHSELG7_Msk (0x80UL) /*!< VADC BRSSEL: CHSELG7 (Bitfield-Mask: 0x01) */ 11063 11064 /* --------------------------------- VADC_BRSPND -------------------------------- */ 11065 #define VADC_BRSPND_CHPNDG0_Pos (0UL) /*!< VADC BRSPND: CHPNDG0 (Bit 0) */ 11066 #define VADC_BRSPND_CHPNDG0_Msk (0x1UL) /*!< VADC BRSPND: CHPNDG0 (Bitfield-Mask: 0x01) */ 11067 #define VADC_BRSPND_CHPNDG1_Pos (1UL) /*!< VADC BRSPND: CHPNDG1 (Bit 1) */ 11068 #define VADC_BRSPND_CHPNDG1_Msk (0x2UL) /*!< VADC BRSPND: CHPNDG1 (Bitfield-Mask: 0x01) */ 11069 #define VADC_BRSPND_CHPNDG2_Pos (2UL) /*!< VADC BRSPND: CHPNDG2 (Bit 2) */ 11070 #define VADC_BRSPND_CHPNDG2_Msk (0x4UL) /*!< VADC BRSPND: CHPNDG2 (Bitfield-Mask: 0x01) */ 11071 #define VADC_BRSPND_CHPNDG3_Pos (3UL) /*!< VADC BRSPND: CHPNDG3 (Bit 3) */ 11072 #define VADC_BRSPND_CHPNDG3_Msk (0x8UL) /*!< VADC BRSPND: CHPNDG3 (Bitfield-Mask: 0x01) */ 11073 #define VADC_BRSPND_CHPNDG4_Pos (4UL) /*!< VADC BRSPND: CHPNDG4 (Bit 4) */ 11074 #define VADC_BRSPND_CHPNDG4_Msk (0x10UL) /*!< VADC BRSPND: CHPNDG4 (Bitfield-Mask: 0x01) */ 11075 #define VADC_BRSPND_CHPNDG5_Pos (5UL) /*!< VADC BRSPND: CHPNDG5 (Bit 5) */ 11076 #define VADC_BRSPND_CHPNDG5_Msk (0x20UL) /*!< VADC BRSPND: CHPNDG5 (Bitfield-Mask: 0x01) */ 11077 #define VADC_BRSPND_CHPNDG6_Pos (6UL) /*!< VADC BRSPND: CHPNDG6 (Bit 6) */ 11078 #define VADC_BRSPND_CHPNDG6_Msk (0x40UL) /*!< VADC BRSPND: CHPNDG6 (Bitfield-Mask: 0x01) */ 11079 #define VADC_BRSPND_CHPNDG7_Pos (7UL) /*!< VADC BRSPND: CHPNDG7 (Bit 7) */ 11080 #define VADC_BRSPND_CHPNDG7_Msk (0x80UL) /*!< VADC BRSPND: CHPNDG7 (Bitfield-Mask: 0x01) */ 11081 11082 /* -------------------------------- VADC_BRSCTRL -------------------------------- */ 11083 #define VADC_BRSCTRL_XTSEL_Pos (8UL) /*!< VADC BRSCTRL: XTSEL (Bit 8) */ 11084 #define VADC_BRSCTRL_XTSEL_Msk (0xf00UL) /*!< VADC BRSCTRL: XTSEL (Bitfield-Mask: 0x0f) */ 11085 #define VADC_BRSCTRL_XTLVL_Pos (12UL) /*!< VADC BRSCTRL: XTLVL (Bit 12) */ 11086 #define VADC_BRSCTRL_XTLVL_Msk (0x1000UL) /*!< VADC BRSCTRL: XTLVL (Bitfield-Mask: 0x01) */ 11087 #define VADC_BRSCTRL_XTMODE_Pos (13UL) /*!< VADC BRSCTRL: XTMODE (Bit 13) */ 11088 #define VADC_BRSCTRL_XTMODE_Msk (0x6000UL) /*!< VADC BRSCTRL: XTMODE (Bitfield-Mask: 0x03) */ 11089 #define VADC_BRSCTRL_XTWC_Pos (15UL) /*!< VADC BRSCTRL: XTWC (Bit 15) */ 11090 #define VADC_BRSCTRL_XTWC_Msk (0x8000UL) /*!< VADC BRSCTRL: XTWC (Bitfield-Mask: 0x01) */ 11091 #define VADC_BRSCTRL_GTSEL_Pos (16UL) /*!< VADC BRSCTRL: GTSEL (Bit 16) */ 11092 #define VADC_BRSCTRL_GTSEL_Msk (0xf0000UL) /*!< VADC BRSCTRL: GTSEL (Bitfield-Mask: 0x0f) */ 11093 #define VADC_BRSCTRL_GTLVL_Pos (20UL) /*!< VADC BRSCTRL: GTLVL (Bit 20) */ 11094 #define VADC_BRSCTRL_GTLVL_Msk (0x100000UL) /*!< VADC BRSCTRL: GTLVL (Bitfield-Mask: 0x01) */ 11095 #define VADC_BRSCTRL_GTWC_Pos (23UL) /*!< VADC BRSCTRL: GTWC (Bit 23) */ 11096 #define VADC_BRSCTRL_GTWC_Msk (0x800000UL) /*!< VADC BRSCTRL: GTWC (Bitfield-Mask: 0x01) */ 11097 11098 /* --------------------------------- VADC_BRSMR --------------------------------- */ 11099 #define VADC_BRSMR_ENGT_Pos (0UL) /*!< VADC BRSMR: ENGT (Bit 0) */ 11100 #define VADC_BRSMR_ENGT_Msk (0x3UL) /*!< VADC BRSMR: ENGT (Bitfield-Mask: 0x03) */ 11101 #define VADC_BRSMR_ENTR_Pos (2UL) /*!< VADC BRSMR: ENTR (Bit 2) */ 11102 #define VADC_BRSMR_ENTR_Msk (0x4UL) /*!< VADC BRSMR: ENTR (Bitfield-Mask: 0x01) */ 11103 #define VADC_BRSMR_ENSI_Pos (3UL) /*!< VADC BRSMR: ENSI (Bit 3) */ 11104 #define VADC_BRSMR_ENSI_Msk (0x8UL) /*!< VADC BRSMR: ENSI (Bitfield-Mask: 0x01) */ 11105 #define VADC_BRSMR_SCAN_Pos (4UL) /*!< VADC BRSMR: SCAN (Bit 4) */ 11106 #define VADC_BRSMR_SCAN_Msk (0x10UL) /*!< VADC BRSMR: SCAN (Bitfield-Mask: 0x01) */ 11107 #define VADC_BRSMR_LDM_Pos (5UL) /*!< VADC BRSMR: LDM (Bit 5) */ 11108 #define VADC_BRSMR_LDM_Msk (0x20UL) /*!< VADC BRSMR: LDM (Bitfield-Mask: 0x01) */ 11109 #define VADC_BRSMR_REQGT_Pos (7UL) /*!< VADC BRSMR: REQGT (Bit 7) */ 11110 #define VADC_BRSMR_REQGT_Msk (0x80UL) /*!< VADC BRSMR: REQGT (Bitfield-Mask: 0x01) */ 11111 #define VADC_BRSMR_CLRPND_Pos (8UL) /*!< VADC BRSMR: CLRPND (Bit 8) */ 11112 #define VADC_BRSMR_CLRPND_Msk (0x100UL) /*!< VADC BRSMR: CLRPND (Bitfield-Mask: 0x01) */ 11113 #define VADC_BRSMR_LDEV_Pos (9UL) /*!< VADC BRSMR: LDEV (Bit 9) */ 11114 #define VADC_BRSMR_LDEV_Msk (0x200UL) /*!< VADC BRSMR: LDEV (Bitfield-Mask: 0x01) */ 11115 #define VADC_BRSMR_RPTDIS_Pos (16UL) /*!< VADC BRSMR: RPTDIS (Bit 16) */ 11116 #define VADC_BRSMR_RPTDIS_Msk (0x10000UL) /*!< VADC BRSMR: RPTDIS (Bitfield-Mask: 0x01) */ 11117 11118 /* -------------------------------- VADC_GLOBRCR -------------------------------- */ 11119 #define VADC_GLOBRCR_DRCTR_Pos (16UL) /*!< VADC GLOBRCR: DRCTR (Bit 16) */ 11120 #define VADC_GLOBRCR_DRCTR_Msk (0xf0000UL) /*!< VADC GLOBRCR: DRCTR (Bitfield-Mask: 0x0f) */ 11121 #define VADC_GLOBRCR_WFR_Pos (24UL) /*!< VADC GLOBRCR: WFR (Bit 24) */ 11122 #define VADC_GLOBRCR_WFR_Msk (0x1000000UL) /*!< VADC GLOBRCR: WFR (Bitfield-Mask: 0x01) */ 11123 #define VADC_GLOBRCR_SRGEN_Pos (31UL) /*!< VADC GLOBRCR: SRGEN (Bit 31) */ 11124 #define VADC_GLOBRCR_SRGEN_Msk (0x80000000UL) /*!< VADC GLOBRCR: SRGEN (Bitfield-Mask: 0x01) */ 11125 11126 /* -------------------------------- VADC_GLOBRES -------------------------------- */ 11127 #define VADC_GLOBRES_RESULT_Pos (0UL) /*!< VADC GLOBRES: RESULT (Bit 0) */ 11128 #define VADC_GLOBRES_RESULT_Msk (0xffffUL) /*!< VADC GLOBRES: RESULT (Bitfield-Mask: 0xffff) */ 11129 #define VADC_GLOBRES_GNR_Pos (16UL) /*!< VADC GLOBRES: GNR (Bit 16) */ 11130 #define VADC_GLOBRES_GNR_Msk (0xf0000UL) /*!< VADC GLOBRES: GNR (Bitfield-Mask: 0x0f) */ 11131 #define VADC_GLOBRES_CHNR_Pos (20UL) /*!< VADC GLOBRES: CHNR (Bit 20) */ 11132 #define VADC_GLOBRES_CHNR_Msk (0x1f00000UL) /*!< VADC GLOBRES: CHNR (Bitfield-Mask: 0x1f) */ 11133 #define VADC_GLOBRES_EMUX_Pos (25UL) /*!< VADC GLOBRES: EMUX (Bit 25) */ 11134 #define VADC_GLOBRES_EMUX_Msk (0xe000000UL) /*!< VADC GLOBRES: EMUX (Bitfield-Mask: 0x07) */ 11135 #define VADC_GLOBRES_CRS_Pos (28UL) /*!< VADC GLOBRES: CRS (Bit 28) */ 11136 #define VADC_GLOBRES_CRS_Msk (0x30000000UL) /*!< VADC GLOBRES: CRS (Bitfield-Mask: 0x03) */ 11137 #define VADC_GLOBRES_FCR_Pos (30UL) /*!< VADC GLOBRES: FCR (Bit 30) */ 11138 #define VADC_GLOBRES_FCR_Msk (0x40000000UL) /*!< VADC GLOBRES: FCR (Bitfield-Mask: 0x01) */ 11139 #define VADC_GLOBRES_VF_Pos (31UL) /*!< VADC GLOBRES: VF (Bit 31) */ 11140 #define VADC_GLOBRES_VF_Msk (0x80000000UL) /*!< VADC GLOBRES: VF (Bitfield-Mask: 0x01) */ 11141 11142 /* -------------------------------- VADC_GLOBRESD ------------------------------- */ 11143 #define VADC_GLOBRESD_RESULT_Pos (0UL) /*!< VADC GLOBRESD: RESULT (Bit 0) */ 11144 #define VADC_GLOBRESD_RESULT_Msk (0xffffUL) /*!< VADC GLOBRESD: RESULT (Bitfield-Mask: 0xffff) */ 11145 #define VADC_GLOBRESD_GNR_Pos (16UL) /*!< VADC GLOBRESD: GNR (Bit 16) */ 11146 #define VADC_GLOBRESD_GNR_Msk (0xf0000UL) /*!< VADC GLOBRESD: GNR (Bitfield-Mask: 0x0f) */ 11147 #define VADC_GLOBRESD_CHNR_Pos (20UL) /*!< VADC GLOBRESD: CHNR (Bit 20) */ 11148 #define VADC_GLOBRESD_CHNR_Msk (0x1f00000UL) /*!< VADC GLOBRESD: CHNR (Bitfield-Mask: 0x1f) */ 11149 #define VADC_GLOBRESD_EMUX_Pos (25UL) /*!< VADC GLOBRESD: EMUX (Bit 25) */ 11150 #define VADC_GLOBRESD_EMUX_Msk (0xe000000UL) /*!< VADC GLOBRESD: EMUX (Bitfield-Mask: 0x07) */ 11151 #define VADC_GLOBRESD_CRS_Pos (28UL) /*!< VADC GLOBRESD: CRS (Bit 28) */ 11152 #define VADC_GLOBRESD_CRS_Msk (0x30000000UL) /*!< VADC GLOBRESD: CRS (Bitfield-Mask: 0x03) */ 11153 #define VADC_GLOBRESD_FCR_Pos (30UL) /*!< VADC GLOBRESD: FCR (Bit 30) */ 11154 #define VADC_GLOBRESD_FCR_Msk (0x40000000UL) /*!< VADC GLOBRESD: FCR (Bitfield-Mask: 0x01) */ 11155 #define VADC_GLOBRESD_VF_Pos (31UL) /*!< VADC GLOBRESD: VF (Bit 31) */ 11156 #define VADC_GLOBRESD_VF_Msk (0x80000000UL) /*!< VADC GLOBRESD: VF (Bitfield-Mask: 0x01) */ 11157 11158 /* -------------------------------- VADC_EMUXSEL -------------------------------- */ 11159 #define VADC_EMUXSEL_EMUXGRP0_Pos (0UL) /*!< VADC EMUXSEL: EMUXGRP0 (Bit 0) */ 11160 #define VADC_EMUXSEL_EMUXGRP0_Msk (0xfUL) /*!< VADC EMUXSEL: EMUXGRP0 (Bitfield-Mask: 0x0f) */ 11161 #define VADC_EMUXSEL_EMUXGRP1_Pos (4UL) /*!< VADC EMUXSEL: EMUXGRP1 (Bit 4) */ 11162 #define VADC_EMUXSEL_EMUXGRP1_Msk (0xf0UL) /*!< VADC EMUXSEL: EMUXGRP1 (Bitfield-Mask: 0x0f) */ 11163 11164 11165 /* ================================================================================ */ 11166 /* ================ Group 'VADC_G' Position & Mask ================ */ 11167 /* ================================================================================ */ 11168 11169 11170 /* -------------------------------- VADC_G_ARBCFG ------------------------------- */ 11171 #define VADC_G_ARBCFG_ANONC_Pos (0UL) /*!< VADC_G ARBCFG: ANONC (Bit 0) */ 11172 #define VADC_G_ARBCFG_ANONC_Msk (0x3UL) /*!< VADC_G ARBCFG: ANONC (Bitfield-Mask: 0x03) */ 11173 #define VADC_G_ARBCFG_ARBRND_Pos (4UL) /*!< VADC_G ARBCFG: ARBRND (Bit 4) */ 11174 #define VADC_G_ARBCFG_ARBRND_Msk (0x30UL) /*!< VADC_G ARBCFG: ARBRND (Bitfield-Mask: 0x03) */ 11175 #define VADC_G_ARBCFG_ARBM_Pos (7UL) /*!< VADC_G ARBCFG: ARBM (Bit 7) */ 11176 #define VADC_G_ARBCFG_ARBM_Msk (0x80UL) /*!< VADC_G ARBCFG: ARBM (Bitfield-Mask: 0x01) */ 11177 #define VADC_G_ARBCFG_ANONS_Pos (16UL) /*!< VADC_G ARBCFG: ANONS (Bit 16) */ 11178 #define VADC_G_ARBCFG_ANONS_Msk (0x30000UL) /*!< VADC_G ARBCFG: ANONS (Bitfield-Mask: 0x03) */ 11179 #define VADC_G_ARBCFG_CAL_Pos (28UL) /*!< VADC_G ARBCFG: CAL (Bit 28) */ 11180 #define VADC_G_ARBCFG_CAL_Msk (0x10000000UL) /*!< VADC_G ARBCFG: CAL (Bitfield-Mask: 0x01) */ 11181 #define VADC_G_ARBCFG_BUSY_Pos (30UL) /*!< VADC_G ARBCFG: BUSY (Bit 30) */ 11182 #define VADC_G_ARBCFG_BUSY_Msk (0x40000000UL) /*!< VADC_G ARBCFG: BUSY (Bitfield-Mask: 0x01) */ 11183 #define VADC_G_ARBCFG_SAMPLE_Pos (31UL) /*!< VADC_G ARBCFG: SAMPLE (Bit 31) */ 11184 #define VADC_G_ARBCFG_SAMPLE_Msk (0x80000000UL) /*!< VADC_G ARBCFG: SAMPLE (Bitfield-Mask: 0x01) */ 11185 11186 /* -------------------------------- VADC_G_ARBPR -------------------------------- */ 11187 #define VADC_G_ARBPR_PRIO0_Pos (0UL) /*!< VADC_G ARBPR: PRIO0 (Bit 0) */ 11188 #define VADC_G_ARBPR_PRIO0_Msk (0x3UL) /*!< VADC_G ARBPR: PRIO0 (Bitfield-Mask: 0x03) */ 11189 #define VADC_G_ARBPR_CSM0_Pos (3UL) /*!< VADC_G ARBPR: CSM0 (Bit 3) */ 11190 #define VADC_G_ARBPR_CSM0_Msk (0x8UL) /*!< VADC_G ARBPR: CSM0 (Bitfield-Mask: 0x01) */ 11191 #define VADC_G_ARBPR_PRIO1_Pos (4UL) /*!< VADC_G ARBPR: PRIO1 (Bit 4) */ 11192 #define VADC_G_ARBPR_PRIO1_Msk (0x30UL) /*!< VADC_G ARBPR: PRIO1 (Bitfield-Mask: 0x03) */ 11193 #define VADC_G_ARBPR_CSM1_Pos (7UL) /*!< VADC_G ARBPR: CSM1 (Bit 7) */ 11194 #define VADC_G_ARBPR_CSM1_Msk (0x80UL) /*!< VADC_G ARBPR: CSM1 (Bitfield-Mask: 0x01) */ 11195 #define VADC_G_ARBPR_PRIO2_Pos (8UL) /*!< VADC_G ARBPR: PRIO2 (Bit 8) */ 11196 #define VADC_G_ARBPR_PRIO2_Msk (0x300UL) /*!< VADC_G ARBPR: PRIO2 (Bitfield-Mask: 0x03) */ 11197 #define VADC_G_ARBPR_CSM2_Pos (11UL) /*!< VADC_G ARBPR: CSM2 (Bit 11) */ 11198 #define VADC_G_ARBPR_CSM2_Msk (0x800UL) /*!< VADC_G ARBPR: CSM2 (Bitfield-Mask: 0x01) */ 11199 #define VADC_G_ARBPR_ASEN0_Pos (24UL) /*!< VADC_G ARBPR: ASEN0 (Bit 24) */ 11200 #define VADC_G_ARBPR_ASEN0_Msk (0x1000000UL) /*!< VADC_G ARBPR: ASEN0 (Bitfield-Mask: 0x01) */ 11201 #define VADC_G_ARBPR_ASEN1_Pos (25UL) /*!< VADC_G ARBPR: ASEN1 (Bit 25) */ 11202 #define VADC_G_ARBPR_ASEN1_Msk (0x2000000UL) /*!< VADC_G ARBPR: ASEN1 (Bitfield-Mask: 0x01) */ 11203 #define VADC_G_ARBPR_ASEN2_Pos (26UL) /*!< VADC_G ARBPR: ASEN2 (Bit 26) */ 11204 #define VADC_G_ARBPR_ASEN2_Msk (0x4000000UL) /*!< VADC_G ARBPR: ASEN2 (Bitfield-Mask: 0x01) */ 11205 11206 /* -------------------------------- VADC_G_CHASS -------------------------------- */ 11207 #define VADC_G_CHASS_ASSCH0_Pos (0UL) /*!< VADC_G CHASS: ASSCH0 (Bit 0) */ 11208 #define VADC_G_CHASS_ASSCH0_Msk (0x1UL) /*!< VADC_G CHASS: ASSCH0 (Bitfield-Mask: 0x01) */ 11209 #define VADC_G_CHASS_ASSCH1_Pos (1UL) /*!< VADC_G CHASS: ASSCH1 (Bit 1) */ 11210 #define VADC_G_CHASS_ASSCH1_Msk (0x2UL) /*!< VADC_G CHASS: ASSCH1 (Bitfield-Mask: 0x01) */ 11211 #define VADC_G_CHASS_ASSCH2_Pos (2UL) /*!< VADC_G CHASS: ASSCH2 (Bit 2) */ 11212 #define VADC_G_CHASS_ASSCH2_Msk (0x4UL) /*!< VADC_G CHASS: ASSCH2 (Bitfield-Mask: 0x01) */ 11213 #define VADC_G_CHASS_ASSCH3_Pos (3UL) /*!< VADC_G CHASS: ASSCH3 (Bit 3) */ 11214 #define VADC_G_CHASS_ASSCH3_Msk (0x8UL) /*!< VADC_G CHASS: ASSCH3 (Bitfield-Mask: 0x01) */ 11215 #define VADC_G_CHASS_ASSCH4_Pos (4UL) /*!< VADC_G CHASS: ASSCH4 (Bit 4) */ 11216 #define VADC_G_CHASS_ASSCH4_Msk (0x10UL) /*!< VADC_G CHASS: ASSCH4 (Bitfield-Mask: 0x01) */ 11217 #define VADC_G_CHASS_ASSCH5_Pos (5UL) /*!< VADC_G CHASS: ASSCH5 (Bit 5) */ 11218 #define VADC_G_CHASS_ASSCH5_Msk (0x20UL) /*!< VADC_G CHASS: ASSCH5 (Bitfield-Mask: 0x01) */ 11219 #define VADC_G_CHASS_ASSCH6_Pos (6UL) /*!< VADC_G CHASS: ASSCH6 (Bit 6) */ 11220 #define VADC_G_CHASS_ASSCH6_Msk (0x40UL) /*!< VADC_G CHASS: ASSCH6 (Bitfield-Mask: 0x01) */ 11221 #define VADC_G_CHASS_ASSCH7_Pos (7UL) /*!< VADC_G CHASS: ASSCH7 (Bit 7) */ 11222 #define VADC_G_CHASS_ASSCH7_Msk (0x80UL) /*!< VADC_G CHASS: ASSCH7 (Bitfield-Mask: 0x01) */ 11223 11224 /* -------------------------------- VADC_G_ICLASS ------------------------------- */ 11225 #define VADC_G_ICLASS_STCS_Pos (0UL) /*!< VADC_G ICLASS: STCS (Bit 0) */ 11226 #define VADC_G_ICLASS_STCS_Msk (0x1fUL) /*!< VADC_G ICLASS: STCS (Bitfield-Mask: 0x1f) */ 11227 #define VADC_G_ICLASS_CMS_Pos (8UL) /*!< VADC_G ICLASS: CMS (Bit 8) */ 11228 #define VADC_G_ICLASS_CMS_Msk (0x700UL) /*!< VADC_G ICLASS: CMS (Bitfield-Mask: 0x07) */ 11229 #define VADC_G_ICLASS_STCE_Pos (16UL) /*!< VADC_G ICLASS: STCE (Bit 16) */ 11230 #define VADC_G_ICLASS_STCE_Msk (0x1f0000UL) /*!< VADC_G ICLASS: STCE (Bitfield-Mask: 0x1f) */ 11231 #define VADC_G_ICLASS_CME_Pos (24UL) /*!< VADC_G ICLASS: CME (Bit 24) */ 11232 #define VADC_G_ICLASS_CME_Msk (0x7000000UL) /*!< VADC_G ICLASS: CME (Bitfield-Mask: 0x07) */ 11233 11234 /* -------------------------------- VADC_G_ALIAS -------------------------------- */ 11235 #define VADC_G_ALIAS_ALIAS0_Pos (0UL) /*!< VADC_G ALIAS: ALIAS0 (Bit 0) */ 11236 #define VADC_G_ALIAS_ALIAS0_Msk (0x1fUL) /*!< VADC_G ALIAS: ALIAS0 (Bitfield-Mask: 0x1f) */ 11237 #define VADC_G_ALIAS_ALIAS1_Pos (8UL) /*!< VADC_G ALIAS: ALIAS1 (Bit 8) */ 11238 #define VADC_G_ALIAS_ALIAS1_Msk (0x1f00UL) /*!< VADC_G ALIAS: ALIAS1 (Bitfield-Mask: 0x1f) */ 11239 11240 /* -------------------------------- VADC_G_BOUND -------------------------------- */ 11241 #define VADC_G_BOUND_BOUNDARY0_Pos (0UL) /*!< VADC_G BOUND: BOUNDARY0 (Bit 0) */ 11242 #define VADC_G_BOUND_BOUNDARY0_Msk (0xfffUL) /*!< VADC_G BOUND: BOUNDARY0 (Bitfield-Mask: 0xfff) */ 11243 #define VADC_G_BOUND_BOUNDARY1_Pos (16UL) /*!< VADC_G BOUND: BOUNDARY1 (Bit 16) */ 11244 #define VADC_G_BOUND_BOUNDARY1_Msk (0xfff0000UL) /*!< VADC_G BOUND: BOUNDARY1 (Bitfield-Mask: 0xfff) */ 11245 11246 /* -------------------------------- VADC_G_SYNCTR ------------------------------- */ 11247 #define VADC_G_SYNCTR_STSEL_Pos (0UL) /*!< VADC_G SYNCTR: STSEL (Bit 0) */ 11248 #define VADC_G_SYNCTR_STSEL_Msk (0x3UL) /*!< VADC_G SYNCTR: STSEL (Bitfield-Mask: 0x03) */ 11249 #define VADC_G_SYNCTR_EVALR1_Pos (4UL) /*!< VADC_G SYNCTR: EVALR1 (Bit 4) */ 11250 #define VADC_G_SYNCTR_EVALR1_Msk (0x10UL) /*!< VADC_G SYNCTR: EVALR1 (Bitfield-Mask: 0x01) */ 11251 #define VADC_G_SYNCTR_EVALR2_Pos (5UL) /*!< VADC_G SYNCTR: EVALR2 (Bit 5) */ 11252 #define VADC_G_SYNCTR_EVALR2_Msk (0x20UL) /*!< VADC_G SYNCTR: EVALR2 (Bitfield-Mask: 0x01) */ 11253 #define VADC_G_SYNCTR_EVALR3_Pos (6UL) /*!< VADC_G SYNCTR: EVALR3 (Bit 6) */ 11254 #define VADC_G_SYNCTR_EVALR3_Msk (0x40UL) /*!< VADC_G SYNCTR: EVALR3 (Bitfield-Mask: 0x01) */ 11255 11256 /* --------------------------------- VADC_G_BFL --------------------------------- */ 11257 #define VADC_G_BFL_BFL0_Pos (0UL) /*!< VADC_G BFL: BFL0 (Bit 0) */ 11258 #define VADC_G_BFL_BFL0_Msk (0x1UL) /*!< VADC_G BFL: BFL0 (Bitfield-Mask: 0x01) */ 11259 #define VADC_G_BFL_BFL1_Pos (1UL) /*!< VADC_G BFL: BFL1 (Bit 1) */ 11260 #define VADC_G_BFL_BFL1_Msk (0x2UL) /*!< VADC_G BFL: BFL1 (Bitfield-Mask: 0x01) */ 11261 #define VADC_G_BFL_BFL2_Pos (2UL) /*!< VADC_G BFL: BFL2 (Bit 2) */ 11262 #define VADC_G_BFL_BFL2_Msk (0x4UL) /*!< VADC_G BFL: BFL2 (Bitfield-Mask: 0x01) */ 11263 #define VADC_G_BFL_BFL3_Pos (3UL) /*!< VADC_G BFL: BFL3 (Bit 3) */ 11264 #define VADC_G_BFL_BFL3_Msk (0x8UL) /*!< VADC_G BFL: BFL3 (Bitfield-Mask: 0x01) */ 11265 #define VADC_G_BFL_BFE0_Pos (16UL) /*!< VADC_G BFL: BFE0 (Bit 16) */ 11266 #define VADC_G_BFL_BFE0_Msk (0x10000UL) /*!< VADC_G BFL: BFE0 (Bitfield-Mask: 0x01) */ 11267 #define VADC_G_BFL_BFE1_Pos (17UL) /*!< VADC_G BFL: BFE1 (Bit 17) */ 11268 #define VADC_G_BFL_BFE1_Msk (0x20000UL) /*!< VADC_G BFL: BFE1 (Bitfield-Mask: 0x01) */ 11269 #define VADC_G_BFL_BFE2_Pos (18UL) /*!< VADC_G BFL: BFE2 (Bit 18) */ 11270 #define VADC_G_BFL_BFE2_Msk (0x40000UL) /*!< VADC_G BFL: BFE2 (Bitfield-Mask: 0x01) */ 11271 #define VADC_G_BFL_BFE3_Pos (19UL) /*!< VADC_G BFL: BFE3 (Bit 19) */ 11272 #define VADC_G_BFL_BFE3_Msk (0x80000UL) /*!< VADC_G BFL: BFE3 (Bitfield-Mask: 0x01) */ 11273 11274 /* -------------------------------- VADC_G_QCTRL0 ------------------------------- */ 11275 #define VADC_G_QCTRL0_XTSEL_Pos (8UL) /*!< VADC_G QCTRL0: XTSEL (Bit 8) */ 11276 #define VADC_G_QCTRL0_XTSEL_Msk (0xf00UL) /*!< VADC_G QCTRL0: XTSEL (Bitfield-Mask: 0x0f) */ 11277 #define VADC_G_QCTRL0_XTLVL_Pos (12UL) /*!< VADC_G QCTRL0: XTLVL (Bit 12) */ 11278 #define VADC_G_QCTRL0_XTLVL_Msk (0x1000UL) /*!< VADC_G QCTRL0: XTLVL (Bitfield-Mask: 0x01) */ 11279 #define VADC_G_QCTRL0_XTMODE_Pos (13UL) /*!< VADC_G QCTRL0: XTMODE (Bit 13) */ 11280 #define VADC_G_QCTRL0_XTMODE_Msk (0x6000UL) /*!< VADC_G QCTRL0: XTMODE (Bitfield-Mask: 0x03) */ 11281 #define VADC_G_QCTRL0_XTWC_Pos (15UL) /*!< VADC_G QCTRL0: XTWC (Bit 15) */ 11282 #define VADC_G_QCTRL0_XTWC_Msk (0x8000UL) /*!< VADC_G QCTRL0: XTWC (Bitfield-Mask: 0x01) */ 11283 #define VADC_G_QCTRL0_GTSEL_Pos (16UL) /*!< VADC_G QCTRL0: GTSEL (Bit 16) */ 11284 #define VADC_G_QCTRL0_GTSEL_Msk (0xf0000UL) /*!< VADC_G QCTRL0: GTSEL (Bitfield-Mask: 0x0f) */ 11285 #define VADC_G_QCTRL0_GTLVL_Pos (20UL) /*!< VADC_G QCTRL0: GTLVL (Bit 20) */ 11286 #define VADC_G_QCTRL0_GTLVL_Msk (0x100000UL) /*!< VADC_G QCTRL0: GTLVL (Bitfield-Mask: 0x01) */ 11287 #define VADC_G_QCTRL0_GTWC_Pos (23UL) /*!< VADC_G QCTRL0: GTWC (Bit 23) */ 11288 #define VADC_G_QCTRL0_GTWC_Msk (0x800000UL) /*!< VADC_G QCTRL0: GTWC (Bitfield-Mask: 0x01) */ 11289 #define VADC_G_QCTRL0_TMEN_Pos (28UL) /*!< VADC_G QCTRL0: TMEN (Bit 28) */ 11290 #define VADC_G_QCTRL0_TMEN_Msk (0x10000000UL) /*!< VADC_G QCTRL0: TMEN (Bitfield-Mask: 0x01) */ 11291 #define VADC_G_QCTRL0_TMWC_Pos (31UL) /*!< VADC_G QCTRL0: TMWC (Bit 31) */ 11292 #define VADC_G_QCTRL0_TMWC_Msk (0x80000000UL) /*!< VADC_G QCTRL0: TMWC (Bitfield-Mask: 0x01) */ 11293 11294 /* --------------------------------- VADC_G_QMR0 -------------------------------- */ 11295 #define VADC_G_QMR0_ENGT_Pos (0UL) /*!< VADC_G QMR0: ENGT (Bit 0) */ 11296 #define VADC_G_QMR0_ENGT_Msk (0x3UL) /*!< VADC_G QMR0: ENGT (Bitfield-Mask: 0x03) */ 11297 #define VADC_G_QMR0_ENTR_Pos (2UL) /*!< VADC_G QMR0: ENTR (Bit 2) */ 11298 #define VADC_G_QMR0_ENTR_Msk (0x4UL) /*!< VADC_G QMR0: ENTR (Bitfield-Mask: 0x01) */ 11299 #define VADC_G_QMR0_CLRV_Pos (8UL) /*!< VADC_G QMR0: CLRV (Bit 8) */ 11300 #define VADC_G_QMR0_CLRV_Msk (0x100UL) /*!< VADC_G QMR0: CLRV (Bitfield-Mask: 0x01) */ 11301 #define VADC_G_QMR0_TREV_Pos (9UL) /*!< VADC_G QMR0: TREV (Bit 9) */ 11302 #define VADC_G_QMR0_TREV_Msk (0x200UL) /*!< VADC_G QMR0: TREV (Bitfield-Mask: 0x01) */ 11303 #define VADC_G_QMR0_FLUSH_Pos (10UL) /*!< VADC_G QMR0: FLUSH (Bit 10) */ 11304 #define VADC_G_QMR0_FLUSH_Msk (0x400UL) /*!< VADC_G QMR0: FLUSH (Bitfield-Mask: 0x01) */ 11305 #define VADC_G_QMR0_CEV_Pos (11UL) /*!< VADC_G QMR0: CEV (Bit 11) */ 11306 #define VADC_G_QMR0_CEV_Msk (0x800UL) /*!< VADC_G QMR0: CEV (Bitfield-Mask: 0x01) */ 11307 #define VADC_G_QMR0_RPTDIS_Pos (16UL) /*!< VADC_G QMR0: RPTDIS (Bit 16) */ 11308 #define VADC_G_QMR0_RPTDIS_Msk (0x10000UL) /*!< VADC_G QMR0: RPTDIS (Bitfield-Mask: 0x01) */ 11309 11310 /* --------------------------------- VADC_G_QSR0 -------------------------------- */ 11311 #define VADC_G_QSR0_FILL_Pos (0UL) /*!< VADC_G QSR0: FILL (Bit 0) */ 11312 #define VADC_G_QSR0_FILL_Msk (0xfUL) /*!< VADC_G QSR0: FILL (Bitfield-Mask: 0x0f) */ 11313 #define VADC_G_QSR0_EMPTY_Pos (5UL) /*!< VADC_G QSR0: EMPTY (Bit 5) */ 11314 #define VADC_G_QSR0_EMPTY_Msk (0x20UL) /*!< VADC_G QSR0: EMPTY (Bitfield-Mask: 0x01) */ 11315 #define VADC_G_QSR0_REQGT_Pos (7UL) /*!< VADC_G QSR0: REQGT (Bit 7) */ 11316 #define VADC_G_QSR0_REQGT_Msk (0x80UL) /*!< VADC_G QSR0: REQGT (Bitfield-Mask: 0x01) */ 11317 #define VADC_G_QSR0_EV_Pos (8UL) /*!< VADC_G QSR0: EV (Bit 8) */ 11318 #define VADC_G_QSR0_EV_Msk (0x100UL) /*!< VADC_G QSR0: EV (Bitfield-Mask: 0x01) */ 11319 11320 /* --------------------------------- VADC_G_Q0R0 -------------------------------- */ 11321 #define VADC_G_Q0R0_REQCHNR_Pos (0UL) /*!< VADC_G Q0R0: REQCHNR (Bit 0) */ 11322 #define VADC_G_Q0R0_REQCHNR_Msk (0x1fUL) /*!< VADC_G Q0R0: REQCHNR (Bitfield-Mask: 0x1f) */ 11323 #define VADC_G_Q0R0_RF_Pos (5UL) /*!< VADC_G Q0R0: RF (Bit 5) */ 11324 #define VADC_G_Q0R0_RF_Msk (0x20UL) /*!< VADC_G Q0R0: RF (Bitfield-Mask: 0x01) */ 11325 #define VADC_G_Q0R0_ENSI_Pos (6UL) /*!< VADC_G Q0R0: ENSI (Bit 6) */ 11326 #define VADC_G_Q0R0_ENSI_Msk (0x40UL) /*!< VADC_G Q0R0: ENSI (Bitfield-Mask: 0x01) */ 11327 #define VADC_G_Q0R0_EXTR_Pos (7UL) /*!< VADC_G Q0R0: EXTR (Bit 7) */ 11328 #define VADC_G_Q0R0_EXTR_Msk (0x80UL) /*!< VADC_G Q0R0: EXTR (Bitfield-Mask: 0x01) */ 11329 #define VADC_G_Q0R0_V_Pos (8UL) /*!< VADC_G Q0R0: V (Bit 8) */ 11330 #define VADC_G_Q0R0_V_Msk (0x100UL) /*!< VADC_G Q0R0: V (Bitfield-Mask: 0x01) */ 11331 11332 /* -------------------------------- VADC_G_QINR0 -------------------------------- */ 11333 #define VADC_G_QINR0_REQCHNR_Pos (0UL) /*!< VADC_G QINR0: REQCHNR (Bit 0) */ 11334 #define VADC_G_QINR0_REQCHNR_Msk (0x1fUL) /*!< VADC_G QINR0: REQCHNR (Bitfield-Mask: 0x1f) */ 11335 #define VADC_G_QINR0_RF_Pos (5UL) /*!< VADC_G QINR0: RF (Bit 5) */ 11336 #define VADC_G_QINR0_RF_Msk (0x20UL) /*!< VADC_G QINR0: RF (Bitfield-Mask: 0x01) */ 11337 #define VADC_G_QINR0_ENSI_Pos (6UL) /*!< VADC_G QINR0: ENSI (Bit 6) */ 11338 #define VADC_G_QINR0_ENSI_Msk (0x40UL) /*!< VADC_G QINR0: ENSI (Bitfield-Mask: 0x01) */ 11339 #define VADC_G_QINR0_EXTR_Pos (7UL) /*!< VADC_G QINR0: EXTR (Bit 7) */ 11340 #define VADC_G_QINR0_EXTR_Msk (0x80UL) /*!< VADC_G QINR0: EXTR (Bitfield-Mask: 0x01) */ 11341 11342 /* -------------------------------- VADC_G_QBUR0 -------------------------------- */ 11343 #define VADC_G_QBUR0_REQCHNR_Pos (0UL) /*!< VADC_G QBUR0: REQCHNR (Bit 0) */ 11344 #define VADC_G_QBUR0_REQCHNR_Msk (0x1fUL) /*!< VADC_G QBUR0: REQCHNR (Bitfield-Mask: 0x1f) */ 11345 #define VADC_G_QBUR0_RF_Pos (5UL) /*!< VADC_G QBUR0: RF (Bit 5) */ 11346 #define VADC_G_QBUR0_RF_Msk (0x20UL) /*!< VADC_G QBUR0: RF (Bitfield-Mask: 0x01) */ 11347 #define VADC_G_QBUR0_ENSI_Pos (6UL) /*!< VADC_G QBUR0: ENSI (Bit 6) */ 11348 #define VADC_G_QBUR0_ENSI_Msk (0x40UL) /*!< VADC_G QBUR0: ENSI (Bitfield-Mask: 0x01) */ 11349 #define VADC_G_QBUR0_EXTR_Pos (7UL) /*!< VADC_G QBUR0: EXTR (Bit 7) */ 11350 #define VADC_G_QBUR0_EXTR_Msk (0x80UL) /*!< VADC_G QBUR0: EXTR (Bitfield-Mask: 0x01) */ 11351 #define VADC_G_QBUR0_V_Pos (8UL) /*!< VADC_G QBUR0: V (Bit 8) */ 11352 #define VADC_G_QBUR0_V_Msk (0x100UL) /*!< VADC_G QBUR0: V (Bitfield-Mask: 0x01) */ 11353 11354 /* -------------------------------- VADC_G_ASCTRL ------------------------------- */ 11355 #define VADC_G_ASCTRL_XTSEL_Pos (8UL) /*!< VADC_G ASCTRL: XTSEL (Bit 8) */ 11356 #define VADC_G_ASCTRL_XTSEL_Msk (0xf00UL) /*!< VADC_G ASCTRL: XTSEL (Bitfield-Mask: 0x0f) */ 11357 #define VADC_G_ASCTRL_XTLVL_Pos (12UL) /*!< VADC_G ASCTRL: XTLVL (Bit 12) */ 11358 #define VADC_G_ASCTRL_XTLVL_Msk (0x1000UL) /*!< VADC_G ASCTRL: XTLVL (Bitfield-Mask: 0x01) */ 11359 #define VADC_G_ASCTRL_XTMODE_Pos (13UL) /*!< VADC_G ASCTRL: XTMODE (Bit 13) */ 11360 #define VADC_G_ASCTRL_XTMODE_Msk (0x6000UL) /*!< VADC_G ASCTRL: XTMODE (Bitfield-Mask: 0x03) */ 11361 #define VADC_G_ASCTRL_XTWC_Pos (15UL) /*!< VADC_G ASCTRL: XTWC (Bit 15) */ 11362 #define VADC_G_ASCTRL_XTWC_Msk (0x8000UL) /*!< VADC_G ASCTRL: XTWC (Bitfield-Mask: 0x01) */ 11363 #define VADC_G_ASCTRL_GTSEL_Pos (16UL) /*!< VADC_G ASCTRL: GTSEL (Bit 16) */ 11364 #define VADC_G_ASCTRL_GTSEL_Msk (0xf0000UL) /*!< VADC_G ASCTRL: GTSEL (Bitfield-Mask: 0x0f) */ 11365 #define VADC_G_ASCTRL_GTLVL_Pos (20UL) /*!< VADC_G ASCTRL: GTLVL (Bit 20) */ 11366 #define VADC_G_ASCTRL_GTLVL_Msk (0x100000UL) /*!< VADC_G ASCTRL: GTLVL (Bitfield-Mask: 0x01) */ 11367 #define VADC_G_ASCTRL_GTWC_Pos (23UL) /*!< VADC_G ASCTRL: GTWC (Bit 23) */ 11368 #define VADC_G_ASCTRL_GTWC_Msk (0x800000UL) /*!< VADC_G ASCTRL: GTWC (Bitfield-Mask: 0x01) */ 11369 #define VADC_G_ASCTRL_TMEN_Pos (28UL) /*!< VADC_G ASCTRL: TMEN (Bit 28) */ 11370 #define VADC_G_ASCTRL_TMEN_Msk (0x10000000UL) /*!< VADC_G ASCTRL: TMEN (Bitfield-Mask: 0x01) */ 11371 #define VADC_G_ASCTRL_TMWC_Pos (31UL) /*!< VADC_G ASCTRL: TMWC (Bit 31) */ 11372 #define VADC_G_ASCTRL_TMWC_Msk (0x80000000UL) /*!< VADC_G ASCTRL: TMWC (Bitfield-Mask: 0x01) */ 11373 11374 /* --------------------------------- VADC_G_ASMR -------------------------------- */ 11375 #define VADC_G_ASMR_ENGT_Pos (0UL) /*!< VADC_G ASMR: ENGT (Bit 0) */ 11376 #define VADC_G_ASMR_ENGT_Msk (0x3UL) /*!< VADC_G ASMR: ENGT (Bitfield-Mask: 0x03) */ 11377 #define VADC_G_ASMR_ENTR_Pos (2UL) /*!< VADC_G ASMR: ENTR (Bit 2) */ 11378 #define VADC_G_ASMR_ENTR_Msk (0x4UL) /*!< VADC_G ASMR: ENTR (Bitfield-Mask: 0x01) */ 11379 #define VADC_G_ASMR_ENSI_Pos (3UL) /*!< VADC_G ASMR: ENSI (Bit 3) */ 11380 #define VADC_G_ASMR_ENSI_Msk (0x8UL) /*!< VADC_G ASMR: ENSI (Bitfield-Mask: 0x01) */ 11381 #define VADC_G_ASMR_SCAN_Pos (4UL) /*!< VADC_G ASMR: SCAN (Bit 4) */ 11382 #define VADC_G_ASMR_SCAN_Msk (0x10UL) /*!< VADC_G ASMR: SCAN (Bitfield-Mask: 0x01) */ 11383 #define VADC_G_ASMR_LDM_Pos (5UL) /*!< VADC_G ASMR: LDM (Bit 5) */ 11384 #define VADC_G_ASMR_LDM_Msk (0x20UL) /*!< VADC_G ASMR: LDM (Bitfield-Mask: 0x01) */ 11385 #define VADC_G_ASMR_REQGT_Pos (7UL) /*!< VADC_G ASMR: REQGT (Bit 7) */ 11386 #define VADC_G_ASMR_REQGT_Msk (0x80UL) /*!< VADC_G ASMR: REQGT (Bitfield-Mask: 0x01) */ 11387 #define VADC_G_ASMR_CLRPND_Pos (8UL) /*!< VADC_G ASMR: CLRPND (Bit 8) */ 11388 #define VADC_G_ASMR_CLRPND_Msk (0x100UL) /*!< VADC_G ASMR: CLRPND (Bitfield-Mask: 0x01) */ 11389 #define VADC_G_ASMR_LDEV_Pos (9UL) /*!< VADC_G ASMR: LDEV (Bit 9) */ 11390 #define VADC_G_ASMR_LDEV_Msk (0x200UL) /*!< VADC_G ASMR: LDEV (Bitfield-Mask: 0x01) */ 11391 #define VADC_G_ASMR_RPTDIS_Pos (16UL) /*!< VADC_G ASMR: RPTDIS (Bit 16) */ 11392 #define VADC_G_ASMR_RPTDIS_Msk (0x10000UL) /*!< VADC_G ASMR: RPTDIS (Bitfield-Mask: 0x01) */ 11393 11394 /* -------------------------------- VADC_G_ASSEL -------------------------------- */ 11395 #define VADC_G_ASSEL_CHSEL0_Pos (0UL) /*!< VADC_G ASSEL: CHSEL0 (Bit 0) */ 11396 #define VADC_G_ASSEL_CHSEL0_Msk (0x1UL) /*!< VADC_G ASSEL: CHSEL0 (Bitfield-Mask: 0x01) */ 11397 #define VADC_G_ASSEL_CHSEL1_Pos (1UL) /*!< VADC_G ASSEL: CHSEL1 (Bit 1) */ 11398 #define VADC_G_ASSEL_CHSEL1_Msk (0x2UL) /*!< VADC_G ASSEL: CHSEL1 (Bitfield-Mask: 0x01) */ 11399 #define VADC_G_ASSEL_CHSEL2_Pos (2UL) /*!< VADC_G ASSEL: CHSEL2 (Bit 2) */ 11400 #define VADC_G_ASSEL_CHSEL2_Msk (0x4UL) /*!< VADC_G ASSEL: CHSEL2 (Bitfield-Mask: 0x01) */ 11401 #define VADC_G_ASSEL_CHSEL3_Pos (3UL) /*!< VADC_G ASSEL: CHSEL3 (Bit 3) */ 11402 #define VADC_G_ASSEL_CHSEL3_Msk (0x8UL) /*!< VADC_G ASSEL: CHSEL3 (Bitfield-Mask: 0x01) */ 11403 #define VADC_G_ASSEL_CHSEL4_Pos (4UL) /*!< VADC_G ASSEL: CHSEL4 (Bit 4) */ 11404 #define VADC_G_ASSEL_CHSEL4_Msk (0x10UL) /*!< VADC_G ASSEL: CHSEL4 (Bitfield-Mask: 0x01) */ 11405 #define VADC_G_ASSEL_CHSEL5_Pos (5UL) /*!< VADC_G ASSEL: CHSEL5 (Bit 5) */ 11406 #define VADC_G_ASSEL_CHSEL5_Msk (0x20UL) /*!< VADC_G ASSEL: CHSEL5 (Bitfield-Mask: 0x01) */ 11407 #define VADC_G_ASSEL_CHSEL6_Pos (6UL) /*!< VADC_G ASSEL: CHSEL6 (Bit 6) */ 11408 #define VADC_G_ASSEL_CHSEL6_Msk (0x40UL) /*!< VADC_G ASSEL: CHSEL6 (Bitfield-Mask: 0x01) */ 11409 #define VADC_G_ASSEL_CHSEL7_Pos (7UL) /*!< VADC_G ASSEL: CHSEL7 (Bit 7) */ 11410 #define VADC_G_ASSEL_CHSEL7_Msk (0x80UL) /*!< VADC_G ASSEL: CHSEL7 (Bitfield-Mask: 0x01) */ 11411 11412 /* -------------------------------- VADC_G_ASPND -------------------------------- */ 11413 #define VADC_G_ASPND_CHPND0_Pos (0UL) /*!< VADC_G ASPND: CHPND0 (Bit 0) */ 11414 #define VADC_G_ASPND_CHPND0_Msk (0x1UL) /*!< VADC_G ASPND: CHPND0 (Bitfield-Mask: 0x01) */ 11415 #define VADC_G_ASPND_CHPND1_Pos (1UL) /*!< VADC_G ASPND: CHPND1 (Bit 1) */ 11416 #define VADC_G_ASPND_CHPND1_Msk (0x2UL) /*!< VADC_G ASPND: CHPND1 (Bitfield-Mask: 0x01) */ 11417 #define VADC_G_ASPND_CHPND2_Pos (2UL) /*!< VADC_G ASPND: CHPND2 (Bit 2) */ 11418 #define VADC_G_ASPND_CHPND2_Msk (0x4UL) /*!< VADC_G ASPND: CHPND2 (Bitfield-Mask: 0x01) */ 11419 #define VADC_G_ASPND_CHPND3_Pos (3UL) /*!< VADC_G ASPND: CHPND3 (Bit 3) */ 11420 #define VADC_G_ASPND_CHPND3_Msk (0x8UL) /*!< VADC_G ASPND: CHPND3 (Bitfield-Mask: 0x01) */ 11421 #define VADC_G_ASPND_CHPND4_Pos (4UL) /*!< VADC_G ASPND: CHPND4 (Bit 4) */ 11422 #define VADC_G_ASPND_CHPND4_Msk (0x10UL) /*!< VADC_G ASPND: CHPND4 (Bitfield-Mask: 0x01) */ 11423 #define VADC_G_ASPND_CHPND5_Pos (5UL) /*!< VADC_G ASPND: CHPND5 (Bit 5) */ 11424 #define VADC_G_ASPND_CHPND5_Msk (0x20UL) /*!< VADC_G ASPND: CHPND5 (Bitfield-Mask: 0x01) */ 11425 #define VADC_G_ASPND_CHPND6_Pos (6UL) /*!< VADC_G ASPND: CHPND6 (Bit 6) */ 11426 #define VADC_G_ASPND_CHPND6_Msk (0x40UL) /*!< VADC_G ASPND: CHPND6 (Bitfield-Mask: 0x01) */ 11427 #define VADC_G_ASPND_CHPND7_Pos (7UL) /*!< VADC_G ASPND: CHPND7 (Bit 7) */ 11428 #define VADC_G_ASPND_CHPND7_Msk (0x80UL) /*!< VADC_G ASPND: CHPND7 (Bitfield-Mask: 0x01) */ 11429 11430 /* -------------------------------- VADC_G_CEFLAG ------------------------------- */ 11431 #define VADC_G_CEFLAG_CEV0_Pos (0UL) /*!< VADC_G CEFLAG: CEV0 (Bit 0) */ 11432 #define VADC_G_CEFLAG_CEV0_Msk (0x1UL) /*!< VADC_G CEFLAG: CEV0 (Bitfield-Mask: 0x01) */ 11433 #define VADC_G_CEFLAG_CEV1_Pos (1UL) /*!< VADC_G CEFLAG: CEV1 (Bit 1) */ 11434 #define VADC_G_CEFLAG_CEV1_Msk (0x2UL) /*!< VADC_G CEFLAG: CEV1 (Bitfield-Mask: 0x01) */ 11435 #define VADC_G_CEFLAG_CEV2_Pos (2UL) /*!< VADC_G CEFLAG: CEV2 (Bit 2) */ 11436 #define VADC_G_CEFLAG_CEV2_Msk (0x4UL) /*!< VADC_G CEFLAG: CEV2 (Bitfield-Mask: 0x01) */ 11437 #define VADC_G_CEFLAG_CEV3_Pos (3UL) /*!< VADC_G CEFLAG: CEV3 (Bit 3) */ 11438 #define VADC_G_CEFLAG_CEV3_Msk (0x8UL) /*!< VADC_G CEFLAG: CEV3 (Bitfield-Mask: 0x01) */ 11439 #define VADC_G_CEFLAG_CEV4_Pos (4UL) /*!< VADC_G CEFLAG: CEV4 (Bit 4) */ 11440 #define VADC_G_CEFLAG_CEV4_Msk (0x10UL) /*!< VADC_G CEFLAG: CEV4 (Bitfield-Mask: 0x01) */ 11441 #define VADC_G_CEFLAG_CEV5_Pos (5UL) /*!< VADC_G CEFLAG: CEV5 (Bit 5) */ 11442 #define VADC_G_CEFLAG_CEV5_Msk (0x20UL) /*!< VADC_G CEFLAG: CEV5 (Bitfield-Mask: 0x01) */ 11443 #define VADC_G_CEFLAG_CEV6_Pos (6UL) /*!< VADC_G CEFLAG: CEV6 (Bit 6) */ 11444 #define VADC_G_CEFLAG_CEV6_Msk (0x40UL) /*!< VADC_G CEFLAG: CEV6 (Bitfield-Mask: 0x01) */ 11445 #define VADC_G_CEFLAG_CEV7_Pos (7UL) /*!< VADC_G CEFLAG: CEV7 (Bit 7) */ 11446 #define VADC_G_CEFLAG_CEV7_Msk (0x80UL) /*!< VADC_G CEFLAG: CEV7 (Bitfield-Mask: 0x01) */ 11447 11448 /* -------------------------------- VADC_G_REFLAG ------------------------------- */ 11449 #define VADC_G_REFLAG_REV0_Pos (0UL) /*!< VADC_G REFLAG: REV0 (Bit 0) */ 11450 #define VADC_G_REFLAG_REV0_Msk (0x1UL) /*!< VADC_G REFLAG: REV0 (Bitfield-Mask: 0x01) */ 11451 #define VADC_G_REFLAG_REV1_Pos (1UL) /*!< VADC_G REFLAG: REV1 (Bit 1) */ 11452 #define VADC_G_REFLAG_REV1_Msk (0x2UL) /*!< VADC_G REFLAG: REV1 (Bitfield-Mask: 0x01) */ 11453 #define VADC_G_REFLAG_REV2_Pos (2UL) /*!< VADC_G REFLAG: REV2 (Bit 2) */ 11454 #define VADC_G_REFLAG_REV2_Msk (0x4UL) /*!< VADC_G REFLAG: REV2 (Bitfield-Mask: 0x01) */ 11455 #define VADC_G_REFLAG_REV3_Pos (3UL) /*!< VADC_G REFLAG: REV3 (Bit 3) */ 11456 #define VADC_G_REFLAG_REV3_Msk (0x8UL) /*!< VADC_G REFLAG: REV3 (Bitfield-Mask: 0x01) */ 11457 #define VADC_G_REFLAG_REV4_Pos (4UL) /*!< VADC_G REFLAG: REV4 (Bit 4) */ 11458 #define VADC_G_REFLAG_REV4_Msk (0x10UL) /*!< VADC_G REFLAG: REV4 (Bitfield-Mask: 0x01) */ 11459 #define VADC_G_REFLAG_REV5_Pos (5UL) /*!< VADC_G REFLAG: REV5 (Bit 5) */ 11460 #define VADC_G_REFLAG_REV5_Msk (0x20UL) /*!< VADC_G REFLAG: REV5 (Bitfield-Mask: 0x01) */ 11461 #define VADC_G_REFLAG_REV6_Pos (6UL) /*!< VADC_G REFLAG: REV6 (Bit 6) */ 11462 #define VADC_G_REFLAG_REV6_Msk (0x40UL) /*!< VADC_G REFLAG: REV6 (Bitfield-Mask: 0x01) */ 11463 #define VADC_G_REFLAG_REV7_Pos (7UL) /*!< VADC_G REFLAG: REV7 (Bit 7) */ 11464 #define VADC_G_REFLAG_REV7_Msk (0x80UL) /*!< VADC_G REFLAG: REV7 (Bitfield-Mask: 0x01) */ 11465 #define VADC_G_REFLAG_REV8_Pos (8UL) /*!< VADC_G REFLAG: REV8 (Bit 8) */ 11466 #define VADC_G_REFLAG_REV8_Msk (0x100UL) /*!< VADC_G REFLAG: REV8 (Bitfield-Mask: 0x01) */ 11467 #define VADC_G_REFLAG_REV9_Pos (9UL) /*!< VADC_G REFLAG: REV9 (Bit 9) */ 11468 #define VADC_G_REFLAG_REV9_Msk (0x200UL) /*!< VADC_G REFLAG: REV9 (Bitfield-Mask: 0x01) */ 11469 #define VADC_G_REFLAG_REV10_Pos (10UL) /*!< VADC_G REFLAG: REV10 (Bit 10) */ 11470 #define VADC_G_REFLAG_REV10_Msk (0x400UL) /*!< VADC_G REFLAG: REV10 (Bitfield-Mask: 0x01) */ 11471 #define VADC_G_REFLAG_REV11_Pos (11UL) /*!< VADC_G REFLAG: REV11 (Bit 11) */ 11472 #define VADC_G_REFLAG_REV11_Msk (0x800UL) /*!< VADC_G REFLAG: REV11 (Bitfield-Mask: 0x01) */ 11473 #define VADC_G_REFLAG_REV12_Pos (12UL) /*!< VADC_G REFLAG: REV12 (Bit 12) */ 11474 #define VADC_G_REFLAG_REV12_Msk (0x1000UL) /*!< VADC_G REFLAG: REV12 (Bitfield-Mask: 0x01) */ 11475 #define VADC_G_REFLAG_REV13_Pos (13UL) /*!< VADC_G REFLAG: REV13 (Bit 13) */ 11476 #define VADC_G_REFLAG_REV13_Msk (0x2000UL) /*!< VADC_G REFLAG: REV13 (Bitfield-Mask: 0x01) */ 11477 #define VADC_G_REFLAG_REV14_Pos (14UL) /*!< VADC_G REFLAG: REV14 (Bit 14) */ 11478 #define VADC_G_REFLAG_REV14_Msk (0x4000UL) /*!< VADC_G REFLAG: REV14 (Bitfield-Mask: 0x01) */ 11479 #define VADC_G_REFLAG_REV15_Pos (15UL) /*!< VADC_G REFLAG: REV15 (Bit 15) */ 11480 #define VADC_G_REFLAG_REV15_Msk (0x8000UL) /*!< VADC_G REFLAG: REV15 (Bitfield-Mask: 0x01) */ 11481 11482 /* -------------------------------- VADC_G_SEFLAG ------------------------------- */ 11483 #define VADC_G_SEFLAG_SEV0_Pos (0UL) /*!< VADC_G SEFLAG: SEV0 (Bit 0) */ 11484 #define VADC_G_SEFLAG_SEV0_Msk (0x1UL) /*!< VADC_G SEFLAG: SEV0 (Bitfield-Mask: 0x01) */ 11485 #define VADC_G_SEFLAG_SEV1_Pos (1UL) /*!< VADC_G SEFLAG: SEV1 (Bit 1) */ 11486 #define VADC_G_SEFLAG_SEV1_Msk (0x2UL) /*!< VADC_G SEFLAG: SEV1 (Bitfield-Mask: 0x01) */ 11487 11488 /* -------------------------------- VADC_G_CEFCLR ------------------------------- */ 11489 #define VADC_G_CEFCLR_CEV0_Pos (0UL) /*!< VADC_G CEFCLR: CEV0 (Bit 0) */ 11490 #define VADC_G_CEFCLR_CEV0_Msk (0x1UL) /*!< VADC_G CEFCLR: CEV0 (Bitfield-Mask: 0x01) */ 11491 #define VADC_G_CEFCLR_CEV1_Pos (1UL) /*!< VADC_G CEFCLR: CEV1 (Bit 1) */ 11492 #define VADC_G_CEFCLR_CEV1_Msk (0x2UL) /*!< VADC_G CEFCLR: CEV1 (Bitfield-Mask: 0x01) */ 11493 #define VADC_G_CEFCLR_CEV2_Pos (2UL) /*!< VADC_G CEFCLR: CEV2 (Bit 2) */ 11494 #define VADC_G_CEFCLR_CEV2_Msk (0x4UL) /*!< VADC_G CEFCLR: CEV2 (Bitfield-Mask: 0x01) */ 11495 #define VADC_G_CEFCLR_CEV3_Pos (3UL) /*!< VADC_G CEFCLR: CEV3 (Bit 3) */ 11496 #define VADC_G_CEFCLR_CEV3_Msk (0x8UL) /*!< VADC_G CEFCLR: CEV3 (Bitfield-Mask: 0x01) */ 11497 #define VADC_G_CEFCLR_CEV4_Pos (4UL) /*!< VADC_G CEFCLR: CEV4 (Bit 4) */ 11498 #define VADC_G_CEFCLR_CEV4_Msk (0x10UL) /*!< VADC_G CEFCLR: CEV4 (Bitfield-Mask: 0x01) */ 11499 #define VADC_G_CEFCLR_CEV5_Pos (5UL) /*!< VADC_G CEFCLR: CEV5 (Bit 5) */ 11500 #define VADC_G_CEFCLR_CEV5_Msk (0x20UL) /*!< VADC_G CEFCLR: CEV5 (Bitfield-Mask: 0x01) */ 11501 #define VADC_G_CEFCLR_CEV6_Pos (6UL) /*!< VADC_G CEFCLR: CEV6 (Bit 6) */ 11502 #define VADC_G_CEFCLR_CEV6_Msk (0x40UL) /*!< VADC_G CEFCLR: CEV6 (Bitfield-Mask: 0x01) */ 11503 #define VADC_G_CEFCLR_CEV7_Pos (7UL) /*!< VADC_G CEFCLR: CEV7 (Bit 7) */ 11504 #define VADC_G_CEFCLR_CEV7_Msk (0x80UL) /*!< VADC_G CEFCLR: CEV7 (Bitfield-Mask: 0x01) */ 11505 11506 /* -------------------------------- VADC_G_REFCLR ------------------------------- */ 11507 #define VADC_G_REFCLR_REV0_Pos (0UL) /*!< VADC_G REFCLR: REV0 (Bit 0) */ 11508 #define VADC_G_REFCLR_REV0_Msk (0x1UL) /*!< VADC_G REFCLR: REV0 (Bitfield-Mask: 0x01) */ 11509 #define VADC_G_REFCLR_REV1_Pos (1UL) /*!< VADC_G REFCLR: REV1 (Bit 1) */ 11510 #define VADC_G_REFCLR_REV1_Msk (0x2UL) /*!< VADC_G REFCLR: REV1 (Bitfield-Mask: 0x01) */ 11511 #define VADC_G_REFCLR_REV2_Pos (2UL) /*!< VADC_G REFCLR: REV2 (Bit 2) */ 11512 #define VADC_G_REFCLR_REV2_Msk (0x4UL) /*!< VADC_G REFCLR: REV2 (Bitfield-Mask: 0x01) */ 11513 #define VADC_G_REFCLR_REV3_Pos (3UL) /*!< VADC_G REFCLR: REV3 (Bit 3) */ 11514 #define VADC_G_REFCLR_REV3_Msk (0x8UL) /*!< VADC_G REFCLR: REV3 (Bitfield-Mask: 0x01) */ 11515 #define VADC_G_REFCLR_REV4_Pos (4UL) /*!< VADC_G REFCLR: REV4 (Bit 4) */ 11516 #define VADC_G_REFCLR_REV4_Msk (0x10UL) /*!< VADC_G REFCLR: REV4 (Bitfield-Mask: 0x01) */ 11517 #define VADC_G_REFCLR_REV5_Pos (5UL) /*!< VADC_G REFCLR: REV5 (Bit 5) */ 11518 #define VADC_G_REFCLR_REV5_Msk (0x20UL) /*!< VADC_G REFCLR: REV5 (Bitfield-Mask: 0x01) */ 11519 #define VADC_G_REFCLR_REV6_Pos (6UL) /*!< VADC_G REFCLR: REV6 (Bit 6) */ 11520 #define VADC_G_REFCLR_REV6_Msk (0x40UL) /*!< VADC_G REFCLR: REV6 (Bitfield-Mask: 0x01) */ 11521 #define VADC_G_REFCLR_REV7_Pos (7UL) /*!< VADC_G REFCLR: REV7 (Bit 7) */ 11522 #define VADC_G_REFCLR_REV7_Msk (0x80UL) /*!< VADC_G REFCLR: REV7 (Bitfield-Mask: 0x01) */ 11523 #define VADC_G_REFCLR_REV8_Pos (8UL) /*!< VADC_G REFCLR: REV8 (Bit 8) */ 11524 #define VADC_G_REFCLR_REV8_Msk (0x100UL) /*!< VADC_G REFCLR: REV8 (Bitfield-Mask: 0x01) */ 11525 #define VADC_G_REFCLR_REV9_Pos (9UL) /*!< VADC_G REFCLR: REV9 (Bit 9) */ 11526 #define VADC_G_REFCLR_REV9_Msk (0x200UL) /*!< VADC_G REFCLR: REV9 (Bitfield-Mask: 0x01) */ 11527 #define VADC_G_REFCLR_REV10_Pos (10UL) /*!< VADC_G REFCLR: REV10 (Bit 10) */ 11528 #define VADC_G_REFCLR_REV10_Msk (0x400UL) /*!< VADC_G REFCLR: REV10 (Bitfield-Mask: 0x01) */ 11529 #define VADC_G_REFCLR_REV11_Pos (11UL) /*!< VADC_G REFCLR: REV11 (Bit 11) */ 11530 #define VADC_G_REFCLR_REV11_Msk (0x800UL) /*!< VADC_G REFCLR: REV11 (Bitfield-Mask: 0x01) */ 11531 #define VADC_G_REFCLR_REV12_Pos (12UL) /*!< VADC_G REFCLR: REV12 (Bit 12) */ 11532 #define VADC_G_REFCLR_REV12_Msk (0x1000UL) /*!< VADC_G REFCLR: REV12 (Bitfield-Mask: 0x01) */ 11533 #define VADC_G_REFCLR_REV13_Pos (13UL) /*!< VADC_G REFCLR: REV13 (Bit 13) */ 11534 #define VADC_G_REFCLR_REV13_Msk (0x2000UL) /*!< VADC_G REFCLR: REV13 (Bitfield-Mask: 0x01) */ 11535 #define VADC_G_REFCLR_REV14_Pos (14UL) /*!< VADC_G REFCLR: REV14 (Bit 14) */ 11536 #define VADC_G_REFCLR_REV14_Msk (0x4000UL) /*!< VADC_G REFCLR: REV14 (Bitfield-Mask: 0x01) */ 11537 #define VADC_G_REFCLR_REV15_Pos (15UL) /*!< VADC_G REFCLR: REV15 (Bit 15) */ 11538 #define VADC_G_REFCLR_REV15_Msk (0x8000UL) /*!< VADC_G REFCLR: REV15 (Bitfield-Mask: 0x01) */ 11539 11540 /* -------------------------------- VADC_G_SEFCLR ------------------------------- */ 11541 #define VADC_G_SEFCLR_SEV0_Pos (0UL) /*!< VADC_G SEFCLR: SEV0 (Bit 0) */ 11542 #define VADC_G_SEFCLR_SEV0_Msk (0x1UL) /*!< VADC_G SEFCLR: SEV0 (Bitfield-Mask: 0x01) */ 11543 #define VADC_G_SEFCLR_SEV1_Pos (1UL) /*!< VADC_G SEFCLR: SEV1 (Bit 1) */ 11544 #define VADC_G_SEFCLR_SEV1_Msk (0x2UL) /*!< VADC_G SEFCLR: SEV1 (Bitfield-Mask: 0x01) */ 11545 11546 /* -------------------------------- VADC_G_CEVNP0 ------------------------------- */ 11547 #define VADC_G_CEVNP0_CEV0NP_Pos (0UL) /*!< VADC_G CEVNP0: CEV0NP (Bit 0) */ 11548 #define VADC_G_CEVNP0_CEV0NP_Msk (0xfUL) /*!< VADC_G CEVNP0: CEV0NP (Bitfield-Mask: 0x0f) */ 11549 #define VADC_G_CEVNP0_CEV1NP_Pos (4UL) /*!< VADC_G CEVNP0: CEV1NP (Bit 4) */ 11550 #define VADC_G_CEVNP0_CEV1NP_Msk (0xf0UL) /*!< VADC_G CEVNP0: CEV1NP (Bitfield-Mask: 0x0f) */ 11551 #define VADC_G_CEVNP0_CEV2NP_Pos (8UL) /*!< VADC_G CEVNP0: CEV2NP (Bit 8) */ 11552 #define VADC_G_CEVNP0_CEV2NP_Msk (0xf00UL) /*!< VADC_G CEVNP0: CEV2NP (Bitfield-Mask: 0x0f) */ 11553 #define VADC_G_CEVNP0_CEV3NP_Pos (12UL) /*!< VADC_G CEVNP0: CEV3NP (Bit 12) */ 11554 #define VADC_G_CEVNP0_CEV3NP_Msk (0xf000UL) /*!< VADC_G CEVNP0: CEV3NP (Bitfield-Mask: 0x0f) */ 11555 #define VADC_G_CEVNP0_CEV4NP_Pos (16UL) /*!< VADC_G CEVNP0: CEV4NP (Bit 16) */ 11556 #define VADC_G_CEVNP0_CEV4NP_Msk (0xf0000UL) /*!< VADC_G CEVNP0: CEV4NP (Bitfield-Mask: 0x0f) */ 11557 #define VADC_G_CEVNP0_CEV5NP_Pos (20UL) /*!< VADC_G CEVNP0: CEV5NP (Bit 20) */ 11558 #define VADC_G_CEVNP0_CEV5NP_Msk (0xf00000UL) /*!< VADC_G CEVNP0: CEV5NP (Bitfield-Mask: 0x0f) */ 11559 #define VADC_G_CEVNP0_CEV6NP_Pos (24UL) /*!< VADC_G CEVNP0: CEV6NP (Bit 24) */ 11560 #define VADC_G_CEVNP0_CEV6NP_Msk (0xf000000UL) /*!< VADC_G CEVNP0: CEV6NP (Bitfield-Mask: 0x0f) */ 11561 #define VADC_G_CEVNP0_CEV7NP_Pos (28UL) /*!< VADC_G CEVNP0: CEV7NP (Bit 28) */ 11562 #define VADC_G_CEVNP0_CEV7NP_Msk (0xf0000000UL) /*!< VADC_G CEVNP0: CEV7NP (Bitfield-Mask: 0x0f) */ 11563 11564 /* -------------------------------- VADC_G_REVNP0 ------------------------------- */ 11565 #define VADC_G_REVNP0_REV0NP_Pos (0UL) /*!< VADC_G REVNP0: REV0NP (Bit 0) */ 11566 #define VADC_G_REVNP0_REV0NP_Msk (0xfUL) /*!< VADC_G REVNP0: REV0NP (Bitfield-Mask: 0x0f) */ 11567 #define VADC_G_REVNP0_REV1NP_Pos (4UL) /*!< VADC_G REVNP0: REV1NP (Bit 4) */ 11568 #define VADC_G_REVNP0_REV1NP_Msk (0xf0UL) /*!< VADC_G REVNP0: REV1NP (Bitfield-Mask: 0x0f) */ 11569 #define VADC_G_REVNP0_REV2NP_Pos (8UL) /*!< VADC_G REVNP0: REV2NP (Bit 8) */ 11570 #define VADC_G_REVNP0_REV2NP_Msk (0xf00UL) /*!< VADC_G REVNP0: REV2NP (Bitfield-Mask: 0x0f) */ 11571 #define VADC_G_REVNP0_REV3NP_Pos (12UL) /*!< VADC_G REVNP0: REV3NP (Bit 12) */ 11572 #define VADC_G_REVNP0_REV3NP_Msk (0xf000UL) /*!< VADC_G REVNP0: REV3NP (Bitfield-Mask: 0x0f) */ 11573 #define VADC_G_REVNP0_REV4NP_Pos (16UL) /*!< VADC_G REVNP0: REV4NP (Bit 16) */ 11574 #define VADC_G_REVNP0_REV4NP_Msk (0xf0000UL) /*!< VADC_G REVNP0: REV4NP (Bitfield-Mask: 0x0f) */ 11575 #define VADC_G_REVNP0_REV5NP_Pos (20UL) /*!< VADC_G REVNP0: REV5NP (Bit 20) */ 11576 #define VADC_G_REVNP0_REV5NP_Msk (0xf00000UL) /*!< VADC_G REVNP0: REV5NP (Bitfield-Mask: 0x0f) */ 11577 #define VADC_G_REVNP0_REV6NP_Pos (24UL) /*!< VADC_G REVNP0: REV6NP (Bit 24) */ 11578 #define VADC_G_REVNP0_REV6NP_Msk (0xf000000UL) /*!< VADC_G REVNP0: REV6NP (Bitfield-Mask: 0x0f) */ 11579 #define VADC_G_REVNP0_REV7NP_Pos (28UL) /*!< VADC_G REVNP0: REV7NP (Bit 28) */ 11580 #define VADC_G_REVNP0_REV7NP_Msk (0xf0000000UL) /*!< VADC_G REVNP0: REV7NP (Bitfield-Mask: 0x0f) */ 11581 11582 /* -------------------------------- VADC_G_REVNP1 ------------------------------- */ 11583 #define VADC_G_REVNP1_REV8NP_Pos (0UL) /*!< VADC_G REVNP1: REV8NP (Bit 0) */ 11584 #define VADC_G_REVNP1_REV8NP_Msk (0xfUL) /*!< VADC_G REVNP1: REV8NP (Bitfield-Mask: 0x0f) */ 11585 #define VADC_G_REVNP1_REV9NP_Pos (4UL) /*!< VADC_G REVNP1: REV9NP (Bit 4) */ 11586 #define VADC_G_REVNP1_REV9NP_Msk (0xf0UL) /*!< VADC_G REVNP1: REV9NP (Bitfield-Mask: 0x0f) */ 11587 #define VADC_G_REVNP1_REV10NP_Pos (8UL) /*!< VADC_G REVNP1: REV10NP (Bit 8) */ 11588 #define VADC_G_REVNP1_REV10NP_Msk (0xf00UL) /*!< VADC_G REVNP1: REV10NP (Bitfield-Mask: 0x0f) */ 11589 #define VADC_G_REVNP1_REV11NP_Pos (12UL) /*!< VADC_G REVNP1: REV11NP (Bit 12) */ 11590 #define VADC_G_REVNP1_REV11NP_Msk (0xf000UL) /*!< VADC_G REVNP1: REV11NP (Bitfield-Mask: 0x0f) */ 11591 #define VADC_G_REVNP1_REV12NP_Pos (16UL) /*!< VADC_G REVNP1: REV12NP (Bit 16) */ 11592 #define VADC_G_REVNP1_REV12NP_Msk (0xf0000UL) /*!< VADC_G REVNP1: REV12NP (Bitfield-Mask: 0x0f) */ 11593 #define VADC_G_REVNP1_REV13NP_Pos (20UL) /*!< VADC_G REVNP1: REV13NP (Bit 20) */ 11594 #define VADC_G_REVNP1_REV13NP_Msk (0xf00000UL) /*!< VADC_G REVNP1: REV13NP (Bitfield-Mask: 0x0f) */ 11595 #define VADC_G_REVNP1_REV14NP_Pos (24UL) /*!< VADC_G REVNP1: REV14NP (Bit 24) */ 11596 #define VADC_G_REVNP1_REV14NP_Msk (0xf000000UL) /*!< VADC_G REVNP1: REV14NP (Bitfield-Mask: 0x0f) */ 11597 #define VADC_G_REVNP1_REV15NP_Pos (28UL) /*!< VADC_G REVNP1: REV15NP (Bit 28) */ 11598 #define VADC_G_REVNP1_REV15NP_Msk (0xf0000000UL) /*!< VADC_G REVNP1: REV15NP (Bitfield-Mask: 0x0f) */ 11599 11600 /* -------------------------------- VADC_G_SEVNP -------------------------------- */ 11601 #define VADC_G_SEVNP_SEV0NP_Pos (0UL) /*!< VADC_G SEVNP: SEV0NP (Bit 0) */ 11602 #define VADC_G_SEVNP_SEV0NP_Msk (0xfUL) /*!< VADC_G SEVNP: SEV0NP (Bitfield-Mask: 0x0f) */ 11603 #define VADC_G_SEVNP_SEV1NP_Pos (4UL) /*!< VADC_G SEVNP: SEV1NP (Bit 4) */ 11604 #define VADC_G_SEVNP_SEV1NP_Msk (0xf0UL) /*!< VADC_G SEVNP: SEV1NP (Bitfield-Mask: 0x0f) */ 11605 11606 /* -------------------------------- VADC_G_SRACT -------------------------------- */ 11607 #define VADC_G_SRACT_AGSR0_Pos (0UL) /*!< VADC_G SRACT: AGSR0 (Bit 0) */ 11608 #define VADC_G_SRACT_AGSR0_Msk (0x1UL) /*!< VADC_G SRACT: AGSR0 (Bitfield-Mask: 0x01) */ 11609 #define VADC_G_SRACT_AGSR1_Pos (1UL) /*!< VADC_G SRACT: AGSR1 (Bit 1) */ 11610 #define VADC_G_SRACT_AGSR1_Msk (0x2UL) /*!< VADC_G SRACT: AGSR1 (Bitfield-Mask: 0x01) */ 11611 #define VADC_G_SRACT_AGSR2_Pos (2UL) /*!< VADC_G SRACT: AGSR2 (Bit 2) */ 11612 #define VADC_G_SRACT_AGSR2_Msk (0x4UL) /*!< VADC_G SRACT: AGSR2 (Bitfield-Mask: 0x01) */ 11613 #define VADC_G_SRACT_AGSR3_Pos (3UL) /*!< VADC_G SRACT: AGSR3 (Bit 3) */ 11614 #define VADC_G_SRACT_AGSR3_Msk (0x8UL) /*!< VADC_G SRACT: AGSR3 (Bitfield-Mask: 0x01) */ 11615 #define VADC_G_SRACT_ASSR0_Pos (8UL) /*!< VADC_G SRACT: ASSR0 (Bit 8) */ 11616 #define VADC_G_SRACT_ASSR0_Msk (0x100UL) /*!< VADC_G SRACT: ASSR0 (Bitfield-Mask: 0x01) */ 11617 #define VADC_G_SRACT_ASSR1_Pos (9UL) /*!< VADC_G SRACT: ASSR1 (Bit 9) */ 11618 #define VADC_G_SRACT_ASSR1_Msk (0x200UL) /*!< VADC_G SRACT: ASSR1 (Bitfield-Mask: 0x01) */ 11619 #define VADC_G_SRACT_ASSR2_Pos (10UL) /*!< VADC_G SRACT: ASSR2 (Bit 10) */ 11620 #define VADC_G_SRACT_ASSR2_Msk (0x400UL) /*!< VADC_G SRACT: ASSR2 (Bitfield-Mask: 0x01) */ 11621 #define VADC_G_SRACT_ASSR3_Pos (11UL) /*!< VADC_G SRACT: ASSR3 (Bit 11) */ 11622 #define VADC_G_SRACT_ASSR3_Msk (0x800UL) /*!< VADC_G SRACT: ASSR3 (Bitfield-Mask: 0x01) */ 11623 11624 /* ------------------------------- VADC_G_EMUXCTR ------------------------------- */ 11625 #define VADC_G_EMUXCTR_EMUXSET_Pos (0UL) /*!< VADC_G EMUXCTR: EMUXSET (Bit 0) */ 11626 #define VADC_G_EMUXCTR_EMUXSET_Msk (0x7UL) /*!< VADC_G EMUXCTR: EMUXSET (Bitfield-Mask: 0x07) */ 11627 #define VADC_G_EMUXCTR_EMUXACT_Pos (8UL) /*!< VADC_G EMUXCTR: EMUXACT (Bit 8) */ 11628 #define VADC_G_EMUXCTR_EMUXACT_Msk (0x700UL) /*!< VADC_G EMUXCTR: EMUXACT (Bitfield-Mask: 0x07) */ 11629 #define VADC_G_EMUXCTR_EMUXCH_Pos (16UL) /*!< VADC_G EMUXCTR: EMUXCH (Bit 16) */ 11630 #define VADC_G_EMUXCTR_EMUXCH_Msk (0x1f0000UL) /*!< VADC_G EMUXCTR: EMUXCH (Bitfield-Mask: 0x1f) */ 11631 #define VADC_G_EMUXCTR_EMUXMODE_Pos (26UL) /*!< VADC_G EMUXCTR: EMUXMODE (Bit 26) */ 11632 #define VADC_G_EMUXCTR_EMUXMODE_Msk (0xc000000UL) /*!< VADC_G EMUXCTR: EMUXMODE (Bitfield-Mask: 0x03) */ 11633 #define VADC_G_EMUXCTR_EMXCOD_Pos (28UL) /*!< VADC_G EMUXCTR: EMXCOD (Bit 28) */ 11634 #define VADC_G_EMUXCTR_EMXCOD_Msk (0x10000000UL) /*!< VADC_G EMUXCTR: EMXCOD (Bitfield-Mask: 0x01) */ 11635 #define VADC_G_EMUXCTR_EMXST_Pos (29UL) /*!< VADC_G EMUXCTR: EMXST (Bit 29) */ 11636 #define VADC_G_EMUXCTR_EMXST_Msk (0x20000000UL) /*!< VADC_G EMUXCTR: EMXST (Bitfield-Mask: 0x01) */ 11637 #define VADC_G_EMUXCTR_EMXWC_Pos (31UL) /*!< VADC_G EMUXCTR: EMXWC (Bit 31) */ 11638 #define VADC_G_EMUXCTR_EMXWC_Msk (0x80000000UL) /*!< VADC_G EMUXCTR: EMXWC (Bitfield-Mask: 0x01) */ 11639 11640 /* --------------------------------- VADC_G_VFR --------------------------------- */ 11641 #define VADC_G_VFR_VF0_Pos (0UL) /*!< VADC_G VFR: VF0 (Bit 0) */ 11642 #define VADC_G_VFR_VF0_Msk (0x1UL) /*!< VADC_G VFR: VF0 (Bitfield-Mask: 0x01) */ 11643 #define VADC_G_VFR_VF1_Pos (1UL) /*!< VADC_G VFR: VF1 (Bit 1) */ 11644 #define VADC_G_VFR_VF1_Msk (0x2UL) /*!< VADC_G VFR: VF1 (Bitfield-Mask: 0x01) */ 11645 #define VADC_G_VFR_VF2_Pos (2UL) /*!< VADC_G VFR: VF2 (Bit 2) */ 11646 #define VADC_G_VFR_VF2_Msk (0x4UL) /*!< VADC_G VFR: VF2 (Bitfield-Mask: 0x01) */ 11647 #define VADC_G_VFR_VF3_Pos (3UL) /*!< VADC_G VFR: VF3 (Bit 3) */ 11648 #define VADC_G_VFR_VF3_Msk (0x8UL) /*!< VADC_G VFR: VF3 (Bitfield-Mask: 0x01) */ 11649 #define VADC_G_VFR_VF4_Pos (4UL) /*!< VADC_G VFR: VF4 (Bit 4) */ 11650 #define VADC_G_VFR_VF4_Msk (0x10UL) /*!< VADC_G VFR: VF4 (Bitfield-Mask: 0x01) */ 11651 #define VADC_G_VFR_VF5_Pos (5UL) /*!< VADC_G VFR: VF5 (Bit 5) */ 11652 #define VADC_G_VFR_VF5_Msk (0x20UL) /*!< VADC_G VFR: VF5 (Bitfield-Mask: 0x01) */ 11653 #define VADC_G_VFR_VF6_Pos (6UL) /*!< VADC_G VFR: VF6 (Bit 6) */ 11654 #define VADC_G_VFR_VF6_Msk (0x40UL) /*!< VADC_G VFR: VF6 (Bitfield-Mask: 0x01) */ 11655 #define VADC_G_VFR_VF7_Pos (7UL) /*!< VADC_G VFR: VF7 (Bit 7) */ 11656 #define VADC_G_VFR_VF7_Msk (0x80UL) /*!< VADC_G VFR: VF7 (Bitfield-Mask: 0x01) */ 11657 #define VADC_G_VFR_VF8_Pos (8UL) /*!< VADC_G VFR: VF8 (Bit 8) */ 11658 #define VADC_G_VFR_VF8_Msk (0x100UL) /*!< VADC_G VFR: VF8 (Bitfield-Mask: 0x01) */ 11659 #define VADC_G_VFR_VF9_Pos (9UL) /*!< VADC_G VFR: VF9 (Bit 9) */ 11660 #define VADC_G_VFR_VF9_Msk (0x200UL) /*!< VADC_G VFR: VF9 (Bitfield-Mask: 0x01) */ 11661 #define VADC_G_VFR_VF10_Pos (10UL) /*!< VADC_G VFR: VF10 (Bit 10) */ 11662 #define VADC_G_VFR_VF10_Msk (0x400UL) /*!< VADC_G VFR: VF10 (Bitfield-Mask: 0x01) */ 11663 #define VADC_G_VFR_VF11_Pos (11UL) /*!< VADC_G VFR: VF11 (Bit 11) */ 11664 #define VADC_G_VFR_VF11_Msk (0x800UL) /*!< VADC_G VFR: VF11 (Bitfield-Mask: 0x01) */ 11665 #define VADC_G_VFR_VF12_Pos (12UL) /*!< VADC_G VFR: VF12 (Bit 12) */ 11666 #define VADC_G_VFR_VF12_Msk (0x1000UL) /*!< VADC_G VFR: VF12 (Bitfield-Mask: 0x01) */ 11667 #define VADC_G_VFR_VF13_Pos (13UL) /*!< VADC_G VFR: VF13 (Bit 13) */ 11668 #define VADC_G_VFR_VF13_Msk (0x2000UL) /*!< VADC_G VFR: VF13 (Bitfield-Mask: 0x01) */ 11669 #define VADC_G_VFR_VF14_Pos (14UL) /*!< VADC_G VFR: VF14 (Bit 14) */ 11670 #define VADC_G_VFR_VF14_Msk (0x4000UL) /*!< VADC_G VFR: VF14 (Bitfield-Mask: 0x01) */ 11671 #define VADC_G_VFR_VF15_Pos (15UL) /*!< VADC_G VFR: VF15 (Bit 15) */ 11672 #define VADC_G_VFR_VF15_Msk (0x8000UL) /*!< VADC_G VFR: VF15 (Bitfield-Mask: 0x01) */ 11673 11674 /* -------------------------------- VADC_G_CHCTR -------------------------------- */ 11675 #define VADC_G_CHCTR_ICLSEL_Pos (0UL) /*!< VADC_G CHCTR: ICLSEL (Bit 0) */ 11676 #define VADC_G_CHCTR_ICLSEL_Msk (0x3UL) /*!< VADC_G CHCTR: ICLSEL (Bitfield-Mask: 0x03) */ 11677 #define VADC_G_CHCTR_BNDSELL_Pos (4UL) /*!< VADC_G CHCTR: BNDSELL (Bit 4) */ 11678 #define VADC_G_CHCTR_BNDSELL_Msk (0x30UL) /*!< VADC_G CHCTR: BNDSELL (Bitfield-Mask: 0x03) */ 11679 #define VADC_G_CHCTR_BNDSELU_Pos (6UL) /*!< VADC_G CHCTR: BNDSELU (Bit 6) */ 11680 #define VADC_G_CHCTR_BNDSELU_Msk (0xc0UL) /*!< VADC_G CHCTR: BNDSELU (Bitfield-Mask: 0x03) */ 11681 #define VADC_G_CHCTR_CHEVMODE_Pos (8UL) /*!< VADC_G CHCTR: CHEVMODE (Bit 8) */ 11682 #define VADC_G_CHCTR_CHEVMODE_Msk (0x300UL) /*!< VADC_G CHCTR: CHEVMODE (Bitfield-Mask: 0x03) */ 11683 #define VADC_G_CHCTR_SYNC_Pos (10UL) /*!< VADC_G CHCTR: SYNC (Bit 10) */ 11684 #define VADC_G_CHCTR_SYNC_Msk (0x400UL) /*!< VADC_G CHCTR: SYNC (Bitfield-Mask: 0x01) */ 11685 #define VADC_G_CHCTR_REFSEL_Pos (11UL) /*!< VADC_G CHCTR: REFSEL (Bit 11) */ 11686 #define VADC_G_CHCTR_REFSEL_Msk (0x800UL) /*!< VADC_G CHCTR: REFSEL (Bitfield-Mask: 0x01) */ 11687 #define VADC_G_CHCTR_RESREG_Pos (16UL) /*!< VADC_G CHCTR: RESREG (Bit 16) */ 11688 #define VADC_G_CHCTR_RESREG_Msk (0xf0000UL) /*!< VADC_G CHCTR: RESREG (Bitfield-Mask: 0x0f) */ 11689 #define VADC_G_CHCTR_RESTBS_Pos (20UL) /*!< VADC_G CHCTR: RESTBS (Bit 20) */ 11690 #define VADC_G_CHCTR_RESTBS_Msk (0x100000UL) /*!< VADC_G CHCTR: RESTBS (Bitfield-Mask: 0x01) */ 11691 #define VADC_G_CHCTR_RESPOS_Pos (21UL) /*!< VADC_G CHCTR: RESPOS (Bit 21) */ 11692 #define VADC_G_CHCTR_RESPOS_Msk (0x200000UL) /*!< VADC_G CHCTR: RESPOS (Bitfield-Mask: 0x01) */ 11693 #define VADC_G_CHCTR_BWDCH_Pos (28UL) /*!< VADC_G CHCTR: BWDCH (Bit 28) */ 11694 #define VADC_G_CHCTR_BWDCH_Msk (0x30000000UL) /*!< VADC_G CHCTR: BWDCH (Bitfield-Mask: 0x03) */ 11695 #define VADC_G_CHCTR_BWDEN_Pos (30UL) /*!< VADC_G CHCTR: BWDEN (Bit 30) */ 11696 #define VADC_G_CHCTR_BWDEN_Msk (0x40000000UL) /*!< VADC_G CHCTR: BWDEN (Bitfield-Mask: 0x01) */ 11697 11698 /* --------------------------------- VADC_G_RCR --------------------------------- */ 11699 #define VADC_G_RCR_DRCTR_Pos (16UL) /*!< VADC_G RCR: DRCTR (Bit 16) */ 11700 #define VADC_G_RCR_DRCTR_Msk (0xf0000UL) /*!< VADC_G RCR: DRCTR (Bitfield-Mask: 0x0f) */ 11701 #define VADC_G_RCR_DMM_Pos (20UL) /*!< VADC_G RCR: DMM (Bit 20) */ 11702 #define VADC_G_RCR_DMM_Msk (0x300000UL) /*!< VADC_G RCR: DMM (Bitfield-Mask: 0x03) */ 11703 #define VADC_G_RCR_WFR_Pos (24UL) /*!< VADC_G RCR: WFR (Bit 24) */ 11704 #define VADC_G_RCR_WFR_Msk (0x1000000UL) /*!< VADC_G RCR: WFR (Bitfield-Mask: 0x01) */ 11705 #define VADC_G_RCR_FEN_Pos (25UL) /*!< VADC_G RCR: FEN (Bit 25) */ 11706 #define VADC_G_RCR_FEN_Msk (0x6000000UL) /*!< VADC_G RCR: FEN (Bitfield-Mask: 0x03) */ 11707 #define VADC_G_RCR_SRGEN_Pos (31UL) /*!< VADC_G RCR: SRGEN (Bit 31) */ 11708 #define VADC_G_RCR_SRGEN_Msk (0x80000000UL) /*!< VADC_G RCR: SRGEN (Bitfield-Mask: 0x01) */ 11709 11710 /* --------------------------------- VADC_G_RES --------------------------------- */ 11711 #define VADC_G_RES_RESULT_Pos (0UL) /*!< VADC_G RES: RESULT (Bit 0) */ 11712 #define VADC_G_RES_RESULT_Msk (0xffffUL) /*!< VADC_G RES: RESULT (Bitfield-Mask: 0xffff) */ 11713 #define VADC_G_RES_DRC_Pos (16UL) /*!< VADC_G RES: DRC (Bit 16) */ 11714 #define VADC_G_RES_DRC_Msk (0xf0000UL) /*!< VADC_G RES: DRC (Bitfield-Mask: 0x0f) */ 11715 #define VADC_G_RES_CHNR_Pos (20UL) /*!< VADC_G RES: CHNR (Bit 20) */ 11716 #define VADC_G_RES_CHNR_Msk (0x1f00000UL) /*!< VADC_G RES: CHNR (Bitfield-Mask: 0x1f) */ 11717 #define VADC_G_RES_EMUX_Pos (25UL) /*!< VADC_G RES: EMUX (Bit 25) */ 11718 #define VADC_G_RES_EMUX_Msk (0xe000000UL) /*!< VADC_G RES: EMUX (Bitfield-Mask: 0x07) */ 11719 #define VADC_G_RES_CRS_Pos (28UL) /*!< VADC_G RES: CRS (Bit 28) */ 11720 #define VADC_G_RES_CRS_Msk (0x30000000UL) /*!< VADC_G RES: CRS (Bitfield-Mask: 0x03) */ 11721 #define VADC_G_RES_FCR_Pos (30UL) /*!< VADC_G RES: FCR (Bit 30) */ 11722 #define VADC_G_RES_FCR_Msk (0x40000000UL) /*!< VADC_G RES: FCR (Bitfield-Mask: 0x01) */ 11723 #define VADC_G_RES_VF_Pos (31UL) /*!< VADC_G RES: VF (Bit 31) */ 11724 #define VADC_G_RES_VF_Msk (0x80000000UL) /*!< VADC_G RES: VF (Bitfield-Mask: 0x01) */ 11725 11726 /* --------------------------------- VADC_G_RESD -------------------------------- */ 11727 #define VADC_G_RESD_RESULT_Pos (0UL) /*!< VADC_G RESD: RESULT (Bit 0) */ 11728 #define VADC_G_RESD_RESULT_Msk (0xffffUL) /*!< VADC_G RESD: RESULT (Bitfield-Mask: 0xffff) */ 11729 #define VADC_G_RESD_DRC_Pos (16UL) /*!< VADC_G RESD: DRC (Bit 16) */ 11730 #define VADC_G_RESD_DRC_Msk (0xf0000UL) /*!< VADC_G RESD: DRC (Bitfield-Mask: 0x0f) */ 11731 #define VADC_G_RESD_CHNR_Pos (20UL) /*!< VADC_G RESD: CHNR (Bit 20) */ 11732 #define VADC_G_RESD_CHNR_Msk (0x1f00000UL) /*!< VADC_G RESD: CHNR (Bitfield-Mask: 0x1f) */ 11733 #define VADC_G_RESD_EMUX_Pos (25UL) /*!< VADC_G RESD: EMUX (Bit 25) */ 11734 #define VADC_G_RESD_EMUX_Msk (0xe000000UL) /*!< VADC_G RESD: EMUX (Bitfield-Mask: 0x07) */ 11735 #define VADC_G_RESD_CRS_Pos (28UL) /*!< VADC_G RESD: CRS (Bit 28) */ 11736 #define VADC_G_RESD_CRS_Msk (0x30000000UL) /*!< VADC_G RESD: CRS (Bitfield-Mask: 0x03) */ 11737 #define VADC_G_RESD_FCR_Pos (30UL) /*!< VADC_G RESD: FCR (Bit 30) */ 11738 #define VADC_G_RESD_FCR_Msk (0x40000000UL) /*!< VADC_G RESD: FCR (Bitfield-Mask: 0x01) */ 11739 #define VADC_G_RESD_VF_Pos (31UL) /*!< VADC_G RESD: VF (Bit 31) */ 11740 #define VADC_G_RESD_VF_Msk (0x80000000UL) /*!< VADC_G RESD: VF (Bitfield-Mask: 0x01) */ 11741 11742 11743 /* ================================================================================ */ 11744 /* ================ struct 'DSD' Position & Mask ================ */ 11745 /* ================================================================================ */ 11746 11747 11748 /* ----------------------------------- DSD_CLC ---------------------------------- */ 11749 #define DSD_CLC_DISR_Pos (0UL) /*!< DSD CLC: DISR (Bit 0) */ 11750 #define DSD_CLC_DISR_Msk (0x1UL) /*!< DSD CLC: DISR (Bitfield-Mask: 0x01) */ 11751 #define DSD_CLC_DISS_Pos (1UL) /*!< DSD CLC: DISS (Bit 1) */ 11752 #define DSD_CLC_DISS_Msk (0x2UL) /*!< DSD CLC: DISS (Bitfield-Mask: 0x01) */ 11753 #define DSD_CLC_EDIS_Pos (3UL) /*!< DSD CLC: EDIS (Bit 3) */ 11754 #define DSD_CLC_EDIS_Msk (0x8UL) /*!< DSD CLC: EDIS (Bitfield-Mask: 0x01) */ 11755 11756 /* ----------------------------------- DSD_ID ----------------------------------- */ 11757 #define DSD_ID_MOD_REV_Pos (0UL) /*!< DSD ID: MOD_REV (Bit 0) */ 11758 #define DSD_ID_MOD_REV_Msk (0xffUL) /*!< DSD ID: MOD_REV (Bitfield-Mask: 0xff) */ 11759 #define DSD_ID_MOD_TYPE_Pos (8UL) /*!< DSD ID: MOD_TYPE (Bit 8) */ 11760 #define DSD_ID_MOD_TYPE_Msk (0xff00UL) /*!< DSD ID: MOD_TYPE (Bitfield-Mask: 0xff) */ 11761 #define DSD_ID_MOD_NUMBER_Pos (16UL) /*!< DSD ID: MOD_NUMBER (Bit 16) */ 11762 #define DSD_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< DSD ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ 11763 11764 /* ----------------------------------- DSD_OCS ---------------------------------- */ 11765 #define DSD_OCS_SUS_Pos (24UL) /*!< DSD OCS: SUS (Bit 24) */ 11766 #define DSD_OCS_SUS_Msk (0xf000000UL) /*!< DSD OCS: SUS (Bitfield-Mask: 0x0f) */ 11767 #define DSD_OCS_SUS_P_Pos (28UL) /*!< DSD OCS: SUS_P (Bit 28) */ 11768 #define DSD_OCS_SUS_P_Msk (0x10000000UL) /*!< DSD OCS: SUS_P (Bitfield-Mask: 0x01) */ 11769 #define DSD_OCS_SUSSTA_Pos (29UL) /*!< DSD OCS: SUSSTA (Bit 29) */ 11770 #define DSD_OCS_SUSSTA_Msk (0x20000000UL) /*!< DSD OCS: SUSSTA (Bitfield-Mask: 0x01) */ 11771 11772 /* --------------------------------- DSD_GLOBCFG -------------------------------- */ 11773 #define DSD_GLOBCFG_MCSEL_Pos (0UL) /*!< DSD GLOBCFG: MCSEL (Bit 0) */ 11774 #define DSD_GLOBCFG_MCSEL_Msk (0x7UL) /*!< DSD GLOBCFG: MCSEL (Bitfield-Mask: 0x07) */ 11775 11776 /* --------------------------------- DSD_GLOBRC --------------------------------- */ 11777 #define DSD_GLOBRC_CH0RUN_Pos (0UL) /*!< DSD GLOBRC: CH0RUN (Bit 0) */ 11778 #define DSD_GLOBRC_CH0RUN_Msk (0x1UL) /*!< DSD GLOBRC: CH0RUN (Bitfield-Mask: 0x01) */ 11779 #define DSD_GLOBRC_CH1RUN_Pos (1UL) /*!< DSD GLOBRC: CH1RUN (Bit 1) */ 11780 #define DSD_GLOBRC_CH1RUN_Msk (0x2UL) /*!< DSD GLOBRC: CH1RUN (Bitfield-Mask: 0x01) */ 11781 #define DSD_GLOBRC_CH2RUN_Pos (2UL) /*!< DSD GLOBRC: CH2RUN (Bit 2) */ 11782 #define DSD_GLOBRC_CH2RUN_Msk (0x4UL) /*!< DSD GLOBRC: CH2RUN (Bitfield-Mask: 0x01) */ 11783 #define DSD_GLOBRC_CH3RUN_Pos (3UL) /*!< DSD GLOBRC: CH3RUN (Bit 3) */ 11784 #define DSD_GLOBRC_CH3RUN_Msk (0x8UL) /*!< DSD GLOBRC: CH3RUN (Bitfield-Mask: 0x01) */ 11785 11786 /* ---------------------------------- DSD_CGCFG --------------------------------- */ 11787 #define DSD_CGCFG_CGMOD_Pos (0UL) /*!< DSD CGCFG: CGMOD (Bit 0) */ 11788 #define DSD_CGCFG_CGMOD_Msk (0x3UL) /*!< DSD CGCFG: CGMOD (Bitfield-Mask: 0x03) */ 11789 #define DSD_CGCFG_BREV_Pos (2UL) /*!< DSD CGCFG: BREV (Bit 2) */ 11790 #define DSD_CGCFG_BREV_Msk (0x4UL) /*!< DSD CGCFG: BREV (Bitfield-Mask: 0x01) */ 11791 #define DSD_CGCFG_SIGPOL_Pos (3UL) /*!< DSD CGCFG: SIGPOL (Bit 3) */ 11792 #define DSD_CGCFG_SIGPOL_Msk (0x8UL) /*!< DSD CGCFG: SIGPOL (Bitfield-Mask: 0x01) */ 11793 #define DSD_CGCFG_DIVCG_Pos (4UL) /*!< DSD CGCFG: DIVCG (Bit 4) */ 11794 #define DSD_CGCFG_DIVCG_Msk (0xf0UL) /*!< DSD CGCFG: DIVCG (Bitfield-Mask: 0x0f) */ 11795 #define DSD_CGCFG_RUN_Pos (15UL) /*!< DSD CGCFG: RUN (Bit 15) */ 11796 #define DSD_CGCFG_RUN_Msk (0x8000UL) /*!< DSD CGCFG: RUN (Bitfield-Mask: 0x01) */ 11797 #define DSD_CGCFG_BITCOUNT_Pos (16UL) /*!< DSD CGCFG: BITCOUNT (Bit 16) */ 11798 #define DSD_CGCFG_BITCOUNT_Msk (0x1f0000UL) /*!< DSD CGCFG: BITCOUNT (Bitfield-Mask: 0x1f) */ 11799 #define DSD_CGCFG_STEPCOUNT_Pos (24UL) /*!< DSD CGCFG: STEPCOUNT (Bit 24) */ 11800 #define DSD_CGCFG_STEPCOUNT_Msk (0xf000000UL) /*!< DSD CGCFG: STEPCOUNT (Bitfield-Mask: 0x0f) */ 11801 #define DSD_CGCFG_STEPS_Pos (28UL) /*!< DSD CGCFG: STEPS (Bit 28) */ 11802 #define DSD_CGCFG_STEPS_Msk (0x10000000UL) /*!< DSD CGCFG: STEPS (Bitfield-Mask: 0x01) */ 11803 #define DSD_CGCFG_STEPD_Pos (29UL) /*!< DSD CGCFG: STEPD (Bit 29) */ 11804 #define DSD_CGCFG_STEPD_Msk (0x20000000UL) /*!< DSD CGCFG: STEPD (Bitfield-Mask: 0x01) */ 11805 #define DSD_CGCFG_SGNCG_Pos (30UL) /*!< DSD CGCFG: SGNCG (Bit 30) */ 11806 #define DSD_CGCFG_SGNCG_Msk (0x40000000UL) /*!< DSD CGCFG: SGNCG (Bitfield-Mask: 0x01) */ 11807 11808 /* --------------------------------- DSD_EVFLAG --------------------------------- */ 11809 #define DSD_EVFLAG_RESEV0_Pos (0UL) /*!< DSD EVFLAG: RESEV0 (Bit 0) */ 11810 #define DSD_EVFLAG_RESEV0_Msk (0x1UL) /*!< DSD EVFLAG: RESEV0 (Bitfield-Mask: 0x01) */ 11811 #define DSD_EVFLAG_RESEV1_Pos (1UL) /*!< DSD EVFLAG: RESEV1 (Bit 1) */ 11812 #define DSD_EVFLAG_RESEV1_Msk (0x2UL) /*!< DSD EVFLAG: RESEV1 (Bitfield-Mask: 0x01) */ 11813 #define DSD_EVFLAG_RESEV2_Pos (2UL) /*!< DSD EVFLAG: RESEV2 (Bit 2) */ 11814 #define DSD_EVFLAG_RESEV2_Msk (0x4UL) /*!< DSD EVFLAG: RESEV2 (Bitfield-Mask: 0x01) */ 11815 #define DSD_EVFLAG_RESEV3_Pos (3UL) /*!< DSD EVFLAG: RESEV3 (Bit 3) */ 11816 #define DSD_EVFLAG_RESEV3_Msk (0x8UL) /*!< DSD EVFLAG: RESEV3 (Bitfield-Mask: 0x01) */ 11817 #define DSD_EVFLAG_ALEV0_Pos (16UL) /*!< DSD EVFLAG: ALEV0 (Bit 16) */ 11818 #define DSD_EVFLAG_ALEV0_Msk (0x10000UL) /*!< DSD EVFLAG: ALEV0 (Bitfield-Mask: 0x01) */ 11819 #define DSD_EVFLAG_ALEV1_Pos (17UL) /*!< DSD EVFLAG: ALEV1 (Bit 17) */ 11820 #define DSD_EVFLAG_ALEV1_Msk (0x20000UL) /*!< DSD EVFLAG: ALEV1 (Bitfield-Mask: 0x01) */ 11821 #define DSD_EVFLAG_ALEV2_Pos (18UL) /*!< DSD EVFLAG: ALEV2 (Bit 18) */ 11822 #define DSD_EVFLAG_ALEV2_Msk (0x40000UL) /*!< DSD EVFLAG: ALEV2 (Bitfield-Mask: 0x01) */ 11823 #define DSD_EVFLAG_ALEV3_Pos (19UL) /*!< DSD EVFLAG: ALEV3 (Bit 19) */ 11824 #define DSD_EVFLAG_ALEV3_Msk (0x80000UL) /*!< DSD EVFLAG: ALEV3 (Bitfield-Mask: 0x01) */ 11825 #define DSD_EVFLAG_ALEV4_Pos (20UL) /*!< DSD EVFLAG: ALEV4 (Bit 20) */ 11826 #define DSD_EVFLAG_ALEV4_Msk (0x100000UL) /*!< DSD EVFLAG: ALEV4 (Bitfield-Mask: 0x01) */ 11827 #define DSD_EVFLAG_ALEV5_Pos (21UL) /*!< DSD EVFLAG: ALEV5 (Bit 21) */ 11828 #define DSD_EVFLAG_ALEV5_Msk (0x200000UL) /*!< DSD EVFLAG: ALEV5 (Bitfield-Mask: 0x01) */ 11829 #define DSD_EVFLAG_ALEV6_Pos (22UL) /*!< DSD EVFLAG: ALEV6 (Bit 22) */ 11830 #define DSD_EVFLAG_ALEV6_Msk (0x400000UL) /*!< DSD EVFLAG: ALEV6 (Bitfield-Mask: 0x01) */ 11831 #define DSD_EVFLAG_ALEV7_Pos (23UL) /*!< DSD EVFLAG: ALEV7 (Bit 23) */ 11832 #define DSD_EVFLAG_ALEV7_Msk (0x800000UL) /*!< DSD EVFLAG: ALEV7 (Bitfield-Mask: 0x01) */ 11833 #define DSD_EVFLAG_ALEV8_Pos (24UL) /*!< DSD EVFLAG: ALEV8 (Bit 24) */ 11834 #define DSD_EVFLAG_ALEV8_Msk (0x1000000UL) /*!< DSD EVFLAG: ALEV8 (Bitfield-Mask: 0x01) */ 11835 #define DSD_EVFLAG_ALEV9_Pos (25UL) /*!< DSD EVFLAG: ALEV9 (Bit 25) */ 11836 #define DSD_EVFLAG_ALEV9_Msk (0x2000000UL) /*!< DSD EVFLAG: ALEV9 (Bitfield-Mask: 0x01) */ 11837 11838 /* -------------------------------- DSD_EVFLAGCLR ------------------------------- */ 11839 #define DSD_EVFLAGCLR_RESEC0_Pos (0UL) /*!< DSD EVFLAGCLR: RESEC0 (Bit 0) */ 11840 #define DSD_EVFLAGCLR_RESEC0_Msk (0x1UL) /*!< DSD EVFLAGCLR: RESEC0 (Bitfield-Mask: 0x01) */ 11841 #define DSD_EVFLAGCLR_RESEC1_Pos (1UL) /*!< DSD EVFLAGCLR: RESEC1 (Bit 1) */ 11842 #define DSD_EVFLAGCLR_RESEC1_Msk (0x2UL) /*!< DSD EVFLAGCLR: RESEC1 (Bitfield-Mask: 0x01) */ 11843 #define DSD_EVFLAGCLR_RESEC2_Pos (2UL) /*!< DSD EVFLAGCLR: RESEC2 (Bit 2) */ 11844 #define DSD_EVFLAGCLR_RESEC2_Msk (0x4UL) /*!< DSD EVFLAGCLR: RESEC2 (Bitfield-Mask: 0x01) */ 11845 #define DSD_EVFLAGCLR_RESEC3_Pos (3UL) /*!< DSD EVFLAGCLR: RESEC3 (Bit 3) */ 11846 #define DSD_EVFLAGCLR_RESEC3_Msk (0x8UL) /*!< DSD EVFLAGCLR: RESEC3 (Bitfield-Mask: 0x01) */ 11847 #define DSD_EVFLAGCLR_ALEC0_Pos (16UL) /*!< DSD EVFLAGCLR: ALEC0 (Bit 16) */ 11848 #define DSD_EVFLAGCLR_ALEC0_Msk (0x10000UL) /*!< DSD EVFLAGCLR: ALEC0 (Bitfield-Mask: 0x01) */ 11849 #define DSD_EVFLAGCLR_ALEC1_Pos (17UL) /*!< DSD EVFLAGCLR: ALEC1 (Bit 17) */ 11850 #define DSD_EVFLAGCLR_ALEC1_Msk (0x20000UL) /*!< DSD EVFLAGCLR: ALEC1 (Bitfield-Mask: 0x01) */ 11851 #define DSD_EVFLAGCLR_ALEC2_Pos (18UL) /*!< DSD EVFLAGCLR: ALEC2 (Bit 18) */ 11852 #define DSD_EVFLAGCLR_ALEC2_Msk (0x40000UL) /*!< DSD EVFLAGCLR: ALEC2 (Bitfield-Mask: 0x01) */ 11853 #define DSD_EVFLAGCLR_ALEC3_Pos (19UL) /*!< DSD EVFLAGCLR: ALEC3 (Bit 19) */ 11854 #define DSD_EVFLAGCLR_ALEC3_Msk (0x80000UL) /*!< DSD EVFLAGCLR: ALEC3 (Bitfield-Mask: 0x01) */ 11855 11856 11857 /* ================================================================================ */ 11858 /* ================ Group 'DSD_CH' Position & Mask ================ */ 11859 /* ================================================================================ */ 11860 11861 11862 /* -------------------------------- DSD_CH_MODCFG ------------------------------- */ 11863 #define DSD_CH_MODCFG_DIVM_Pos (16UL) /*!< DSD_CH MODCFG: DIVM (Bit 16) */ 11864 #define DSD_CH_MODCFG_DIVM_Msk (0xf0000UL) /*!< DSD_CH MODCFG: DIVM (Bitfield-Mask: 0x0f) */ 11865 #define DSD_CH_MODCFG_DWC_Pos (23UL) /*!< DSD_CH MODCFG: DWC (Bit 23) */ 11866 #define DSD_CH_MODCFG_DWC_Msk (0x800000UL) /*!< DSD_CH MODCFG: DWC (Bitfield-Mask: 0x01) */ 11867 11868 /* -------------------------------- DSD_CH_DICFG -------------------------------- */ 11869 #define DSD_CH_DICFG_DSRC_Pos (0UL) /*!< DSD_CH DICFG: DSRC (Bit 0) */ 11870 #define DSD_CH_DICFG_DSRC_Msk (0xfUL) /*!< DSD_CH DICFG: DSRC (Bitfield-Mask: 0x0f) */ 11871 #define DSD_CH_DICFG_DSWC_Pos (7UL) /*!< DSD_CH DICFG: DSWC (Bit 7) */ 11872 #define DSD_CH_DICFG_DSWC_Msk (0x80UL) /*!< DSD_CH DICFG: DSWC (Bitfield-Mask: 0x01) */ 11873 #define DSD_CH_DICFG_ITRMODE_Pos (8UL) /*!< DSD_CH DICFG: ITRMODE (Bit 8) */ 11874 #define DSD_CH_DICFG_ITRMODE_Msk (0x300UL) /*!< DSD_CH DICFG: ITRMODE (Bitfield-Mask: 0x03) */ 11875 #define DSD_CH_DICFG_TSTRMODE_Pos (10UL) /*!< DSD_CH DICFG: TSTRMODE (Bit 10) */ 11876 #define DSD_CH_DICFG_TSTRMODE_Msk (0xc00UL) /*!< DSD_CH DICFG: TSTRMODE (Bitfield-Mask: 0x03) */ 11877 #define DSD_CH_DICFG_TRSEL_Pos (12UL) /*!< DSD_CH DICFG: TRSEL (Bit 12) */ 11878 #define DSD_CH_DICFG_TRSEL_Msk (0x7000UL) /*!< DSD_CH DICFG: TRSEL (Bitfield-Mask: 0x07) */ 11879 #define DSD_CH_DICFG_TRWC_Pos (15UL) /*!< DSD_CH DICFG: TRWC (Bit 15) */ 11880 #define DSD_CH_DICFG_TRWC_Msk (0x8000UL) /*!< DSD_CH DICFG: TRWC (Bitfield-Mask: 0x01) */ 11881 #define DSD_CH_DICFG_CSRC_Pos (16UL) /*!< DSD_CH DICFG: CSRC (Bit 16) */ 11882 #define DSD_CH_DICFG_CSRC_Msk (0xf0000UL) /*!< DSD_CH DICFG: CSRC (Bitfield-Mask: 0x0f) */ 11883 #define DSD_CH_DICFG_STROBE_Pos (20UL) /*!< DSD_CH DICFG: STROBE (Bit 20) */ 11884 #define DSD_CH_DICFG_STROBE_Msk (0xf00000UL) /*!< DSD_CH DICFG: STROBE (Bitfield-Mask: 0x0f) */ 11885 #define DSD_CH_DICFG_SCWC_Pos (31UL) /*!< DSD_CH DICFG: SCWC (Bit 31) */ 11886 #define DSD_CH_DICFG_SCWC_Msk (0x80000000UL) /*!< DSD_CH DICFG: SCWC (Bitfield-Mask: 0x01) */ 11887 11888 /* -------------------------------- DSD_CH_FCFGC -------------------------------- */ 11889 #define DSD_CH_FCFGC_CFMDF_Pos (0UL) /*!< DSD_CH FCFGC: CFMDF (Bit 0) */ 11890 #define DSD_CH_FCFGC_CFMDF_Msk (0xffUL) /*!< DSD_CH FCFGC: CFMDF (Bitfield-Mask: 0xff) */ 11891 #define DSD_CH_FCFGC_CFMC_Pos (8UL) /*!< DSD_CH FCFGC: CFMC (Bit 8) */ 11892 #define DSD_CH_FCFGC_CFMC_Msk (0x300UL) /*!< DSD_CH FCFGC: CFMC (Bitfield-Mask: 0x03) */ 11893 #define DSD_CH_FCFGC_CFEN_Pos (10UL) /*!< DSD_CH FCFGC: CFEN (Bit 10) */ 11894 #define DSD_CH_FCFGC_CFEN_Msk (0x400UL) /*!< DSD_CH FCFGC: CFEN (Bitfield-Mask: 0x01) */ 11895 #define DSD_CH_FCFGC_SRGM_Pos (14UL) /*!< DSD_CH FCFGC: SRGM (Bit 14) */ 11896 #define DSD_CH_FCFGC_SRGM_Msk (0xc000UL) /*!< DSD_CH FCFGC: SRGM (Bitfield-Mask: 0x03) */ 11897 #define DSD_CH_FCFGC_CFMSV_Pos (16UL) /*!< DSD_CH FCFGC: CFMSV (Bit 16) */ 11898 #define DSD_CH_FCFGC_CFMSV_Msk (0xff0000UL) /*!< DSD_CH FCFGC: CFMSV (Bitfield-Mask: 0xff) */ 11899 #define DSD_CH_FCFGC_CFMDCNT_Pos (24UL) /*!< DSD_CH FCFGC: CFMDCNT (Bit 24) */ 11900 #define DSD_CH_FCFGC_CFMDCNT_Msk (0xff000000UL) /*!< DSD_CH FCFGC: CFMDCNT (Bitfield-Mask: 0xff) */ 11901 11902 /* -------------------------------- DSD_CH_FCFGA -------------------------------- */ 11903 #define DSD_CH_FCFGA_CFADF_Pos (0UL) /*!< DSD_CH FCFGA: CFADF (Bit 0) */ 11904 #define DSD_CH_FCFGA_CFADF_Msk (0xffUL) /*!< DSD_CH FCFGA: CFADF (Bitfield-Mask: 0xff) */ 11905 #define DSD_CH_FCFGA_CFAC_Pos (8UL) /*!< DSD_CH FCFGA: CFAC (Bit 8) */ 11906 #define DSD_CH_FCFGA_CFAC_Msk (0x300UL) /*!< DSD_CH FCFGA: CFAC (Bitfield-Mask: 0x03) */ 11907 #define DSD_CH_FCFGA_SRGA_Pos (10UL) /*!< DSD_CH FCFGA: SRGA (Bit 10) */ 11908 #define DSD_CH_FCFGA_SRGA_Msk (0xc00UL) /*!< DSD_CH FCFGA: SRGA (Bitfield-Mask: 0x03) */ 11909 #define DSD_CH_FCFGA_ESEL_Pos (12UL) /*!< DSD_CH FCFGA: ESEL (Bit 12) */ 11910 #define DSD_CH_FCFGA_ESEL_Msk (0x3000UL) /*!< DSD_CH FCFGA: ESEL (Bitfield-Mask: 0x03) */ 11911 #define DSD_CH_FCFGA_EGT_Pos (14UL) /*!< DSD_CH FCFGA: EGT (Bit 14) */ 11912 #define DSD_CH_FCFGA_EGT_Msk (0x4000UL) /*!< DSD_CH FCFGA: EGT (Bitfield-Mask: 0x01) */ 11913 #define DSD_CH_FCFGA_CFADCNT_Pos (24UL) /*!< DSD_CH FCFGA: CFADCNT (Bit 24) */ 11914 #define DSD_CH_FCFGA_CFADCNT_Msk (0xff000000UL) /*!< DSD_CH FCFGA: CFADCNT (Bitfield-Mask: 0xff) */ 11915 11916 /* -------------------------------- DSD_CH_IWCTR -------------------------------- */ 11917 #define DSD_CH_IWCTR_NVALCNT_Pos (0UL) /*!< DSD_CH IWCTR: NVALCNT (Bit 0) */ 11918 #define DSD_CH_IWCTR_NVALCNT_Msk (0x3fUL) /*!< DSD_CH IWCTR: NVALCNT (Bitfield-Mask: 0x3f) */ 11919 #define DSD_CH_IWCTR_INTEN_Pos (7UL) /*!< DSD_CH IWCTR: INTEN (Bit 7) */ 11920 #define DSD_CH_IWCTR_INTEN_Msk (0x80UL) /*!< DSD_CH IWCTR: INTEN (Bitfield-Mask: 0x01) */ 11921 #define DSD_CH_IWCTR_REPCNT_Pos (8UL) /*!< DSD_CH IWCTR: REPCNT (Bit 8) */ 11922 #define DSD_CH_IWCTR_REPCNT_Msk (0xf00UL) /*!< DSD_CH IWCTR: REPCNT (Bitfield-Mask: 0x0f) */ 11923 #define DSD_CH_IWCTR_REPVAL_Pos (12UL) /*!< DSD_CH IWCTR: REPVAL (Bit 12) */ 11924 #define DSD_CH_IWCTR_REPVAL_Msk (0xf000UL) /*!< DSD_CH IWCTR: REPVAL (Bitfield-Mask: 0x0f) */ 11925 #define DSD_CH_IWCTR_NVALDIS_Pos (16UL) /*!< DSD_CH IWCTR: NVALDIS (Bit 16) */ 11926 #define DSD_CH_IWCTR_NVALDIS_Msk (0x3f0000UL) /*!< DSD_CH IWCTR: NVALDIS (Bitfield-Mask: 0x3f) */ 11927 #define DSD_CH_IWCTR_IWS_Pos (23UL) /*!< DSD_CH IWCTR: IWS (Bit 23) */ 11928 #define DSD_CH_IWCTR_IWS_Msk (0x800000UL) /*!< DSD_CH IWCTR: IWS (Bitfield-Mask: 0x01) */ 11929 #define DSD_CH_IWCTR_NVALINT_Pos (24UL) /*!< DSD_CH IWCTR: NVALINT (Bit 24) */ 11930 #define DSD_CH_IWCTR_NVALINT_Msk (0x3f000000UL) /*!< DSD_CH IWCTR: NVALINT (Bitfield-Mask: 0x3f) */ 11931 11932 /* ------------------------------- DSD_CH_BOUNDSEL ------------------------------ */ 11933 #define DSD_CH_BOUNDSEL_BOUNDARYL_Pos (0UL) /*!< DSD_CH BOUNDSEL: BOUNDARYL (Bit 0) */ 11934 #define DSD_CH_BOUNDSEL_BOUNDARYL_Msk (0xffffUL) /*!< DSD_CH BOUNDSEL: BOUNDARYL (Bitfield-Mask: 0xffff) */ 11935 #define DSD_CH_BOUNDSEL_BOUNDARYU_Pos (16UL) /*!< DSD_CH BOUNDSEL: BOUNDARYU (Bit 16) */ 11936 #define DSD_CH_BOUNDSEL_BOUNDARYU_Msk (0xffff0000UL) /*!< DSD_CH BOUNDSEL: BOUNDARYU (Bitfield-Mask: 0xffff) */ 11937 11938 /* --------------------------------- DSD_CH_RESM -------------------------------- */ 11939 #define DSD_CH_RESM_RESULT_Pos (0UL) /*!< DSD_CH RESM: RESULT (Bit 0) */ 11940 #define DSD_CH_RESM_RESULT_Msk (0xffffUL) /*!< DSD_CH RESM: RESULT (Bitfield-Mask: 0xffff) */ 11941 11942 /* --------------------------------- DSD_CH_OFFM -------------------------------- */ 11943 #define DSD_CH_OFFM_OFFSET_Pos (0UL) /*!< DSD_CH OFFM: OFFSET (Bit 0) */ 11944 #define DSD_CH_OFFM_OFFSET_Msk (0xffffUL) /*!< DSD_CH OFFM: OFFSET (Bitfield-Mask: 0xffff) */ 11945 11946 /* --------------------------------- DSD_CH_RESA -------------------------------- */ 11947 #define DSD_CH_RESA_RESULT_Pos (0UL) /*!< DSD_CH RESA: RESULT (Bit 0) */ 11948 #define DSD_CH_RESA_RESULT_Msk (0xffffUL) /*!< DSD_CH RESA: RESULT (Bitfield-Mask: 0xffff) */ 11949 11950 /* -------------------------------- DSD_CH_TSTMP -------------------------------- */ 11951 #define DSD_CH_TSTMP_RESULT_Pos (0UL) /*!< DSD_CH TSTMP: RESULT (Bit 0) */ 11952 #define DSD_CH_TSTMP_RESULT_Msk (0xffffUL) /*!< DSD_CH TSTMP: RESULT (Bitfield-Mask: 0xffff) */ 11953 #define DSD_CH_TSTMP_CFMDCNT_Pos (16UL) /*!< DSD_CH TSTMP: CFMDCNT (Bit 16) */ 11954 #define DSD_CH_TSTMP_CFMDCNT_Msk (0xff0000UL) /*!< DSD_CH TSTMP: CFMDCNT (Bitfield-Mask: 0xff) */ 11955 #define DSD_CH_TSTMP_NVALCNT_Pos (24UL) /*!< DSD_CH TSTMP: NVALCNT (Bit 24) */ 11956 #define DSD_CH_TSTMP_NVALCNT_Msk (0x3f000000UL) /*!< DSD_CH TSTMP: NVALCNT (Bitfield-Mask: 0x3f) */ 11957 11958 /* -------------------------------- DSD_CH_CGSYNC ------------------------------- */ 11959 #define DSD_CH_CGSYNC_SDCOUNT_Pos (0UL) /*!< DSD_CH CGSYNC: SDCOUNT (Bit 0) */ 11960 #define DSD_CH_CGSYNC_SDCOUNT_Msk (0xffUL) /*!< DSD_CH CGSYNC: SDCOUNT (Bitfield-Mask: 0xff) */ 11961 #define DSD_CH_CGSYNC_SDCAP_Pos (8UL) /*!< DSD_CH CGSYNC: SDCAP (Bit 8) */ 11962 #define DSD_CH_CGSYNC_SDCAP_Msk (0xff00UL) /*!< DSD_CH CGSYNC: SDCAP (Bitfield-Mask: 0xff) */ 11963 #define DSD_CH_CGSYNC_SDPOS_Pos (16UL) /*!< DSD_CH CGSYNC: SDPOS (Bit 16) */ 11964 #define DSD_CH_CGSYNC_SDPOS_Msk (0xff0000UL) /*!< DSD_CH CGSYNC: SDPOS (Bitfield-Mask: 0xff) */ 11965 #define DSD_CH_CGSYNC_SDNEG_Pos (24UL) /*!< DSD_CH CGSYNC: SDNEG (Bit 24) */ 11966 #define DSD_CH_CGSYNC_SDNEG_Msk (0xff000000UL) /*!< DSD_CH CGSYNC: SDNEG (Bitfield-Mask: 0xff) */ 11967 11968 /* ------------------------------- DSD_CH_RECTCFG ------------------------------- */ 11969 #define DSD_CH_RECTCFG_RFEN_Pos (0UL) /*!< DSD_CH RECTCFG: RFEN (Bit 0) */ 11970 #define DSD_CH_RECTCFG_RFEN_Msk (0x1UL) /*!< DSD_CH RECTCFG: RFEN (Bitfield-Mask: 0x01) */ 11971 #define DSD_CH_RECTCFG_SSRC_Pos (4UL) /*!< DSD_CH RECTCFG: SSRC (Bit 4) */ 11972 #define DSD_CH_RECTCFG_SSRC_Msk (0x30UL) /*!< DSD_CH RECTCFG: SSRC (Bitfield-Mask: 0x03) */ 11973 #define DSD_CH_RECTCFG_SDVAL_Pos (15UL) /*!< DSD_CH RECTCFG: SDVAL (Bit 15) */ 11974 #define DSD_CH_RECTCFG_SDVAL_Msk (0x8000UL) /*!< DSD_CH RECTCFG: SDVAL (Bitfield-Mask: 0x01) */ 11975 #define DSD_CH_RECTCFG_SGNCS_Pos (30UL) /*!< DSD_CH RECTCFG: SGNCS (Bit 30) */ 11976 #define DSD_CH_RECTCFG_SGNCS_Msk (0x40000000UL) /*!< DSD_CH RECTCFG: SGNCS (Bitfield-Mask: 0x01) */ 11977 #define DSD_CH_RECTCFG_SGND_Pos (31UL) /*!< DSD_CH RECTCFG: SGND (Bit 31) */ 11978 #define DSD_CH_RECTCFG_SGND_Msk (0x80000000UL) /*!< DSD_CH RECTCFG: SGND (Bitfield-Mask: 0x01) */ 11979 11980 11981 /* ================================================================================ */ 11982 /* ================ struct 'DAC' Position & Mask ================ */ 11983 /* ================================================================================ */ 11984 11985 11986 /* ----------------------------------- DAC_ID ----------------------------------- */ 11987 #define DAC_ID_MODR_Pos (0UL) /*!< DAC ID: MODR (Bit 0) */ 11988 #define DAC_ID_MODR_Msk (0xffUL) /*!< DAC ID: MODR (Bitfield-Mask: 0xff) */ 11989 #define DAC_ID_MODT_Pos (8UL) /*!< DAC ID: MODT (Bit 8) */ 11990 #define DAC_ID_MODT_Msk (0xff00UL) /*!< DAC ID: MODT (Bitfield-Mask: 0xff) */ 11991 #define DAC_ID_MODN_Pos (16UL) /*!< DAC ID: MODN (Bit 16) */ 11992 #define DAC_ID_MODN_Msk (0xffff0000UL) /*!< DAC ID: MODN (Bitfield-Mask: 0xffff) */ 11993 11994 /* -------------------------------- DAC_DAC0CFG0 -------------------------------- */ 11995 #define DAC_DAC0CFG0_FREQ_Pos (0UL) /*!< DAC DAC0CFG0: FREQ (Bit 0) */ 11996 #define DAC_DAC0CFG0_FREQ_Msk (0xfffffUL) /*!< DAC DAC0CFG0: FREQ (Bitfield-Mask: 0xfffff) */ 11997 #define DAC_DAC0CFG0_MODE_Pos (20UL) /*!< DAC DAC0CFG0: MODE (Bit 20) */ 11998 #define DAC_DAC0CFG0_MODE_Msk (0x700000UL) /*!< DAC DAC0CFG0: MODE (Bitfield-Mask: 0x07) */ 11999 #define DAC_DAC0CFG0_SIGN_Pos (23UL) /*!< DAC DAC0CFG0: SIGN (Bit 23) */ 12000 #define DAC_DAC0CFG0_SIGN_Msk (0x800000UL) /*!< DAC DAC0CFG0: SIGN (Bitfield-Mask: 0x01) */ 12001 #define DAC_DAC0CFG0_FIFOIND_Pos (24UL) /*!< DAC DAC0CFG0: FIFOIND (Bit 24) */ 12002 #define DAC_DAC0CFG0_FIFOIND_Msk (0x3000000UL) /*!< DAC DAC0CFG0: FIFOIND (Bitfield-Mask: 0x03) */ 12003 #define DAC_DAC0CFG0_FIFOEMP_Pos (26UL) /*!< DAC DAC0CFG0: FIFOEMP (Bit 26) */ 12004 #define DAC_DAC0CFG0_FIFOEMP_Msk (0x4000000UL) /*!< DAC DAC0CFG0: FIFOEMP (Bitfield-Mask: 0x01) */ 12005 #define DAC_DAC0CFG0_FIFOFUL_Pos (27UL) /*!< DAC DAC0CFG0: FIFOFUL (Bit 27) */ 12006 #define DAC_DAC0CFG0_FIFOFUL_Msk (0x8000000UL) /*!< DAC DAC0CFG0: FIFOFUL (Bitfield-Mask: 0x01) */ 12007 #define DAC_DAC0CFG0_SIGNEN_Pos (29UL) /*!< DAC DAC0CFG0: SIGNEN (Bit 29) */ 12008 #define DAC_DAC0CFG0_SIGNEN_Msk (0x20000000UL) /*!< DAC DAC0CFG0: SIGNEN (Bitfield-Mask: 0x01) */ 12009 #define DAC_DAC0CFG0_SREN_Pos (30UL) /*!< DAC DAC0CFG0: SREN (Bit 30) */ 12010 #define DAC_DAC0CFG0_SREN_Msk (0x40000000UL) /*!< DAC DAC0CFG0: SREN (Bitfield-Mask: 0x01) */ 12011 #define DAC_DAC0CFG0_RUN_Pos (31UL) /*!< DAC DAC0CFG0: RUN (Bit 31) */ 12012 #define DAC_DAC0CFG0_RUN_Msk (0x80000000UL) /*!< DAC DAC0CFG0: RUN (Bitfield-Mask: 0x01) */ 12013 12014 /* -------------------------------- DAC_DAC0CFG1 -------------------------------- */ 12015 #define DAC_DAC0CFG1_SCALE_Pos (0UL) /*!< DAC DAC0CFG1: SCALE (Bit 0) */ 12016 #define DAC_DAC0CFG1_SCALE_Msk (0x7UL) /*!< DAC DAC0CFG1: SCALE (Bitfield-Mask: 0x07) */ 12017 #define DAC_DAC0CFG1_MULDIV_Pos (3UL) /*!< DAC DAC0CFG1: MULDIV (Bit 3) */ 12018 #define DAC_DAC0CFG1_MULDIV_Msk (0x8UL) /*!< DAC DAC0CFG1: MULDIV (Bitfield-Mask: 0x01) */ 12019 #define DAC_DAC0CFG1_OFFS_Pos (4UL) /*!< DAC DAC0CFG1: OFFS (Bit 4) */ 12020 #define DAC_DAC0CFG1_OFFS_Msk (0xff0UL) /*!< DAC DAC0CFG1: OFFS (Bitfield-Mask: 0xff) */ 12021 #define DAC_DAC0CFG1_TRIGSEL_Pos (12UL) /*!< DAC DAC0CFG1: TRIGSEL (Bit 12) */ 12022 #define DAC_DAC0CFG1_TRIGSEL_Msk (0x7000UL) /*!< DAC DAC0CFG1: TRIGSEL (Bitfield-Mask: 0x07) */ 12023 #define DAC_DAC0CFG1_DATMOD_Pos (15UL) /*!< DAC DAC0CFG1: DATMOD (Bit 15) */ 12024 #define DAC_DAC0CFG1_DATMOD_Msk (0x8000UL) /*!< DAC DAC0CFG1: DATMOD (Bitfield-Mask: 0x01) */ 12025 #define DAC_DAC0CFG1_SWTRIG_Pos (16UL) /*!< DAC DAC0CFG1: SWTRIG (Bit 16) */ 12026 #define DAC_DAC0CFG1_SWTRIG_Msk (0x10000UL) /*!< DAC DAC0CFG1: SWTRIG (Bitfield-Mask: 0x01) */ 12027 #define DAC_DAC0CFG1_TRIGMOD_Pos (17UL) /*!< DAC DAC0CFG1: TRIGMOD (Bit 17) */ 12028 #define DAC_DAC0CFG1_TRIGMOD_Msk (0x60000UL) /*!< DAC DAC0CFG1: TRIGMOD (Bitfield-Mask: 0x03) */ 12029 #define DAC_DAC0CFG1_ANACFG_Pos (19UL) /*!< DAC DAC0CFG1: ANACFG (Bit 19) */ 12030 #define DAC_DAC0CFG1_ANACFG_Msk (0xf80000UL) /*!< DAC DAC0CFG1: ANACFG (Bitfield-Mask: 0x1f) */ 12031 #define DAC_DAC0CFG1_ANAEN_Pos (24UL) /*!< DAC DAC0CFG1: ANAEN (Bit 24) */ 12032 #define DAC_DAC0CFG1_ANAEN_Msk (0x1000000UL) /*!< DAC DAC0CFG1: ANAEN (Bitfield-Mask: 0x01) */ 12033 #define DAC_DAC0CFG1_REFCFGL_Pos (28UL) /*!< DAC DAC0CFG1: REFCFGL (Bit 28) */ 12034 #define DAC_DAC0CFG1_REFCFGL_Msk (0xf0000000UL) /*!< DAC DAC0CFG1: REFCFGL (Bitfield-Mask: 0x0f) */ 12035 12036 /* -------------------------------- DAC_DAC1CFG0 -------------------------------- */ 12037 #define DAC_DAC1CFG0_FREQ_Pos (0UL) /*!< DAC DAC1CFG0: FREQ (Bit 0) */ 12038 #define DAC_DAC1CFG0_FREQ_Msk (0xfffffUL) /*!< DAC DAC1CFG0: FREQ (Bitfield-Mask: 0xfffff) */ 12039 #define DAC_DAC1CFG0_MODE_Pos (20UL) /*!< DAC DAC1CFG0: MODE (Bit 20) */ 12040 #define DAC_DAC1CFG0_MODE_Msk (0x700000UL) /*!< DAC DAC1CFG0: MODE (Bitfield-Mask: 0x07) */ 12041 #define DAC_DAC1CFG0_SIGN_Pos (23UL) /*!< DAC DAC1CFG0: SIGN (Bit 23) */ 12042 #define DAC_DAC1CFG0_SIGN_Msk (0x800000UL) /*!< DAC DAC1CFG0: SIGN (Bitfield-Mask: 0x01) */ 12043 #define DAC_DAC1CFG0_FIFOIND_Pos (24UL) /*!< DAC DAC1CFG0: FIFOIND (Bit 24) */ 12044 #define DAC_DAC1CFG0_FIFOIND_Msk (0x3000000UL) /*!< DAC DAC1CFG0: FIFOIND (Bitfield-Mask: 0x03) */ 12045 #define DAC_DAC1CFG0_FIFOEMP_Pos (26UL) /*!< DAC DAC1CFG0: FIFOEMP (Bit 26) */ 12046 #define DAC_DAC1CFG0_FIFOEMP_Msk (0x4000000UL) /*!< DAC DAC1CFG0: FIFOEMP (Bitfield-Mask: 0x01) */ 12047 #define DAC_DAC1CFG0_FIFOFUL_Pos (27UL) /*!< DAC DAC1CFG0: FIFOFUL (Bit 27) */ 12048 #define DAC_DAC1CFG0_FIFOFUL_Msk (0x8000000UL) /*!< DAC DAC1CFG0: FIFOFUL (Bitfield-Mask: 0x01) */ 12049 #define DAC_DAC1CFG0_SIGNEN_Pos (29UL) /*!< DAC DAC1CFG0: SIGNEN (Bit 29) */ 12050 #define DAC_DAC1CFG0_SIGNEN_Msk (0x20000000UL) /*!< DAC DAC1CFG0: SIGNEN (Bitfield-Mask: 0x01) */ 12051 #define DAC_DAC1CFG0_SREN_Pos (30UL) /*!< DAC DAC1CFG0: SREN (Bit 30) */ 12052 #define DAC_DAC1CFG0_SREN_Msk (0x40000000UL) /*!< DAC DAC1CFG0: SREN (Bitfield-Mask: 0x01) */ 12053 #define DAC_DAC1CFG0_RUN_Pos (31UL) /*!< DAC DAC1CFG0: RUN (Bit 31) */ 12054 #define DAC_DAC1CFG0_RUN_Msk (0x80000000UL) /*!< DAC DAC1CFG0: RUN (Bitfield-Mask: 0x01) */ 12055 12056 /* -------------------------------- DAC_DAC1CFG1 -------------------------------- */ 12057 #define DAC_DAC1CFG1_SCALE_Pos (0UL) /*!< DAC DAC1CFG1: SCALE (Bit 0) */ 12058 #define DAC_DAC1CFG1_SCALE_Msk (0x7UL) /*!< DAC DAC1CFG1: SCALE (Bitfield-Mask: 0x07) */ 12059 #define DAC_DAC1CFG1_MULDIV_Pos (3UL) /*!< DAC DAC1CFG1: MULDIV (Bit 3) */ 12060 #define DAC_DAC1CFG1_MULDIV_Msk (0x8UL) /*!< DAC DAC1CFG1: MULDIV (Bitfield-Mask: 0x01) */ 12061 #define DAC_DAC1CFG1_OFFS_Pos (4UL) /*!< DAC DAC1CFG1: OFFS (Bit 4) */ 12062 #define DAC_DAC1CFG1_OFFS_Msk (0xff0UL) /*!< DAC DAC1CFG1: OFFS (Bitfield-Mask: 0xff) */ 12063 #define DAC_DAC1CFG1_TRIGSEL_Pos (12UL) /*!< DAC DAC1CFG1: TRIGSEL (Bit 12) */ 12064 #define DAC_DAC1CFG1_TRIGSEL_Msk (0x7000UL) /*!< DAC DAC1CFG1: TRIGSEL (Bitfield-Mask: 0x07) */ 12065 #define DAC_DAC1CFG1_SWTRIG_Pos (16UL) /*!< DAC DAC1CFG1: SWTRIG (Bit 16) */ 12066 #define DAC_DAC1CFG1_SWTRIG_Msk (0x10000UL) /*!< DAC DAC1CFG1: SWTRIG (Bitfield-Mask: 0x01) */ 12067 #define DAC_DAC1CFG1_TRIGMOD_Pos (17UL) /*!< DAC DAC1CFG1: TRIGMOD (Bit 17) */ 12068 #define DAC_DAC1CFG1_TRIGMOD_Msk (0x60000UL) /*!< DAC DAC1CFG1: TRIGMOD (Bitfield-Mask: 0x03) */ 12069 #define DAC_DAC1CFG1_ANACFG_Pos (19UL) /*!< DAC DAC1CFG1: ANACFG (Bit 19) */ 12070 #define DAC_DAC1CFG1_ANACFG_Msk (0xf80000UL) /*!< DAC DAC1CFG1: ANACFG (Bitfield-Mask: 0x1f) */ 12071 #define DAC_DAC1CFG1_ANAEN_Pos (24UL) /*!< DAC DAC1CFG1: ANAEN (Bit 24) */ 12072 #define DAC_DAC1CFG1_ANAEN_Msk (0x1000000UL) /*!< DAC DAC1CFG1: ANAEN (Bitfield-Mask: 0x01) */ 12073 #define DAC_DAC1CFG1_REFCFGH_Pos (28UL) /*!< DAC DAC1CFG1: REFCFGH (Bit 28) */ 12074 #define DAC_DAC1CFG1_REFCFGH_Msk (0xf0000000UL) /*!< DAC DAC1CFG1: REFCFGH (Bitfield-Mask: 0x0f) */ 12075 12076 /* -------------------------------- DAC_DAC0DATA -------------------------------- */ 12077 #define DAC_DAC0DATA_DATA0_Pos (0UL) /*!< DAC DAC0DATA: DATA0 (Bit 0) */ 12078 #define DAC_DAC0DATA_DATA0_Msk (0xfffUL) /*!< DAC DAC0DATA: DATA0 (Bitfield-Mask: 0xfff) */ 12079 12080 /* -------------------------------- DAC_DAC1DATA -------------------------------- */ 12081 #define DAC_DAC1DATA_DATA1_Pos (0UL) /*!< DAC DAC1DATA: DATA1 (Bit 0) */ 12082 #define DAC_DAC1DATA_DATA1_Msk (0xfffUL) /*!< DAC DAC1DATA: DATA1 (Bitfield-Mask: 0xfff) */ 12083 12084 /* -------------------------------- DAC_DAC01DATA ------------------------------- */ 12085 #define DAC_DAC01DATA_DATA0_Pos (0UL) /*!< DAC DAC01DATA: DATA0 (Bit 0) */ 12086 #define DAC_DAC01DATA_DATA0_Msk (0xfffUL) /*!< DAC DAC01DATA: DATA0 (Bitfield-Mask: 0xfff) */ 12087 #define DAC_DAC01DATA_DATA1_Pos (16UL) /*!< DAC DAC01DATA: DATA1 (Bit 16) */ 12088 #define DAC_DAC01DATA_DATA1_Msk (0xfff0000UL) /*!< DAC DAC01DATA: DATA1 (Bitfield-Mask: 0xfff) */ 12089 12090 /* -------------------------------- DAC_DAC0PATL -------------------------------- */ 12091 #define DAC_DAC0PATL_PAT0_Pos (0UL) /*!< DAC DAC0PATL: PAT0 (Bit 0) */ 12092 #define DAC_DAC0PATL_PAT0_Msk (0x1fUL) /*!< DAC DAC0PATL: PAT0 (Bitfield-Mask: 0x1f) */ 12093 #define DAC_DAC0PATL_PAT1_Pos (5UL) /*!< DAC DAC0PATL: PAT1 (Bit 5) */ 12094 #define DAC_DAC0PATL_PAT1_Msk (0x3e0UL) /*!< DAC DAC0PATL: PAT1 (Bitfield-Mask: 0x1f) */ 12095 #define DAC_DAC0PATL_PAT2_Pos (10UL) /*!< DAC DAC0PATL: PAT2 (Bit 10) */ 12096 #define DAC_DAC0PATL_PAT2_Msk (0x7c00UL) /*!< DAC DAC0PATL: PAT2 (Bitfield-Mask: 0x1f) */ 12097 #define DAC_DAC0PATL_PAT3_Pos (15UL) /*!< DAC DAC0PATL: PAT3 (Bit 15) */ 12098 #define DAC_DAC0PATL_PAT3_Msk (0xf8000UL) /*!< DAC DAC0PATL: PAT3 (Bitfield-Mask: 0x1f) */ 12099 #define DAC_DAC0PATL_PAT4_Pos (20UL) /*!< DAC DAC0PATL: PAT4 (Bit 20) */ 12100 #define DAC_DAC0PATL_PAT4_Msk (0x1f00000UL) /*!< DAC DAC0PATL: PAT4 (Bitfield-Mask: 0x1f) */ 12101 #define DAC_DAC0PATL_PAT5_Pos (25UL) /*!< DAC DAC0PATL: PAT5 (Bit 25) */ 12102 #define DAC_DAC0PATL_PAT5_Msk (0x3e000000UL) /*!< DAC DAC0PATL: PAT5 (Bitfield-Mask: 0x1f) */ 12103 12104 /* -------------------------------- DAC_DAC0PATH -------------------------------- */ 12105 #define DAC_DAC0PATH_PAT6_Pos (0UL) /*!< DAC DAC0PATH: PAT6 (Bit 0) */ 12106 #define DAC_DAC0PATH_PAT6_Msk (0x1fUL) /*!< DAC DAC0PATH: PAT6 (Bitfield-Mask: 0x1f) */ 12107 #define DAC_DAC0PATH_PAT7_Pos (5UL) /*!< DAC DAC0PATH: PAT7 (Bit 5) */ 12108 #define DAC_DAC0PATH_PAT7_Msk (0x3e0UL) /*!< DAC DAC0PATH: PAT7 (Bitfield-Mask: 0x1f) */ 12109 #define DAC_DAC0PATH_PAT8_Pos (10UL) /*!< DAC DAC0PATH: PAT8 (Bit 10) */ 12110 #define DAC_DAC0PATH_PAT8_Msk (0x7c00UL) /*!< DAC DAC0PATH: PAT8 (Bitfield-Mask: 0x1f) */ 12111 12112 /* -------------------------------- DAC_DAC1PATL -------------------------------- */ 12113 #define DAC_DAC1PATL_PAT0_Pos (0UL) /*!< DAC DAC1PATL: PAT0 (Bit 0) */ 12114 #define DAC_DAC1PATL_PAT0_Msk (0x1fUL) /*!< DAC DAC1PATL: PAT0 (Bitfield-Mask: 0x1f) */ 12115 #define DAC_DAC1PATL_PAT1_Pos (5UL) /*!< DAC DAC1PATL: PAT1 (Bit 5) */ 12116 #define DAC_DAC1PATL_PAT1_Msk (0x3e0UL) /*!< DAC DAC1PATL: PAT1 (Bitfield-Mask: 0x1f) */ 12117 #define DAC_DAC1PATL_PAT2_Pos (10UL) /*!< DAC DAC1PATL: PAT2 (Bit 10) */ 12118 #define DAC_DAC1PATL_PAT2_Msk (0x7c00UL) /*!< DAC DAC1PATL: PAT2 (Bitfield-Mask: 0x1f) */ 12119 #define DAC_DAC1PATL_PAT3_Pos (15UL) /*!< DAC DAC1PATL: PAT3 (Bit 15) */ 12120 #define DAC_DAC1PATL_PAT3_Msk (0xf8000UL) /*!< DAC DAC1PATL: PAT3 (Bitfield-Mask: 0x1f) */ 12121 #define DAC_DAC1PATL_PAT4_Pos (20UL) /*!< DAC DAC1PATL: PAT4 (Bit 20) */ 12122 #define DAC_DAC1PATL_PAT4_Msk (0x1f00000UL) /*!< DAC DAC1PATL: PAT4 (Bitfield-Mask: 0x1f) */ 12123 #define DAC_DAC1PATL_PAT5_Pos (25UL) /*!< DAC DAC1PATL: PAT5 (Bit 25) */ 12124 #define DAC_DAC1PATL_PAT5_Msk (0x3e000000UL) /*!< DAC DAC1PATL: PAT5 (Bitfield-Mask: 0x1f) */ 12125 12126 /* -------------------------------- DAC_DAC1PATH -------------------------------- */ 12127 #define DAC_DAC1PATH_PAT6_Pos (0UL) /*!< DAC DAC1PATH: PAT6 (Bit 0) */ 12128 #define DAC_DAC1PATH_PAT6_Msk (0x1fUL) /*!< DAC DAC1PATH: PAT6 (Bitfield-Mask: 0x1f) */ 12129 #define DAC_DAC1PATH_PAT7_Pos (5UL) /*!< DAC DAC1PATH: PAT7 (Bit 5) */ 12130 #define DAC_DAC1PATH_PAT7_Msk (0x3e0UL) /*!< DAC DAC1PATH: PAT7 (Bitfield-Mask: 0x1f) */ 12131 #define DAC_DAC1PATH_PAT8_Pos (10UL) /*!< DAC DAC1PATH: PAT8 (Bit 10) */ 12132 #define DAC_DAC1PATH_PAT8_Msk (0x7c00UL) /*!< DAC DAC1PATH: PAT8 (Bitfield-Mask: 0x1f) */ 12133 12134 12135 /* ================================================================================ */ 12136 /* ================ Group 'CCU4' Position & Mask ================ */ 12137 /* ================================================================================ */ 12138 12139 12140 /* --------------------------------- CCU4_GCTRL --------------------------------- */ 12141 #define CCU4_GCTRL_PRBC_Pos (0UL) /*!< CCU4 GCTRL: PRBC (Bit 0) */ 12142 #define CCU4_GCTRL_PRBC_Msk (0x7UL) /*!< CCU4 GCTRL: PRBC (Bitfield-Mask: 0x07) */ 12143 #define CCU4_GCTRL_PCIS_Pos (4UL) /*!< CCU4 GCTRL: PCIS (Bit 4) */ 12144 #define CCU4_GCTRL_PCIS_Msk (0x30UL) /*!< CCU4 GCTRL: PCIS (Bitfield-Mask: 0x03) */ 12145 #define CCU4_GCTRL_SUSCFG_Pos (8UL) /*!< CCU4 GCTRL: SUSCFG (Bit 8) */ 12146 #define CCU4_GCTRL_SUSCFG_Msk (0x300UL) /*!< CCU4 GCTRL: SUSCFG (Bitfield-Mask: 0x03) */ 12147 #define CCU4_GCTRL_MSE0_Pos (10UL) /*!< CCU4 GCTRL: MSE0 (Bit 10) */ 12148 #define CCU4_GCTRL_MSE0_Msk (0x400UL) /*!< CCU4 GCTRL: MSE0 (Bitfield-Mask: 0x01) */ 12149 #define CCU4_GCTRL_MSE1_Pos (11UL) /*!< CCU4 GCTRL: MSE1 (Bit 11) */ 12150 #define CCU4_GCTRL_MSE1_Msk (0x800UL) /*!< CCU4 GCTRL: MSE1 (Bitfield-Mask: 0x01) */ 12151 #define CCU4_GCTRL_MSE2_Pos (12UL) /*!< CCU4 GCTRL: MSE2 (Bit 12) */ 12152 #define CCU4_GCTRL_MSE2_Msk (0x1000UL) /*!< CCU4 GCTRL: MSE2 (Bitfield-Mask: 0x01) */ 12153 #define CCU4_GCTRL_MSE3_Pos (13UL) /*!< CCU4 GCTRL: MSE3 (Bit 13) */ 12154 #define CCU4_GCTRL_MSE3_Msk (0x2000UL) /*!< CCU4 GCTRL: MSE3 (Bitfield-Mask: 0x01) */ 12155 #define CCU4_GCTRL_MSDE_Pos (14UL) /*!< CCU4 GCTRL: MSDE (Bit 14) */ 12156 #define CCU4_GCTRL_MSDE_Msk (0xc000UL) /*!< CCU4 GCTRL: MSDE (Bitfield-Mask: 0x03) */ 12157 12158 /* --------------------------------- CCU4_GSTAT --------------------------------- */ 12159 #define CCU4_GSTAT_S0I_Pos (0UL) /*!< CCU4 GSTAT: S0I (Bit 0) */ 12160 #define CCU4_GSTAT_S0I_Msk (0x1UL) /*!< CCU4 GSTAT: S0I (Bitfield-Mask: 0x01) */ 12161 #define CCU4_GSTAT_S1I_Pos (1UL) /*!< CCU4 GSTAT: S1I (Bit 1) */ 12162 #define CCU4_GSTAT_S1I_Msk (0x2UL) /*!< CCU4 GSTAT: S1I (Bitfield-Mask: 0x01) */ 12163 #define CCU4_GSTAT_S2I_Pos (2UL) /*!< CCU4 GSTAT: S2I (Bit 2) */ 12164 #define CCU4_GSTAT_S2I_Msk (0x4UL) /*!< CCU4 GSTAT: S2I (Bitfield-Mask: 0x01) */ 12165 #define CCU4_GSTAT_S3I_Pos (3UL) /*!< CCU4 GSTAT: S3I (Bit 3) */ 12166 #define CCU4_GSTAT_S3I_Msk (0x8UL) /*!< CCU4 GSTAT: S3I (Bitfield-Mask: 0x01) */ 12167 #define CCU4_GSTAT_PRB_Pos (8UL) /*!< CCU4 GSTAT: PRB (Bit 8) */ 12168 #define CCU4_GSTAT_PRB_Msk (0x100UL) /*!< CCU4 GSTAT: PRB (Bitfield-Mask: 0x01) */ 12169 12170 /* --------------------------------- CCU4_GIDLS --------------------------------- */ 12171 #define CCU4_GIDLS_SS0I_Pos (0UL) /*!< CCU4 GIDLS: SS0I (Bit 0) */ 12172 #define CCU4_GIDLS_SS0I_Msk (0x1UL) /*!< CCU4 GIDLS: SS0I (Bitfield-Mask: 0x01) */ 12173 #define CCU4_GIDLS_SS1I_Pos (1UL) /*!< CCU4 GIDLS: SS1I (Bit 1) */ 12174 #define CCU4_GIDLS_SS1I_Msk (0x2UL) /*!< CCU4 GIDLS: SS1I (Bitfield-Mask: 0x01) */ 12175 #define CCU4_GIDLS_SS2I_Pos (2UL) /*!< CCU4 GIDLS: SS2I (Bit 2) */ 12176 #define CCU4_GIDLS_SS2I_Msk (0x4UL) /*!< CCU4 GIDLS: SS2I (Bitfield-Mask: 0x01) */ 12177 #define CCU4_GIDLS_SS3I_Pos (3UL) /*!< CCU4 GIDLS: SS3I (Bit 3) */ 12178 #define CCU4_GIDLS_SS3I_Msk (0x8UL) /*!< CCU4 GIDLS: SS3I (Bitfield-Mask: 0x01) */ 12179 #define CCU4_GIDLS_CPRB_Pos (8UL) /*!< CCU4 GIDLS: CPRB (Bit 8) */ 12180 #define CCU4_GIDLS_CPRB_Msk (0x100UL) /*!< CCU4 GIDLS: CPRB (Bitfield-Mask: 0x01) */ 12181 #define CCU4_GIDLS_PSIC_Pos (9UL) /*!< CCU4 GIDLS: PSIC (Bit 9) */ 12182 #define CCU4_GIDLS_PSIC_Msk (0x200UL) /*!< CCU4 GIDLS: PSIC (Bitfield-Mask: 0x01) */ 12183 12184 /* --------------------------------- CCU4_GIDLC --------------------------------- */ 12185 #define CCU4_GIDLC_CS0I_Pos (0UL) /*!< CCU4 GIDLC: CS0I (Bit 0) */ 12186 #define CCU4_GIDLC_CS0I_Msk (0x1UL) /*!< CCU4 GIDLC: CS0I (Bitfield-Mask: 0x01) */ 12187 #define CCU4_GIDLC_CS1I_Pos (1UL) /*!< CCU4 GIDLC: CS1I (Bit 1) */ 12188 #define CCU4_GIDLC_CS1I_Msk (0x2UL) /*!< CCU4 GIDLC: CS1I (Bitfield-Mask: 0x01) */ 12189 #define CCU4_GIDLC_CS2I_Pos (2UL) /*!< CCU4 GIDLC: CS2I (Bit 2) */ 12190 #define CCU4_GIDLC_CS2I_Msk (0x4UL) /*!< CCU4 GIDLC: CS2I (Bitfield-Mask: 0x01) */ 12191 #define CCU4_GIDLC_CS3I_Pos (3UL) /*!< CCU4 GIDLC: CS3I (Bit 3) */ 12192 #define CCU4_GIDLC_CS3I_Msk (0x8UL) /*!< CCU4 GIDLC: CS3I (Bitfield-Mask: 0x01) */ 12193 #define CCU4_GIDLC_SPRB_Pos (8UL) /*!< CCU4 GIDLC: SPRB (Bit 8) */ 12194 #define CCU4_GIDLC_SPRB_Msk (0x100UL) /*!< CCU4 GIDLC: SPRB (Bitfield-Mask: 0x01) */ 12195 12196 /* ---------------------------------- CCU4_GCSS --------------------------------- */ 12197 #define CCU4_GCSS_S0SE_Pos (0UL) /*!< CCU4 GCSS: S0SE (Bit 0) */ 12198 #define CCU4_GCSS_S0SE_Msk (0x1UL) /*!< CCU4 GCSS: S0SE (Bitfield-Mask: 0x01) */ 12199 #define CCU4_GCSS_S0DSE_Pos (1UL) /*!< CCU4 GCSS: S0DSE (Bit 1) */ 12200 #define CCU4_GCSS_S0DSE_Msk (0x2UL) /*!< CCU4 GCSS: S0DSE (Bitfield-Mask: 0x01) */ 12201 #define CCU4_GCSS_S0PSE_Pos (2UL) /*!< CCU4 GCSS: S0PSE (Bit 2) */ 12202 #define CCU4_GCSS_S0PSE_Msk (0x4UL) /*!< CCU4 GCSS: S0PSE (Bitfield-Mask: 0x01) */ 12203 #define CCU4_GCSS_S1SE_Pos (4UL) /*!< CCU4 GCSS: S1SE (Bit 4) */ 12204 #define CCU4_GCSS_S1SE_Msk (0x10UL) /*!< CCU4 GCSS: S1SE (Bitfield-Mask: 0x01) */ 12205 #define CCU4_GCSS_S1DSE_Pos (5UL) /*!< CCU4 GCSS: S1DSE (Bit 5) */ 12206 #define CCU4_GCSS_S1DSE_Msk (0x20UL) /*!< CCU4 GCSS: S1DSE (Bitfield-Mask: 0x01) */ 12207 #define CCU4_GCSS_S1PSE_Pos (6UL) /*!< CCU4 GCSS: S1PSE (Bit 6) */ 12208 #define CCU4_GCSS_S1PSE_Msk (0x40UL) /*!< CCU4 GCSS: S1PSE (Bitfield-Mask: 0x01) */ 12209 #define CCU4_GCSS_S2SE_Pos (8UL) /*!< CCU4 GCSS: S2SE (Bit 8) */ 12210 #define CCU4_GCSS_S2SE_Msk (0x100UL) /*!< CCU4 GCSS: S2SE (Bitfield-Mask: 0x01) */ 12211 #define CCU4_GCSS_S2DSE_Pos (9UL) /*!< CCU4 GCSS: S2DSE (Bit 9) */ 12212 #define CCU4_GCSS_S2DSE_Msk (0x200UL) /*!< CCU4 GCSS: S2DSE (Bitfield-Mask: 0x01) */ 12213 #define CCU4_GCSS_S2PSE_Pos (10UL) /*!< CCU4 GCSS: S2PSE (Bit 10) */ 12214 #define CCU4_GCSS_S2PSE_Msk (0x400UL) /*!< CCU4 GCSS: S2PSE (Bitfield-Mask: 0x01) */ 12215 #define CCU4_GCSS_S3SE_Pos (12UL) /*!< CCU4 GCSS: S3SE (Bit 12) */ 12216 #define CCU4_GCSS_S3SE_Msk (0x1000UL) /*!< CCU4 GCSS: S3SE (Bitfield-Mask: 0x01) */ 12217 #define CCU4_GCSS_S3DSE_Pos (13UL) /*!< CCU4 GCSS: S3DSE (Bit 13) */ 12218 #define CCU4_GCSS_S3DSE_Msk (0x2000UL) /*!< CCU4 GCSS: S3DSE (Bitfield-Mask: 0x01) */ 12219 #define CCU4_GCSS_S3PSE_Pos (14UL) /*!< CCU4 GCSS: S3PSE (Bit 14) */ 12220 #define CCU4_GCSS_S3PSE_Msk (0x4000UL) /*!< CCU4 GCSS: S3PSE (Bitfield-Mask: 0x01) */ 12221 #define CCU4_GCSS_S0STS_Pos (16UL) /*!< CCU4 GCSS: S0STS (Bit 16) */ 12222 #define CCU4_GCSS_S0STS_Msk (0x10000UL) /*!< CCU4 GCSS: S0STS (Bitfield-Mask: 0x01) */ 12223 #define CCU4_GCSS_S1STS_Pos (17UL) /*!< CCU4 GCSS: S1STS (Bit 17) */ 12224 #define CCU4_GCSS_S1STS_Msk (0x20000UL) /*!< CCU4 GCSS: S1STS (Bitfield-Mask: 0x01) */ 12225 #define CCU4_GCSS_S2STS_Pos (18UL) /*!< CCU4 GCSS: S2STS (Bit 18) */ 12226 #define CCU4_GCSS_S2STS_Msk (0x40000UL) /*!< CCU4 GCSS: S2STS (Bitfield-Mask: 0x01) */ 12227 #define CCU4_GCSS_S3STS_Pos (19UL) /*!< CCU4 GCSS: S3STS (Bit 19) */ 12228 #define CCU4_GCSS_S3STS_Msk (0x80000UL) /*!< CCU4 GCSS: S3STS (Bitfield-Mask: 0x01) */ 12229 12230 /* ---------------------------------- CCU4_GCSC --------------------------------- */ 12231 #define CCU4_GCSC_S0SC_Pos (0UL) /*!< CCU4 GCSC: S0SC (Bit 0) */ 12232 #define CCU4_GCSC_S0SC_Msk (0x1UL) /*!< CCU4 GCSC: S0SC (Bitfield-Mask: 0x01) */ 12233 #define CCU4_GCSC_S0DSC_Pos (1UL) /*!< CCU4 GCSC: S0DSC (Bit 1) */ 12234 #define CCU4_GCSC_S0DSC_Msk (0x2UL) /*!< CCU4 GCSC: S0DSC (Bitfield-Mask: 0x01) */ 12235 #define CCU4_GCSC_S0PSC_Pos (2UL) /*!< CCU4 GCSC: S0PSC (Bit 2) */ 12236 #define CCU4_GCSC_S0PSC_Msk (0x4UL) /*!< CCU4 GCSC: S0PSC (Bitfield-Mask: 0x01) */ 12237 #define CCU4_GCSC_S1SC_Pos (4UL) /*!< CCU4 GCSC: S1SC (Bit 4) */ 12238 #define CCU4_GCSC_S1SC_Msk (0x10UL) /*!< CCU4 GCSC: S1SC (Bitfield-Mask: 0x01) */ 12239 #define CCU4_GCSC_S1DSC_Pos (5UL) /*!< CCU4 GCSC: S1DSC (Bit 5) */ 12240 #define CCU4_GCSC_S1DSC_Msk (0x20UL) /*!< CCU4 GCSC: S1DSC (Bitfield-Mask: 0x01) */ 12241 #define CCU4_GCSC_S1PSC_Pos (6UL) /*!< CCU4 GCSC: S1PSC (Bit 6) */ 12242 #define CCU4_GCSC_S1PSC_Msk (0x40UL) /*!< CCU4 GCSC: S1PSC (Bitfield-Mask: 0x01) */ 12243 #define CCU4_GCSC_S2SC_Pos (8UL) /*!< CCU4 GCSC: S2SC (Bit 8) */ 12244 #define CCU4_GCSC_S2SC_Msk (0x100UL) /*!< CCU4 GCSC: S2SC (Bitfield-Mask: 0x01) */ 12245 #define CCU4_GCSC_S2DSC_Pos (9UL) /*!< CCU4 GCSC: S2DSC (Bit 9) */ 12246 #define CCU4_GCSC_S2DSC_Msk (0x200UL) /*!< CCU4 GCSC: S2DSC (Bitfield-Mask: 0x01) */ 12247 #define CCU4_GCSC_S2PSC_Pos (10UL) /*!< CCU4 GCSC: S2PSC (Bit 10) */ 12248 #define CCU4_GCSC_S2PSC_Msk (0x400UL) /*!< CCU4 GCSC: S2PSC (Bitfield-Mask: 0x01) */ 12249 #define CCU4_GCSC_S3SC_Pos (12UL) /*!< CCU4 GCSC: S3SC (Bit 12) */ 12250 #define CCU4_GCSC_S3SC_Msk (0x1000UL) /*!< CCU4 GCSC: S3SC (Bitfield-Mask: 0x01) */ 12251 #define CCU4_GCSC_S3DSC_Pos (13UL) /*!< CCU4 GCSC: S3DSC (Bit 13) */ 12252 #define CCU4_GCSC_S3DSC_Msk (0x2000UL) /*!< CCU4 GCSC: S3DSC (Bitfield-Mask: 0x01) */ 12253 #define CCU4_GCSC_S3PSC_Pos (14UL) /*!< CCU4 GCSC: S3PSC (Bit 14) */ 12254 #define CCU4_GCSC_S3PSC_Msk (0x4000UL) /*!< CCU4 GCSC: S3PSC (Bitfield-Mask: 0x01) */ 12255 #define CCU4_GCSC_S0STC_Pos (16UL) /*!< CCU4 GCSC: S0STC (Bit 16) */ 12256 #define CCU4_GCSC_S0STC_Msk (0x10000UL) /*!< CCU4 GCSC: S0STC (Bitfield-Mask: 0x01) */ 12257 #define CCU4_GCSC_S1STC_Pos (17UL) /*!< CCU4 GCSC: S1STC (Bit 17) */ 12258 #define CCU4_GCSC_S1STC_Msk (0x20000UL) /*!< CCU4 GCSC: S1STC (Bitfield-Mask: 0x01) */ 12259 #define CCU4_GCSC_S2STC_Pos (18UL) /*!< CCU4 GCSC: S2STC (Bit 18) */ 12260 #define CCU4_GCSC_S2STC_Msk (0x40000UL) /*!< CCU4 GCSC: S2STC (Bitfield-Mask: 0x01) */ 12261 #define CCU4_GCSC_S3STC_Pos (19UL) /*!< CCU4 GCSC: S3STC (Bit 19) */ 12262 #define CCU4_GCSC_S3STC_Msk (0x80000UL) /*!< CCU4 GCSC: S3STC (Bitfield-Mask: 0x01) */ 12263 12264 /* ---------------------------------- CCU4_GCST --------------------------------- */ 12265 #define CCU4_GCST_S0SS_Pos (0UL) /*!< CCU4 GCST: S0SS (Bit 0) */ 12266 #define CCU4_GCST_S0SS_Msk (0x1UL) /*!< CCU4 GCST: S0SS (Bitfield-Mask: 0x01) */ 12267 #define CCU4_GCST_S0DSS_Pos (1UL) /*!< CCU4 GCST: S0DSS (Bit 1) */ 12268 #define CCU4_GCST_S0DSS_Msk (0x2UL) /*!< CCU4 GCST: S0DSS (Bitfield-Mask: 0x01) */ 12269 #define CCU4_GCST_S0PSS_Pos (2UL) /*!< CCU4 GCST: S0PSS (Bit 2) */ 12270 #define CCU4_GCST_S0PSS_Msk (0x4UL) /*!< CCU4 GCST: S0PSS (Bitfield-Mask: 0x01) */ 12271 #define CCU4_GCST_S1SS_Pos (4UL) /*!< CCU4 GCST: S1SS (Bit 4) */ 12272 #define CCU4_GCST_S1SS_Msk (0x10UL) /*!< CCU4 GCST: S1SS (Bitfield-Mask: 0x01) */ 12273 #define CCU4_GCST_S1DSS_Pos (5UL) /*!< CCU4 GCST: S1DSS (Bit 5) */ 12274 #define CCU4_GCST_S1DSS_Msk (0x20UL) /*!< CCU4 GCST: S1DSS (Bitfield-Mask: 0x01) */ 12275 #define CCU4_GCST_S1PSS_Pos (6UL) /*!< CCU4 GCST: S1PSS (Bit 6) */ 12276 #define CCU4_GCST_S1PSS_Msk (0x40UL) /*!< CCU4 GCST: S1PSS (Bitfield-Mask: 0x01) */ 12277 #define CCU4_GCST_S2SS_Pos (8UL) /*!< CCU4 GCST: S2SS (Bit 8) */ 12278 #define CCU4_GCST_S2SS_Msk (0x100UL) /*!< CCU4 GCST: S2SS (Bitfield-Mask: 0x01) */ 12279 #define CCU4_GCST_S2DSS_Pos (9UL) /*!< CCU4 GCST: S2DSS (Bit 9) */ 12280 #define CCU4_GCST_S2DSS_Msk (0x200UL) /*!< CCU4 GCST: S2DSS (Bitfield-Mask: 0x01) */ 12281 #define CCU4_GCST_S2PSS_Pos (10UL) /*!< CCU4 GCST: S2PSS (Bit 10) */ 12282 #define CCU4_GCST_S2PSS_Msk (0x400UL) /*!< CCU4 GCST: S2PSS (Bitfield-Mask: 0x01) */ 12283 #define CCU4_GCST_S3SS_Pos (12UL) /*!< CCU4 GCST: S3SS (Bit 12) */ 12284 #define CCU4_GCST_S3SS_Msk (0x1000UL) /*!< CCU4 GCST: S3SS (Bitfield-Mask: 0x01) */ 12285 #define CCU4_GCST_S3DSS_Pos (13UL) /*!< CCU4 GCST: S3DSS (Bit 13) */ 12286 #define CCU4_GCST_S3DSS_Msk (0x2000UL) /*!< CCU4 GCST: S3DSS (Bitfield-Mask: 0x01) */ 12287 #define CCU4_GCST_S3PSS_Pos (14UL) /*!< CCU4 GCST: S3PSS (Bit 14) */ 12288 #define CCU4_GCST_S3PSS_Msk (0x4000UL) /*!< CCU4 GCST: S3PSS (Bitfield-Mask: 0x01) */ 12289 #define CCU4_GCST_CC40ST_Pos (16UL) /*!< CCU4 GCST: CC40ST (Bit 16) */ 12290 #define CCU4_GCST_CC40ST_Msk (0x10000UL) /*!< CCU4 GCST: CC40ST (Bitfield-Mask: 0x01) */ 12291 #define CCU4_GCST_CC41ST_Pos (17UL) /*!< CCU4 GCST: CC41ST (Bit 17) */ 12292 #define CCU4_GCST_CC41ST_Msk (0x20000UL) /*!< CCU4 GCST: CC41ST (Bitfield-Mask: 0x01) */ 12293 #define CCU4_GCST_CC42ST_Pos (18UL) /*!< CCU4 GCST: CC42ST (Bit 18) */ 12294 #define CCU4_GCST_CC42ST_Msk (0x40000UL) /*!< CCU4 GCST: CC42ST (Bitfield-Mask: 0x01) */ 12295 #define CCU4_GCST_CC43ST_Pos (19UL) /*!< CCU4 GCST: CC43ST (Bit 19) */ 12296 #define CCU4_GCST_CC43ST_Msk (0x80000UL) /*!< CCU4 GCST: CC43ST (Bitfield-Mask: 0x01) */ 12297 12298 /* ---------------------------------- CCU4_ECRD --------------------------------- */ 12299 #define CCU4_ECRD_CAPV_Pos (0UL) /*!< CCU4 ECRD: CAPV (Bit 0) */ 12300 #define CCU4_ECRD_CAPV_Msk (0xffffUL) /*!< CCU4 ECRD: CAPV (Bitfield-Mask: 0xffff) */ 12301 #define CCU4_ECRD_FPCV_Pos (16UL) /*!< CCU4 ECRD: FPCV (Bit 16) */ 12302 #define CCU4_ECRD_FPCV_Msk (0xf0000UL) /*!< CCU4 ECRD: FPCV (Bitfield-Mask: 0x0f) */ 12303 #define CCU4_ECRD_SPTR_Pos (20UL) /*!< CCU4 ECRD: SPTR (Bit 20) */ 12304 #define CCU4_ECRD_SPTR_Msk (0x300000UL) /*!< CCU4 ECRD: SPTR (Bitfield-Mask: 0x03) */ 12305 #define CCU4_ECRD_VPTR_Pos (22UL) /*!< CCU4 ECRD: VPTR (Bit 22) */ 12306 #define CCU4_ECRD_VPTR_Msk (0xc00000UL) /*!< CCU4 ECRD: VPTR (Bitfield-Mask: 0x03) */ 12307 #define CCU4_ECRD_FFL_Pos (24UL) /*!< CCU4 ECRD: FFL (Bit 24) */ 12308 #define CCU4_ECRD_FFL_Msk (0x1000000UL) /*!< CCU4 ECRD: FFL (Bitfield-Mask: 0x01) */ 12309 12310 /* ---------------------------------- CCU4_MIDR --------------------------------- */ 12311 #define CCU4_MIDR_MODR_Pos (0UL) /*!< CCU4 MIDR: MODR (Bit 0) */ 12312 #define CCU4_MIDR_MODR_Msk (0xffUL) /*!< CCU4 MIDR: MODR (Bitfield-Mask: 0xff) */ 12313 #define CCU4_MIDR_MODT_Pos (8UL) /*!< CCU4 MIDR: MODT (Bit 8) */ 12314 #define CCU4_MIDR_MODT_Msk (0xff00UL) /*!< CCU4 MIDR: MODT (Bitfield-Mask: 0xff) */ 12315 #define CCU4_MIDR_MODN_Pos (16UL) /*!< CCU4 MIDR: MODN (Bit 16) */ 12316 #define CCU4_MIDR_MODN_Msk (0xffff0000UL) /*!< CCU4 MIDR: MODN (Bitfield-Mask: 0xffff) */ 12317 12318 12319 /* ================================================================================ */ 12320 /* ================ Group 'CCU4_CC4' Position & Mask ================ */ 12321 /* ================================================================================ */ 12322 12323 12324 /* -------------------------------- CCU4_CC4_INS -------------------------------- */ 12325 #define CCU4_CC4_INS_EV0IS_Pos (0UL) /*!< CCU4_CC4 INS: EV0IS (Bit 0) */ 12326 #define CCU4_CC4_INS_EV0IS_Msk (0xfUL) /*!< CCU4_CC4 INS: EV0IS (Bitfield-Mask: 0x0f) */ 12327 #define CCU4_CC4_INS_EV1IS_Pos (4UL) /*!< CCU4_CC4 INS: EV1IS (Bit 4) */ 12328 #define CCU4_CC4_INS_EV1IS_Msk (0xf0UL) /*!< CCU4_CC4 INS: EV1IS (Bitfield-Mask: 0x0f) */ 12329 #define CCU4_CC4_INS_EV2IS_Pos (8UL) /*!< CCU4_CC4 INS: EV2IS (Bit 8) */ 12330 #define CCU4_CC4_INS_EV2IS_Msk (0xf00UL) /*!< CCU4_CC4 INS: EV2IS (Bitfield-Mask: 0x0f) */ 12331 #define CCU4_CC4_INS_EV0EM_Pos (16UL) /*!< CCU4_CC4 INS: EV0EM (Bit 16) */ 12332 #define CCU4_CC4_INS_EV0EM_Msk (0x30000UL) /*!< CCU4_CC4 INS: EV0EM (Bitfield-Mask: 0x03) */ 12333 #define CCU4_CC4_INS_EV1EM_Pos (18UL) /*!< CCU4_CC4 INS: EV1EM (Bit 18) */ 12334 #define CCU4_CC4_INS_EV1EM_Msk (0xc0000UL) /*!< CCU4_CC4 INS: EV1EM (Bitfield-Mask: 0x03) */ 12335 #define CCU4_CC4_INS_EV2EM_Pos (20UL) /*!< CCU4_CC4 INS: EV2EM (Bit 20) */ 12336 #define CCU4_CC4_INS_EV2EM_Msk (0x300000UL) /*!< CCU4_CC4 INS: EV2EM (Bitfield-Mask: 0x03) */ 12337 #define CCU4_CC4_INS_EV0LM_Pos (22UL) /*!< CCU4_CC4 INS: EV0LM (Bit 22) */ 12338 #define CCU4_CC4_INS_EV0LM_Msk (0x400000UL) /*!< CCU4_CC4 INS: EV0LM (Bitfield-Mask: 0x01) */ 12339 #define CCU4_CC4_INS_EV1LM_Pos (23UL) /*!< CCU4_CC4 INS: EV1LM (Bit 23) */ 12340 #define CCU4_CC4_INS_EV1LM_Msk (0x800000UL) /*!< CCU4_CC4 INS: EV1LM (Bitfield-Mask: 0x01) */ 12341 #define CCU4_CC4_INS_EV2LM_Pos (24UL) /*!< CCU4_CC4 INS: EV2LM (Bit 24) */ 12342 #define CCU4_CC4_INS_EV2LM_Msk (0x1000000UL) /*!< CCU4_CC4 INS: EV2LM (Bitfield-Mask: 0x01) */ 12343 #define CCU4_CC4_INS_LPF0M_Pos (25UL) /*!< CCU4_CC4 INS: LPF0M (Bit 25) */ 12344 #define CCU4_CC4_INS_LPF0M_Msk (0x6000000UL) /*!< CCU4_CC4 INS: LPF0M (Bitfield-Mask: 0x03) */ 12345 #define CCU4_CC4_INS_LPF1M_Pos (27UL) /*!< CCU4_CC4 INS: LPF1M (Bit 27) */ 12346 #define CCU4_CC4_INS_LPF1M_Msk (0x18000000UL) /*!< CCU4_CC4 INS: LPF1M (Bitfield-Mask: 0x03) */ 12347 #define CCU4_CC4_INS_LPF2M_Pos (29UL) /*!< CCU4_CC4 INS: LPF2M (Bit 29) */ 12348 #define CCU4_CC4_INS_LPF2M_Msk (0x60000000UL) /*!< CCU4_CC4 INS: LPF2M (Bitfield-Mask: 0x03) */ 12349 12350 /* -------------------------------- CCU4_CC4_CMC -------------------------------- */ 12351 #define CCU4_CC4_CMC_STRTS_Pos (0UL) /*!< CCU4_CC4 CMC: STRTS (Bit 0) */ 12352 #define CCU4_CC4_CMC_STRTS_Msk (0x3UL) /*!< CCU4_CC4 CMC: STRTS (Bitfield-Mask: 0x03) */ 12353 #define CCU4_CC4_CMC_ENDS_Pos (2UL) /*!< CCU4_CC4 CMC: ENDS (Bit 2) */ 12354 #define CCU4_CC4_CMC_ENDS_Msk (0xcUL) /*!< CCU4_CC4 CMC: ENDS (Bitfield-Mask: 0x03) */ 12355 #define CCU4_CC4_CMC_CAP0S_Pos (4UL) /*!< CCU4_CC4 CMC: CAP0S (Bit 4) */ 12356 #define CCU4_CC4_CMC_CAP0S_Msk (0x30UL) /*!< CCU4_CC4 CMC: CAP0S (Bitfield-Mask: 0x03) */ 12357 #define CCU4_CC4_CMC_CAP1S_Pos (6UL) /*!< CCU4_CC4 CMC: CAP1S (Bit 6) */ 12358 #define CCU4_CC4_CMC_CAP1S_Msk (0xc0UL) /*!< CCU4_CC4 CMC: CAP1S (Bitfield-Mask: 0x03) */ 12359 #define CCU4_CC4_CMC_GATES_Pos (8UL) /*!< CCU4_CC4 CMC: GATES (Bit 8) */ 12360 #define CCU4_CC4_CMC_GATES_Msk (0x300UL) /*!< CCU4_CC4 CMC: GATES (Bitfield-Mask: 0x03) */ 12361 #define CCU4_CC4_CMC_UDS_Pos (10UL) /*!< CCU4_CC4 CMC: UDS (Bit 10) */ 12362 #define CCU4_CC4_CMC_UDS_Msk (0xc00UL) /*!< CCU4_CC4 CMC: UDS (Bitfield-Mask: 0x03) */ 12363 #define CCU4_CC4_CMC_LDS_Pos (12UL) /*!< CCU4_CC4 CMC: LDS (Bit 12) */ 12364 #define CCU4_CC4_CMC_LDS_Msk (0x3000UL) /*!< CCU4_CC4 CMC: LDS (Bitfield-Mask: 0x03) */ 12365 #define CCU4_CC4_CMC_CNTS_Pos (14UL) /*!< CCU4_CC4 CMC: CNTS (Bit 14) */ 12366 #define CCU4_CC4_CMC_CNTS_Msk (0xc000UL) /*!< CCU4_CC4 CMC: CNTS (Bitfield-Mask: 0x03) */ 12367 #define CCU4_CC4_CMC_OFS_Pos (16UL) /*!< CCU4_CC4 CMC: OFS (Bit 16) */ 12368 #define CCU4_CC4_CMC_OFS_Msk (0x10000UL) /*!< CCU4_CC4 CMC: OFS (Bitfield-Mask: 0x01) */ 12369 #define CCU4_CC4_CMC_TS_Pos (17UL) /*!< CCU4_CC4 CMC: TS (Bit 17) */ 12370 #define CCU4_CC4_CMC_TS_Msk (0x20000UL) /*!< CCU4_CC4 CMC: TS (Bitfield-Mask: 0x01) */ 12371 #define CCU4_CC4_CMC_MOS_Pos (18UL) /*!< CCU4_CC4 CMC: MOS (Bit 18) */ 12372 #define CCU4_CC4_CMC_MOS_Msk (0xc0000UL) /*!< CCU4_CC4 CMC: MOS (Bitfield-Mask: 0x03) */ 12373 #define CCU4_CC4_CMC_TCE_Pos (20UL) /*!< CCU4_CC4 CMC: TCE (Bit 20) */ 12374 #define CCU4_CC4_CMC_TCE_Msk (0x100000UL) /*!< CCU4_CC4 CMC: TCE (Bitfield-Mask: 0x01) */ 12375 12376 /* -------------------------------- CCU4_CC4_TCST ------------------------------- */ 12377 #define CCU4_CC4_TCST_TRB_Pos (0UL) /*!< CCU4_CC4 TCST: TRB (Bit 0) */ 12378 #define CCU4_CC4_TCST_TRB_Msk (0x1UL) /*!< CCU4_CC4 TCST: TRB (Bitfield-Mask: 0x01) */ 12379 #define CCU4_CC4_TCST_CDIR_Pos (1UL) /*!< CCU4_CC4 TCST: CDIR (Bit 1) */ 12380 #define CCU4_CC4_TCST_CDIR_Msk (0x2UL) /*!< CCU4_CC4 TCST: CDIR (Bitfield-Mask: 0x01) */ 12381 12382 /* ------------------------------- CCU4_CC4_TCSET ------------------------------- */ 12383 #define CCU4_CC4_TCSET_TRBS_Pos (0UL) /*!< CCU4_CC4 TCSET: TRBS (Bit 0) */ 12384 #define CCU4_CC4_TCSET_TRBS_Msk (0x1UL) /*!< CCU4_CC4 TCSET: TRBS (Bitfield-Mask: 0x01) */ 12385 12386 /* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */ 12387 #define CCU4_CC4_TCCLR_TRBC_Pos (0UL) /*!< CCU4_CC4 TCCLR: TRBC (Bit 0) */ 12388 #define CCU4_CC4_TCCLR_TRBC_Msk (0x1UL) /*!< CCU4_CC4 TCCLR: TRBC (Bitfield-Mask: 0x01) */ 12389 #define CCU4_CC4_TCCLR_TCC_Pos (1UL) /*!< CCU4_CC4 TCCLR: TCC (Bit 1) */ 12390 #define CCU4_CC4_TCCLR_TCC_Msk (0x2UL) /*!< CCU4_CC4 TCCLR: TCC (Bitfield-Mask: 0x01) */ 12391 #define CCU4_CC4_TCCLR_DITC_Pos (2UL) /*!< CCU4_CC4 TCCLR: DITC (Bit 2) */ 12392 #define CCU4_CC4_TCCLR_DITC_Msk (0x4UL) /*!< CCU4_CC4 TCCLR: DITC (Bitfield-Mask: 0x01) */ 12393 12394 /* --------------------------------- CCU4_CC4_TC -------------------------------- */ 12395 #define CCU4_CC4_TC_TCM_Pos (0UL) /*!< CCU4_CC4 TC: TCM (Bit 0) */ 12396 #define CCU4_CC4_TC_TCM_Msk (0x1UL) /*!< CCU4_CC4 TC: TCM (Bitfield-Mask: 0x01) */ 12397 #define CCU4_CC4_TC_TSSM_Pos (1UL) /*!< CCU4_CC4 TC: TSSM (Bit 1) */ 12398 #define CCU4_CC4_TC_TSSM_Msk (0x2UL) /*!< CCU4_CC4 TC: TSSM (Bitfield-Mask: 0x01) */ 12399 #define CCU4_CC4_TC_CLST_Pos (2UL) /*!< CCU4_CC4 TC: CLST (Bit 2) */ 12400 #define CCU4_CC4_TC_CLST_Msk (0x4UL) /*!< CCU4_CC4 TC: CLST (Bitfield-Mask: 0x01) */ 12401 #define CCU4_CC4_TC_CMOD_Pos (3UL) /*!< CCU4_CC4 TC: CMOD (Bit 3) */ 12402 #define CCU4_CC4_TC_CMOD_Msk (0x8UL) /*!< CCU4_CC4 TC: CMOD (Bitfield-Mask: 0x01) */ 12403 #define CCU4_CC4_TC_ECM_Pos (4UL) /*!< CCU4_CC4 TC: ECM (Bit 4) */ 12404 #define CCU4_CC4_TC_ECM_Msk (0x10UL) /*!< CCU4_CC4 TC: ECM (Bitfield-Mask: 0x01) */ 12405 #define CCU4_CC4_TC_CAPC_Pos (5UL) /*!< CCU4_CC4 TC: CAPC (Bit 5) */ 12406 #define CCU4_CC4_TC_CAPC_Msk (0x60UL) /*!< CCU4_CC4 TC: CAPC (Bitfield-Mask: 0x03) */ 12407 #define CCU4_CC4_TC_ENDM_Pos (8UL) /*!< CCU4_CC4 TC: ENDM (Bit 8) */ 12408 #define CCU4_CC4_TC_ENDM_Msk (0x300UL) /*!< CCU4_CC4 TC: ENDM (Bitfield-Mask: 0x03) */ 12409 #define CCU4_CC4_TC_STRM_Pos (10UL) /*!< CCU4_CC4 TC: STRM (Bit 10) */ 12410 #define CCU4_CC4_TC_STRM_Msk (0x400UL) /*!< CCU4_CC4 TC: STRM (Bitfield-Mask: 0x01) */ 12411 #define CCU4_CC4_TC_SCE_Pos (11UL) /*!< CCU4_CC4 TC: SCE (Bit 11) */ 12412 #define CCU4_CC4_TC_SCE_Msk (0x800UL) /*!< CCU4_CC4 TC: SCE (Bitfield-Mask: 0x01) */ 12413 #define CCU4_CC4_TC_CCS_Pos (12UL) /*!< CCU4_CC4 TC: CCS (Bit 12) */ 12414 #define CCU4_CC4_TC_CCS_Msk (0x1000UL) /*!< CCU4_CC4 TC: CCS (Bitfield-Mask: 0x01) */ 12415 #define CCU4_CC4_TC_DITHE_Pos (13UL) /*!< CCU4_CC4 TC: DITHE (Bit 13) */ 12416 #define CCU4_CC4_TC_DITHE_Msk (0x6000UL) /*!< CCU4_CC4 TC: DITHE (Bitfield-Mask: 0x03) */ 12417 #define CCU4_CC4_TC_DIM_Pos (15UL) /*!< CCU4_CC4 TC: DIM (Bit 15) */ 12418 #define CCU4_CC4_TC_DIM_Msk (0x8000UL) /*!< CCU4_CC4 TC: DIM (Bitfield-Mask: 0x01) */ 12419 #define CCU4_CC4_TC_FPE_Pos (16UL) /*!< CCU4_CC4 TC: FPE (Bit 16) */ 12420 #define CCU4_CC4_TC_FPE_Msk (0x10000UL) /*!< CCU4_CC4 TC: FPE (Bitfield-Mask: 0x01) */ 12421 #define CCU4_CC4_TC_TRAPE_Pos (17UL) /*!< CCU4_CC4 TC: TRAPE (Bit 17) */ 12422 #define CCU4_CC4_TC_TRAPE_Msk (0x20000UL) /*!< CCU4_CC4 TC: TRAPE (Bitfield-Mask: 0x01) */ 12423 #define CCU4_CC4_TC_TRPSE_Pos (21UL) /*!< CCU4_CC4 TC: TRPSE (Bit 21) */ 12424 #define CCU4_CC4_TC_TRPSE_Msk (0x200000UL) /*!< CCU4_CC4 TC: TRPSE (Bitfield-Mask: 0x01) */ 12425 #define CCU4_CC4_TC_TRPSW_Pos (22UL) /*!< CCU4_CC4 TC: TRPSW (Bit 22) */ 12426 #define CCU4_CC4_TC_TRPSW_Msk (0x400000UL) /*!< CCU4_CC4 TC: TRPSW (Bitfield-Mask: 0x01) */ 12427 #define CCU4_CC4_TC_EMS_Pos (23UL) /*!< CCU4_CC4 TC: EMS (Bit 23) */ 12428 #define CCU4_CC4_TC_EMS_Msk (0x800000UL) /*!< CCU4_CC4 TC: EMS (Bitfield-Mask: 0x01) */ 12429 #define CCU4_CC4_TC_EMT_Pos (24UL) /*!< CCU4_CC4 TC: EMT (Bit 24) */ 12430 #define CCU4_CC4_TC_EMT_Msk (0x1000000UL) /*!< CCU4_CC4 TC: EMT (Bitfield-Mask: 0x01) */ 12431 #define CCU4_CC4_TC_MCME_Pos (25UL) /*!< CCU4_CC4 TC: MCME (Bit 25) */ 12432 #define CCU4_CC4_TC_MCME_Msk (0x2000000UL) /*!< CCU4_CC4 TC: MCME (Bitfield-Mask: 0x01) */ 12433 12434 /* -------------------------------- CCU4_CC4_PSL -------------------------------- */ 12435 #define CCU4_CC4_PSL_PSL_Pos (0UL) /*!< CCU4_CC4 PSL: PSL (Bit 0) */ 12436 #define CCU4_CC4_PSL_PSL_Msk (0x1UL) /*!< CCU4_CC4 PSL: PSL (Bitfield-Mask: 0x01) */ 12437 12438 /* -------------------------------- CCU4_CC4_DIT -------------------------------- */ 12439 #define CCU4_CC4_DIT_DCV_Pos (0UL) /*!< CCU4_CC4 DIT: DCV (Bit 0) */ 12440 #define CCU4_CC4_DIT_DCV_Msk (0xfUL) /*!< CCU4_CC4 DIT: DCV (Bitfield-Mask: 0x0f) */ 12441 #define CCU4_CC4_DIT_DCNT_Pos (8UL) /*!< CCU4_CC4 DIT: DCNT (Bit 8) */ 12442 #define CCU4_CC4_DIT_DCNT_Msk (0xf00UL) /*!< CCU4_CC4 DIT: DCNT (Bitfield-Mask: 0x0f) */ 12443 12444 /* -------------------------------- CCU4_CC4_DITS ------------------------------- */ 12445 #define CCU4_CC4_DITS_DCVS_Pos (0UL) /*!< CCU4_CC4 DITS: DCVS (Bit 0) */ 12446 #define CCU4_CC4_DITS_DCVS_Msk (0xfUL) /*!< CCU4_CC4 DITS: DCVS (Bitfield-Mask: 0x0f) */ 12447 12448 /* -------------------------------- CCU4_CC4_PSC -------------------------------- */ 12449 #define CCU4_CC4_PSC_PSIV_Pos (0UL) /*!< CCU4_CC4 PSC: PSIV (Bit 0) */ 12450 #define CCU4_CC4_PSC_PSIV_Msk (0xfUL) /*!< CCU4_CC4 PSC: PSIV (Bitfield-Mask: 0x0f) */ 12451 12452 /* -------------------------------- CCU4_CC4_FPC -------------------------------- */ 12453 #define CCU4_CC4_FPC_PCMP_Pos (0UL) /*!< CCU4_CC4 FPC: PCMP (Bit 0) */ 12454 #define CCU4_CC4_FPC_PCMP_Msk (0xfUL) /*!< CCU4_CC4 FPC: PCMP (Bitfield-Mask: 0x0f) */ 12455 #define CCU4_CC4_FPC_PVAL_Pos (8UL) /*!< CCU4_CC4 FPC: PVAL (Bit 8) */ 12456 #define CCU4_CC4_FPC_PVAL_Msk (0xf00UL) /*!< CCU4_CC4 FPC: PVAL (Bitfield-Mask: 0x0f) */ 12457 12458 /* -------------------------------- CCU4_CC4_FPCS ------------------------------- */ 12459 #define CCU4_CC4_FPCS_PCMP_Pos (0UL) /*!< CCU4_CC4 FPCS: PCMP (Bit 0) */ 12460 #define CCU4_CC4_FPCS_PCMP_Msk (0xfUL) /*!< CCU4_CC4 FPCS: PCMP (Bitfield-Mask: 0x0f) */ 12461 12462 /* --------------------------------- CCU4_CC4_PR -------------------------------- */ 12463 #define CCU4_CC4_PR_PR_Pos (0UL) /*!< CCU4_CC4 PR: PR (Bit 0) */ 12464 #define CCU4_CC4_PR_PR_Msk (0xffffUL) /*!< CCU4_CC4 PR: PR (Bitfield-Mask: 0xffff) */ 12465 12466 /* -------------------------------- CCU4_CC4_PRS -------------------------------- */ 12467 #define CCU4_CC4_PRS_PRS_Pos (0UL) /*!< CCU4_CC4 PRS: PRS (Bit 0) */ 12468 #define CCU4_CC4_PRS_PRS_Msk (0xffffUL) /*!< CCU4_CC4 PRS: PRS (Bitfield-Mask: 0xffff) */ 12469 12470 /* --------------------------------- CCU4_CC4_CR -------------------------------- */ 12471 #define CCU4_CC4_CR_CR_Pos (0UL) /*!< CCU4_CC4 CR: CR (Bit 0) */ 12472 #define CCU4_CC4_CR_CR_Msk (0xffffUL) /*!< CCU4_CC4 CR: CR (Bitfield-Mask: 0xffff) */ 12473 12474 /* -------------------------------- CCU4_CC4_CRS -------------------------------- */ 12475 #define CCU4_CC4_CRS_CRS_Pos (0UL) /*!< CCU4_CC4 CRS: CRS (Bit 0) */ 12476 #define CCU4_CC4_CRS_CRS_Msk (0xffffUL) /*!< CCU4_CC4 CRS: CRS (Bitfield-Mask: 0xffff) */ 12477 12478 /* ------------------------------- CCU4_CC4_TIMER ------------------------------- */ 12479 #define CCU4_CC4_TIMER_TVAL_Pos (0UL) /*!< CCU4_CC4 TIMER: TVAL (Bit 0) */ 12480 #define CCU4_CC4_TIMER_TVAL_Msk (0xffffUL) /*!< CCU4_CC4 TIMER: TVAL (Bitfield-Mask: 0xffff) */ 12481 12482 /* --------------------------------- CCU4_CC4_CV -------------------------------- */ 12483 #define CCU4_CC4_CV_CAPTV_Pos (0UL) /*!< CCU4_CC4 CV: CAPTV (Bit 0) */ 12484 #define CCU4_CC4_CV_CAPTV_Msk (0xffffUL) /*!< CCU4_CC4 CV: CAPTV (Bitfield-Mask: 0xffff) */ 12485 #define CCU4_CC4_CV_FPCV_Pos (16UL) /*!< CCU4_CC4 CV: FPCV (Bit 16) */ 12486 #define CCU4_CC4_CV_FPCV_Msk (0xf0000UL) /*!< CCU4_CC4 CV: FPCV (Bitfield-Mask: 0x0f) */ 12487 #define CCU4_CC4_CV_FFL_Pos (20UL) /*!< CCU4_CC4 CV: FFL (Bit 20) */ 12488 #define CCU4_CC4_CV_FFL_Msk (0x100000UL) /*!< CCU4_CC4 CV: FFL (Bitfield-Mask: 0x01) */ 12489 12490 /* -------------------------------- CCU4_CC4_INTS ------------------------------- */ 12491 #define CCU4_CC4_INTS_PMUS_Pos (0UL) /*!< CCU4_CC4 INTS: PMUS (Bit 0) */ 12492 #define CCU4_CC4_INTS_PMUS_Msk (0x1UL) /*!< CCU4_CC4 INTS: PMUS (Bitfield-Mask: 0x01) */ 12493 #define CCU4_CC4_INTS_OMDS_Pos (1UL) /*!< CCU4_CC4 INTS: OMDS (Bit 1) */ 12494 #define CCU4_CC4_INTS_OMDS_Msk (0x2UL) /*!< CCU4_CC4 INTS: OMDS (Bitfield-Mask: 0x01) */ 12495 #define CCU4_CC4_INTS_CMUS_Pos (2UL) /*!< CCU4_CC4 INTS: CMUS (Bit 2) */ 12496 #define CCU4_CC4_INTS_CMUS_Msk (0x4UL) /*!< CCU4_CC4 INTS: CMUS (Bitfield-Mask: 0x01) */ 12497 #define CCU4_CC4_INTS_CMDS_Pos (3UL) /*!< CCU4_CC4 INTS: CMDS (Bit 3) */ 12498 #define CCU4_CC4_INTS_CMDS_Msk (0x8UL) /*!< CCU4_CC4 INTS: CMDS (Bitfield-Mask: 0x01) */ 12499 #define CCU4_CC4_INTS_E0AS_Pos (8UL) /*!< CCU4_CC4 INTS: E0AS (Bit 8) */ 12500 #define CCU4_CC4_INTS_E0AS_Msk (0x100UL) /*!< CCU4_CC4 INTS: E0AS (Bitfield-Mask: 0x01) */ 12501 #define CCU4_CC4_INTS_E1AS_Pos (9UL) /*!< CCU4_CC4 INTS: E1AS (Bit 9) */ 12502 #define CCU4_CC4_INTS_E1AS_Msk (0x200UL) /*!< CCU4_CC4 INTS: E1AS (Bitfield-Mask: 0x01) */ 12503 #define CCU4_CC4_INTS_E2AS_Pos (10UL) /*!< CCU4_CC4 INTS: E2AS (Bit 10) */ 12504 #define CCU4_CC4_INTS_E2AS_Msk (0x400UL) /*!< CCU4_CC4 INTS: E2AS (Bitfield-Mask: 0x01) */ 12505 #define CCU4_CC4_INTS_TRPF_Pos (11UL) /*!< CCU4_CC4 INTS: TRPF (Bit 11) */ 12506 #define CCU4_CC4_INTS_TRPF_Msk (0x800UL) /*!< CCU4_CC4 INTS: TRPF (Bitfield-Mask: 0x01) */ 12507 12508 /* -------------------------------- CCU4_CC4_INTE ------------------------------- */ 12509 #define CCU4_CC4_INTE_PME_Pos (0UL) /*!< CCU4_CC4 INTE: PME (Bit 0) */ 12510 #define CCU4_CC4_INTE_PME_Msk (0x1UL) /*!< CCU4_CC4 INTE: PME (Bitfield-Mask: 0x01) */ 12511 #define CCU4_CC4_INTE_OME_Pos (1UL) /*!< CCU4_CC4 INTE: OME (Bit 1) */ 12512 #define CCU4_CC4_INTE_OME_Msk (0x2UL) /*!< CCU4_CC4 INTE: OME (Bitfield-Mask: 0x01) */ 12513 #define CCU4_CC4_INTE_CMUE_Pos (2UL) /*!< CCU4_CC4 INTE: CMUE (Bit 2) */ 12514 #define CCU4_CC4_INTE_CMUE_Msk (0x4UL) /*!< CCU4_CC4 INTE: CMUE (Bitfield-Mask: 0x01) */ 12515 #define CCU4_CC4_INTE_CMDE_Pos (3UL) /*!< CCU4_CC4 INTE: CMDE (Bit 3) */ 12516 #define CCU4_CC4_INTE_CMDE_Msk (0x8UL) /*!< CCU4_CC4 INTE: CMDE (Bitfield-Mask: 0x01) */ 12517 #define CCU4_CC4_INTE_E0AE_Pos (8UL) /*!< CCU4_CC4 INTE: E0AE (Bit 8) */ 12518 #define CCU4_CC4_INTE_E0AE_Msk (0x100UL) /*!< CCU4_CC4 INTE: E0AE (Bitfield-Mask: 0x01) */ 12519 #define CCU4_CC4_INTE_E1AE_Pos (9UL) /*!< CCU4_CC4 INTE: E1AE (Bit 9) */ 12520 #define CCU4_CC4_INTE_E1AE_Msk (0x200UL) /*!< CCU4_CC4 INTE: E1AE (Bitfield-Mask: 0x01) */ 12521 #define CCU4_CC4_INTE_E2AE_Pos (10UL) /*!< CCU4_CC4 INTE: E2AE (Bit 10) */ 12522 #define CCU4_CC4_INTE_E2AE_Msk (0x400UL) /*!< CCU4_CC4 INTE: E2AE (Bitfield-Mask: 0x01) */ 12523 12524 /* -------------------------------- CCU4_CC4_SRS -------------------------------- */ 12525 #define CCU4_CC4_SRS_POSR_Pos (0UL) /*!< CCU4_CC4 SRS: POSR (Bit 0) */ 12526 #define CCU4_CC4_SRS_POSR_Msk (0x3UL) /*!< CCU4_CC4 SRS: POSR (Bitfield-Mask: 0x03) */ 12527 #define CCU4_CC4_SRS_CMSR_Pos (2UL) /*!< CCU4_CC4 SRS: CMSR (Bit 2) */ 12528 #define CCU4_CC4_SRS_CMSR_Msk (0xcUL) /*!< CCU4_CC4 SRS: CMSR (Bitfield-Mask: 0x03) */ 12529 #define CCU4_CC4_SRS_E0SR_Pos (8UL) /*!< CCU4_CC4 SRS: E0SR (Bit 8) */ 12530 #define CCU4_CC4_SRS_E0SR_Msk (0x300UL) /*!< CCU4_CC4 SRS: E0SR (Bitfield-Mask: 0x03) */ 12531 #define CCU4_CC4_SRS_E1SR_Pos (10UL) /*!< CCU4_CC4 SRS: E1SR (Bit 10) */ 12532 #define CCU4_CC4_SRS_E1SR_Msk (0xc00UL) /*!< CCU4_CC4 SRS: E1SR (Bitfield-Mask: 0x03) */ 12533 #define CCU4_CC4_SRS_E2SR_Pos (12UL) /*!< CCU4_CC4 SRS: E2SR (Bit 12) */ 12534 #define CCU4_CC4_SRS_E2SR_Msk (0x3000UL) /*!< CCU4_CC4 SRS: E2SR (Bitfield-Mask: 0x03) */ 12535 12536 /* -------------------------------- CCU4_CC4_SWS -------------------------------- */ 12537 #define CCU4_CC4_SWS_SPM_Pos (0UL) /*!< CCU4_CC4 SWS: SPM (Bit 0) */ 12538 #define CCU4_CC4_SWS_SPM_Msk (0x1UL) /*!< CCU4_CC4 SWS: SPM (Bitfield-Mask: 0x01) */ 12539 #define CCU4_CC4_SWS_SOM_Pos (1UL) /*!< CCU4_CC4 SWS: SOM (Bit 1) */ 12540 #define CCU4_CC4_SWS_SOM_Msk (0x2UL) /*!< CCU4_CC4 SWS: SOM (Bitfield-Mask: 0x01) */ 12541 #define CCU4_CC4_SWS_SCMU_Pos (2UL) /*!< CCU4_CC4 SWS: SCMU (Bit 2) */ 12542 #define CCU4_CC4_SWS_SCMU_Msk (0x4UL) /*!< CCU4_CC4 SWS: SCMU (Bitfield-Mask: 0x01) */ 12543 #define CCU4_CC4_SWS_SCMD_Pos (3UL) /*!< CCU4_CC4 SWS: SCMD (Bit 3) */ 12544 #define CCU4_CC4_SWS_SCMD_Msk (0x8UL) /*!< CCU4_CC4 SWS: SCMD (Bitfield-Mask: 0x01) */ 12545 #define CCU4_CC4_SWS_SE0A_Pos (8UL) /*!< CCU4_CC4 SWS: SE0A (Bit 8) */ 12546 #define CCU4_CC4_SWS_SE0A_Msk (0x100UL) /*!< CCU4_CC4 SWS: SE0A (Bitfield-Mask: 0x01) */ 12547 #define CCU4_CC4_SWS_SE1A_Pos (9UL) /*!< CCU4_CC4 SWS: SE1A (Bit 9) */ 12548 #define CCU4_CC4_SWS_SE1A_Msk (0x200UL) /*!< CCU4_CC4 SWS: SE1A (Bitfield-Mask: 0x01) */ 12549 #define CCU4_CC4_SWS_SE2A_Pos (10UL) /*!< CCU4_CC4 SWS: SE2A (Bit 10) */ 12550 #define CCU4_CC4_SWS_SE2A_Msk (0x400UL) /*!< CCU4_CC4 SWS: SE2A (Bitfield-Mask: 0x01) */ 12551 #define CCU4_CC4_SWS_STRPF_Pos (11UL) /*!< CCU4_CC4 SWS: STRPF (Bit 11) */ 12552 #define CCU4_CC4_SWS_STRPF_Msk (0x800UL) /*!< CCU4_CC4 SWS: STRPF (Bitfield-Mask: 0x01) */ 12553 12554 /* -------------------------------- CCU4_CC4_SWR -------------------------------- */ 12555 #define CCU4_CC4_SWR_RPM_Pos (0UL) /*!< CCU4_CC4 SWR: RPM (Bit 0) */ 12556 #define CCU4_CC4_SWR_RPM_Msk (0x1UL) /*!< CCU4_CC4 SWR: RPM (Bitfield-Mask: 0x01) */ 12557 #define CCU4_CC4_SWR_ROM_Pos (1UL) /*!< CCU4_CC4 SWR: ROM (Bit 1) */ 12558 #define CCU4_CC4_SWR_ROM_Msk (0x2UL) /*!< CCU4_CC4 SWR: ROM (Bitfield-Mask: 0x01) */ 12559 #define CCU4_CC4_SWR_RCMU_Pos (2UL) /*!< CCU4_CC4 SWR: RCMU (Bit 2) */ 12560 #define CCU4_CC4_SWR_RCMU_Msk (0x4UL) /*!< CCU4_CC4 SWR: RCMU (Bitfield-Mask: 0x01) */ 12561 #define CCU4_CC4_SWR_RCMD_Pos (3UL) /*!< CCU4_CC4 SWR: RCMD (Bit 3) */ 12562 #define CCU4_CC4_SWR_RCMD_Msk (0x8UL) /*!< CCU4_CC4 SWR: RCMD (Bitfield-Mask: 0x01) */ 12563 #define CCU4_CC4_SWR_RE0A_Pos (8UL) /*!< CCU4_CC4 SWR: RE0A (Bit 8) */ 12564 #define CCU4_CC4_SWR_RE0A_Msk (0x100UL) /*!< CCU4_CC4 SWR: RE0A (Bitfield-Mask: 0x01) */ 12565 #define CCU4_CC4_SWR_RE1A_Pos (9UL) /*!< CCU4_CC4 SWR: RE1A (Bit 9) */ 12566 #define CCU4_CC4_SWR_RE1A_Msk (0x200UL) /*!< CCU4_CC4 SWR: RE1A (Bitfield-Mask: 0x01) */ 12567 #define CCU4_CC4_SWR_RE2A_Pos (10UL) /*!< CCU4_CC4 SWR: RE2A (Bit 10) */ 12568 #define CCU4_CC4_SWR_RE2A_Msk (0x400UL) /*!< CCU4_CC4 SWR: RE2A (Bitfield-Mask: 0x01) */ 12569 #define CCU4_CC4_SWR_RTRPF_Pos (11UL) /*!< CCU4_CC4 SWR: RTRPF (Bit 11) */ 12570 #define CCU4_CC4_SWR_RTRPF_Msk (0x800UL) /*!< CCU4_CC4 SWR: RTRPF (Bitfield-Mask: 0x01) */ 12571 12572 12573 /* ================================================================================ */ 12574 /* ================ Group 'CCU8' Position & Mask ================ */ 12575 /* ================================================================================ */ 12576 12577 12578 /* --------------------------------- CCU8_GCTRL --------------------------------- */ 12579 #define CCU8_GCTRL_PRBC_Pos (0UL) /*!< CCU8 GCTRL: PRBC (Bit 0) */ 12580 #define CCU8_GCTRL_PRBC_Msk (0x7UL) /*!< CCU8 GCTRL: PRBC (Bitfield-Mask: 0x07) */ 12581 #define CCU8_GCTRL_PCIS_Pos (4UL) /*!< CCU8 GCTRL: PCIS (Bit 4) */ 12582 #define CCU8_GCTRL_PCIS_Msk (0x30UL) /*!< CCU8 GCTRL: PCIS (Bitfield-Mask: 0x03) */ 12583 #define CCU8_GCTRL_SUSCFG_Pos (8UL) /*!< CCU8 GCTRL: SUSCFG (Bit 8) */ 12584 #define CCU8_GCTRL_SUSCFG_Msk (0x300UL) /*!< CCU8 GCTRL: SUSCFG (Bitfield-Mask: 0x03) */ 12585 #define CCU8_GCTRL_MSE0_Pos (10UL) /*!< CCU8 GCTRL: MSE0 (Bit 10) */ 12586 #define CCU8_GCTRL_MSE0_Msk (0x400UL) /*!< CCU8 GCTRL: MSE0 (Bitfield-Mask: 0x01) */ 12587 #define CCU8_GCTRL_MSE1_Pos (11UL) /*!< CCU8 GCTRL: MSE1 (Bit 11) */ 12588 #define CCU8_GCTRL_MSE1_Msk (0x800UL) /*!< CCU8 GCTRL: MSE1 (Bitfield-Mask: 0x01) */ 12589 #define CCU8_GCTRL_MSE2_Pos (12UL) /*!< CCU8 GCTRL: MSE2 (Bit 12) */ 12590 #define CCU8_GCTRL_MSE2_Msk (0x1000UL) /*!< CCU8 GCTRL: MSE2 (Bitfield-Mask: 0x01) */ 12591 #define CCU8_GCTRL_MSE3_Pos (13UL) /*!< CCU8 GCTRL: MSE3 (Bit 13) */ 12592 #define CCU8_GCTRL_MSE3_Msk (0x2000UL) /*!< CCU8 GCTRL: MSE3 (Bitfield-Mask: 0x01) */ 12593 #define CCU8_GCTRL_MSDE_Pos (14UL) /*!< CCU8 GCTRL: MSDE (Bit 14) */ 12594 #define CCU8_GCTRL_MSDE_Msk (0xc000UL) /*!< CCU8 GCTRL: MSDE (Bitfield-Mask: 0x03) */ 12595 12596 /* --------------------------------- CCU8_GSTAT --------------------------------- */ 12597 #define CCU8_GSTAT_S0I_Pos (0UL) /*!< CCU8 GSTAT: S0I (Bit 0) */ 12598 #define CCU8_GSTAT_S0I_Msk (0x1UL) /*!< CCU8 GSTAT: S0I (Bitfield-Mask: 0x01) */ 12599 #define CCU8_GSTAT_S1I_Pos (1UL) /*!< CCU8 GSTAT: S1I (Bit 1) */ 12600 #define CCU8_GSTAT_S1I_Msk (0x2UL) /*!< CCU8 GSTAT: S1I (Bitfield-Mask: 0x01) */ 12601 #define CCU8_GSTAT_S2I_Pos (2UL) /*!< CCU8 GSTAT: S2I (Bit 2) */ 12602 #define CCU8_GSTAT_S2I_Msk (0x4UL) /*!< CCU8 GSTAT: S2I (Bitfield-Mask: 0x01) */ 12603 #define CCU8_GSTAT_S3I_Pos (3UL) /*!< CCU8 GSTAT: S3I (Bit 3) */ 12604 #define CCU8_GSTAT_S3I_Msk (0x8UL) /*!< CCU8 GSTAT: S3I (Bitfield-Mask: 0x01) */ 12605 #define CCU8_GSTAT_PRB_Pos (8UL) /*!< CCU8 GSTAT: PRB (Bit 8) */ 12606 #define CCU8_GSTAT_PRB_Msk (0x100UL) /*!< CCU8 GSTAT: PRB (Bitfield-Mask: 0x01) */ 12607 #define CCU8_GSTAT_PCRB_Pos (10UL) /*!< CCU8 GSTAT: PCRB (Bit 10) */ 12608 #define CCU8_GSTAT_PCRB_Msk (0x400UL) /*!< CCU8 GSTAT: PCRB (Bitfield-Mask: 0x01) */ 12609 12610 /* --------------------------------- CCU8_GIDLS --------------------------------- */ 12611 #define CCU8_GIDLS_SS0I_Pos (0UL) /*!< CCU8 GIDLS: SS0I (Bit 0) */ 12612 #define CCU8_GIDLS_SS0I_Msk (0x1UL) /*!< CCU8 GIDLS: SS0I (Bitfield-Mask: 0x01) */ 12613 #define CCU8_GIDLS_SS1I_Pos (1UL) /*!< CCU8 GIDLS: SS1I (Bit 1) */ 12614 #define CCU8_GIDLS_SS1I_Msk (0x2UL) /*!< CCU8 GIDLS: SS1I (Bitfield-Mask: 0x01) */ 12615 #define CCU8_GIDLS_SS2I_Pos (2UL) /*!< CCU8 GIDLS: SS2I (Bit 2) */ 12616 #define CCU8_GIDLS_SS2I_Msk (0x4UL) /*!< CCU8 GIDLS: SS2I (Bitfield-Mask: 0x01) */ 12617 #define CCU8_GIDLS_SS3I_Pos (3UL) /*!< CCU8 GIDLS: SS3I (Bit 3) */ 12618 #define CCU8_GIDLS_SS3I_Msk (0x8UL) /*!< CCU8 GIDLS: SS3I (Bitfield-Mask: 0x01) */ 12619 #define CCU8_GIDLS_CPRB_Pos (8UL) /*!< CCU8 GIDLS: CPRB (Bit 8) */ 12620 #define CCU8_GIDLS_CPRB_Msk (0x100UL) /*!< CCU8 GIDLS: CPRB (Bitfield-Mask: 0x01) */ 12621 #define CCU8_GIDLS_PSIC_Pos (9UL) /*!< CCU8 GIDLS: PSIC (Bit 9) */ 12622 #define CCU8_GIDLS_PSIC_Msk (0x200UL) /*!< CCU8 GIDLS: PSIC (Bitfield-Mask: 0x01) */ 12623 #define CCU8_GIDLS_CPCH_Pos (10UL) /*!< CCU8 GIDLS: CPCH (Bit 10) */ 12624 #define CCU8_GIDLS_CPCH_Msk (0x400UL) /*!< CCU8 GIDLS: CPCH (Bitfield-Mask: 0x01) */ 12625 12626 /* --------------------------------- CCU8_GIDLC --------------------------------- */ 12627 #define CCU8_GIDLC_CS0I_Pos (0UL) /*!< CCU8 GIDLC: CS0I (Bit 0) */ 12628 #define CCU8_GIDLC_CS0I_Msk (0x1UL) /*!< CCU8 GIDLC: CS0I (Bitfield-Mask: 0x01) */ 12629 #define CCU8_GIDLC_CS1I_Pos (1UL) /*!< CCU8 GIDLC: CS1I (Bit 1) */ 12630 #define CCU8_GIDLC_CS1I_Msk (0x2UL) /*!< CCU8 GIDLC: CS1I (Bitfield-Mask: 0x01) */ 12631 #define CCU8_GIDLC_CS2I_Pos (2UL) /*!< CCU8 GIDLC: CS2I (Bit 2) */ 12632 #define CCU8_GIDLC_CS2I_Msk (0x4UL) /*!< CCU8 GIDLC: CS2I (Bitfield-Mask: 0x01) */ 12633 #define CCU8_GIDLC_CS3I_Pos (3UL) /*!< CCU8 GIDLC: CS3I (Bit 3) */ 12634 #define CCU8_GIDLC_CS3I_Msk (0x8UL) /*!< CCU8 GIDLC: CS3I (Bitfield-Mask: 0x01) */ 12635 #define CCU8_GIDLC_SPRB_Pos (8UL) /*!< CCU8 GIDLC: SPRB (Bit 8) */ 12636 #define CCU8_GIDLC_SPRB_Msk (0x100UL) /*!< CCU8 GIDLC: SPRB (Bitfield-Mask: 0x01) */ 12637 #define CCU8_GIDLC_SPCH_Pos (10UL) /*!< CCU8 GIDLC: SPCH (Bit 10) */ 12638 #define CCU8_GIDLC_SPCH_Msk (0x400UL) /*!< CCU8 GIDLC: SPCH (Bitfield-Mask: 0x01) */ 12639 12640 /* ---------------------------------- CCU8_GCSS --------------------------------- */ 12641 #define CCU8_GCSS_S0SE_Pos (0UL) /*!< CCU8 GCSS: S0SE (Bit 0) */ 12642 #define CCU8_GCSS_S0SE_Msk (0x1UL) /*!< CCU8 GCSS: S0SE (Bitfield-Mask: 0x01) */ 12643 #define CCU8_GCSS_S0DSE_Pos (1UL) /*!< CCU8 GCSS: S0DSE (Bit 1) */ 12644 #define CCU8_GCSS_S0DSE_Msk (0x2UL) /*!< CCU8 GCSS: S0DSE (Bitfield-Mask: 0x01) */ 12645 #define CCU8_GCSS_S0PSE_Pos (2UL) /*!< CCU8 GCSS: S0PSE (Bit 2) */ 12646 #define CCU8_GCSS_S0PSE_Msk (0x4UL) /*!< CCU8 GCSS: S0PSE (Bitfield-Mask: 0x01) */ 12647 #define CCU8_GCSS_S1SE_Pos (4UL) /*!< CCU8 GCSS: S1SE (Bit 4) */ 12648 #define CCU8_GCSS_S1SE_Msk (0x10UL) /*!< CCU8 GCSS: S1SE (Bitfield-Mask: 0x01) */ 12649 #define CCU8_GCSS_S1DSE_Pos (5UL) /*!< CCU8 GCSS: S1DSE (Bit 5) */ 12650 #define CCU8_GCSS_S1DSE_Msk (0x20UL) /*!< CCU8 GCSS: S1DSE (Bitfield-Mask: 0x01) */ 12651 #define CCU8_GCSS_S1PSE_Pos (6UL) /*!< CCU8 GCSS: S1PSE (Bit 6) */ 12652 #define CCU8_GCSS_S1PSE_Msk (0x40UL) /*!< CCU8 GCSS: S1PSE (Bitfield-Mask: 0x01) */ 12653 #define CCU8_GCSS_S2SE_Pos (8UL) /*!< CCU8 GCSS: S2SE (Bit 8) */ 12654 #define CCU8_GCSS_S2SE_Msk (0x100UL) /*!< CCU8 GCSS: S2SE (Bitfield-Mask: 0x01) */ 12655 #define CCU8_GCSS_S2DSE_Pos (9UL) /*!< CCU8 GCSS: S2DSE (Bit 9) */ 12656 #define CCU8_GCSS_S2DSE_Msk (0x200UL) /*!< CCU8 GCSS: S2DSE (Bitfield-Mask: 0x01) */ 12657 #define CCU8_GCSS_S2PSE_Pos (10UL) /*!< CCU8 GCSS: S2PSE (Bit 10) */ 12658 #define CCU8_GCSS_S2PSE_Msk (0x400UL) /*!< CCU8 GCSS: S2PSE (Bitfield-Mask: 0x01) */ 12659 #define CCU8_GCSS_S3SE_Pos (12UL) /*!< CCU8 GCSS: S3SE (Bit 12) */ 12660 #define CCU8_GCSS_S3SE_Msk (0x1000UL) /*!< CCU8 GCSS: S3SE (Bitfield-Mask: 0x01) */ 12661 #define CCU8_GCSS_S3DSE_Pos (13UL) /*!< CCU8 GCSS: S3DSE (Bit 13) */ 12662 #define CCU8_GCSS_S3DSE_Msk (0x2000UL) /*!< CCU8 GCSS: S3DSE (Bitfield-Mask: 0x01) */ 12663 #define CCU8_GCSS_S3PSE_Pos (14UL) /*!< CCU8 GCSS: S3PSE (Bit 14) */ 12664 #define CCU8_GCSS_S3PSE_Msk (0x4000UL) /*!< CCU8 GCSS: S3PSE (Bitfield-Mask: 0x01) */ 12665 #define CCU8_GCSS_S0ST1S_Pos (16UL) /*!< CCU8 GCSS: S0ST1S (Bit 16) */ 12666 #define CCU8_GCSS_S0ST1S_Msk (0x10000UL) /*!< CCU8 GCSS: S0ST1S (Bitfield-Mask: 0x01) */ 12667 #define CCU8_GCSS_S1ST1S_Pos (17UL) /*!< CCU8 GCSS: S1ST1S (Bit 17) */ 12668 #define CCU8_GCSS_S1ST1S_Msk (0x20000UL) /*!< CCU8 GCSS: S1ST1S (Bitfield-Mask: 0x01) */ 12669 #define CCU8_GCSS_S2ST1S_Pos (18UL) /*!< CCU8 GCSS: S2ST1S (Bit 18) */ 12670 #define CCU8_GCSS_S2ST1S_Msk (0x40000UL) /*!< CCU8 GCSS: S2ST1S (Bitfield-Mask: 0x01) */ 12671 #define CCU8_GCSS_S3ST1S_Pos (19UL) /*!< CCU8 GCSS: S3ST1S (Bit 19) */ 12672 #define CCU8_GCSS_S3ST1S_Msk (0x80000UL) /*!< CCU8 GCSS: S3ST1S (Bitfield-Mask: 0x01) */ 12673 #define CCU8_GCSS_S0ST2S_Pos (20UL) /*!< CCU8 GCSS: S0ST2S (Bit 20) */ 12674 #define CCU8_GCSS_S0ST2S_Msk (0x100000UL) /*!< CCU8 GCSS: S0ST2S (Bitfield-Mask: 0x01) */ 12675 #define CCU8_GCSS_S1ST2S_Pos (21UL) /*!< CCU8 GCSS: S1ST2S (Bit 21) */ 12676 #define CCU8_GCSS_S1ST2S_Msk (0x200000UL) /*!< CCU8 GCSS: S1ST2S (Bitfield-Mask: 0x01) */ 12677 #define CCU8_GCSS_S2ST2S_Pos (22UL) /*!< CCU8 GCSS: S2ST2S (Bit 22) */ 12678 #define CCU8_GCSS_S2ST2S_Msk (0x400000UL) /*!< CCU8 GCSS: S2ST2S (Bitfield-Mask: 0x01) */ 12679 #define CCU8_GCSS_S3ST2S_Pos (23UL) /*!< CCU8 GCSS: S3ST2S (Bit 23) */ 12680 #define CCU8_GCSS_S3ST2S_Msk (0x800000UL) /*!< CCU8 GCSS: S3ST2S (Bitfield-Mask: 0x01) */ 12681 12682 /* ---------------------------------- CCU8_GCSC --------------------------------- */ 12683 #define CCU8_GCSC_S0SC_Pos (0UL) /*!< CCU8 GCSC: S0SC (Bit 0) */ 12684 #define CCU8_GCSC_S0SC_Msk (0x1UL) /*!< CCU8 GCSC: S0SC (Bitfield-Mask: 0x01) */ 12685 #define CCU8_GCSC_S0DSC_Pos (1UL) /*!< CCU8 GCSC: S0DSC (Bit 1) */ 12686 #define CCU8_GCSC_S0DSC_Msk (0x2UL) /*!< CCU8 GCSC: S0DSC (Bitfield-Mask: 0x01) */ 12687 #define CCU8_GCSC_S0PSC_Pos (2UL) /*!< CCU8 GCSC: S0PSC (Bit 2) */ 12688 #define CCU8_GCSC_S0PSC_Msk (0x4UL) /*!< CCU8 GCSC: S0PSC (Bitfield-Mask: 0x01) */ 12689 #define CCU8_GCSC_S1SC_Pos (4UL) /*!< CCU8 GCSC: S1SC (Bit 4) */ 12690 #define CCU8_GCSC_S1SC_Msk (0x10UL) /*!< CCU8 GCSC: S1SC (Bitfield-Mask: 0x01) */ 12691 #define CCU8_GCSC_S1DSC_Pos (5UL) /*!< CCU8 GCSC: S1DSC (Bit 5) */ 12692 #define CCU8_GCSC_S1DSC_Msk (0x20UL) /*!< CCU8 GCSC: S1DSC (Bitfield-Mask: 0x01) */ 12693 #define CCU8_GCSC_S1PSC_Pos (6UL) /*!< CCU8 GCSC: S1PSC (Bit 6) */ 12694 #define CCU8_GCSC_S1PSC_Msk (0x40UL) /*!< CCU8 GCSC: S1PSC (Bitfield-Mask: 0x01) */ 12695 #define CCU8_GCSC_S2SC_Pos (8UL) /*!< CCU8 GCSC: S2SC (Bit 8) */ 12696 #define CCU8_GCSC_S2SC_Msk (0x100UL) /*!< CCU8 GCSC: S2SC (Bitfield-Mask: 0x01) */ 12697 #define CCU8_GCSC_S2DSC_Pos (9UL) /*!< CCU8 GCSC: S2DSC (Bit 9) */ 12698 #define CCU8_GCSC_S2DSC_Msk (0x200UL) /*!< CCU8 GCSC: S2DSC (Bitfield-Mask: 0x01) */ 12699 #define CCU8_GCSC_S2PSC_Pos (10UL) /*!< CCU8 GCSC: S2PSC (Bit 10) */ 12700 #define CCU8_GCSC_S2PSC_Msk (0x400UL) /*!< CCU8 GCSC: S2PSC (Bitfield-Mask: 0x01) */ 12701 #define CCU8_GCSC_S3SC_Pos (12UL) /*!< CCU8 GCSC: S3SC (Bit 12) */ 12702 #define CCU8_GCSC_S3SC_Msk (0x1000UL) /*!< CCU8 GCSC: S3SC (Bitfield-Mask: 0x01) */ 12703 #define CCU8_GCSC_S3DSC_Pos (13UL) /*!< CCU8 GCSC: S3DSC (Bit 13) */ 12704 #define CCU8_GCSC_S3DSC_Msk (0x2000UL) /*!< CCU8 GCSC: S3DSC (Bitfield-Mask: 0x01) */ 12705 #define CCU8_GCSC_S3PSC_Pos (14UL) /*!< CCU8 GCSC: S3PSC (Bit 14) */ 12706 #define CCU8_GCSC_S3PSC_Msk (0x4000UL) /*!< CCU8 GCSC: S3PSC (Bitfield-Mask: 0x01) */ 12707 #define CCU8_GCSC_S0ST1C_Pos (16UL) /*!< CCU8 GCSC: S0ST1C (Bit 16) */ 12708 #define CCU8_GCSC_S0ST1C_Msk (0x10000UL) /*!< CCU8 GCSC: S0ST1C (Bitfield-Mask: 0x01) */ 12709 #define CCU8_GCSC_S1ST1C_Pos (17UL) /*!< CCU8 GCSC: S1ST1C (Bit 17) */ 12710 #define CCU8_GCSC_S1ST1C_Msk (0x20000UL) /*!< CCU8 GCSC: S1ST1C (Bitfield-Mask: 0x01) */ 12711 #define CCU8_GCSC_S2ST1C_Pos (18UL) /*!< CCU8 GCSC: S2ST1C (Bit 18) */ 12712 #define CCU8_GCSC_S2ST1C_Msk (0x40000UL) /*!< CCU8 GCSC: S2ST1C (Bitfield-Mask: 0x01) */ 12713 #define CCU8_GCSC_S3ST1C_Pos (19UL) /*!< CCU8 GCSC: S3ST1C (Bit 19) */ 12714 #define CCU8_GCSC_S3ST1C_Msk (0x80000UL) /*!< CCU8 GCSC: S3ST1C (Bitfield-Mask: 0x01) */ 12715 #define CCU8_GCSC_S0ST2C_Pos (20UL) /*!< CCU8 GCSC: S0ST2C (Bit 20) */ 12716 #define CCU8_GCSC_S0ST2C_Msk (0x100000UL) /*!< CCU8 GCSC: S0ST2C (Bitfield-Mask: 0x01) */ 12717 #define CCU8_GCSC_S1ST2C_Pos (21UL) /*!< CCU8 GCSC: S1ST2C (Bit 21) */ 12718 #define CCU8_GCSC_S1ST2C_Msk (0x200000UL) /*!< CCU8 GCSC: S1ST2C (Bitfield-Mask: 0x01) */ 12719 #define CCU8_GCSC_S2ST2C_Pos (22UL) /*!< CCU8 GCSC: S2ST2C (Bit 22) */ 12720 #define CCU8_GCSC_S2ST2C_Msk (0x400000UL) /*!< CCU8 GCSC: S2ST2C (Bitfield-Mask: 0x01) */ 12721 #define CCU8_GCSC_S3ST2C_Pos (23UL) /*!< CCU8 GCSC: S3ST2C (Bit 23) */ 12722 #define CCU8_GCSC_S3ST2C_Msk (0x800000UL) /*!< CCU8 GCSC: S3ST2C (Bitfield-Mask: 0x01) */ 12723 12724 /* ---------------------------------- CCU8_GCST --------------------------------- */ 12725 #define CCU8_GCST_S0SS_Pos (0UL) /*!< CCU8 GCST: S0SS (Bit 0) */ 12726 #define CCU8_GCST_S0SS_Msk (0x1UL) /*!< CCU8 GCST: S0SS (Bitfield-Mask: 0x01) */ 12727 #define CCU8_GCST_S0DSS_Pos (1UL) /*!< CCU8 GCST: S0DSS (Bit 1) */ 12728 #define CCU8_GCST_S0DSS_Msk (0x2UL) /*!< CCU8 GCST: S0DSS (Bitfield-Mask: 0x01) */ 12729 #define CCU8_GCST_S0PSS_Pos (2UL) /*!< CCU8 GCST: S0PSS (Bit 2) */ 12730 #define CCU8_GCST_S0PSS_Msk (0x4UL) /*!< CCU8 GCST: S0PSS (Bitfield-Mask: 0x01) */ 12731 #define CCU8_GCST_S1SS_Pos (4UL) /*!< CCU8 GCST: S1SS (Bit 4) */ 12732 #define CCU8_GCST_S1SS_Msk (0x10UL) /*!< CCU8 GCST: S1SS (Bitfield-Mask: 0x01) */ 12733 #define CCU8_GCST_S1DSS_Pos (5UL) /*!< CCU8 GCST: S1DSS (Bit 5) */ 12734 #define CCU8_GCST_S1DSS_Msk (0x20UL) /*!< CCU8 GCST: S1DSS (Bitfield-Mask: 0x01) */ 12735 #define CCU8_GCST_S1PSS_Pos (6UL) /*!< CCU8 GCST: S1PSS (Bit 6) */ 12736 #define CCU8_GCST_S1PSS_Msk (0x40UL) /*!< CCU8 GCST: S1PSS (Bitfield-Mask: 0x01) */ 12737 #define CCU8_GCST_S2SS_Pos (8UL) /*!< CCU8 GCST: S2SS (Bit 8) */ 12738 #define CCU8_GCST_S2SS_Msk (0x100UL) /*!< CCU8 GCST: S2SS (Bitfield-Mask: 0x01) */ 12739 #define CCU8_GCST_S2DSS_Pos (9UL) /*!< CCU8 GCST: S2DSS (Bit 9) */ 12740 #define CCU8_GCST_S2DSS_Msk (0x200UL) /*!< CCU8 GCST: S2DSS (Bitfield-Mask: 0x01) */ 12741 #define CCU8_GCST_S2PSS_Pos (10UL) /*!< CCU8 GCST: S2PSS (Bit 10) */ 12742 #define CCU8_GCST_S2PSS_Msk (0x400UL) /*!< CCU8 GCST: S2PSS (Bitfield-Mask: 0x01) */ 12743 #define CCU8_GCST_S3SS_Pos (12UL) /*!< CCU8 GCST: S3SS (Bit 12) */ 12744 #define CCU8_GCST_S3SS_Msk (0x1000UL) /*!< CCU8 GCST: S3SS (Bitfield-Mask: 0x01) */ 12745 #define CCU8_GCST_S3DSS_Pos (13UL) /*!< CCU8 GCST: S3DSS (Bit 13) */ 12746 #define CCU8_GCST_S3DSS_Msk (0x2000UL) /*!< CCU8 GCST: S3DSS (Bitfield-Mask: 0x01) */ 12747 #define CCU8_GCST_S3PSS_Pos (14UL) /*!< CCU8 GCST: S3PSS (Bit 14) */ 12748 #define CCU8_GCST_S3PSS_Msk (0x4000UL) /*!< CCU8 GCST: S3PSS (Bitfield-Mask: 0x01) */ 12749 #define CCU8_GCST_CC80ST1_Pos (16UL) /*!< CCU8 GCST: CC80ST1 (Bit 16) */ 12750 #define CCU8_GCST_CC80ST1_Msk (0x10000UL) /*!< CCU8 GCST: CC80ST1 (Bitfield-Mask: 0x01) */ 12751 #define CCU8_GCST_CC81ST1_Pos (17UL) /*!< CCU8 GCST: CC81ST1 (Bit 17) */ 12752 #define CCU8_GCST_CC81ST1_Msk (0x20000UL) /*!< CCU8 GCST: CC81ST1 (Bitfield-Mask: 0x01) */ 12753 #define CCU8_GCST_CC82ST1_Pos (18UL) /*!< CCU8 GCST: CC82ST1 (Bit 18) */ 12754 #define CCU8_GCST_CC82ST1_Msk (0x40000UL) /*!< CCU8 GCST: CC82ST1 (Bitfield-Mask: 0x01) */ 12755 #define CCU8_GCST_CC83ST1_Pos (19UL) /*!< CCU8 GCST: CC83ST1 (Bit 19) */ 12756 #define CCU8_GCST_CC83ST1_Msk (0x80000UL) /*!< CCU8 GCST: CC83ST1 (Bitfield-Mask: 0x01) */ 12757 #define CCU8_GCST_CC80ST2_Pos (20UL) /*!< CCU8 GCST: CC80ST2 (Bit 20) */ 12758 #define CCU8_GCST_CC80ST2_Msk (0x100000UL) /*!< CCU8 GCST: CC80ST2 (Bitfield-Mask: 0x01) */ 12759 #define CCU8_GCST_CC81ST2_Pos (21UL) /*!< CCU8 GCST: CC81ST2 (Bit 21) */ 12760 #define CCU8_GCST_CC81ST2_Msk (0x200000UL) /*!< CCU8 GCST: CC81ST2 (Bitfield-Mask: 0x01) */ 12761 #define CCU8_GCST_CC82ST2_Pos (22UL) /*!< CCU8 GCST: CC82ST2 (Bit 22) */ 12762 #define CCU8_GCST_CC82ST2_Msk (0x400000UL) /*!< CCU8 GCST: CC82ST2 (Bitfield-Mask: 0x01) */ 12763 #define CCU8_GCST_CC83ST2_Pos (23UL) /*!< CCU8 GCST: CC83ST2 (Bit 23) */ 12764 #define CCU8_GCST_CC83ST2_Msk (0x800000UL) /*!< CCU8 GCST: CC83ST2 (Bitfield-Mask: 0x01) */ 12765 12766 /* --------------------------------- CCU8_GPCHK --------------------------------- */ 12767 #define CCU8_GPCHK_PASE_Pos (0UL) /*!< CCU8 GPCHK: PASE (Bit 0) */ 12768 #define CCU8_GPCHK_PASE_Msk (0x1UL) /*!< CCU8 GPCHK: PASE (Bitfield-Mask: 0x01) */ 12769 #define CCU8_GPCHK_PACS_Pos (1UL) /*!< CCU8 GPCHK: PACS (Bit 1) */ 12770 #define CCU8_GPCHK_PACS_Msk (0x6UL) /*!< CCU8 GPCHK: PACS (Bitfield-Mask: 0x03) */ 12771 #define CCU8_GPCHK_PISEL_Pos (3UL) /*!< CCU8 GPCHK: PISEL (Bit 3) */ 12772 #define CCU8_GPCHK_PISEL_Msk (0x18UL) /*!< CCU8 GPCHK: PISEL (Bitfield-Mask: 0x03) */ 12773 #define CCU8_GPCHK_PCDS_Pos (5UL) /*!< CCU8 GPCHK: PCDS (Bit 5) */ 12774 #define CCU8_GPCHK_PCDS_Msk (0x60UL) /*!< CCU8 GPCHK: PCDS (Bitfield-Mask: 0x03) */ 12775 #define CCU8_GPCHK_PCTS_Pos (7UL) /*!< CCU8 GPCHK: PCTS (Bit 7) */ 12776 #define CCU8_GPCHK_PCTS_Msk (0x80UL) /*!< CCU8 GPCHK: PCTS (Bitfield-Mask: 0x01) */ 12777 #define CCU8_GPCHK_PCST_Pos (15UL) /*!< CCU8 GPCHK: PCST (Bit 15) */ 12778 #define CCU8_GPCHK_PCST_Msk (0x8000UL) /*!< CCU8 GPCHK: PCST (Bitfield-Mask: 0x01) */ 12779 #define CCU8_GPCHK_PCSEL0_Pos (16UL) /*!< CCU8 GPCHK: PCSEL0 (Bit 16) */ 12780 #define CCU8_GPCHK_PCSEL0_Msk (0xf0000UL) /*!< CCU8 GPCHK: PCSEL0 (Bitfield-Mask: 0x0f) */ 12781 #define CCU8_GPCHK_PCSEL1_Pos (20UL) /*!< CCU8 GPCHK: PCSEL1 (Bit 20) */ 12782 #define CCU8_GPCHK_PCSEL1_Msk (0xf00000UL) /*!< CCU8 GPCHK: PCSEL1 (Bitfield-Mask: 0x0f) */ 12783 #define CCU8_GPCHK_PCSEL2_Pos (24UL) /*!< CCU8 GPCHK: PCSEL2 (Bit 24) */ 12784 #define CCU8_GPCHK_PCSEL2_Msk (0xf000000UL) /*!< CCU8 GPCHK: PCSEL2 (Bitfield-Mask: 0x0f) */ 12785 #define CCU8_GPCHK_PCSEL3_Pos (28UL) /*!< CCU8 GPCHK: PCSEL3 (Bit 28) */ 12786 #define CCU8_GPCHK_PCSEL3_Msk (0xf0000000UL) /*!< CCU8 GPCHK: PCSEL3 (Bitfield-Mask: 0x0f) */ 12787 12788 /* ---------------------------------- CCU8_ECRD --------------------------------- */ 12789 #define CCU8_ECRD_CAPV_Pos (0UL) /*!< CCU8 ECRD: CAPV (Bit 0) */ 12790 #define CCU8_ECRD_CAPV_Msk (0xffffUL) /*!< CCU8 ECRD: CAPV (Bitfield-Mask: 0xffff) */ 12791 #define CCU8_ECRD_FPCV_Pos (16UL) /*!< CCU8 ECRD: FPCV (Bit 16) */ 12792 #define CCU8_ECRD_FPCV_Msk (0xf0000UL) /*!< CCU8 ECRD: FPCV (Bitfield-Mask: 0x0f) */ 12793 #define CCU8_ECRD_SPTR_Pos (20UL) /*!< CCU8 ECRD: SPTR (Bit 20) */ 12794 #define CCU8_ECRD_SPTR_Msk (0x300000UL) /*!< CCU8 ECRD: SPTR (Bitfield-Mask: 0x03) */ 12795 #define CCU8_ECRD_VPTR_Pos (22UL) /*!< CCU8 ECRD: VPTR (Bit 22) */ 12796 #define CCU8_ECRD_VPTR_Msk (0xc00000UL) /*!< CCU8 ECRD: VPTR (Bitfield-Mask: 0x03) */ 12797 #define CCU8_ECRD_FFL_Pos (24UL) /*!< CCU8 ECRD: FFL (Bit 24) */ 12798 #define CCU8_ECRD_FFL_Msk (0x1000000UL) /*!< CCU8 ECRD: FFL (Bitfield-Mask: 0x01) */ 12799 12800 /* ---------------------------------- CCU8_MIDR --------------------------------- */ 12801 #define CCU8_MIDR_MODR_Pos (0UL) /*!< CCU8 MIDR: MODR (Bit 0) */ 12802 #define CCU8_MIDR_MODR_Msk (0xffUL) /*!< CCU8 MIDR: MODR (Bitfield-Mask: 0xff) */ 12803 #define CCU8_MIDR_MODT_Pos (8UL) /*!< CCU8 MIDR: MODT (Bit 8) */ 12804 #define CCU8_MIDR_MODT_Msk (0xff00UL) /*!< CCU8 MIDR: MODT (Bitfield-Mask: 0xff) */ 12805 #define CCU8_MIDR_MODN_Pos (16UL) /*!< CCU8 MIDR: MODN (Bit 16) */ 12806 #define CCU8_MIDR_MODN_Msk (0xffff0000UL) /*!< CCU8 MIDR: MODN (Bitfield-Mask: 0xffff) */ 12807 12808 12809 /* ================================================================================ */ 12810 /* ================ Group 'CCU8_CC8' Position & Mask ================ */ 12811 /* ================================================================================ */ 12812 12813 12814 /* -------------------------------- CCU8_CC8_INS -------------------------------- */ 12815 #define CCU8_CC8_INS_EV0IS_Pos (0UL) /*!< CCU8_CC8 INS: EV0IS (Bit 0) */ 12816 #define CCU8_CC8_INS_EV0IS_Msk (0xfUL) /*!< CCU8_CC8 INS: EV0IS (Bitfield-Mask: 0x0f) */ 12817 #define CCU8_CC8_INS_EV1IS_Pos (4UL) /*!< CCU8_CC8 INS: EV1IS (Bit 4) */ 12818 #define CCU8_CC8_INS_EV1IS_Msk (0xf0UL) /*!< CCU8_CC8 INS: EV1IS (Bitfield-Mask: 0x0f) */ 12819 #define CCU8_CC8_INS_EV2IS_Pos (8UL) /*!< CCU8_CC8 INS: EV2IS (Bit 8) */ 12820 #define CCU8_CC8_INS_EV2IS_Msk (0xf00UL) /*!< CCU8_CC8 INS: EV2IS (Bitfield-Mask: 0x0f) */ 12821 #define CCU8_CC8_INS_EV0EM_Pos (16UL) /*!< CCU8_CC8 INS: EV0EM (Bit 16) */ 12822 #define CCU8_CC8_INS_EV0EM_Msk (0x30000UL) /*!< CCU8_CC8 INS: EV0EM (Bitfield-Mask: 0x03) */ 12823 #define CCU8_CC8_INS_EV1EM_Pos (18UL) /*!< CCU8_CC8 INS: EV1EM (Bit 18) */ 12824 #define CCU8_CC8_INS_EV1EM_Msk (0xc0000UL) /*!< CCU8_CC8 INS: EV1EM (Bitfield-Mask: 0x03) */ 12825 #define CCU8_CC8_INS_EV2EM_Pos (20UL) /*!< CCU8_CC8 INS: EV2EM (Bit 20) */ 12826 #define CCU8_CC8_INS_EV2EM_Msk (0x300000UL) /*!< CCU8_CC8 INS: EV2EM (Bitfield-Mask: 0x03) */ 12827 #define CCU8_CC8_INS_EV0LM_Pos (22UL) /*!< CCU8_CC8 INS: EV0LM (Bit 22) */ 12828 #define CCU8_CC8_INS_EV0LM_Msk (0x400000UL) /*!< CCU8_CC8 INS: EV0LM (Bitfield-Mask: 0x01) */ 12829 #define CCU8_CC8_INS_EV1LM_Pos (23UL) /*!< CCU8_CC8 INS: EV1LM (Bit 23) */ 12830 #define CCU8_CC8_INS_EV1LM_Msk (0x800000UL) /*!< CCU8_CC8 INS: EV1LM (Bitfield-Mask: 0x01) */ 12831 #define CCU8_CC8_INS_EV2LM_Pos (24UL) /*!< CCU8_CC8 INS: EV2LM (Bit 24) */ 12832 #define CCU8_CC8_INS_EV2LM_Msk (0x1000000UL) /*!< CCU8_CC8 INS: EV2LM (Bitfield-Mask: 0x01) */ 12833 #define CCU8_CC8_INS_LPF0M_Pos (25UL) /*!< CCU8_CC8 INS: LPF0M (Bit 25) */ 12834 #define CCU8_CC8_INS_LPF0M_Msk (0x6000000UL) /*!< CCU8_CC8 INS: LPF0M (Bitfield-Mask: 0x03) */ 12835 #define CCU8_CC8_INS_LPF1M_Pos (27UL) /*!< CCU8_CC8 INS: LPF1M (Bit 27) */ 12836 #define CCU8_CC8_INS_LPF1M_Msk (0x18000000UL) /*!< CCU8_CC8 INS: LPF1M (Bitfield-Mask: 0x03) */ 12837 #define CCU8_CC8_INS_LPF2M_Pos (29UL) /*!< CCU8_CC8 INS: LPF2M (Bit 29) */ 12838 #define CCU8_CC8_INS_LPF2M_Msk (0x60000000UL) /*!< CCU8_CC8 INS: LPF2M (Bitfield-Mask: 0x03) */ 12839 12840 /* -------------------------------- CCU8_CC8_CMC -------------------------------- */ 12841 #define CCU8_CC8_CMC_STRTS_Pos (0UL) /*!< CCU8_CC8 CMC: STRTS (Bit 0) */ 12842 #define CCU8_CC8_CMC_STRTS_Msk (0x3UL) /*!< CCU8_CC8 CMC: STRTS (Bitfield-Mask: 0x03) */ 12843 #define CCU8_CC8_CMC_ENDS_Pos (2UL) /*!< CCU8_CC8 CMC: ENDS (Bit 2) */ 12844 #define CCU8_CC8_CMC_ENDS_Msk (0xcUL) /*!< CCU8_CC8 CMC: ENDS (Bitfield-Mask: 0x03) */ 12845 #define CCU8_CC8_CMC_CAP0S_Pos (4UL) /*!< CCU8_CC8 CMC: CAP0S (Bit 4) */ 12846 #define CCU8_CC8_CMC_CAP0S_Msk (0x30UL) /*!< CCU8_CC8 CMC: CAP0S (Bitfield-Mask: 0x03) */ 12847 #define CCU8_CC8_CMC_CAP1S_Pos (6UL) /*!< CCU8_CC8 CMC: CAP1S (Bit 6) */ 12848 #define CCU8_CC8_CMC_CAP1S_Msk (0xc0UL) /*!< CCU8_CC8 CMC: CAP1S (Bitfield-Mask: 0x03) */ 12849 #define CCU8_CC8_CMC_GATES_Pos (8UL) /*!< CCU8_CC8 CMC: GATES (Bit 8) */ 12850 #define CCU8_CC8_CMC_GATES_Msk (0x300UL) /*!< CCU8_CC8 CMC: GATES (Bitfield-Mask: 0x03) */ 12851 #define CCU8_CC8_CMC_UDS_Pos (10UL) /*!< CCU8_CC8 CMC: UDS (Bit 10) */ 12852 #define CCU8_CC8_CMC_UDS_Msk (0xc00UL) /*!< CCU8_CC8 CMC: UDS (Bitfield-Mask: 0x03) */ 12853 #define CCU8_CC8_CMC_LDS_Pos (12UL) /*!< CCU8_CC8 CMC: LDS (Bit 12) */ 12854 #define CCU8_CC8_CMC_LDS_Msk (0x3000UL) /*!< CCU8_CC8 CMC: LDS (Bitfield-Mask: 0x03) */ 12855 #define CCU8_CC8_CMC_CNTS_Pos (14UL) /*!< CCU8_CC8 CMC: CNTS (Bit 14) */ 12856 #define CCU8_CC8_CMC_CNTS_Msk (0xc000UL) /*!< CCU8_CC8 CMC: CNTS (Bitfield-Mask: 0x03) */ 12857 #define CCU8_CC8_CMC_OFS_Pos (16UL) /*!< CCU8_CC8 CMC: OFS (Bit 16) */ 12858 #define CCU8_CC8_CMC_OFS_Msk (0x10000UL) /*!< CCU8_CC8 CMC: OFS (Bitfield-Mask: 0x01) */ 12859 #define CCU8_CC8_CMC_TS_Pos (17UL) /*!< CCU8_CC8 CMC: TS (Bit 17) */ 12860 #define CCU8_CC8_CMC_TS_Msk (0x20000UL) /*!< CCU8_CC8 CMC: TS (Bitfield-Mask: 0x01) */ 12861 #define CCU8_CC8_CMC_MOS_Pos (18UL) /*!< CCU8_CC8 CMC: MOS (Bit 18) */ 12862 #define CCU8_CC8_CMC_MOS_Msk (0xc0000UL) /*!< CCU8_CC8 CMC: MOS (Bitfield-Mask: 0x03) */ 12863 #define CCU8_CC8_CMC_TCE_Pos (20UL) /*!< CCU8_CC8 CMC: TCE (Bit 20) */ 12864 #define CCU8_CC8_CMC_TCE_Msk (0x100000UL) /*!< CCU8_CC8 CMC: TCE (Bitfield-Mask: 0x01) */ 12865 12866 /* -------------------------------- CCU8_CC8_TCST ------------------------------- */ 12867 #define CCU8_CC8_TCST_TRB_Pos (0UL) /*!< CCU8_CC8 TCST: TRB (Bit 0) */ 12868 #define CCU8_CC8_TCST_TRB_Msk (0x1UL) /*!< CCU8_CC8 TCST: TRB (Bitfield-Mask: 0x01) */ 12869 #define CCU8_CC8_TCST_CDIR_Pos (1UL) /*!< CCU8_CC8 TCST: CDIR (Bit 1) */ 12870 #define CCU8_CC8_TCST_CDIR_Msk (0x2UL) /*!< CCU8_CC8 TCST: CDIR (Bitfield-Mask: 0x01) */ 12871 #define CCU8_CC8_TCST_DTR1_Pos (3UL) /*!< CCU8_CC8 TCST: DTR1 (Bit 3) */ 12872 #define CCU8_CC8_TCST_DTR1_Msk (0x8UL) /*!< CCU8_CC8 TCST: DTR1 (Bitfield-Mask: 0x01) */ 12873 #define CCU8_CC8_TCST_DTR2_Pos (4UL) /*!< CCU8_CC8 TCST: DTR2 (Bit 4) */ 12874 #define CCU8_CC8_TCST_DTR2_Msk (0x10UL) /*!< CCU8_CC8 TCST: DTR2 (Bitfield-Mask: 0x01) */ 12875 12876 /* ------------------------------- CCU8_CC8_TCSET ------------------------------- */ 12877 #define CCU8_CC8_TCSET_TRBS_Pos (0UL) /*!< CCU8_CC8 TCSET: TRBS (Bit 0) */ 12878 #define CCU8_CC8_TCSET_TRBS_Msk (0x1UL) /*!< CCU8_CC8 TCSET: TRBS (Bitfield-Mask: 0x01) */ 12879 12880 /* ------------------------------- CCU8_CC8_TCCLR ------------------------------- */ 12881 #define CCU8_CC8_TCCLR_TRBC_Pos (0UL) /*!< CCU8_CC8 TCCLR: TRBC (Bit 0) */ 12882 #define CCU8_CC8_TCCLR_TRBC_Msk (0x1UL) /*!< CCU8_CC8 TCCLR: TRBC (Bitfield-Mask: 0x01) */ 12883 #define CCU8_CC8_TCCLR_TCC_Pos (1UL) /*!< CCU8_CC8 TCCLR: TCC (Bit 1) */ 12884 #define CCU8_CC8_TCCLR_TCC_Msk (0x2UL) /*!< CCU8_CC8 TCCLR: TCC (Bitfield-Mask: 0x01) */ 12885 #define CCU8_CC8_TCCLR_DITC_Pos (2UL) /*!< CCU8_CC8 TCCLR: DITC (Bit 2) */ 12886 #define CCU8_CC8_TCCLR_DITC_Msk (0x4UL) /*!< CCU8_CC8 TCCLR: DITC (Bitfield-Mask: 0x01) */ 12887 #define CCU8_CC8_TCCLR_DTC1C_Pos (3UL) /*!< CCU8_CC8 TCCLR: DTC1C (Bit 3) */ 12888 #define CCU8_CC8_TCCLR_DTC1C_Msk (0x8UL) /*!< CCU8_CC8 TCCLR: DTC1C (Bitfield-Mask: 0x01) */ 12889 #define CCU8_CC8_TCCLR_DTC2C_Pos (4UL) /*!< CCU8_CC8 TCCLR: DTC2C (Bit 4) */ 12890 #define CCU8_CC8_TCCLR_DTC2C_Msk (0x10UL) /*!< CCU8_CC8 TCCLR: DTC2C (Bitfield-Mask: 0x01) */ 12891 12892 /* --------------------------------- CCU8_CC8_TC -------------------------------- */ 12893 #define CCU8_CC8_TC_TCM_Pos (0UL) /*!< CCU8_CC8 TC: TCM (Bit 0) */ 12894 #define CCU8_CC8_TC_TCM_Msk (0x1UL) /*!< CCU8_CC8 TC: TCM (Bitfield-Mask: 0x01) */ 12895 #define CCU8_CC8_TC_TSSM_Pos (1UL) /*!< CCU8_CC8 TC: TSSM (Bit 1) */ 12896 #define CCU8_CC8_TC_TSSM_Msk (0x2UL) /*!< CCU8_CC8 TC: TSSM (Bitfield-Mask: 0x01) */ 12897 #define CCU8_CC8_TC_CLST_Pos (2UL) /*!< CCU8_CC8 TC: CLST (Bit 2) */ 12898 #define CCU8_CC8_TC_CLST_Msk (0x4UL) /*!< CCU8_CC8 TC: CLST (Bitfield-Mask: 0x01) */ 12899 #define CCU8_CC8_TC_CMOD_Pos (3UL) /*!< CCU8_CC8 TC: CMOD (Bit 3) */ 12900 #define CCU8_CC8_TC_CMOD_Msk (0x8UL) /*!< CCU8_CC8 TC: CMOD (Bitfield-Mask: 0x01) */ 12901 #define CCU8_CC8_TC_ECM_Pos (4UL) /*!< CCU8_CC8 TC: ECM (Bit 4) */ 12902 #define CCU8_CC8_TC_ECM_Msk (0x10UL) /*!< CCU8_CC8 TC: ECM (Bitfield-Mask: 0x01) */ 12903 #define CCU8_CC8_TC_CAPC_Pos (5UL) /*!< CCU8_CC8 TC: CAPC (Bit 5) */ 12904 #define CCU8_CC8_TC_CAPC_Msk (0x60UL) /*!< CCU8_CC8 TC: CAPC (Bitfield-Mask: 0x03) */ 12905 #define CCU8_CC8_TC_TLS_Pos (7UL) /*!< CCU8_CC8 TC: TLS (Bit 7) */ 12906 #define CCU8_CC8_TC_TLS_Msk (0x80UL) /*!< CCU8_CC8 TC: TLS (Bitfield-Mask: 0x01) */ 12907 #define CCU8_CC8_TC_ENDM_Pos (8UL) /*!< CCU8_CC8 TC: ENDM (Bit 8) */ 12908 #define CCU8_CC8_TC_ENDM_Msk (0x300UL) /*!< CCU8_CC8 TC: ENDM (Bitfield-Mask: 0x03) */ 12909 #define CCU8_CC8_TC_STRM_Pos (10UL) /*!< CCU8_CC8 TC: STRM (Bit 10) */ 12910 #define CCU8_CC8_TC_STRM_Msk (0x400UL) /*!< CCU8_CC8 TC: STRM (Bitfield-Mask: 0x01) */ 12911 #define CCU8_CC8_TC_SCE_Pos (11UL) /*!< CCU8_CC8 TC: SCE (Bit 11) */ 12912 #define CCU8_CC8_TC_SCE_Msk (0x800UL) /*!< CCU8_CC8 TC: SCE (Bitfield-Mask: 0x01) */ 12913 #define CCU8_CC8_TC_CCS_Pos (12UL) /*!< CCU8_CC8 TC: CCS (Bit 12) */ 12914 #define CCU8_CC8_TC_CCS_Msk (0x1000UL) /*!< CCU8_CC8 TC: CCS (Bitfield-Mask: 0x01) */ 12915 #define CCU8_CC8_TC_DITHE_Pos (13UL) /*!< CCU8_CC8 TC: DITHE (Bit 13) */ 12916 #define CCU8_CC8_TC_DITHE_Msk (0x6000UL) /*!< CCU8_CC8 TC: DITHE (Bitfield-Mask: 0x03) */ 12917 #define CCU8_CC8_TC_DIM_Pos (15UL) /*!< CCU8_CC8 TC: DIM (Bit 15) */ 12918 #define CCU8_CC8_TC_DIM_Msk (0x8000UL) /*!< CCU8_CC8 TC: DIM (Bitfield-Mask: 0x01) */ 12919 #define CCU8_CC8_TC_FPE_Pos (16UL) /*!< CCU8_CC8 TC: FPE (Bit 16) */ 12920 #define CCU8_CC8_TC_FPE_Msk (0x10000UL) /*!< CCU8_CC8 TC: FPE (Bitfield-Mask: 0x01) */ 12921 #define CCU8_CC8_TC_TRAPE0_Pos (17UL) /*!< CCU8_CC8 TC: TRAPE0 (Bit 17) */ 12922 #define CCU8_CC8_TC_TRAPE0_Msk (0x20000UL) /*!< CCU8_CC8 TC: TRAPE0 (Bitfield-Mask: 0x01) */ 12923 #define CCU8_CC8_TC_TRAPE1_Pos (18UL) /*!< CCU8_CC8 TC: TRAPE1 (Bit 18) */ 12924 #define CCU8_CC8_TC_TRAPE1_Msk (0x40000UL) /*!< CCU8_CC8 TC: TRAPE1 (Bitfield-Mask: 0x01) */ 12925 #define CCU8_CC8_TC_TRAPE2_Pos (19UL) /*!< CCU8_CC8 TC: TRAPE2 (Bit 19) */ 12926 #define CCU8_CC8_TC_TRAPE2_Msk (0x80000UL) /*!< CCU8_CC8 TC: TRAPE2 (Bitfield-Mask: 0x01) */ 12927 #define CCU8_CC8_TC_TRAPE3_Pos (20UL) /*!< CCU8_CC8 TC: TRAPE3 (Bit 20) */ 12928 #define CCU8_CC8_TC_TRAPE3_Msk (0x100000UL) /*!< CCU8_CC8 TC: TRAPE3 (Bitfield-Mask: 0x01) */ 12929 #define CCU8_CC8_TC_TRPSE_Pos (21UL) /*!< CCU8_CC8 TC: TRPSE (Bit 21) */ 12930 #define CCU8_CC8_TC_TRPSE_Msk (0x200000UL) /*!< CCU8_CC8 TC: TRPSE (Bitfield-Mask: 0x01) */ 12931 #define CCU8_CC8_TC_TRPSW_Pos (22UL) /*!< CCU8_CC8 TC: TRPSW (Bit 22) */ 12932 #define CCU8_CC8_TC_TRPSW_Msk (0x400000UL) /*!< CCU8_CC8 TC: TRPSW (Bitfield-Mask: 0x01) */ 12933 #define CCU8_CC8_TC_EMS_Pos (23UL) /*!< CCU8_CC8 TC: EMS (Bit 23) */ 12934 #define CCU8_CC8_TC_EMS_Msk (0x800000UL) /*!< CCU8_CC8 TC: EMS (Bitfield-Mask: 0x01) */ 12935 #define CCU8_CC8_TC_EMT_Pos (24UL) /*!< CCU8_CC8 TC: EMT (Bit 24) */ 12936 #define CCU8_CC8_TC_EMT_Msk (0x1000000UL) /*!< CCU8_CC8 TC: EMT (Bitfield-Mask: 0x01) */ 12937 #define CCU8_CC8_TC_MCME1_Pos (25UL) /*!< CCU8_CC8 TC: MCME1 (Bit 25) */ 12938 #define CCU8_CC8_TC_MCME1_Msk (0x2000000UL) /*!< CCU8_CC8 TC: MCME1 (Bitfield-Mask: 0x01) */ 12939 #define CCU8_CC8_TC_MCME2_Pos (26UL) /*!< CCU8_CC8 TC: MCME2 (Bit 26) */ 12940 #define CCU8_CC8_TC_MCME2_Msk (0x4000000UL) /*!< CCU8_CC8 TC: MCME2 (Bitfield-Mask: 0x01) */ 12941 #define CCU8_CC8_TC_EME_Pos (27UL) /*!< CCU8_CC8 TC: EME (Bit 27) */ 12942 #define CCU8_CC8_TC_EME_Msk (0x18000000UL) /*!< CCU8_CC8 TC: EME (Bitfield-Mask: 0x03) */ 12943 #define CCU8_CC8_TC_STOS_Pos (29UL) /*!< CCU8_CC8 TC: STOS (Bit 29) */ 12944 #define CCU8_CC8_TC_STOS_Msk (0x60000000UL) /*!< CCU8_CC8 TC: STOS (Bitfield-Mask: 0x03) */ 12945 12946 /* -------------------------------- CCU8_CC8_PSL -------------------------------- */ 12947 #define CCU8_CC8_PSL_PSL11_Pos (0UL) /*!< CCU8_CC8 PSL: PSL11 (Bit 0) */ 12948 #define CCU8_CC8_PSL_PSL11_Msk (0x1UL) /*!< CCU8_CC8 PSL: PSL11 (Bitfield-Mask: 0x01) */ 12949 #define CCU8_CC8_PSL_PSL12_Pos (1UL) /*!< CCU8_CC8 PSL: PSL12 (Bit 1) */ 12950 #define CCU8_CC8_PSL_PSL12_Msk (0x2UL) /*!< CCU8_CC8 PSL: PSL12 (Bitfield-Mask: 0x01) */ 12951 #define CCU8_CC8_PSL_PSL21_Pos (2UL) /*!< CCU8_CC8 PSL: PSL21 (Bit 2) */ 12952 #define CCU8_CC8_PSL_PSL21_Msk (0x4UL) /*!< CCU8_CC8 PSL: PSL21 (Bitfield-Mask: 0x01) */ 12953 #define CCU8_CC8_PSL_PSL22_Pos (3UL) /*!< CCU8_CC8 PSL: PSL22 (Bit 3) */ 12954 #define CCU8_CC8_PSL_PSL22_Msk (0x8UL) /*!< CCU8_CC8 PSL: PSL22 (Bitfield-Mask: 0x01) */ 12955 12956 /* -------------------------------- CCU8_CC8_DIT -------------------------------- */ 12957 #define CCU8_CC8_DIT_DCV_Pos (0UL) /*!< CCU8_CC8 DIT: DCV (Bit 0) */ 12958 #define CCU8_CC8_DIT_DCV_Msk (0xfUL) /*!< CCU8_CC8 DIT: DCV (Bitfield-Mask: 0x0f) */ 12959 #define CCU8_CC8_DIT_DCNT_Pos (8UL) /*!< CCU8_CC8 DIT: DCNT (Bit 8) */ 12960 #define CCU8_CC8_DIT_DCNT_Msk (0xf00UL) /*!< CCU8_CC8 DIT: DCNT (Bitfield-Mask: 0x0f) */ 12961 12962 /* -------------------------------- CCU8_CC8_DITS ------------------------------- */ 12963 #define CCU8_CC8_DITS_DCVS_Pos (0UL) /*!< CCU8_CC8 DITS: DCVS (Bit 0) */ 12964 #define CCU8_CC8_DITS_DCVS_Msk (0xfUL) /*!< CCU8_CC8 DITS: DCVS (Bitfield-Mask: 0x0f) */ 12965 12966 /* -------------------------------- CCU8_CC8_PSC -------------------------------- */ 12967 #define CCU8_CC8_PSC_PSIV_Pos (0UL) /*!< CCU8_CC8 PSC: PSIV (Bit 0) */ 12968 #define CCU8_CC8_PSC_PSIV_Msk (0xfUL) /*!< CCU8_CC8 PSC: PSIV (Bitfield-Mask: 0x0f) */ 12969 12970 /* -------------------------------- CCU8_CC8_FPC -------------------------------- */ 12971 #define CCU8_CC8_FPC_PCMP_Pos (0UL) /*!< CCU8_CC8 FPC: PCMP (Bit 0) */ 12972 #define CCU8_CC8_FPC_PCMP_Msk (0xfUL) /*!< CCU8_CC8 FPC: PCMP (Bitfield-Mask: 0x0f) */ 12973 #define CCU8_CC8_FPC_PVAL_Pos (8UL) /*!< CCU8_CC8 FPC: PVAL (Bit 8) */ 12974 #define CCU8_CC8_FPC_PVAL_Msk (0xf00UL) /*!< CCU8_CC8 FPC: PVAL (Bitfield-Mask: 0x0f) */ 12975 12976 /* -------------------------------- CCU8_CC8_FPCS ------------------------------- */ 12977 #define CCU8_CC8_FPCS_PCMP_Pos (0UL) /*!< CCU8_CC8 FPCS: PCMP (Bit 0) */ 12978 #define CCU8_CC8_FPCS_PCMP_Msk (0xfUL) /*!< CCU8_CC8 FPCS: PCMP (Bitfield-Mask: 0x0f) */ 12979 12980 /* --------------------------------- CCU8_CC8_PR -------------------------------- */ 12981 #define CCU8_CC8_PR_PR_Pos (0UL) /*!< CCU8_CC8 PR: PR (Bit 0) */ 12982 #define CCU8_CC8_PR_PR_Msk (0xffffUL) /*!< CCU8_CC8 PR: PR (Bitfield-Mask: 0xffff) */ 12983 12984 /* -------------------------------- CCU8_CC8_PRS -------------------------------- */ 12985 #define CCU8_CC8_PRS_PRS_Pos (0UL) /*!< CCU8_CC8 PRS: PRS (Bit 0) */ 12986 #define CCU8_CC8_PRS_PRS_Msk (0xffffUL) /*!< CCU8_CC8 PRS: PRS (Bitfield-Mask: 0xffff) */ 12987 12988 /* -------------------------------- CCU8_CC8_CR1 -------------------------------- */ 12989 #define CCU8_CC8_CR1_CR1_Pos (0UL) /*!< CCU8_CC8 CR1: CR1 (Bit 0) */ 12990 #define CCU8_CC8_CR1_CR1_Msk (0xffffUL) /*!< CCU8_CC8 CR1: CR1 (Bitfield-Mask: 0xffff) */ 12991 12992 /* -------------------------------- CCU8_CC8_CR1S ------------------------------- */ 12993 #define CCU8_CC8_CR1S_CR1S_Pos (0UL) /*!< CCU8_CC8 CR1S: CR1S (Bit 0) */ 12994 #define CCU8_CC8_CR1S_CR1S_Msk (0xffffUL) /*!< CCU8_CC8 CR1S: CR1S (Bitfield-Mask: 0xffff) */ 12995 12996 /* -------------------------------- CCU8_CC8_CR2 -------------------------------- */ 12997 #define CCU8_CC8_CR2_CR2_Pos (0UL) /*!< CCU8_CC8 CR2: CR2 (Bit 0) */ 12998 #define CCU8_CC8_CR2_CR2_Msk (0xffffUL) /*!< CCU8_CC8 CR2: CR2 (Bitfield-Mask: 0xffff) */ 12999 13000 /* -------------------------------- CCU8_CC8_CR2S ------------------------------- */ 13001 #define CCU8_CC8_CR2S_CR2S_Pos (0UL) /*!< CCU8_CC8 CR2S: CR2S (Bit 0) */ 13002 #define CCU8_CC8_CR2S_CR2S_Msk (0xffffUL) /*!< CCU8_CC8 CR2S: CR2S (Bitfield-Mask: 0xffff) */ 13003 13004 /* -------------------------------- CCU8_CC8_CHC -------------------------------- */ 13005 #define CCU8_CC8_CHC_ASE_Pos (0UL) /*!< CCU8_CC8 CHC: ASE (Bit 0) */ 13006 #define CCU8_CC8_CHC_ASE_Msk (0x1UL) /*!< CCU8_CC8 CHC: ASE (Bitfield-Mask: 0x01) */ 13007 #define CCU8_CC8_CHC_OCS1_Pos (1UL) /*!< CCU8_CC8 CHC: OCS1 (Bit 1) */ 13008 #define CCU8_CC8_CHC_OCS1_Msk (0x2UL) /*!< CCU8_CC8 CHC: OCS1 (Bitfield-Mask: 0x01) */ 13009 #define CCU8_CC8_CHC_OCS2_Pos (2UL) /*!< CCU8_CC8 CHC: OCS2 (Bit 2) */ 13010 #define CCU8_CC8_CHC_OCS2_Msk (0x4UL) /*!< CCU8_CC8 CHC: OCS2 (Bitfield-Mask: 0x01) */ 13011 #define CCU8_CC8_CHC_OCS3_Pos (3UL) /*!< CCU8_CC8 CHC: OCS3 (Bit 3) */ 13012 #define CCU8_CC8_CHC_OCS3_Msk (0x8UL) /*!< CCU8_CC8 CHC: OCS3 (Bitfield-Mask: 0x01) */ 13013 #define CCU8_CC8_CHC_OCS4_Pos (4UL) /*!< CCU8_CC8 CHC: OCS4 (Bit 4) */ 13014 #define CCU8_CC8_CHC_OCS4_Msk (0x10UL) /*!< CCU8_CC8 CHC: OCS4 (Bitfield-Mask: 0x01) */ 13015 13016 /* -------------------------------- CCU8_CC8_DTC -------------------------------- */ 13017 #define CCU8_CC8_DTC_DTE1_Pos (0UL) /*!< CCU8_CC8 DTC: DTE1 (Bit 0) */ 13018 #define CCU8_CC8_DTC_DTE1_Msk (0x1UL) /*!< CCU8_CC8 DTC: DTE1 (Bitfield-Mask: 0x01) */ 13019 #define CCU8_CC8_DTC_DTE2_Pos (1UL) /*!< CCU8_CC8 DTC: DTE2 (Bit 1) */ 13020 #define CCU8_CC8_DTC_DTE2_Msk (0x2UL) /*!< CCU8_CC8 DTC: DTE2 (Bitfield-Mask: 0x01) */ 13021 #define CCU8_CC8_DTC_DCEN1_Pos (2UL) /*!< CCU8_CC8 DTC: DCEN1 (Bit 2) */ 13022 #define CCU8_CC8_DTC_DCEN1_Msk (0x4UL) /*!< CCU8_CC8 DTC: DCEN1 (Bitfield-Mask: 0x01) */ 13023 #define CCU8_CC8_DTC_DCEN2_Pos (3UL) /*!< CCU8_CC8 DTC: DCEN2 (Bit 3) */ 13024 #define CCU8_CC8_DTC_DCEN2_Msk (0x8UL) /*!< CCU8_CC8 DTC: DCEN2 (Bitfield-Mask: 0x01) */ 13025 #define CCU8_CC8_DTC_DCEN3_Pos (4UL) /*!< CCU8_CC8 DTC: DCEN3 (Bit 4) */ 13026 #define CCU8_CC8_DTC_DCEN3_Msk (0x10UL) /*!< CCU8_CC8 DTC: DCEN3 (Bitfield-Mask: 0x01) */ 13027 #define CCU8_CC8_DTC_DCEN4_Pos (5UL) /*!< CCU8_CC8 DTC: DCEN4 (Bit 5) */ 13028 #define CCU8_CC8_DTC_DCEN4_Msk (0x20UL) /*!< CCU8_CC8 DTC: DCEN4 (Bitfield-Mask: 0x01) */ 13029 #define CCU8_CC8_DTC_DTCC_Pos (6UL) /*!< CCU8_CC8 DTC: DTCC (Bit 6) */ 13030 #define CCU8_CC8_DTC_DTCC_Msk (0xc0UL) /*!< CCU8_CC8 DTC: DTCC (Bitfield-Mask: 0x03) */ 13031 13032 /* -------------------------------- CCU8_CC8_DC1R ------------------------------- */ 13033 #define CCU8_CC8_DC1R_DT1R_Pos (0UL) /*!< CCU8_CC8 DC1R: DT1R (Bit 0) */ 13034 #define CCU8_CC8_DC1R_DT1R_Msk (0xffUL) /*!< CCU8_CC8 DC1R: DT1R (Bitfield-Mask: 0xff) */ 13035 #define CCU8_CC8_DC1R_DT1F_Pos (8UL) /*!< CCU8_CC8 DC1R: DT1F (Bit 8) */ 13036 #define CCU8_CC8_DC1R_DT1F_Msk (0xff00UL) /*!< CCU8_CC8 DC1R: DT1F (Bitfield-Mask: 0xff) */ 13037 13038 /* -------------------------------- CCU8_CC8_DC2R ------------------------------- */ 13039 #define CCU8_CC8_DC2R_DT2R_Pos (0UL) /*!< CCU8_CC8 DC2R: DT2R (Bit 0) */ 13040 #define CCU8_CC8_DC2R_DT2R_Msk (0xffUL) /*!< CCU8_CC8 DC2R: DT2R (Bitfield-Mask: 0xff) */ 13041 #define CCU8_CC8_DC2R_DT2F_Pos (8UL) /*!< CCU8_CC8 DC2R: DT2F (Bit 8) */ 13042 #define CCU8_CC8_DC2R_DT2F_Msk (0xff00UL) /*!< CCU8_CC8 DC2R: DT2F (Bitfield-Mask: 0xff) */ 13043 13044 /* ------------------------------- CCU8_CC8_TIMER ------------------------------- */ 13045 #define CCU8_CC8_TIMER_TVAL_Pos (0UL) /*!< CCU8_CC8 TIMER: TVAL (Bit 0) */ 13046 #define CCU8_CC8_TIMER_TVAL_Msk (0xffffUL) /*!< CCU8_CC8 TIMER: TVAL (Bitfield-Mask: 0xffff) */ 13047 13048 /* --------------------------------- CCU8_CC8_CV -------------------------------- */ 13049 #define CCU8_CC8_CV_CAPTV_Pos (0UL) /*!< CCU8_CC8 CV: CAPTV (Bit 0) */ 13050 #define CCU8_CC8_CV_CAPTV_Msk (0xffffUL) /*!< CCU8_CC8 CV: CAPTV (Bitfield-Mask: 0xffff) */ 13051 #define CCU8_CC8_CV_FPCV_Pos (16UL) /*!< CCU8_CC8 CV: FPCV (Bit 16) */ 13052 #define CCU8_CC8_CV_FPCV_Msk (0xf0000UL) /*!< CCU8_CC8 CV: FPCV (Bitfield-Mask: 0x0f) */ 13053 #define CCU8_CC8_CV_FFL_Pos (20UL) /*!< CCU8_CC8 CV: FFL (Bit 20) */ 13054 #define CCU8_CC8_CV_FFL_Msk (0x100000UL) /*!< CCU8_CC8 CV: FFL (Bitfield-Mask: 0x01) */ 13055 13056 /* -------------------------------- CCU8_CC8_INTS ------------------------------- */ 13057 #define CCU8_CC8_INTS_PMUS_Pos (0UL) /*!< CCU8_CC8 INTS: PMUS (Bit 0) */ 13058 #define CCU8_CC8_INTS_PMUS_Msk (0x1UL) /*!< CCU8_CC8 INTS: PMUS (Bitfield-Mask: 0x01) */ 13059 #define CCU8_CC8_INTS_OMDS_Pos (1UL) /*!< CCU8_CC8 INTS: OMDS (Bit 1) */ 13060 #define CCU8_CC8_INTS_OMDS_Msk (0x2UL) /*!< CCU8_CC8 INTS: OMDS (Bitfield-Mask: 0x01) */ 13061 #define CCU8_CC8_INTS_CMU1S_Pos (2UL) /*!< CCU8_CC8 INTS: CMU1S (Bit 2) */ 13062 #define CCU8_CC8_INTS_CMU1S_Msk (0x4UL) /*!< CCU8_CC8 INTS: CMU1S (Bitfield-Mask: 0x01) */ 13063 #define CCU8_CC8_INTS_CMD1S_Pos (3UL) /*!< CCU8_CC8 INTS: CMD1S (Bit 3) */ 13064 #define CCU8_CC8_INTS_CMD1S_Msk (0x8UL) /*!< CCU8_CC8 INTS: CMD1S (Bitfield-Mask: 0x01) */ 13065 #define CCU8_CC8_INTS_CMU2S_Pos (4UL) /*!< CCU8_CC8 INTS: CMU2S (Bit 4) */ 13066 #define CCU8_CC8_INTS_CMU2S_Msk (0x10UL) /*!< CCU8_CC8 INTS: CMU2S (Bitfield-Mask: 0x01) */ 13067 #define CCU8_CC8_INTS_CMD2S_Pos (5UL) /*!< CCU8_CC8 INTS: CMD2S (Bit 5) */ 13068 #define CCU8_CC8_INTS_CMD2S_Msk (0x20UL) /*!< CCU8_CC8 INTS: CMD2S (Bitfield-Mask: 0x01) */ 13069 #define CCU8_CC8_INTS_E0AS_Pos (8UL) /*!< CCU8_CC8 INTS: E0AS (Bit 8) */ 13070 #define CCU8_CC8_INTS_E0AS_Msk (0x100UL) /*!< CCU8_CC8 INTS: E0AS (Bitfield-Mask: 0x01) */ 13071 #define CCU8_CC8_INTS_E1AS_Pos (9UL) /*!< CCU8_CC8 INTS: E1AS (Bit 9) */ 13072 #define CCU8_CC8_INTS_E1AS_Msk (0x200UL) /*!< CCU8_CC8 INTS: E1AS (Bitfield-Mask: 0x01) */ 13073 #define CCU8_CC8_INTS_E2AS_Pos (10UL) /*!< CCU8_CC8 INTS: E2AS (Bit 10) */ 13074 #define CCU8_CC8_INTS_E2AS_Msk (0x400UL) /*!< CCU8_CC8 INTS: E2AS (Bitfield-Mask: 0x01) */ 13075 #define CCU8_CC8_INTS_TRPF_Pos (11UL) /*!< CCU8_CC8 INTS: TRPF (Bit 11) */ 13076 #define CCU8_CC8_INTS_TRPF_Msk (0x800UL) /*!< CCU8_CC8 INTS: TRPF (Bitfield-Mask: 0x01) */ 13077 13078 /* -------------------------------- CCU8_CC8_INTE ------------------------------- */ 13079 #define CCU8_CC8_INTE_PME_Pos (0UL) /*!< CCU8_CC8 INTE: PME (Bit 0) */ 13080 #define CCU8_CC8_INTE_PME_Msk (0x1UL) /*!< CCU8_CC8 INTE: PME (Bitfield-Mask: 0x01) */ 13081 #define CCU8_CC8_INTE_OME_Pos (1UL) /*!< CCU8_CC8 INTE: OME (Bit 1) */ 13082 #define CCU8_CC8_INTE_OME_Msk (0x2UL) /*!< CCU8_CC8 INTE: OME (Bitfield-Mask: 0x01) */ 13083 #define CCU8_CC8_INTE_CMU1E_Pos (2UL) /*!< CCU8_CC8 INTE: CMU1E (Bit 2) */ 13084 #define CCU8_CC8_INTE_CMU1E_Msk (0x4UL) /*!< CCU8_CC8 INTE: CMU1E (Bitfield-Mask: 0x01) */ 13085 #define CCU8_CC8_INTE_CMD1E_Pos (3UL) /*!< CCU8_CC8 INTE: CMD1E (Bit 3) */ 13086 #define CCU8_CC8_INTE_CMD1E_Msk (0x8UL) /*!< CCU8_CC8 INTE: CMD1E (Bitfield-Mask: 0x01) */ 13087 #define CCU8_CC8_INTE_CMU2E_Pos (4UL) /*!< CCU8_CC8 INTE: CMU2E (Bit 4) */ 13088 #define CCU8_CC8_INTE_CMU2E_Msk (0x10UL) /*!< CCU8_CC8 INTE: CMU2E (Bitfield-Mask: 0x01) */ 13089 #define CCU8_CC8_INTE_CMD2E_Pos (5UL) /*!< CCU8_CC8 INTE: CMD2E (Bit 5) */ 13090 #define CCU8_CC8_INTE_CMD2E_Msk (0x20UL) /*!< CCU8_CC8 INTE: CMD2E (Bitfield-Mask: 0x01) */ 13091 #define CCU8_CC8_INTE_E0AE_Pos (8UL) /*!< CCU8_CC8 INTE: E0AE (Bit 8) */ 13092 #define CCU8_CC8_INTE_E0AE_Msk (0x100UL) /*!< CCU8_CC8 INTE: E0AE (Bitfield-Mask: 0x01) */ 13093 #define CCU8_CC8_INTE_E1AE_Pos (9UL) /*!< CCU8_CC8 INTE: E1AE (Bit 9) */ 13094 #define CCU8_CC8_INTE_E1AE_Msk (0x200UL) /*!< CCU8_CC8 INTE: E1AE (Bitfield-Mask: 0x01) */ 13095 #define CCU8_CC8_INTE_E2AE_Pos (10UL) /*!< CCU8_CC8 INTE: E2AE (Bit 10) */ 13096 #define CCU8_CC8_INTE_E2AE_Msk (0x400UL) /*!< CCU8_CC8 INTE: E2AE (Bitfield-Mask: 0x01) */ 13097 13098 /* -------------------------------- CCU8_CC8_SRS -------------------------------- */ 13099 #define CCU8_CC8_SRS_POSR_Pos (0UL) /*!< CCU8_CC8 SRS: POSR (Bit 0) */ 13100 #define CCU8_CC8_SRS_POSR_Msk (0x3UL) /*!< CCU8_CC8 SRS: POSR (Bitfield-Mask: 0x03) */ 13101 #define CCU8_CC8_SRS_CM1SR_Pos (2UL) /*!< CCU8_CC8 SRS: CM1SR (Bit 2) */ 13102 #define CCU8_CC8_SRS_CM1SR_Msk (0xcUL) /*!< CCU8_CC8 SRS: CM1SR (Bitfield-Mask: 0x03) */ 13103 #define CCU8_CC8_SRS_CM2SR_Pos (4UL) /*!< CCU8_CC8 SRS: CM2SR (Bit 4) */ 13104 #define CCU8_CC8_SRS_CM2SR_Msk (0x30UL) /*!< CCU8_CC8 SRS: CM2SR (Bitfield-Mask: 0x03) */ 13105 #define CCU8_CC8_SRS_E0SR_Pos (8UL) /*!< CCU8_CC8 SRS: E0SR (Bit 8) */ 13106 #define CCU8_CC8_SRS_E0SR_Msk (0x300UL) /*!< CCU8_CC8 SRS: E0SR (Bitfield-Mask: 0x03) */ 13107 #define CCU8_CC8_SRS_E1SR_Pos (10UL) /*!< CCU8_CC8 SRS: E1SR (Bit 10) */ 13108 #define CCU8_CC8_SRS_E1SR_Msk (0xc00UL) /*!< CCU8_CC8 SRS: E1SR (Bitfield-Mask: 0x03) */ 13109 #define CCU8_CC8_SRS_E2SR_Pos (12UL) /*!< CCU8_CC8 SRS: E2SR (Bit 12) */ 13110 #define CCU8_CC8_SRS_E2SR_Msk (0x3000UL) /*!< CCU8_CC8 SRS: E2SR (Bitfield-Mask: 0x03) */ 13111 13112 /* -------------------------------- CCU8_CC8_SWS -------------------------------- */ 13113 #define CCU8_CC8_SWS_SPM_Pos (0UL) /*!< CCU8_CC8 SWS: SPM (Bit 0) */ 13114 #define CCU8_CC8_SWS_SPM_Msk (0x1UL) /*!< CCU8_CC8 SWS: SPM (Bitfield-Mask: 0x01) */ 13115 #define CCU8_CC8_SWS_SOM_Pos (1UL) /*!< CCU8_CC8 SWS: SOM (Bit 1) */ 13116 #define CCU8_CC8_SWS_SOM_Msk (0x2UL) /*!< CCU8_CC8 SWS: SOM (Bitfield-Mask: 0x01) */ 13117 #define CCU8_CC8_SWS_SCM1U_Pos (2UL) /*!< CCU8_CC8 SWS: SCM1U (Bit 2) */ 13118 #define CCU8_CC8_SWS_SCM1U_Msk (0x4UL) /*!< CCU8_CC8 SWS: SCM1U (Bitfield-Mask: 0x01) */ 13119 #define CCU8_CC8_SWS_SCM1D_Pos (3UL) /*!< CCU8_CC8 SWS: SCM1D (Bit 3) */ 13120 #define CCU8_CC8_SWS_SCM1D_Msk (0x8UL) /*!< CCU8_CC8 SWS: SCM1D (Bitfield-Mask: 0x01) */ 13121 #define CCU8_CC8_SWS_SCM2U_Pos (4UL) /*!< CCU8_CC8 SWS: SCM2U (Bit 4) */ 13122 #define CCU8_CC8_SWS_SCM2U_Msk (0x10UL) /*!< CCU8_CC8 SWS: SCM2U (Bitfield-Mask: 0x01) */ 13123 #define CCU8_CC8_SWS_SCM2D_Pos (5UL) /*!< CCU8_CC8 SWS: SCM2D (Bit 5) */ 13124 #define CCU8_CC8_SWS_SCM2D_Msk (0x20UL) /*!< CCU8_CC8 SWS: SCM2D (Bitfield-Mask: 0x01) */ 13125 #define CCU8_CC8_SWS_SE0A_Pos (8UL) /*!< CCU8_CC8 SWS: SE0A (Bit 8) */ 13126 #define CCU8_CC8_SWS_SE0A_Msk (0x100UL) /*!< CCU8_CC8 SWS: SE0A (Bitfield-Mask: 0x01) */ 13127 #define CCU8_CC8_SWS_SE1A_Pos (9UL) /*!< CCU8_CC8 SWS: SE1A (Bit 9) */ 13128 #define CCU8_CC8_SWS_SE1A_Msk (0x200UL) /*!< CCU8_CC8 SWS: SE1A (Bitfield-Mask: 0x01) */ 13129 #define CCU8_CC8_SWS_SE2A_Pos (10UL) /*!< CCU8_CC8 SWS: SE2A (Bit 10) */ 13130 #define CCU8_CC8_SWS_SE2A_Msk (0x400UL) /*!< CCU8_CC8 SWS: SE2A (Bitfield-Mask: 0x01) */ 13131 #define CCU8_CC8_SWS_STRPF_Pos (11UL) /*!< CCU8_CC8 SWS: STRPF (Bit 11) */ 13132 #define CCU8_CC8_SWS_STRPF_Msk (0x800UL) /*!< CCU8_CC8 SWS: STRPF (Bitfield-Mask: 0x01) */ 13133 13134 /* -------------------------------- CCU8_CC8_SWR -------------------------------- */ 13135 #define CCU8_CC8_SWR_RPM_Pos (0UL) /*!< CCU8_CC8 SWR: RPM (Bit 0) */ 13136 #define CCU8_CC8_SWR_RPM_Msk (0x1UL) /*!< CCU8_CC8 SWR: RPM (Bitfield-Mask: 0x01) */ 13137 #define CCU8_CC8_SWR_ROM_Pos (1UL) /*!< CCU8_CC8 SWR: ROM (Bit 1) */ 13138 #define CCU8_CC8_SWR_ROM_Msk (0x2UL) /*!< CCU8_CC8 SWR: ROM (Bitfield-Mask: 0x01) */ 13139 #define CCU8_CC8_SWR_RCM1U_Pos (2UL) /*!< CCU8_CC8 SWR: RCM1U (Bit 2) */ 13140 #define CCU8_CC8_SWR_RCM1U_Msk (0x4UL) /*!< CCU8_CC8 SWR: RCM1U (Bitfield-Mask: 0x01) */ 13141 #define CCU8_CC8_SWR_RCM1D_Pos (3UL) /*!< CCU8_CC8 SWR: RCM1D (Bit 3) */ 13142 #define CCU8_CC8_SWR_RCM1D_Msk (0x8UL) /*!< CCU8_CC8 SWR: RCM1D (Bitfield-Mask: 0x01) */ 13143 #define CCU8_CC8_SWR_RCM2U_Pos (4UL) /*!< CCU8_CC8 SWR: RCM2U (Bit 4) */ 13144 #define CCU8_CC8_SWR_RCM2U_Msk (0x10UL) /*!< CCU8_CC8 SWR: RCM2U (Bitfield-Mask: 0x01) */ 13145 #define CCU8_CC8_SWR_RCM2D_Pos (5UL) /*!< CCU8_CC8 SWR: RCM2D (Bit 5) */ 13146 #define CCU8_CC8_SWR_RCM2D_Msk (0x20UL) /*!< CCU8_CC8 SWR: RCM2D (Bitfield-Mask: 0x01) */ 13147 #define CCU8_CC8_SWR_RE0A_Pos (8UL) /*!< CCU8_CC8 SWR: RE0A (Bit 8) */ 13148 #define CCU8_CC8_SWR_RE0A_Msk (0x100UL) /*!< CCU8_CC8 SWR: RE0A (Bitfield-Mask: 0x01) */ 13149 #define CCU8_CC8_SWR_RE1A_Pos (9UL) /*!< CCU8_CC8 SWR: RE1A (Bit 9) */ 13150 #define CCU8_CC8_SWR_RE1A_Msk (0x200UL) /*!< CCU8_CC8 SWR: RE1A (Bitfield-Mask: 0x01) */ 13151 #define CCU8_CC8_SWR_RE2A_Pos (10UL) /*!< CCU8_CC8 SWR: RE2A (Bit 10) */ 13152 #define CCU8_CC8_SWR_RE2A_Msk (0x400UL) /*!< CCU8_CC8 SWR: RE2A (Bitfield-Mask: 0x01) */ 13153 #define CCU8_CC8_SWR_RTRPF_Pos (11UL) /*!< CCU8_CC8 SWR: RTRPF (Bit 11) */ 13154 #define CCU8_CC8_SWR_RTRPF_Msk (0x800UL) /*!< CCU8_CC8 SWR: RTRPF (Bitfield-Mask: 0x01) */ 13155 13156 13157 /* ================================================================================ */ 13158 /* ================ Group 'POSIF' Position & Mask ================ */ 13159 /* ================================================================================ */ 13160 13161 13162 /* --------------------------------- POSIF_PCONF -------------------------------- */ 13163 #define POSIF_PCONF_FSEL_Pos (0UL) /*!< POSIF PCONF: FSEL (Bit 0) */ 13164 #define POSIF_PCONF_FSEL_Msk (0x3UL) /*!< POSIF PCONF: FSEL (Bitfield-Mask: 0x03) */ 13165 #define POSIF_PCONF_QDCM_Pos (2UL) /*!< POSIF PCONF: QDCM (Bit 2) */ 13166 #define POSIF_PCONF_QDCM_Msk (0x4UL) /*!< POSIF PCONF: QDCM (Bitfield-Mask: 0x01) */ 13167 #define POSIF_PCONF_HIDG_Pos (4UL) /*!< POSIF PCONF: HIDG (Bit 4) */ 13168 #define POSIF_PCONF_HIDG_Msk (0x10UL) /*!< POSIF PCONF: HIDG (Bitfield-Mask: 0x01) */ 13169 #define POSIF_PCONF_MCUE_Pos (5UL) /*!< POSIF PCONF: MCUE (Bit 5) */ 13170 #define POSIF_PCONF_MCUE_Msk (0x20UL) /*!< POSIF PCONF: MCUE (Bitfield-Mask: 0x01) */ 13171 #define POSIF_PCONF_INSEL0_Pos (8UL) /*!< POSIF PCONF: INSEL0 (Bit 8) */ 13172 #define POSIF_PCONF_INSEL0_Msk (0x300UL) /*!< POSIF PCONF: INSEL0 (Bitfield-Mask: 0x03) */ 13173 #define POSIF_PCONF_INSEL1_Pos (10UL) /*!< POSIF PCONF: INSEL1 (Bit 10) */ 13174 #define POSIF_PCONF_INSEL1_Msk (0xc00UL) /*!< POSIF PCONF: INSEL1 (Bitfield-Mask: 0x03) */ 13175 #define POSIF_PCONF_INSEL2_Pos (12UL) /*!< POSIF PCONF: INSEL2 (Bit 12) */ 13176 #define POSIF_PCONF_INSEL2_Msk (0x3000UL) /*!< POSIF PCONF: INSEL2 (Bitfield-Mask: 0x03) */ 13177 #define POSIF_PCONF_DSEL_Pos (16UL) /*!< POSIF PCONF: DSEL (Bit 16) */ 13178 #define POSIF_PCONF_DSEL_Msk (0x10000UL) /*!< POSIF PCONF: DSEL (Bitfield-Mask: 0x01) */ 13179 #define POSIF_PCONF_SPES_Pos (17UL) /*!< POSIF PCONF: SPES (Bit 17) */ 13180 #define POSIF_PCONF_SPES_Msk (0x20000UL) /*!< POSIF PCONF: SPES (Bitfield-Mask: 0x01) */ 13181 #define POSIF_PCONF_MSETS_Pos (18UL) /*!< POSIF PCONF: MSETS (Bit 18) */ 13182 #define POSIF_PCONF_MSETS_Msk (0x1c0000UL) /*!< POSIF PCONF: MSETS (Bitfield-Mask: 0x07) */ 13183 #define POSIF_PCONF_MSES_Pos (21UL) /*!< POSIF PCONF: MSES (Bit 21) */ 13184 #define POSIF_PCONF_MSES_Msk (0x200000UL) /*!< POSIF PCONF: MSES (Bitfield-Mask: 0x01) */ 13185 #define POSIF_PCONF_MSYNS_Pos (22UL) /*!< POSIF PCONF: MSYNS (Bit 22) */ 13186 #define POSIF_PCONF_MSYNS_Msk (0xc00000UL) /*!< POSIF PCONF: MSYNS (Bitfield-Mask: 0x03) */ 13187 #define POSIF_PCONF_EWIS_Pos (24UL) /*!< POSIF PCONF: EWIS (Bit 24) */ 13188 #define POSIF_PCONF_EWIS_Msk (0x3000000UL) /*!< POSIF PCONF: EWIS (Bitfield-Mask: 0x03) */ 13189 #define POSIF_PCONF_EWIE_Pos (26UL) /*!< POSIF PCONF: EWIE (Bit 26) */ 13190 #define POSIF_PCONF_EWIE_Msk (0x4000000UL) /*!< POSIF PCONF: EWIE (Bitfield-Mask: 0x01) */ 13191 #define POSIF_PCONF_EWIL_Pos (27UL) /*!< POSIF PCONF: EWIL (Bit 27) */ 13192 #define POSIF_PCONF_EWIL_Msk (0x8000000UL) /*!< POSIF PCONF: EWIL (Bitfield-Mask: 0x01) */ 13193 #define POSIF_PCONF_LPC_Pos (28UL) /*!< POSIF PCONF: LPC (Bit 28) */ 13194 #define POSIF_PCONF_LPC_Msk (0x70000000UL) /*!< POSIF PCONF: LPC (Bitfield-Mask: 0x07) */ 13195 13196 /* --------------------------------- POSIF_PSUS --------------------------------- */ 13197 #define POSIF_PSUS_QSUS_Pos (0UL) /*!< POSIF PSUS: QSUS (Bit 0) */ 13198 #define POSIF_PSUS_QSUS_Msk (0x3UL) /*!< POSIF PSUS: QSUS (Bitfield-Mask: 0x03) */ 13199 #define POSIF_PSUS_MSUS_Pos (2UL) /*!< POSIF PSUS: MSUS (Bit 2) */ 13200 #define POSIF_PSUS_MSUS_Msk (0xcUL) /*!< POSIF PSUS: MSUS (Bitfield-Mask: 0x03) */ 13201 13202 /* --------------------------------- POSIF_PRUNS -------------------------------- */ 13203 #define POSIF_PRUNS_SRB_Pos (0UL) /*!< POSIF PRUNS: SRB (Bit 0) */ 13204 #define POSIF_PRUNS_SRB_Msk (0x1UL) /*!< POSIF PRUNS: SRB (Bitfield-Mask: 0x01) */ 13205 13206 /* --------------------------------- POSIF_PRUNC -------------------------------- */ 13207 #define POSIF_PRUNC_CRB_Pos (0UL) /*!< POSIF PRUNC: CRB (Bit 0) */ 13208 #define POSIF_PRUNC_CRB_Msk (0x1UL) /*!< POSIF PRUNC: CRB (Bitfield-Mask: 0x01) */ 13209 #define POSIF_PRUNC_CSM_Pos (1UL) /*!< POSIF PRUNC: CSM (Bit 1) */ 13210 #define POSIF_PRUNC_CSM_Msk (0x2UL) /*!< POSIF PRUNC: CSM (Bitfield-Mask: 0x01) */ 13211 13212 /* --------------------------------- POSIF_PRUN --------------------------------- */ 13213 #define POSIF_PRUN_RB_Pos (0UL) /*!< POSIF PRUN: RB (Bit 0) */ 13214 #define POSIF_PRUN_RB_Msk (0x1UL) /*!< POSIF PRUN: RB (Bitfield-Mask: 0x01) */ 13215 13216 /* --------------------------------- POSIF_MIDR --------------------------------- */ 13217 #define POSIF_MIDR_MODR_Pos (0UL) /*!< POSIF MIDR: MODR (Bit 0) */ 13218 #define POSIF_MIDR_MODR_Msk (0xffUL) /*!< POSIF MIDR: MODR (Bitfield-Mask: 0xff) */ 13219 #define POSIF_MIDR_MODT_Pos (8UL) /*!< POSIF MIDR: MODT (Bit 8) */ 13220 #define POSIF_MIDR_MODT_Msk (0xff00UL) /*!< POSIF MIDR: MODT (Bitfield-Mask: 0xff) */ 13221 #define POSIF_MIDR_MODN_Pos (16UL) /*!< POSIF MIDR: MODN (Bit 16) */ 13222 #define POSIF_MIDR_MODN_Msk (0xffff0000UL) /*!< POSIF MIDR: MODN (Bitfield-Mask: 0xffff) */ 13223 13224 /* --------------------------------- POSIF_HALP --------------------------------- */ 13225 #define POSIF_HALP_HCP_Pos (0UL) /*!< POSIF HALP: HCP (Bit 0) */ 13226 #define POSIF_HALP_HCP_Msk (0x7UL) /*!< POSIF HALP: HCP (Bitfield-Mask: 0x07) */ 13227 #define POSIF_HALP_HEP_Pos (3UL) /*!< POSIF HALP: HEP (Bit 3) */ 13228 #define POSIF_HALP_HEP_Msk (0x38UL) /*!< POSIF HALP: HEP (Bitfield-Mask: 0x07) */ 13229 13230 /* --------------------------------- POSIF_HALPS -------------------------------- */ 13231 #define POSIF_HALPS_HCPS_Pos (0UL) /*!< POSIF HALPS: HCPS (Bit 0) */ 13232 #define POSIF_HALPS_HCPS_Msk (0x7UL) /*!< POSIF HALPS: HCPS (Bitfield-Mask: 0x07) */ 13233 #define POSIF_HALPS_HEPS_Pos (3UL) /*!< POSIF HALPS: HEPS (Bit 3) */ 13234 #define POSIF_HALPS_HEPS_Msk (0x38UL) /*!< POSIF HALPS: HEPS (Bitfield-Mask: 0x07) */ 13235 13236 /* ---------------------------------- POSIF_MCM --------------------------------- */ 13237 #define POSIF_MCM_MCMP_Pos (0UL) /*!< POSIF MCM: MCMP (Bit 0) */ 13238 #define POSIF_MCM_MCMP_Msk (0xffffUL) /*!< POSIF MCM: MCMP (Bitfield-Mask: 0xffff) */ 13239 13240 /* --------------------------------- POSIF_MCSM --------------------------------- */ 13241 #define POSIF_MCSM_MCMPS_Pos (0UL) /*!< POSIF MCSM: MCMPS (Bit 0) */ 13242 #define POSIF_MCSM_MCMPS_Msk (0xffffUL) /*!< POSIF MCSM: MCMPS (Bitfield-Mask: 0xffff) */ 13243 13244 /* --------------------------------- POSIF_MCMS --------------------------------- */ 13245 #define POSIF_MCMS_MNPS_Pos (0UL) /*!< POSIF MCMS: MNPS (Bit 0) */ 13246 #define POSIF_MCMS_MNPS_Msk (0x1UL) /*!< POSIF MCMS: MNPS (Bitfield-Mask: 0x01) */ 13247 #define POSIF_MCMS_STHR_Pos (1UL) /*!< POSIF MCMS: STHR (Bit 1) */ 13248 #define POSIF_MCMS_STHR_Msk (0x2UL) /*!< POSIF MCMS: STHR (Bitfield-Mask: 0x01) */ 13249 #define POSIF_MCMS_STMR_Pos (2UL) /*!< POSIF MCMS: STMR (Bit 2) */ 13250 #define POSIF_MCMS_STMR_Msk (0x4UL) /*!< POSIF MCMS: STMR (Bitfield-Mask: 0x01) */ 13251 13252 /* --------------------------------- POSIF_MCMC --------------------------------- */ 13253 #define POSIF_MCMC_MNPC_Pos (0UL) /*!< POSIF MCMC: MNPC (Bit 0) */ 13254 #define POSIF_MCMC_MNPC_Msk (0x1UL) /*!< POSIF MCMC: MNPC (Bitfield-Mask: 0x01) */ 13255 #define POSIF_MCMC_MPC_Pos (1UL) /*!< POSIF MCMC: MPC (Bit 1) */ 13256 #define POSIF_MCMC_MPC_Msk (0x2UL) /*!< POSIF MCMC: MPC (Bitfield-Mask: 0x01) */ 13257 13258 /* --------------------------------- POSIF_MCMF --------------------------------- */ 13259 #define POSIF_MCMF_MSS_Pos (0UL) /*!< POSIF MCMF: MSS (Bit 0) */ 13260 #define POSIF_MCMF_MSS_Msk (0x1UL) /*!< POSIF MCMF: MSS (Bitfield-Mask: 0x01) */ 13261 13262 /* ---------------------------------- POSIF_QDC --------------------------------- */ 13263 #define POSIF_QDC_PALS_Pos (0UL) /*!< POSIF QDC: PALS (Bit 0) */ 13264 #define POSIF_QDC_PALS_Msk (0x1UL) /*!< POSIF QDC: PALS (Bitfield-Mask: 0x01) */ 13265 #define POSIF_QDC_PBLS_Pos (1UL) /*!< POSIF QDC: PBLS (Bit 1) */ 13266 #define POSIF_QDC_PBLS_Msk (0x2UL) /*!< POSIF QDC: PBLS (Bitfield-Mask: 0x01) */ 13267 #define POSIF_QDC_PHS_Pos (2UL) /*!< POSIF QDC: PHS (Bit 2) */ 13268 #define POSIF_QDC_PHS_Msk (0x4UL) /*!< POSIF QDC: PHS (Bitfield-Mask: 0x01) */ 13269 #define POSIF_QDC_ICM_Pos (4UL) /*!< POSIF QDC: ICM (Bit 4) */ 13270 #define POSIF_QDC_ICM_Msk (0x30UL) /*!< POSIF QDC: ICM (Bitfield-Mask: 0x03) */ 13271 #define POSIF_QDC_DVAL_Pos (8UL) /*!< POSIF QDC: DVAL (Bit 8) */ 13272 #define POSIF_QDC_DVAL_Msk (0x100UL) /*!< POSIF QDC: DVAL (Bitfield-Mask: 0x01) */ 13273 13274 /* --------------------------------- POSIF_PFLG --------------------------------- */ 13275 #define POSIF_PFLG_CHES_Pos (0UL) /*!< POSIF PFLG: CHES (Bit 0) */ 13276 #define POSIF_PFLG_CHES_Msk (0x1UL) /*!< POSIF PFLG: CHES (Bitfield-Mask: 0x01) */ 13277 #define POSIF_PFLG_WHES_Pos (1UL) /*!< POSIF PFLG: WHES (Bit 1) */ 13278 #define POSIF_PFLG_WHES_Msk (0x2UL) /*!< POSIF PFLG: WHES (Bitfield-Mask: 0x01) */ 13279 #define POSIF_PFLG_HIES_Pos (2UL) /*!< POSIF PFLG: HIES (Bit 2) */ 13280 #define POSIF_PFLG_HIES_Msk (0x4UL) /*!< POSIF PFLG: HIES (Bitfield-Mask: 0x01) */ 13281 #define POSIF_PFLG_MSTS_Pos (4UL) /*!< POSIF PFLG: MSTS (Bit 4) */ 13282 #define POSIF_PFLG_MSTS_Msk (0x10UL) /*!< POSIF PFLG: MSTS (Bitfield-Mask: 0x01) */ 13283 #define POSIF_PFLG_INDXS_Pos (8UL) /*!< POSIF PFLG: INDXS (Bit 8) */ 13284 #define POSIF_PFLG_INDXS_Msk (0x100UL) /*!< POSIF PFLG: INDXS (Bitfield-Mask: 0x01) */ 13285 #define POSIF_PFLG_ERRS_Pos (9UL) /*!< POSIF PFLG: ERRS (Bit 9) */ 13286 #define POSIF_PFLG_ERRS_Msk (0x200UL) /*!< POSIF PFLG: ERRS (Bitfield-Mask: 0x01) */ 13287 #define POSIF_PFLG_CNTS_Pos (10UL) /*!< POSIF PFLG: CNTS (Bit 10) */ 13288 #define POSIF_PFLG_CNTS_Msk (0x400UL) /*!< POSIF PFLG: CNTS (Bitfield-Mask: 0x01) */ 13289 #define POSIF_PFLG_DIRS_Pos (11UL) /*!< POSIF PFLG: DIRS (Bit 11) */ 13290 #define POSIF_PFLG_DIRS_Msk (0x800UL) /*!< POSIF PFLG: DIRS (Bitfield-Mask: 0x01) */ 13291 #define POSIF_PFLG_PCLKS_Pos (12UL) /*!< POSIF PFLG: PCLKS (Bit 12) */ 13292 #define POSIF_PFLG_PCLKS_Msk (0x1000UL) /*!< POSIF PFLG: PCLKS (Bitfield-Mask: 0x01) */ 13293 13294 /* --------------------------------- POSIF_PFLGE -------------------------------- */ 13295 #define POSIF_PFLGE_ECHE_Pos (0UL) /*!< POSIF PFLGE: ECHE (Bit 0) */ 13296 #define POSIF_PFLGE_ECHE_Msk (0x1UL) /*!< POSIF PFLGE: ECHE (Bitfield-Mask: 0x01) */ 13297 #define POSIF_PFLGE_EWHE_Pos (1UL) /*!< POSIF PFLGE: EWHE (Bit 1) */ 13298 #define POSIF_PFLGE_EWHE_Msk (0x2UL) /*!< POSIF PFLGE: EWHE (Bitfield-Mask: 0x01) */ 13299 #define POSIF_PFLGE_EHIE_Pos (2UL) /*!< POSIF PFLGE: EHIE (Bit 2) */ 13300 #define POSIF_PFLGE_EHIE_Msk (0x4UL) /*!< POSIF PFLGE: EHIE (Bitfield-Mask: 0x01) */ 13301 #define POSIF_PFLGE_EMST_Pos (4UL) /*!< POSIF PFLGE: EMST (Bit 4) */ 13302 #define POSIF_PFLGE_EMST_Msk (0x10UL) /*!< POSIF PFLGE: EMST (Bitfield-Mask: 0x01) */ 13303 #define POSIF_PFLGE_EINDX_Pos (8UL) /*!< POSIF PFLGE: EINDX (Bit 8) */ 13304 #define POSIF_PFLGE_EINDX_Msk (0x100UL) /*!< POSIF PFLGE: EINDX (Bitfield-Mask: 0x01) */ 13305 #define POSIF_PFLGE_EERR_Pos (9UL) /*!< POSIF PFLGE: EERR (Bit 9) */ 13306 #define POSIF_PFLGE_EERR_Msk (0x200UL) /*!< POSIF PFLGE: EERR (Bitfield-Mask: 0x01) */ 13307 #define POSIF_PFLGE_ECNT_Pos (10UL) /*!< POSIF PFLGE: ECNT (Bit 10) */ 13308 #define POSIF_PFLGE_ECNT_Msk (0x400UL) /*!< POSIF PFLGE: ECNT (Bitfield-Mask: 0x01) */ 13309 #define POSIF_PFLGE_EDIR_Pos (11UL) /*!< POSIF PFLGE: EDIR (Bit 11) */ 13310 #define POSIF_PFLGE_EDIR_Msk (0x800UL) /*!< POSIF PFLGE: EDIR (Bitfield-Mask: 0x01) */ 13311 #define POSIF_PFLGE_EPCLK_Pos (12UL) /*!< POSIF PFLGE: EPCLK (Bit 12) */ 13312 #define POSIF_PFLGE_EPCLK_Msk (0x1000UL) /*!< POSIF PFLGE: EPCLK (Bitfield-Mask: 0x01) */ 13313 #define POSIF_PFLGE_CHESEL_Pos (16UL) /*!< POSIF PFLGE: CHESEL (Bit 16) */ 13314 #define POSIF_PFLGE_CHESEL_Msk (0x10000UL) /*!< POSIF PFLGE: CHESEL (Bitfield-Mask: 0x01) */ 13315 #define POSIF_PFLGE_WHESEL_Pos (17UL) /*!< POSIF PFLGE: WHESEL (Bit 17) */ 13316 #define POSIF_PFLGE_WHESEL_Msk (0x20000UL) /*!< POSIF PFLGE: WHESEL (Bitfield-Mask: 0x01) */ 13317 #define POSIF_PFLGE_HIESEL_Pos (18UL) /*!< POSIF PFLGE: HIESEL (Bit 18) */ 13318 #define POSIF_PFLGE_HIESEL_Msk (0x40000UL) /*!< POSIF PFLGE: HIESEL (Bitfield-Mask: 0x01) */ 13319 #define POSIF_PFLGE_MSTSEL_Pos (20UL) /*!< POSIF PFLGE: MSTSEL (Bit 20) */ 13320 #define POSIF_PFLGE_MSTSEL_Msk (0x100000UL) /*!< POSIF PFLGE: MSTSEL (Bitfield-Mask: 0x01) */ 13321 #define POSIF_PFLGE_INDSEL_Pos (24UL) /*!< POSIF PFLGE: INDSEL (Bit 24) */ 13322 #define POSIF_PFLGE_INDSEL_Msk (0x1000000UL) /*!< POSIF PFLGE: INDSEL (Bitfield-Mask: 0x01) */ 13323 #define POSIF_PFLGE_ERRSEL_Pos (25UL) /*!< POSIF PFLGE: ERRSEL (Bit 25) */ 13324 #define POSIF_PFLGE_ERRSEL_Msk (0x2000000UL) /*!< POSIF PFLGE: ERRSEL (Bitfield-Mask: 0x01) */ 13325 #define POSIF_PFLGE_CNTSEL_Pos (26UL) /*!< POSIF PFLGE: CNTSEL (Bit 26) */ 13326 #define POSIF_PFLGE_CNTSEL_Msk (0x4000000UL) /*!< POSIF PFLGE: CNTSEL (Bitfield-Mask: 0x01) */ 13327 #define POSIF_PFLGE_DIRSEL_Pos (27UL) /*!< POSIF PFLGE: DIRSEL (Bit 27) */ 13328 #define POSIF_PFLGE_DIRSEL_Msk (0x8000000UL) /*!< POSIF PFLGE: DIRSEL (Bitfield-Mask: 0x01) */ 13329 #define POSIF_PFLGE_PCLSEL_Pos (28UL) /*!< POSIF PFLGE: PCLSEL (Bit 28) */ 13330 #define POSIF_PFLGE_PCLSEL_Msk (0x10000000UL) /*!< POSIF PFLGE: PCLSEL (Bitfield-Mask: 0x01) */ 13331 13332 /* --------------------------------- POSIF_SPFLG -------------------------------- */ 13333 #define POSIF_SPFLG_SCHE_Pos (0UL) /*!< POSIF SPFLG: SCHE (Bit 0) */ 13334 #define POSIF_SPFLG_SCHE_Msk (0x1UL) /*!< POSIF SPFLG: SCHE (Bitfield-Mask: 0x01) */ 13335 #define POSIF_SPFLG_SWHE_Pos (1UL) /*!< POSIF SPFLG: SWHE (Bit 1) */ 13336 #define POSIF_SPFLG_SWHE_Msk (0x2UL) /*!< POSIF SPFLG: SWHE (Bitfield-Mask: 0x01) */ 13337 #define POSIF_SPFLG_SHIE_Pos (2UL) /*!< POSIF SPFLG: SHIE (Bit 2) */ 13338 #define POSIF_SPFLG_SHIE_Msk (0x4UL) /*!< POSIF SPFLG: SHIE (Bitfield-Mask: 0x01) */ 13339 #define POSIF_SPFLG_SMST_Pos (4UL) /*!< POSIF SPFLG: SMST (Bit 4) */ 13340 #define POSIF_SPFLG_SMST_Msk (0x10UL) /*!< POSIF SPFLG: SMST (Bitfield-Mask: 0x01) */ 13341 #define POSIF_SPFLG_SINDX_Pos (8UL) /*!< POSIF SPFLG: SINDX (Bit 8) */ 13342 #define POSIF_SPFLG_SINDX_Msk (0x100UL) /*!< POSIF SPFLG: SINDX (Bitfield-Mask: 0x01) */ 13343 #define POSIF_SPFLG_SERR_Pos (9UL) /*!< POSIF SPFLG: SERR (Bit 9) */ 13344 #define POSIF_SPFLG_SERR_Msk (0x200UL) /*!< POSIF SPFLG: SERR (Bitfield-Mask: 0x01) */ 13345 #define POSIF_SPFLG_SCNT_Pos (10UL) /*!< POSIF SPFLG: SCNT (Bit 10) */ 13346 #define POSIF_SPFLG_SCNT_Msk (0x400UL) /*!< POSIF SPFLG: SCNT (Bitfield-Mask: 0x01) */ 13347 #define POSIF_SPFLG_SDIR_Pos (11UL) /*!< POSIF SPFLG: SDIR (Bit 11) */ 13348 #define POSIF_SPFLG_SDIR_Msk (0x800UL) /*!< POSIF SPFLG: SDIR (Bitfield-Mask: 0x01) */ 13349 #define POSIF_SPFLG_SPCLK_Pos (12UL) /*!< POSIF SPFLG: SPCLK (Bit 12) */ 13350 #define POSIF_SPFLG_SPCLK_Msk (0x1000UL) /*!< POSIF SPFLG: SPCLK (Bitfield-Mask: 0x01) */ 13351 13352 /* --------------------------------- POSIF_RPFLG -------------------------------- */ 13353 #define POSIF_RPFLG_RCHE_Pos (0UL) /*!< POSIF RPFLG: RCHE (Bit 0) */ 13354 #define POSIF_RPFLG_RCHE_Msk (0x1UL) /*!< POSIF RPFLG: RCHE (Bitfield-Mask: 0x01) */ 13355 #define POSIF_RPFLG_RWHE_Pos (1UL) /*!< POSIF RPFLG: RWHE (Bit 1) */ 13356 #define POSIF_RPFLG_RWHE_Msk (0x2UL) /*!< POSIF RPFLG: RWHE (Bitfield-Mask: 0x01) */ 13357 #define POSIF_RPFLG_RHIE_Pos (2UL) /*!< POSIF RPFLG: RHIE (Bit 2) */ 13358 #define POSIF_RPFLG_RHIE_Msk (0x4UL) /*!< POSIF RPFLG: RHIE (Bitfield-Mask: 0x01) */ 13359 #define POSIF_RPFLG_RMST_Pos (4UL) /*!< POSIF RPFLG: RMST (Bit 4) */ 13360 #define POSIF_RPFLG_RMST_Msk (0x10UL) /*!< POSIF RPFLG: RMST (Bitfield-Mask: 0x01) */ 13361 #define POSIF_RPFLG_RINDX_Pos (8UL) /*!< POSIF RPFLG: RINDX (Bit 8) */ 13362 #define POSIF_RPFLG_RINDX_Msk (0x100UL) /*!< POSIF RPFLG: RINDX (Bitfield-Mask: 0x01) */ 13363 #define POSIF_RPFLG_RERR_Pos (9UL) /*!< POSIF RPFLG: RERR (Bit 9) */ 13364 #define POSIF_RPFLG_RERR_Msk (0x200UL) /*!< POSIF RPFLG: RERR (Bitfield-Mask: 0x01) */ 13365 #define POSIF_RPFLG_RCNT_Pos (10UL) /*!< POSIF RPFLG: RCNT (Bit 10) */ 13366 #define POSIF_RPFLG_RCNT_Msk (0x400UL) /*!< POSIF RPFLG: RCNT (Bitfield-Mask: 0x01) */ 13367 #define POSIF_RPFLG_RDIR_Pos (11UL) /*!< POSIF RPFLG: RDIR (Bit 11) */ 13368 #define POSIF_RPFLG_RDIR_Msk (0x800UL) /*!< POSIF RPFLG: RDIR (Bitfield-Mask: 0x01) */ 13369 #define POSIF_RPFLG_RPCLK_Pos (12UL) /*!< POSIF RPFLG: RPCLK (Bit 12) */ 13370 #define POSIF_RPFLG_RPCLK_Msk (0x1000UL) /*!< POSIF RPFLG: RPCLK (Bitfield-Mask: 0x01) */ 13371 13372 /* --------------------------------- POSIF_PDBG --------------------------------- */ 13373 #define POSIF_PDBG_QCSV_Pos (0UL) /*!< POSIF PDBG: QCSV (Bit 0) */ 13374 #define POSIF_PDBG_QCSV_Msk (0x3UL) /*!< POSIF PDBG: QCSV (Bitfield-Mask: 0x03) */ 13375 #define POSIF_PDBG_QPSV_Pos (2UL) /*!< POSIF PDBG: QPSV (Bit 2) */ 13376 #define POSIF_PDBG_QPSV_Msk (0xcUL) /*!< POSIF PDBG: QPSV (Bitfield-Mask: 0x03) */ 13377 #define POSIF_PDBG_IVAL_Pos (4UL) /*!< POSIF PDBG: IVAL (Bit 4) */ 13378 #define POSIF_PDBG_IVAL_Msk (0x10UL) /*!< POSIF PDBG: IVAL (Bitfield-Mask: 0x01) */ 13379 #define POSIF_PDBG_HSP_Pos (5UL) /*!< POSIF PDBG: HSP (Bit 5) */ 13380 #define POSIF_PDBG_HSP_Msk (0xe0UL) /*!< POSIF PDBG: HSP (Bitfield-Mask: 0x07) */ 13381 #define POSIF_PDBG_LPP0_Pos (8UL) /*!< POSIF PDBG: LPP0 (Bit 8) */ 13382 #define POSIF_PDBG_LPP0_Msk (0x3f00UL) /*!< POSIF PDBG: LPP0 (Bitfield-Mask: 0x3f) */ 13383 #define POSIF_PDBG_LPP1_Pos (16UL) /*!< POSIF PDBG: LPP1 (Bit 16) */ 13384 #define POSIF_PDBG_LPP1_Msk (0x3f0000UL) /*!< POSIF PDBG: LPP1 (Bitfield-Mask: 0x3f) */ 13385 #define POSIF_PDBG_LPP2_Pos (22UL) /*!< POSIF PDBG: LPP2 (Bit 22) */ 13386 #define POSIF_PDBG_LPP2_Msk (0xfc00000UL) /*!< POSIF PDBG: LPP2 (Bitfield-Mask: 0x3f) */ 13387 13388 13389 /* ================================================================================ */ 13390 /* ================ struct 'PORT0' Position & Mask ================ */ 13391 /* ================================================================================ */ 13392 13393 13394 /* ---------------------------------- PORT0_OUT --------------------------------- */ 13395 #define PORT0_OUT_P0_Pos (0UL) /*!< PORT0 OUT: P0 (Bit 0) */ 13396 #define PORT0_OUT_P0_Msk (0x1UL) /*!< PORT0 OUT: P0 (Bitfield-Mask: 0x01) */ 13397 #define PORT0_OUT_P1_Pos (1UL) /*!< PORT0 OUT: P1 (Bit 1) */ 13398 #define PORT0_OUT_P1_Msk (0x2UL) /*!< PORT0 OUT: P1 (Bitfield-Mask: 0x01) */ 13399 #define PORT0_OUT_P2_Pos (2UL) /*!< PORT0 OUT: P2 (Bit 2) */ 13400 #define PORT0_OUT_P2_Msk (0x4UL) /*!< PORT0 OUT: P2 (Bitfield-Mask: 0x01) */ 13401 #define PORT0_OUT_P3_Pos (3UL) /*!< PORT0 OUT: P3 (Bit 3) */ 13402 #define PORT0_OUT_P3_Msk (0x8UL) /*!< PORT0 OUT: P3 (Bitfield-Mask: 0x01) */ 13403 #define PORT0_OUT_P4_Pos (4UL) /*!< PORT0 OUT: P4 (Bit 4) */ 13404 #define PORT0_OUT_P4_Msk (0x10UL) /*!< PORT0 OUT: P4 (Bitfield-Mask: 0x01) */ 13405 #define PORT0_OUT_P5_Pos (5UL) /*!< PORT0 OUT: P5 (Bit 5) */ 13406 #define PORT0_OUT_P5_Msk (0x20UL) /*!< PORT0 OUT: P5 (Bitfield-Mask: 0x01) */ 13407 #define PORT0_OUT_P6_Pos (6UL) /*!< PORT0 OUT: P6 (Bit 6) */ 13408 #define PORT0_OUT_P6_Msk (0x40UL) /*!< PORT0 OUT: P6 (Bitfield-Mask: 0x01) */ 13409 #define PORT0_OUT_P7_Pos (7UL) /*!< PORT0 OUT: P7 (Bit 7) */ 13410 #define PORT0_OUT_P7_Msk (0x80UL) /*!< PORT0 OUT: P7 (Bitfield-Mask: 0x01) */ 13411 #define PORT0_OUT_P8_Pos (8UL) /*!< PORT0 OUT: P8 (Bit 8) */ 13412 #define PORT0_OUT_P8_Msk (0x100UL) /*!< PORT0 OUT: P8 (Bitfield-Mask: 0x01) */ 13413 #define PORT0_OUT_P9_Pos (9UL) /*!< PORT0 OUT: P9 (Bit 9) */ 13414 #define PORT0_OUT_P9_Msk (0x200UL) /*!< PORT0 OUT: P9 (Bitfield-Mask: 0x01) */ 13415 #define PORT0_OUT_P10_Pos (10UL) /*!< PORT0 OUT: P10 (Bit 10) */ 13416 #define PORT0_OUT_P10_Msk (0x400UL) /*!< PORT0 OUT: P10 (Bitfield-Mask: 0x01) */ 13417 #define PORT0_OUT_P11_Pos (11UL) /*!< PORT0 OUT: P11 (Bit 11) */ 13418 #define PORT0_OUT_P11_Msk (0x800UL) /*!< PORT0 OUT: P11 (Bitfield-Mask: 0x01) */ 13419 #define PORT0_OUT_P12_Pos (12UL) /*!< PORT0 OUT: P12 (Bit 12) */ 13420 #define PORT0_OUT_P12_Msk (0x1000UL) /*!< PORT0 OUT: P12 (Bitfield-Mask: 0x01) */ 13421 #define PORT0_OUT_P13_Pos (13UL) /*!< PORT0 OUT: P13 (Bit 13) */ 13422 #define PORT0_OUT_P13_Msk (0x2000UL) /*!< PORT0 OUT: P13 (Bitfield-Mask: 0x01) */ 13423 #define PORT0_OUT_P14_Pos (14UL) /*!< PORT0 OUT: P14 (Bit 14) */ 13424 #define PORT0_OUT_P14_Msk (0x4000UL) /*!< PORT0 OUT: P14 (Bitfield-Mask: 0x01) */ 13425 #define PORT0_OUT_P15_Pos (15UL) /*!< PORT0 OUT: P15 (Bit 15) */ 13426 #define PORT0_OUT_P15_Msk (0x8000UL) /*!< PORT0 OUT: P15 (Bitfield-Mask: 0x01) */ 13427 13428 /* ---------------------------------- PORT0_OMR --------------------------------- */ 13429 #define PORT0_OMR_PS0_Pos (0UL) /*!< PORT0 OMR: PS0 (Bit 0) */ 13430 #define PORT0_OMR_PS0_Msk (0x1UL) /*!< PORT0 OMR: PS0 (Bitfield-Mask: 0x01) */ 13431 #define PORT0_OMR_PS1_Pos (1UL) /*!< PORT0 OMR: PS1 (Bit 1) */ 13432 #define PORT0_OMR_PS1_Msk (0x2UL) /*!< PORT0 OMR: PS1 (Bitfield-Mask: 0x01) */ 13433 #define PORT0_OMR_PS2_Pos (2UL) /*!< PORT0 OMR: PS2 (Bit 2) */ 13434 #define PORT0_OMR_PS2_Msk (0x4UL) /*!< PORT0 OMR: PS2 (Bitfield-Mask: 0x01) */ 13435 #define PORT0_OMR_PS3_Pos (3UL) /*!< PORT0 OMR: PS3 (Bit 3) */ 13436 #define PORT0_OMR_PS3_Msk (0x8UL) /*!< PORT0 OMR: PS3 (Bitfield-Mask: 0x01) */ 13437 #define PORT0_OMR_PS4_Pos (4UL) /*!< PORT0 OMR: PS4 (Bit 4) */ 13438 #define PORT0_OMR_PS4_Msk (0x10UL) /*!< PORT0 OMR: PS4 (Bitfield-Mask: 0x01) */ 13439 #define PORT0_OMR_PS5_Pos (5UL) /*!< PORT0 OMR: PS5 (Bit 5) */ 13440 #define PORT0_OMR_PS5_Msk (0x20UL) /*!< PORT0 OMR: PS5 (Bitfield-Mask: 0x01) */ 13441 #define PORT0_OMR_PS6_Pos (6UL) /*!< PORT0 OMR: PS6 (Bit 6) */ 13442 #define PORT0_OMR_PS6_Msk (0x40UL) /*!< PORT0 OMR: PS6 (Bitfield-Mask: 0x01) */ 13443 #define PORT0_OMR_PS7_Pos (7UL) /*!< PORT0 OMR: PS7 (Bit 7) */ 13444 #define PORT0_OMR_PS7_Msk (0x80UL) /*!< PORT0 OMR: PS7 (Bitfield-Mask: 0x01) */ 13445 #define PORT0_OMR_PS8_Pos (8UL) /*!< PORT0 OMR: PS8 (Bit 8) */ 13446 #define PORT0_OMR_PS8_Msk (0x100UL) /*!< PORT0 OMR: PS8 (Bitfield-Mask: 0x01) */ 13447 #define PORT0_OMR_PS9_Pos (9UL) /*!< PORT0 OMR: PS9 (Bit 9) */ 13448 #define PORT0_OMR_PS9_Msk (0x200UL) /*!< PORT0 OMR: PS9 (Bitfield-Mask: 0x01) */ 13449 #define PORT0_OMR_PS10_Pos (10UL) /*!< PORT0 OMR: PS10 (Bit 10) */ 13450 #define PORT0_OMR_PS10_Msk (0x400UL) /*!< PORT0 OMR: PS10 (Bitfield-Mask: 0x01) */ 13451 #define PORT0_OMR_PS11_Pos (11UL) /*!< PORT0 OMR: PS11 (Bit 11) */ 13452 #define PORT0_OMR_PS11_Msk (0x800UL) /*!< PORT0 OMR: PS11 (Bitfield-Mask: 0x01) */ 13453 #define PORT0_OMR_PS12_Pos (12UL) /*!< PORT0 OMR: PS12 (Bit 12) */ 13454 #define PORT0_OMR_PS12_Msk (0x1000UL) /*!< PORT0 OMR: PS12 (Bitfield-Mask: 0x01) */ 13455 #define PORT0_OMR_PS13_Pos (13UL) /*!< PORT0 OMR: PS13 (Bit 13) */ 13456 #define PORT0_OMR_PS13_Msk (0x2000UL) /*!< PORT0 OMR: PS13 (Bitfield-Mask: 0x01) */ 13457 #define PORT0_OMR_PS14_Pos (14UL) /*!< PORT0 OMR: PS14 (Bit 14) */ 13458 #define PORT0_OMR_PS14_Msk (0x4000UL) /*!< PORT0 OMR: PS14 (Bitfield-Mask: 0x01) */ 13459 #define PORT0_OMR_PS15_Pos (15UL) /*!< PORT0 OMR: PS15 (Bit 15) */ 13460 #define PORT0_OMR_PS15_Msk (0x8000UL) /*!< PORT0 OMR: PS15 (Bitfield-Mask: 0x01) */ 13461 #define PORT0_OMR_PR0_Pos (16UL) /*!< PORT0 OMR: PR0 (Bit 16) */ 13462 #define PORT0_OMR_PR0_Msk (0x10000UL) /*!< PORT0 OMR: PR0 (Bitfield-Mask: 0x01) */ 13463 #define PORT0_OMR_PR1_Pos (17UL) /*!< PORT0 OMR: PR1 (Bit 17) */ 13464 #define PORT0_OMR_PR1_Msk (0x20000UL) /*!< PORT0 OMR: PR1 (Bitfield-Mask: 0x01) */ 13465 #define PORT0_OMR_PR2_Pos (18UL) /*!< PORT0 OMR: PR2 (Bit 18) */ 13466 #define PORT0_OMR_PR2_Msk (0x40000UL) /*!< PORT0 OMR: PR2 (Bitfield-Mask: 0x01) */ 13467 #define PORT0_OMR_PR3_Pos (19UL) /*!< PORT0 OMR: PR3 (Bit 19) */ 13468 #define PORT0_OMR_PR3_Msk (0x80000UL) /*!< PORT0 OMR: PR3 (Bitfield-Mask: 0x01) */ 13469 #define PORT0_OMR_PR4_Pos (20UL) /*!< PORT0 OMR: PR4 (Bit 20) */ 13470 #define PORT0_OMR_PR4_Msk (0x100000UL) /*!< PORT0 OMR: PR4 (Bitfield-Mask: 0x01) */ 13471 #define PORT0_OMR_PR5_Pos (21UL) /*!< PORT0 OMR: PR5 (Bit 21) */ 13472 #define PORT0_OMR_PR5_Msk (0x200000UL) /*!< PORT0 OMR: PR5 (Bitfield-Mask: 0x01) */ 13473 #define PORT0_OMR_PR6_Pos (22UL) /*!< PORT0 OMR: PR6 (Bit 22) */ 13474 #define PORT0_OMR_PR6_Msk (0x400000UL) /*!< PORT0 OMR: PR6 (Bitfield-Mask: 0x01) */ 13475 #define PORT0_OMR_PR7_Pos (23UL) /*!< PORT0 OMR: PR7 (Bit 23) */ 13476 #define PORT0_OMR_PR7_Msk (0x800000UL) /*!< PORT0 OMR: PR7 (Bitfield-Mask: 0x01) */ 13477 #define PORT0_OMR_PR8_Pos (24UL) /*!< PORT0 OMR: PR8 (Bit 24) */ 13478 #define PORT0_OMR_PR8_Msk (0x1000000UL) /*!< PORT0 OMR: PR8 (Bitfield-Mask: 0x01) */ 13479 #define PORT0_OMR_PR9_Pos (25UL) /*!< PORT0 OMR: PR9 (Bit 25) */ 13480 #define PORT0_OMR_PR9_Msk (0x2000000UL) /*!< PORT0 OMR: PR9 (Bitfield-Mask: 0x01) */ 13481 #define PORT0_OMR_PR10_Pos (26UL) /*!< PORT0 OMR: PR10 (Bit 26) */ 13482 #define PORT0_OMR_PR10_Msk (0x4000000UL) /*!< PORT0 OMR: PR10 (Bitfield-Mask: 0x01) */ 13483 #define PORT0_OMR_PR11_Pos (27UL) /*!< PORT0 OMR: PR11 (Bit 27) */ 13484 #define PORT0_OMR_PR11_Msk (0x8000000UL) /*!< PORT0 OMR: PR11 (Bitfield-Mask: 0x01) */ 13485 #define PORT0_OMR_PR12_Pos (28UL) /*!< PORT0 OMR: PR12 (Bit 28) */ 13486 #define PORT0_OMR_PR12_Msk (0x10000000UL) /*!< PORT0 OMR: PR12 (Bitfield-Mask: 0x01) */ 13487 #define PORT0_OMR_PR13_Pos (29UL) /*!< PORT0 OMR: PR13 (Bit 29) */ 13488 #define PORT0_OMR_PR13_Msk (0x20000000UL) /*!< PORT0 OMR: PR13 (Bitfield-Mask: 0x01) */ 13489 #define PORT0_OMR_PR14_Pos (30UL) /*!< PORT0 OMR: PR14 (Bit 30) */ 13490 #define PORT0_OMR_PR14_Msk (0x40000000UL) /*!< PORT0 OMR: PR14 (Bitfield-Mask: 0x01) */ 13491 #define PORT0_OMR_PR15_Pos (31UL) /*!< PORT0 OMR: PR15 (Bit 31) */ 13492 #define PORT0_OMR_PR15_Msk (0x80000000UL) /*!< PORT0 OMR: PR15 (Bitfield-Mask: 0x01) */ 13493 13494 /* --------------------------------- PORT0_IOCR0 -------------------------------- */ 13495 #define PORT0_IOCR0_PC0_Pos (3UL) /*!< PORT0 IOCR0: PC0 (Bit 3) */ 13496 #define PORT0_IOCR0_PC0_Msk (0xf8UL) /*!< PORT0 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 13497 #define PORT0_IOCR0_PC1_Pos (11UL) /*!< PORT0 IOCR0: PC1 (Bit 11) */ 13498 #define PORT0_IOCR0_PC1_Msk (0xf800UL) /*!< PORT0 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 13499 #define PORT0_IOCR0_PC2_Pos (19UL) /*!< PORT0 IOCR0: PC2 (Bit 19) */ 13500 #define PORT0_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT0 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 13501 #define PORT0_IOCR0_PC3_Pos (27UL) /*!< PORT0 IOCR0: PC3 (Bit 27) */ 13502 #define PORT0_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT0 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 13503 13504 /* --------------------------------- PORT0_IOCR4 -------------------------------- */ 13505 #define PORT0_IOCR4_PC4_Pos (3UL) /*!< PORT0 IOCR4: PC4 (Bit 3) */ 13506 #define PORT0_IOCR4_PC4_Msk (0xf8UL) /*!< PORT0 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 13507 #define PORT0_IOCR4_PC5_Pos (11UL) /*!< PORT0 IOCR4: PC5 (Bit 11) */ 13508 #define PORT0_IOCR4_PC5_Msk (0xf800UL) /*!< PORT0 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 13509 #define PORT0_IOCR4_PC6_Pos (19UL) /*!< PORT0 IOCR4: PC6 (Bit 19) */ 13510 #define PORT0_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT0 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 13511 #define PORT0_IOCR4_PC7_Pos (27UL) /*!< PORT0 IOCR4: PC7 (Bit 27) */ 13512 #define PORT0_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT0 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 13513 13514 /* --------------------------------- PORT0_IOCR8 -------------------------------- */ 13515 #define PORT0_IOCR8_PC8_Pos (3UL) /*!< PORT0 IOCR8: PC8 (Bit 3) */ 13516 #define PORT0_IOCR8_PC8_Msk (0xf8UL) /*!< PORT0 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ 13517 #define PORT0_IOCR8_PC9_Pos (11UL) /*!< PORT0 IOCR8: PC9 (Bit 11) */ 13518 #define PORT0_IOCR8_PC9_Msk (0xf800UL) /*!< PORT0 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ 13519 #define PORT0_IOCR8_PC10_Pos (19UL) /*!< PORT0 IOCR8: PC10 (Bit 19) */ 13520 #define PORT0_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT0 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ 13521 #define PORT0_IOCR8_PC11_Pos (27UL) /*!< PORT0 IOCR8: PC11 (Bit 27) */ 13522 #define PORT0_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT0 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ 13523 13524 /* -------------------------------- PORT0_IOCR12 -------------------------------- */ 13525 #define PORT0_IOCR12_PC12_Pos (3UL) /*!< PORT0 IOCR12: PC12 (Bit 3) */ 13526 #define PORT0_IOCR12_PC12_Msk (0xf8UL) /*!< PORT0 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ 13527 #define PORT0_IOCR12_PC13_Pos (11UL) /*!< PORT0 IOCR12: PC13 (Bit 11) */ 13528 #define PORT0_IOCR12_PC13_Msk (0xf800UL) /*!< PORT0 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ 13529 #define PORT0_IOCR12_PC14_Pos (19UL) /*!< PORT0 IOCR12: PC14 (Bit 19) */ 13530 #define PORT0_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT0 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ 13531 #define PORT0_IOCR12_PC15_Pos (27UL) /*!< PORT0 IOCR12: PC15 (Bit 27) */ 13532 #define PORT0_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT0 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ 13533 13534 /* ---------------------------------- PORT0_IN ---------------------------------- */ 13535 #define PORT0_IN_P0_Pos (0UL) /*!< PORT0 IN: P0 (Bit 0) */ 13536 #define PORT0_IN_P0_Msk (0x1UL) /*!< PORT0 IN: P0 (Bitfield-Mask: 0x01) */ 13537 #define PORT0_IN_P1_Pos (1UL) /*!< PORT0 IN: P1 (Bit 1) */ 13538 #define PORT0_IN_P1_Msk (0x2UL) /*!< PORT0 IN: P1 (Bitfield-Mask: 0x01) */ 13539 #define PORT0_IN_P2_Pos (2UL) /*!< PORT0 IN: P2 (Bit 2) */ 13540 #define PORT0_IN_P2_Msk (0x4UL) /*!< PORT0 IN: P2 (Bitfield-Mask: 0x01) */ 13541 #define PORT0_IN_P3_Pos (3UL) /*!< PORT0 IN: P3 (Bit 3) */ 13542 #define PORT0_IN_P3_Msk (0x8UL) /*!< PORT0 IN: P3 (Bitfield-Mask: 0x01) */ 13543 #define PORT0_IN_P4_Pos (4UL) /*!< PORT0 IN: P4 (Bit 4) */ 13544 #define PORT0_IN_P4_Msk (0x10UL) /*!< PORT0 IN: P4 (Bitfield-Mask: 0x01) */ 13545 #define PORT0_IN_P5_Pos (5UL) /*!< PORT0 IN: P5 (Bit 5) */ 13546 #define PORT0_IN_P5_Msk (0x20UL) /*!< PORT0 IN: P5 (Bitfield-Mask: 0x01) */ 13547 #define PORT0_IN_P6_Pos (6UL) /*!< PORT0 IN: P6 (Bit 6) */ 13548 #define PORT0_IN_P6_Msk (0x40UL) /*!< PORT0 IN: P6 (Bitfield-Mask: 0x01) */ 13549 #define PORT0_IN_P7_Pos (7UL) /*!< PORT0 IN: P7 (Bit 7) */ 13550 #define PORT0_IN_P7_Msk (0x80UL) /*!< PORT0 IN: P7 (Bitfield-Mask: 0x01) */ 13551 #define PORT0_IN_P8_Pos (8UL) /*!< PORT0 IN: P8 (Bit 8) */ 13552 #define PORT0_IN_P8_Msk (0x100UL) /*!< PORT0 IN: P8 (Bitfield-Mask: 0x01) */ 13553 #define PORT0_IN_P9_Pos (9UL) /*!< PORT0 IN: P9 (Bit 9) */ 13554 #define PORT0_IN_P9_Msk (0x200UL) /*!< PORT0 IN: P9 (Bitfield-Mask: 0x01) */ 13555 #define PORT0_IN_P10_Pos (10UL) /*!< PORT0 IN: P10 (Bit 10) */ 13556 #define PORT0_IN_P10_Msk (0x400UL) /*!< PORT0 IN: P10 (Bitfield-Mask: 0x01) */ 13557 #define PORT0_IN_P11_Pos (11UL) /*!< PORT0 IN: P11 (Bit 11) */ 13558 #define PORT0_IN_P11_Msk (0x800UL) /*!< PORT0 IN: P11 (Bitfield-Mask: 0x01) */ 13559 #define PORT0_IN_P12_Pos (12UL) /*!< PORT0 IN: P12 (Bit 12) */ 13560 #define PORT0_IN_P12_Msk (0x1000UL) /*!< PORT0 IN: P12 (Bitfield-Mask: 0x01) */ 13561 #define PORT0_IN_P13_Pos (13UL) /*!< PORT0 IN: P13 (Bit 13) */ 13562 #define PORT0_IN_P13_Msk (0x2000UL) /*!< PORT0 IN: P13 (Bitfield-Mask: 0x01) */ 13563 #define PORT0_IN_P14_Pos (14UL) /*!< PORT0 IN: P14 (Bit 14) */ 13564 #define PORT0_IN_P14_Msk (0x4000UL) /*!< PORT0 IN: P14 (Bitfield-Mask: 0x01) */ 13565 #define PORT0_IN_P15_Pos (15UL) /*!< PORT0 IN: P15 (Bit 15) */ 13566 #define PORT0_IN_P15_Msk (0x8000UL) /*!< PORT0 IN: P15 (Bitfield-Mask: 0x01) */ 13567 13568 /* --------------------------------- PORT0_PDR0 --------------------------------- */ 13569 #define PORT0_PDR0_PD0_Pos (0UL) /*!< PORT0 PDR0: PD0 (Bit 0) */ 13570 #define PORT0_PDR0_PD0_Msk (0x7UL) /*!< PORT0 PDR0: PD0 (Bitfield-Mask: 0x07) */ 13571 #define PORT0_PDR0_PD1_Pos (4UL) /*!< PORT0 PDR0: PD1 (Bit 4) */ 13572 #define PORT0_PDR0_PD1_Msk (0x70UL) /*!< PORT0 PDR0: PD1 (Bitfield-Mask: 0x07) */ 13573 #define PORT0_PDR0_PD2_Pos (8UL) /*!< PORT0 PDR0: PD2 (Bit 8) */ 13574 #define PORT0_PDR0_PD2_Msk (0x700UL) /*!< PORT0 PDR0: PD2 (Bitfield-Mask: 0x07) */ 13575 #define PORT0_PDR0_PD3_Pos (12UL) /*!< PORT0 PDR0: PD3 (Bit 12) */ 13576 #define PORT0_PDR0_PD3_Msk (0x7000UL) /*!< PORT0 PDR0: PD3 (Bitfield-Mask: 0x07) */ 13577 #define PORT0_PDR0_PD4_Pos (16UL) /*!< PORT0 PDR0: PD4 (Bit 16) */ 13578 #define PORT0_PDR0_PD4_Msk (0x70000UL) /*!< PORT0 PDR0: PD4 (Bitfield-Mask: 0x07) */ 13579 #define PORT0_PDR0_PD5_Pos (20UL) /*!< PORT0 PDR0: PD5 (Bit 20) */ 13580 #define PORT0_PDR0_PD5_Msk (0x700000UL) /*!< PORT0 PDR0: PD5 (Bitfield-Mask: 0x07) */ 13581 #define PORT0_PDR0_PD6_Pos (24UL) /*!< PORT0 PDR0: PD6 (Bit 24) */ 13582 #define PORT0_PDR0_PD6_Msk (0x7000000UL) /*!< PORT0 PDR0: PD6 (Bitfield-Mask: 0x07) */ 13583 #define PORT0_PDR0_PD7_Pos (28UL) /*!< PORT0 PDR0: PD7 (Bit 28) */ 13584 #define PORT0_PDR0_PD7_Msk (0x70000000UL) /*!< PORT0 PDR0: PD7 (Bitfield-Mask: 0x07) */ 13585 13586 /* --------------------------------- PORT0_PDR1 --------------------------------- */ 13587 #define PORT0_PDR1_PD8_Pos (0UL) /*!< PORT0 PDR1: PD8 (Bit 0) */ 13588 #define PORT0_PDR1_PD8_Msk (0x7UL) /*!< PORT0 PDR1: PD8 (Bitfield-Mask: 0x07) */ 13589 #define PORT0_PDR1_PD9_Pos (4UL) /*!< PORT0 PDR1: PD9 (Bit 4) */ 13590 #define PORT0_PDR1_PD9_Msk (0x70UL) /*!< PORT0 PDR1: PD9 (Bitfield-Mask: 0x07) */ 13591 #define PORT0_PDR1_PD10_Pos (8UL) /*!< PORT0 PDR1: PD10 (Bit 8) */ 13592 #define PORT0_PDR1_PD10_Msk (0x700UL) /*!< PORT0 PDR1: PD10 (Bitfield-Mask: 0x07) */ 13593 #define PORT0_PDR1_PD11_Pos (12UL) /*!< PORT0 PDR1: PD11 (Bit 12) */ 13594 #define PORT0_PDR1_PD11_Msk (0x7000UL) /*!< PORT0 PDR1: PD11 (Bitfield-Mask: 0x07) */ 13595 #define PORT0_PDR1_PD12_Pos (16UL) /*!< PORT0 PDR1: PD12 (Bit 16) */ 13596 #define PORT0_PDR1_PD12_Msk (0x70000UL) /*!< PORT0 PDR1: PD12 (Bitfield-Mask: 0x07) */ 13597 #define PORT0_PDR1_PD13_Pos (20UL) /*!< PORT0 PDR1: PD13 (Bit 20) */ 13598 #define PORT0_PDR1_PD13_Msk (0x700000UL) /*!< PORT0 PDR1: PD13 (Bitfield-Mask: 0x07) */ 13599 #define PORT0_PDR1_PD14_Pos (24UL) /*!< PORT0 PDR1: PD14 (Bit 24) */ 13600 #define PORT0_PDR1_PD14_Msk (0x7000000UL) /*!< PORT0 PDR1: PD14 (Bitfield-Mask: 0x07) */ 13601 #define PORT0_PDR1_PD15_Pos (28UL) /*!< PORT0 PDR1: PD15 (Bit 28) */ 13602 #define PORT0_PDR1_PD15_Msk (0x70000000UL) /*!< PORT0 PDR1: PD15 (Bitfield-Mask: 0x07) */ 13603 13604 /* --------------------------------- PORT0_PDISC -------------------------------- */ 13605 #define PORT0_PDISC_PDIS0_Pos (0UL) /*!< PORT0 PDISC: PDIS0 (Bit 0) */ 13606 #define PORT0_PDISC_PDIS0_Msk (0x1UL) /*!< PORT0 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ 13607 #define PORT0_PDISC_PDIS1_Pos (1UL) /*!< PORT0 PDISC: PDIS1 (Bit 1) */ 13608 #define PORT0_PDISC_PDIS1_Msk (0x2UL) /*!< PORT0 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ 13609 #define PORT0_PDISC_PDIS2_Pos (2UL) /*!< PORT0 PDISC: PDIS2 (Bit 2) */ 13610 #define PORT0_PDISC_PDIS2_Msk (0x4UL) /*!< PORT0 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 13611 #define PORT0_PDISC_PDIS3_Pos (3UL) /*!< PORT0 PDISC: PDIS3 (Bit 3) */ 13612 #define PORT0_PDISC_PDIS3_Msk (0x8UL) /*!< PORT0 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 13613 #define PORT0_PDISC_PDIS4_Pos (4UL) /*!< PORT0 PDISC: PDIS4 (Bit 4) */ 13614 #define PORT0_PDISC_PDIS4_Msk (0x10UL) /*!< PORT0 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 13615 #define PORT0_PDISC_PDIS5_Pos (5UL) /*!< PORT0 PDISC: PDIS5 (Bit 5) */ 13616 #define PORT0_PDISC_PDIS5_Msk (0x20UL) /*!< PORT0 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 13617 #define PORT0_PDISC_PDIS6_Pos (6UL) /*!< PORT0 PDISC: PDIS6 (Bit 6) */ 13618 #define PORT0_PDISC_PDIS6_Msk (0x40UL) /*!< PORT0 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 13619 #define PORT0_PDISC_PDIS7_Pos (7UL) /*!< PORT0 PDISC: PDIS7 (Bit 7) */ 13620 #define PORT0_PDISC_PDIS7_Msk (0x80UL) /*!< PORT0 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 13621 #define PORT0_PDISC_PDIS8_Pos (8UL) /*!< PORT0 PDISC: PDIS8 (Bit 8) */ 13622 #define PORT0_PDISC_PDIS8_Msk (0x100UL) /*!< PORT0 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 13623 #define PORT0_PDISC_PDIS9_Pos (9UL) /*!< PORT0 PDISC: PDIS9 (Bit 9) */ 13624 #define PORT0_PDISC_PDIS9_Msk (0x200UL) /*!< PORT0 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 13625 #define PORT0_PDISC_PDIS10_Pos (10UL) /*!< PORT0 PDISC: PDIS10 (Bit 10) */ 13626 #define PORT0_PDISC_PDIS10_Msk (0x400UL) /*!< PORT0 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ 13627 #define PORT0_PDISC_PDIS11_Pos (11UL) /*!< PORT0 PDISC: PDIS11 (Bit 11) */ 13628 #define PORT0_PDISC_PDIS11_Msk (0x800UL) /*!< PORT0 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ 13629 #define PORT0_PDISC_PDIS12_Pos (12UL) /*!< PORT0 PDISC: PDIS12 (Bit 12) */ 13630 #define PORT0_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT0 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 13631 #define PORT0_PDISC_PDIS13_Pos (13UL) /*!< PORT0 PDISC: PDIS13 (Bit 13) */ 13632 #define PORT0_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT0 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 13633 #define PORT0_PDISC_PDIS14_Pos (14UL) /*!< PORT0 PDISC: PDIS14 (Bit 14) */ 13634 #define PORT0_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT0 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 13635 #define PORT0_PDISC_PDIS15_Pos (15UL) /*!< PORT0 PDISC: PDIS15 (Bit 15) */ 13636 #define PORT0_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT0 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 13637 13638 /* ---------------------------------- PORT0_PPS --------------------------------- */ 13639 #define PORT0_PPS_PPS0_Pos (0UL) /*!< PORT0 PPS: PPS0 (Bit 0) */ 13640 #define PORT0_PPS_PPS0_Msk (0x1UL) /*!< PORT0 PPS: PPS0 (Bitfield-Mask: 0x01) */ 13641 #define PORT0_PPS_PPS1_Pos (1UL) /*!< PORT0 PPS: PPS1 (Bit 1) */ 13642 #define PORT0_PPS_PPS1_Msk (0x2UL) /*!< PORT0 PPS: PPS1 (Bitfield-Mask: 0x01) */ 13643 #define PORT0_PPS_PPS2_Pos (2UL) /*!< PORT0 PPS: PPS2 (Bit 2) */ 13644 #define PORT0_PPS_PPS2_Msk (0x4UL) /*!< PORT0 PPS: PPS2 (Bitfield-Mask: 0x01) */ 13645 #define PORT0_PPS_PPS3_Pos (3UL) /*!< PORT0 PPS: PPS3 (Bit 3) */ 13646 #define PORT0_PPS_PPS3_Msk (0x8UL) /*!< PORT0 PPS: PPS3 (Bitfield-Mask: 0x01) */ 13647 #define PORT0_PPS_PPS4_Pos (4UL) /*!< PORT0 PPS: PPS4 (Bit 4) */ 13648 #define PORT0_PPS_PPS4_Msk (0x10UL) /*!< PORT0 PPS: PPS4 (Bitfield-Mask: 0x01) */ 13649 #define PORT0_PPS_PPS5_Pos (5UL) /*!< PORT0 PPS: PPS5 (Bit 5) */ 13650 #define PORT0_PPS_PPS5_Msk (0x20UL) /*!< PORT0 PPS: PPS5 (Bitfield-Mask: 0x01) */ 13651 #define PORT0_PPS_PPS6_Pos (6UL) /*!< PORT0 PPS: PPS6 (Bit 6) */ 13652 #define PORT0_PPS_PPS6_Msk (0x40UL) /*!< PORT0 PPS: PPS6 (Bitfield-Mask: 0x01) */ 13653 #define PORT0_PPS_PPS7_Pos (7UL) /*!< PORT0 PPS: PPS7 (Bit 7) */ 13654 #define PORT0_PPS_PPS7_Msk (0x80UL) /*!< PORT0 PPS: PPS7 (Bitfield-Mask: 0x01) */ 13655 #define PORT0_PPS_PPS8_Pos (8UL) /*!< PORT0 PPS: PPS8 (Bit 8) */ 13656 #define PORT0_PPS_PPS8_Msk (0x100UL) /*!< PORT0 PPS: PPS8 (Bitfield-Mask: 0x01) */ 13657 #define PORT0_PPS_PPS9_Pos (9UL) /*!< PORT0 PPS: PPS9 (Bit 9) */ 13658 #define PORT0_PPS_PPS9_Msk (0x200UL) /*!< PORT0 PPS: PPS9 (Bitfield-Mask: 0x01) */ 13659 #define PORT0_PPS_PPS10_Pos (10UL) /*!< PORT0 PPS: PPS10 (Bit 10) */ 13660 #define PORT0_PPS_PPS10_Msk (0x400UL) /*!< PORT0 PPS: PPS10 (Bitfield-Mask: 0x01) */ 13661 #define PORT0_PPS_PPS11_Pos (11UL) /*!< PORT0 PPS: PPS11 (Bit 11) */ 13662 #define PORT0_PPS_PPS11_Msk (0x800UL) /*!< PORT0 PPS: PPS11 (Bitfield-Mask: 0x01) */ 13663 #define PORT0_PPS_PPS12_Pos (12UL) /*!< PORT0 PPS: PPS12 (Bit 12) */ 13664 #define PORT0_PPS_PPS12_Msk (0x1000UL) /*!< PORT0 PPS: PPS12 (Bitfield-Mask: 0x01) */ 13665 #define PORT0_PPS_PPS13_Pos (13UL) /*!< PORT0 PPS: PPS13 (Bit 13) */ 13666 #define PORT0_PPS_PPS13_Msk (0x2000UL) /*!< PORT0 PPS: PPS13 (Bitfield-Mask: 0x01) */ 13667 #define PORT0_PPS_PPS14_Pos (14UL) /*!< PORT0 PPS: PPS14 (Bit 14) */ 13668 #define PORT0_PPS_PPS14_Msk (0x4000UL) /*!< PORT0 PPS: PPS14 (Bitfield-Mask: 0x01) */ 13669 #define PORT0_PPS_PPS15_Pos (15UL) /*!< PORT0 PPS: PPS15 (Bit 15) */ 13670 #define PORT0_PPS_PPS15_Msk (0x8000UL) /*!< PORT0 PPS: PPS15 (Bitfield-Mask: 0x01) */ 13671 13672 /* --------------------------------- PORT0_HWSEL -------------------------------- */ 13673 #define PORT0_HWSEL_HW0_Pos (0UL) /*!< PORT0 HWSEL: HW0 (Bit 0) */ 13674 #define PORT0_HWSEL_HW0_Msk (0x3UL) /*!< PORT0 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 13675 #define PORT0_HWSEL_HW1_Pos (2UL) /*!< PORT0 HWSEL: HW1 (Bit 2) */ 13676 #define PORT0_HWSEL_HW1_Msk (0xcUL) /*!< PORT0 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 13677 #define PORT0_HWSEL_HW2_Pos (4UL) /*!< PORT0 HWSEL: HW2 (Bit 4) */ 13678 #define PORT0_HWSEL_HW2_Msk (0x30UL) /*!< PORT0 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 13679 #define PORT0_HWSEL_HW3_Pos (6UL) /*!< PORT0 HWSEL: HW3 (Bit 6) */ 13680 #define PORT0_HWSEL_HW3_Msk (0xc0UL) /*!< PORT0 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 13681 #define PORT0_HWSEL_HW4_Pos (8UL) /*!< PORT0 HWSEL: HW4 (Bit 8) */ 13682 #define PORT0_HWSEL_HW4_Msk (0x300UL) /*!< PORT0 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 13683 #define PORT0_HWSEL_HW5_Pos (10UL) /*!< PORT0 HWSEL: HW5 (Bit 10) */ 13684 #define PORT0_HWSEL_HW5_Msk (0xc00UL) /*!< PORT0 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 13685 #define PORT0_HWSEL_HW6_Pos (12UL) /*!< PORT0 HWSEL: HW6 (Bit 12) */ 13686 #define PORT0_HWSEL_HW6_Msk (0x3000UL) /*!< PORT0 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 13687 #define PORT0_HWSEL_HW7_Pos (14UL) /*!< PORT0 HWSEL: HW7 (Bit 14) */ 13688 #define PORT0_HWSEL_HW7_Msk (0xc000UL) /*!< PORT0 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 13689 #define PORT0_HWSEL_HW8_Pos (16UL) /*!< PORT0 HWSEL: HW8 (Bit 16) */ 13690 #define PORT0_HWSEL_HW8_Msk (0x30000UL) /*!< PORT0 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 13691 #define PORT0_HWSEL_HW9_Pos (18UL) /*!< PORT0 HWSEL: HW9 (Bit 18) */ 13692 #define PORT0_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT0 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 13693 #define PORT0_HWSEL_HW10_Pos (20UL) /*!< PORT0 HWSEL: HW10 (Bit 20) */ 13694 #define PORT0_HWSEL_HW10_Msk (0x300000UL) /*!< PORT0 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 13695 #define PORT0_HWSEL_HW11_Pos (22UL) /*!< PORT0 HWSEL: HW11 (Bit 22) */ 13696 #define PORT0_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT0 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 13697 #define PORT0_HWSEL_HW12_Pos (24UL) /*!< PORT0 HWSEL: HW12 (Bit 24) */ 13698 #define PORT0_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT0 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 13699 #define PORT0_HWSEL_HW13_Pos (26UL) /*!< PORT0 HWSEL: HW13 (Bit 26) */ 13700 #define PORT0_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT0 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 13701 #define PORT0_HWSEL_HW14_Pos (28UL) /*!< PORT0 HWSEL: HW14 (Bit 28) */ 13702 #define PORT0_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT0 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 13703 #define PORT0_HWSEL_HW15_Pos (30UL) /*!< PORT0 HWSEL: HW15 (Bit 30) */ 13704 #define PORT0_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT0 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 13705 13706 13707 /* ================================================================================ */ 13708 /* ================ struct 'PORT1' Position & Mask ================ */ 13709 /* ================================================================================ */ 13710 13711 13712 /* ---------------------------------- PORT1_OUT --------------------------------- */ 13713 #define PORT1_OUT_P0_Pos (0UL) /*!< PORT1 OUT: P0 (Bit 0) */ 13714 #define PORT1_OUT_P0_Msk (0x1UL) /*!< PORT1 OUT: P0 (Bitfield-Mask: 0x01) */ 13715 #define PORT1_OUT_P1_Pos (1UL) /*!< PORT1 OUT: P1 (Bit 1) */ 13716 #define PORT1_OUT_P1_Msk (0x2UL) /*!< PORT1 OUT: P1 (Bitfield-Mask: 0x01) */ 13717 #define PORT1_OUT_P2_Pos (2UL) /*!< PORT1 OUT: P2 (Bit 2) */ 13718 #define PORT1_OUT_P2_Msk (0x4UL) /*!< PORT1 OUT: P2 (Bitfield-Mask: 0x01) */ 13719 #define PORT1_OUT_P3_Pos (3UL) /*!< PORT1 OUT: P3 (Bit 3) */ 13720 #define PORT1_OUT_P3_Msk (0x8UL) /*!< PORT1 OUT: P3 (Bitfield-Mask: 0x01) */ 13721 #define PORT1_OUT_P4_Pos (4UL) /*!< PORT1 OUT: P4 (Bit 4) */ 13722 #define PORT1_OUT_P4_Msk (0x10UL) /*!< PORT1 OUT: P4 (Bitfield-Mask: 0x01) */ 13723 #define PORT1_OUT_P5_Pos (5UL) /*!< PORT1 OUT: P5 (Bit 5) */ 13724 #define PORT1_OUT_P5_Msk (0x20UL) /*!< PORT1 OUT: P5 (Bitfield-Mask: 0x01) */ 13725 #define PORT1_OUT_P6_Pos (6UL) /*!< PORT1 OUT: P6 (Bit 6) */ 13726 #define PORT1_OUT_P6_Msk (0x40UL) /*!< PORT1 OUT: P6 (Bitfield-Mask: 0x01) */ 13727 #define PORT1_OUT_P7_Pos (7UL) /*!< PORT1 OUT: P7 (Bit 7) */ 13728 #define PORT1_OUT_P7_Msk (0x80UL) /*!< PORT1 OUT: P7 (Bitfield-Mask: 0x01) */ 13729 #define PORT1_OUT_P8_Pos (8UL) /*!< PORT1 OUT: P8 (Bit 8) */ 13730 #define PORT1_OUT_P8_Msk (0x100UL) /*!< PORT1 OUT: P8 (Bitfield-Mask: 0x01) */ 13731 #define PORT1_OUT_P9_Pos (9UL) /*!< PORT1 OUT: P9 (Bit 9) */ 13732 #define PORT1_OUT_P9_Msk (0x200UL) /*!< PORT1 OUT: P9 (Bitfield-Mask: 0x01) */ 13733 #define PORT1_OUT_P10_Pos (10UL) /*!< PORT1 OUT: P10 (Bit 10) */ 13734 #define PORT1_OUT_P10_Msk (0x400UL) /*!< PORT1 OUT: P10 (Bitfield-Mask: 0x01) */ 13735 #define PORT1_OUT_P11_Pos (11UL) /*!< PORT1 OUT: P11 (Bit 11) */ 13736 #define PORT1_OUT_P11_Msk (0x800UL) /*!< PORT1 OUT: P11 (Bitfield-Mask: 0x01) */ 13737 #define PORT1_OUT_P12_Pos (12UL) /*!< PORT1 OUT: P12 (Bit 12) */ 13738 #define PORT1_OUT_P12_Msk (0x1000UL) /*!< PORT1 OUT: P12 (Bitfield-Mask: 0x01) */ 13739 #define PORT1_OUT_P13_Pos (13UL) /*!< PORT1 OUT: P13 (Bit 13) */ 13740 #define PORT1_OUT_P13_Msk (0x2000UL) /*!< PORT1 OUT: P13 (Bitfield-Mask: 0x01) */ 13741 #define PORT1_OUT_P14_Pos (14UL) /*!< PORT1 OUT: P14 (Bit 14) */ 13742 #define PORT1_OUT_P14_Msk (0x4000UL) /*!< PORT1 OUT: P14 (Bitfield-Mask: 0x01) */ 13743 #define PORT1_OUT_P15_Pos (15UL) /*!< PORT1 OUT: P15 (Bit 15) */ 13744 #define PORT1_OUT_P15_Msk (0x8000UL) /*!< PORT1 OUT: P15 (Bitfield-Mask: 0x01) */ 13745 13746 /* ---------------------------------- PORT1_OMR --------------------------------- */ 13747 #define PORT1_OMR_PS0_Pos (0UL) /*!< PORT1 OMR: PS0 (Bit 0) */ 13748 #define PORT1_OMR_PS0_Msk (0x1UL) /*!< PORT1 OMR: PS0 (Bitfield-Mask: 0x01) */ 13749 #define PORT1_OMR_PS1_Pos (1UL) /*!< PORT1 OMR: PS1 (Bit 1) */ 13750 #define PORT1_OMR_PS1_Msk (0x2UL) /*!< PORT1 OMR: PS1 (Bitfield-Mask: 0x01) */ 13751 #define PORT1_OMR_PS2_Pos (2UL) /*!< PORT1 OMR: PS2 (Bit 2) */ 13752 #define PORT1_OMR_PS2_Msk (0x4UL) /*!< PORT1 OMR: PS2 (Bitfield-Mask: 0x01) */ 13753 #define PORT1_OMR_PS3_Pos (3UL) /*!< PORT1 OMR: PS3 (Bit 3) */ 13754 #define PORT1_OMR_PS3_Msk (0x8UL) /*!< PORT1 OMR: PS3 (Bitfield-Mask: 0x01) */ 13755 #define PORT1_OMR_PS4_Pos (4UL) /*!< PORT1 OMR: PS4 (Bit 4) */ 13756 #define PORT1_OMR_PS4_Msk (0x10UL) /*!< PORT1 OMR: PS4 (Bitfield-Mask: 0x01) */ 13757 #define PORT1_OMR_PS5_Pos (5UL) /*!< PORT1 OMR: PS5 (Bit 5) */ 13758 #define PORT1_OMR_PS5_Msk (0x20UL) /*!< PORT1 OMR: PS5 (Bitfield-Mask: 0x01) */ 13759 #define PORT1_OMR_PS6_Pos (6UL) /*!< PORT1 OMR: PS6 (Bit 6) */ 13760 #define PORT1_OMR_PS6_Msk (0x40UL) /*!< PORT1 OMR: PS6 (Bitfield-Mask: 0x01) */ 13761 #define PORT1_OMR_PS7_Pos (7UL) /*!< PORT1 OMR: PS7 (Bit 7) */ 13762 #define PORT1_OMR_PS7_Msk (0x80UL) /*!< PORT1 OMR: PS7 (Bitfield-Mask: 0x01) */ 13763 #define PORT1_OMR_PS8_Pos (8UL) /*!< PORT1 OMR: PS8 (Bit 8) */ 13764 #define PORT1_OMR_PS8_Msk (0x100UL) /*!< PORT1 OMR: PS8 (Bitfield-Mask: 0x01) */ 13765 #define PORT1_OMR_PS9_Pos (9UL) /*!< PORT1 OMR: PS9 (Bit 9) */ 13766 #define PORT1_OMR_PS9_Msk (0x200UL) /*!< PORT1 OMR: PS9 (Bitfield-Mask: 0x01) */ 13767 #define PORT1_OMR_PS10_Pos (10UL) /*!< PORT1 OMR: PS10 (Bit 10) */ 13768 #define PORT1_OMR_PS10_Msk (0x400UL) /*!< PORT1 OMR: PS10 (Bitfield-Mask: 0x01) */ 13769 #define PORT1_OMR_PS11_Pos (11UL) /*!< PORT1 OMR: PS11 (Bit 11) */ 13770 #define PORT1_OMR_PS11_Msk (0x800UL) /*!< PORT1 OMR: PS11 (Bitfield-Mask: 0x01) */ 13771 #define PORT1_OMR_PS12_Pos (12UL) /*!< PORT1 OMR: PS12 (Bit 12) */ 13772 #define PORT1_OMR_PS12_Msk (0x1000UL) /*!< PORT1 OMR: PS12 (Bitfield-Mask: 0x01) */ 13773 #define PORT1_OMR_PS13_Pos (13UL) /*!< PORT1 OMR: PS13 (Bit 13) */ 13774 #define PORT1_OMR_PS13_Msk (0x2000UL) /*!< PORT1 OMR: PS13 (Bitfield-Mask: 0x01) */ 13775 #define PORT1_OMR_PS14_Pos (14UL) /*!< PORT1 OMR: PS14 (Bit 14) */ 13776 #define PORT1_OMR_PS14_Msk (0x4000UL) /*!< PORT1 OMR: PS14 (Bitfield-Mask: 0x01) */ 13777 #define PORT1_OMR_PS15_Pos (15UL) /*!< PORT1 OMR: PS15 (Bit 15) */ 13778 #define PORT1_OMR_PS15_Msk (0x8000UL) /*!< PORT1 OMR: PS15 (Bitfield-Mask: 0x01) */ 13779 #define PORT1_OMR_PR0_Pos (16UL) /*!< PORT1 OMR: PR0 (Bit 16) */ 13780 #define PORT1_OMR_PR0_Msk (0x10000UL) /*!< PORT1 OMR: PR0 (Bitfield-Mask: 0x01) */ 13781 #define PORT1_OMR_PR1_Pos (17UL) /*!< PORT1 OMR: PR1 (Bit 17) */ 13782 #define PORT1_OMR_PR1_Msk (0x20000UL) /*!< PORT1 OMR: PR1 (Bitfield-Mask: 0x01) */ 13783 #define PORT1_OMR_PR2_Pos (18UL) /*!< PORT1 OMR: PR2 (Bit 18) */ 13784 #define PORT1_OMR_PR2_Msk (0x40000UL) /*!< PORT1 OMR: PR2 (Bitfield-Mask: 0x01) */ 13785 #define PORT1_OMR_PR3_Pos (19UL) /*!< PORT1 OMR: PR3 (Bit 19) */ 13786 #define PORT1_OMR_PR3_Msk (0x80000UL) /*!< PORT1 OMR: PR3 (Bitfield-Mask: 0x01) */ 13787 #define PORT1_OMR_PR4_Pos (20UL) /*!< PORT1 OMR: PR4 (Bit 20) */ 13788 #define PORT1_OMR_PR4_Msk (0x100000UL) /*!< PORT1 OMR: PR4 (Bitfield-Mask: 0x01) */ 13789 #define PORT1_OMR_PR5_Pos (21UL) /*!< PORT1 OMR: PR5 (Bit 21) */ 13790 #define PORT1_OMR_PR5_Msk (0x200000UL) /*!< PORT1 OMR: PR5 (Bitfield-Mask: 0x01) */ 13791 #define PORT1_OMR_PR6_Pos (22UL) /*!< PORT1 OMR: PR6 (Bit 22) */ 13792 #define PORT1_OMR_PR6_Msk (0x400000UL) /*!< PORT1 OMR: PR6 (Bitfield-Mask: 0x01) */ 13793 #define PORT1_OMR_PR7_Pos (23UL) /*!< PORT1 OMR: PR7 (Bit 23) */ 13794 #define PORT1_OMR_PR7_Msk (0x800000UL) /*!< PORT1 OMR: PR7 (Bitfield-Mask: 0x01) */ 13795 #define PORT1_OMR_PR8_Pos (24UL) /*!< PORT1 OMR: PR8 (Bit 24) */ 13796 #define PORT1_OMR_PR8_Msk (0x1000000UL) /*!< PORT1 OMR: PR8 (Bitfield-Mask: 0x01) */ 13797 #define PORT1_OMR_PR9_Pos (25UL) /*!< PORT1 OMR: PR9 (Bit 25) */ 13798 #define PORT1_OMR_PR9_Msk (0x2000000UL) /*!< PORT1 OMR: PR9 (Bitfield-Mask: 0x01) */ 13799 #define PORT1_OMR_PR10_Pos (26UL) /*!< PORT1 OMR: PR10 (Bit 26) */ 13800 #define PORT1_OMR_PR10_Msk (0x4000000UL) /*!< PORT1 OMR: PR10 (Bitfield-Mask: 0x01) */ 13801 #define PORT1_OMR_PR11_Pos (27UL) /*!< PORT1 OMR: PR11 (Bit 27) */ 13802 #define PORT1_OMR_PR11_Msk (0x8000000UL) /*!< PORT1 OMR: PR11 (Bitfield-Mask: 0x01) */ 13803 #define PORT1_OMR_PR12_Pos (28UL) /*!< PORT1 OMR: PR12 (Bit 28) */ 13804 #define PORT1_OMR_PR12_Msk (0x10000000UL) /*!< PORT1 OMR: PR12 (Bitfield-Mask: 0x01) */ 13805 #define PORT1_OMR_PR13_Pos (29UL) /*!< PORT1 OMR: PR13 (Bit 29) */ 13806 #define PORT1_OMR_PR13_Msk (0x20000000UL) /*!< PORT1 OMR: PR13 (Bitfield-Mask: 0x01) */ 13807 #define PORT1_OMR_PR14_Pos (30UL) /*!< PORT1 OMR: PR14 (Bit 30) */ 13808 #define PORT1_OMR_PR14_Msk (0x40000000UL) /*!< PORT1 OMR: PR14 (Bitfield-Mask: 0x01) */ 13809 #define PORT1_OMR_PR15_Pos (31UL) /*!< PORT1 OMR: PR15 (Bit 31) */ 13810 #define PORT1_OMR_PR15_Msk (0x80000000UL) /*!< PORT1 OMR: PR15 (Bitfield-Mask: 0x01) */ 13811 13812 /* --------------------------------- PORT1_IOCR0 -------------------------------- */ 13813 #define PORT1_IOCR0_PC0_Pos (3UL) /*!< PORT1 IOCR0: PC0 (Bit 3) */ 13814 #define PORT1_IOCR0_PC0_Msk (0xf8UL) /*!< PORT1 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 13815 #define PORT1_IOCR0_PC1_Pos (11UL) /*!< PORT1 IOCR0: PC1 (Bit 11) */ 13816 #define PORT1_IOCR0_PC1_Msk (0xf800UL) /*!< PORT1 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 13817 #define PORT1_IOCR0_PC2_Pos (19UL) /*!< PORT1 IOCR0: PC2 (Bit 19) */ 13818 #define PORT1_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT1 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 13819 #define PORT1_IOCR0_PC3_Pos (27UL) /*!< PORT1 IOCR0: PC3 (Bit 27) */ 13820 #define PORT1_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT1 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 13821 13822 /* --------------------------------- PORT1_IOCR4 -------------------------------- */ 13823 #define PORT1_IOCR4_PC4_Pos (3UL) /*!< PORT1 IOCR4: PC4 (Bit 3) */ 13824 #define PORT1_IOCR4_PC4_Msk (0xf8UL) /*!< PORT1 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 13825 #define PORT1_IOCR4_PC5_Pos (11UL) /*!< PORT1 IOCR4: PC5 (Bit 11) */ 13826 #define PORT1_IOCR4_PC5_Msk (0xf800UL) /*!< PORT1 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 13827 #define PORT1_IOCR4_PC6_Pos (19UL) /*!< PORT1 IOCR4: PC6 (Bit 19) */ 13828 #define PORT1_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT1 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 13829 #define PORT1_IOCR4_PC7_Pos (27UL) /*!< PORT1 IOCR4: PC7 (Bit 27) */ 13830 #define PORT1_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT1 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 13831 13832 /* --------------------------------- PORT1_IOCR8 -------------------------------- */ 13833 #define PORT1_IOCR8_PC8_Pos (3UL) /*!< PORT1 IOCR8: PC8 (Bit 3) */ 13834 #define PORT1_IOCR8_PC8_Msk (0xf8UL) /*!< PORT1 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ 13835 #define PORT1_IOCR8_PC9_Pos (11UL) /*!< PORT1 IOCR8: PC9 (Bit 11) */ 13836 #define PORT1_IOCR8_PC9_Msk (0xf800UL) /*!< PORT1 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ 13837 #define PORT1_IOCR8_PC10_Pos (19UL) /*!< PORT1 IOCR8: PC10 (Bit 19) */ 13838 #define PORT1_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT1 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ 13839 #define PORT1_IOCR8_PC11_Pos (27UL) /*!< PORT1 IOCR8: PC11 (Bit 27) */ 13840 #define PORT1_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT1 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ 13841 13842 /* -------------------------------- PORT1_IOCR12 -------------------------------- */ 13843 #define PORT1_IOCR12_PC12_Pos (3UL) /*!< PORT1 IOCR12: PC12 (Bit 3) */ 13844 #define PORT1_IOCR12_PC12_Msk (0xf8UL) /*!< PORT1 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ 13845 #define PORT1_IOCR12_PC13_Pos (11UL) /*!< PORT1 IOCR12: PC13 (Bit 11) */ 13846 #define PORT1_IOCR12_PC13_Msk (0xf800UL) /*!< PORT1 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ 13847 #define PORT1_IOCR12_PC14_Pos (19UL) /*!< PORT1 IOCR12: PC14 (Bit 19) */ 13848 #define PORT1_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT1 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ 13849 #define PORT1_IOCR12_PC15_Pos (27UL) /*!< PORT1 IOCR12: PC15 (Bit 27) */ 13850 #define PORT1_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT1 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ 13851 13852 /* ---------------------------------- PORT1_IN ---------------------------------- */ 13853 #define PORT1_IN_P0_Pos (0UL) /*!< PORT1 IN: P0 (Bit 0) */ 13854 #define PORT1_IN_P0_Msk (0x1UL) /*!< PORT1 IN: P0 (Bitfield-Mask: 0x01) */ 13855 #define PORT1_IN_P1_Pos (1UL) /*!< PORT1 IN: P1 (Bit 1) */ 13856 #define PORT1_IN_P1_Msk (0x2UL) /*!< PORT1 IN: P1 (Bitfield-Mask: 0x01) */ 13857 #define PORT1_IN_P2_Pos (2UL) /*!< PORT1 IN: P2 (Bit 2) */ 13858 #define PORT1_IN_P2_Msk (0x4UL) /*!< PORT1 IN: P2 (Bitfield-Mask: 0x01) */ 13859 #define PORT1_IN_P3_Pos (3UL) /*!< PORT1 IN: P3 (Bit 3) */ 13860 #define PORT1_IN_P3_Msk (0x8UL) /*!< PORT1 IN: P3 (Bitfield-Mask: 0x01) */ 13861 #define PORT1_IN_P4_Pos (4UL) /*!< PORT1 IN: P4 (Bit 4) */ 13862 #define PORT1_IN_P4_Msk (0x10UL) /*!< PORT1 IN: P4 (Bitfield-Mask: 0x01) */ 13863 #define PORT1_IN_P5_Pos (5UL) /*!< PORT1 IN: P5 (Bit 5) */ 13864 #define PORT1_IN_P5_Msk (0x20UL) /*!< PORT1 IN: P5 (Bitfield-Mask: 0x01) */ 13865 #define PORT1_IN_P6_Pos (6UL) /*!< PORT1 IN: P6 (Bit 6) */ 13866 #define PORT1_IN_P6_Msk (0x40UL) /*!< PORT1 IN: P6 (Bitfield-Mask: 0x01) */ 13867 #define PORT1_IN_P7_Pos (7UL) /*!< PORT1 IN: P7 (Bit 7) */ 13868 #define PORT1_IN_P7_Msk (0x80UL) /*!< PORT1 IN: P7 (Bitfield-Mask: 0x01) */ 13869 #define PORT1_IN_P8_Pos (8UL) /*!< PORT1 IN: P8 (Bit 8) */ 13870 #define PORT1_IN_P8_Msk (0x100UL) /*!< PORT1 IN: P8 (Bitfield-Mask: 0x01) */ 13871 #define PORT1_IN_P9_Pos (9UL) /*!< PORT1 IN: P9 (Bit 9) */ 13872 #define PORT1_IN_P9_Msk (0x200UL) /*!< PORT1 IN: P9 (Bitfield-Mask: 0x01) */ 13873 #define PORT1_IN_P10_Pos (10UL) /*!< PORT1 IN: P10 (Bit 10) */ 13874 #define PORT1_IN_P10_Msk (0x400UL) /*!< PORT1 IN: P10 (Bitfield-Mask: 0x01) */ 13875 #define PORT1_IN_P11_Pos (11UL) /*!< PORT1 IN: P11 (Bit 11) */ 13876 #define PORT1_IN_P11_Msk (0x800UL) /*!< PORT1 IN: P11 (Bitfield-Mask: 0x01) */ 13877 #define PORT1_IN_P12_Pos (12UL) /*!< PORT1 IN: P12 (Bit 12) */ 13878 #define PORT1_IN_P12_Msk (0x1000UL) /*!< PORT1 IN: P12 (Bitfield-Mask: 0x01) */ 13879 #define PORT1_IN_P13_Pos (13UL) /*!< PORT1 IN: P13 (Bit 13) */ 13880 #define PORT1_IN_P13_Msk (0x2000UL) /*!< PORT1 IN: P13 (Bitfield-Mask: 0x01) */ 13881 #define PORT1_IN_P14_Pos (14UL) /*!< PORT1 IN: P14 (Bit 14) */ 13882 #define PORT1_IN_P14_Msk (0x4000UL) /*!< PORT1 IN: P14 (Bitfield-Mask: 0x01) */ 13883 #define PORT1_IN_P15_Pos (15UL) /*!< PORT1 IN: P15 (Bit 15) */ 13884 #define PORT1_IN_P15_Msk (0x8000UL) /*!< PORT1 IN: P15 (Bitfield-Mask: 0x01) */ 13885 13886 /* --------------------------------- PORT1_PDR0 --------------------------------- */ 13887 #define PORT1_PDR0_PD0_Pos (0UL) /*!< PORT1 PDR0: PD0 (Bit 0) */ 13888 #define PORT1_PDR0_PD0_Msk (0x7UL) /*!< PORT1 PDR0: PD0 (Bitfield-Mask: 0x07) */ 13889 #define PORT1_PDR0_PD1_Pos (4UL) /*!< PORT1 PDR0: PD1 (Bit 4) */ 13890 #define PORT1_PDR0_PD1_Msk (0x70UL) /*!< PORT1 PDR0: PD1 (Bitfield-Mask: 0x07) */ 13891 #define PORT1_PDR0_PD2_Pos (8UL) /*!< PORT1 PDR0: PD2 (Bit 8) */ 13892 #define PORT1_PDR0_PD2_Msk (0x700UL) /*!< PORT1 PDR0: PD2 (Bitfield-Mask: 0x07) */ 13893 #define PORT1_PDR0_PD3_Pos (12UL) /*!< PORT1 PDR0: PD3 (Bit 12) */ 13894 #define PORT1_PDR0_PD3_Msk (0x7000UL) /*!< PORT1 PDR0: PD3 (Bitfield-Mask: 0x07) */ 13895 #define PORT1_PDR0_PD4_Pos (16UL) /*!< PORT1 PDR0: PD4 (Bit 16) */ 13896 #define PORT1_PDR0_PD4_Msk (0x70000UL) /*!< PORT1 PDR0: PD4 (Bitfield-Mask: 0x07) */ 13897 #define PORT1_PDR0_PD5_Pos (20UL) /*!< PORT1 PDR0: PD5 (Bit 20) */ 13898 #define PORT1_PDR0_PD5_Msk (0x700000UL) /*!< PORT1 PDR0: PD5 (Bitfield-Mask: 0x07) */ 13899 #define PORT1_PDR0_PD6_Pos (24UL) /*!< PORT1 PDR0: PD6 (Bit 24) */ 13900 #define PORT1_PDR0_PD6_Msk (0x7000000UL) /*!< PORT1 PDR0: PD6 (Bitfield-Mask: 0x07) */ 13901 #define PORT1_PDR0_PD7_Pos (28UL) /*!< PORT1 PDR0: PD7 (Bit 28) */ 13902 #define PORT1_PDR0_PD7_Msk (0x70000000UL) /*!< PORT1 PDR0: PD7 (Bitfield-Mask: 0x07) */ 13903 13904 /* --------------------------------- PORT1_PDR1 --------------------------------- */ 13905 #define PORT1_PDR1_PD8_Pos (0UL) /*!< PORT1 PDR1: PD8 (Bit 0) */ 13906 #define PORT1_PDR1_PD8_Msk (0x7UL) /*!< PORT1 PDR1: PD8 (Bitfield-Mask: 0x07) */ 13907 #define PORT1_PDR1_PD9_Pos (4UL) /*!< PORT1 PDR1: PD9 (Bit 4) */ 13908 #define PORT1_PDR1_PD9_Msk (0x70UL) /*!< PORT1 PDR1: PD9 (Bitfield-Mask: 0x07) */ 13909 #define PORT1_PDR1_PD10_Pos (8UL) /*!< PORT1 PDR1: PD10 (Bit 8) */ 13910 #define PORT1_PDR1_PD10_Msk (0x700UL) /*!< PORT1 PDR1: PD10 (Bitfield-Mask: 0x07) */ 13911 #define PORT1_PDR1_PD11_Pos (12UL) /*!< PORT1 PDR1: PD11 (Bit 12) */ 13912 #define PORT1_PDR1_PD11_Msk (0x7000UL) /*!< PORT1 PDR1: PD11 (Bitfield-Mask: 0x07) */ 13913 #define PORT1_PDR1_PD12_Pos (16UL) /*!< PORT1 PDR1: PD12 (Bit 16) */ 13914 #define PORT1_PDR1_PD12_Msk (0x70000UL) /*!< PORT1 PDR1: PD12 (Bitfield-Mask: 0x07) */ 13915 #define PORT1_PDR1_PD13_Pos (20UL) /*!< PORT1 PDR1: PD13 (Bit 20) */ 13916 #define PORT1_PDR1_PD13_Msk (0x700000UL) /*!< PORT1 PDR1: PD13 (Bitfield-Mask: 0x07) */ 13917 #define PORT1_PDR1_PD14_Pos (24UL) /*!< PORT1 PDR1: PD14 (Bit 24) */ 13918 #define PORT1_PDR1_PD14_Msk (0x7000000UL) /*!< PORT1 PDR1: PD14 (Bitfield-Mask: 0x07) */ 13919 #define PORT1_PDR1_PD15_Pos (28UL) /*!< PORT1 PDR1: PD15 (Bit 28) */ 13920 #define PORT1_PDR1_PD15_Msk (0x70000000UL) /*!< PORT1 PDR1: PD15 (Bitfield-Mask: 0x07) */ 13921 13922 /* --------------------------------- PORT1_PDISC -------------------------------- */ 13923 #define PORT1_PDISC_PDIS0_Pos (0UL) /*!< PORT1 PDISC: PDIS0 (Bit 0) */ 13924 #define PORT1_PDISC_PDIS0_Msk (0x1UL) /*!< PORT1 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ 13925 #define PORT1_PDISC_PDIS1_Pos (1UL) /*!< PORT1 PDISC: PDIS1 (Bit 1) */ 13926 #define PORT1_PDISC_PDIS1_Msk (0x2UL) /*!< PORT1 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ 13927 #define PORT1_PDISC_PDIS2_Pos (2UL) /*!< PORT1 PDISC: PDIS2 (Bit 2) */ 13928 #define PORT1_PDISC_PDIS2_Msk (0x4UL) /*!< PORT1 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 13929 #define PORT1_PDISC_PDIS3_Pos (3UL) /*!< PORT1 PDISC: PDIS3 (Bit 3) */ 13930 #define PORT1_PDISC_PDIS3_Msk (0x8UL) /*!< PORT1 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 13931 #define PORT1_PDISC_PDIS4_Pos (4UL) /*!< PORT1 PDISC: PDIS4 (Bit 4) */ 13932 #define PORT1_PDISC_PDIS4_Msk (0x10UL) /*!< PORT1 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 13933 #define PORT1_PDISC_PDIS5_Pos (5UL) /*!< PORT1 PDISC: PDIS5 (Bit 5) */ 13934 #define PORT1_PDISC_PDIS5_Msk (0x20UL) /*!< PORT1 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 13935 #define PORT1_PDISC_PDIS6_Pos (6UL) /*!< PORT1 PDISC: PDIS6 (Bit 6) */ 13936 #define PORT1_PDISC_PDIS6_Msk (0x40UL) /*!< PORT1 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 13937 #define PORT1_PDISC_PDIS7_Pos (7UL) /*!< PORT1 PDISC: PDIS7 (Bit 7) */ 13938 #define PORT1_PDISC_PDIS7_Msk (0x80UL) /*!< PORT1 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 13939 #define PORT1_PDISC_PDIS8_Pos (8UL) /*!< PORT1 PDISC: PDIS8 (Bit 8) */ 13940 #define PORT1_PDISC_PDIS8_Msk (0x100UL) /*!< PORT1 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 13941 #define PORT1_PDISC_PDIS9_Pos (9UL) /*!< PORT1 PDISC: PDIS9 (Bit 9) */ 13942 #define PORT1_PDISC_PDIS9_Msk (0x200UL) /*!< PORT1 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 13943 #define PORT1_PDISC_PDIS10_Pos (10UL) /*!< PORT1 PDISC: PDIS10 (Bit 10) */ 13944 #define PORT1_PDISC_PDIS10_Msk (0x400UL) /*!< PORT1 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ 13945 #define PORT1_PDISC_PDIS11_Pos (11UL) /*!< PORT1 PDISC: PDIS11 (Bit 11) */ 13946 #define PORT1_PDISC_PDIS11_Msk (0x800UL) /*!< PORT1 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ 13947 #define PORT1_PDISC_PDIS12_Pos (12UL) /*!< PORT1 PDISC: PDIS12 (Bit 12) */ 13948 #define PORT1_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT1 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 13949 #define PORT1_PDISC_PDIS13_Pos (13UL) /*!< PORT1 PDISC: PDIS13 (Bit 13) */ 13950 #define PORT1_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT1 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 13951 #define PORT1_PDISC_PDIS14_Pos (14UL) /*!< PORT1 PDISC: PDIS14 (Bit 14) */ 13952 #define PORT1_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT1 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 13953 #define PORT1_PDISC_PDIS15_Pos (15UL) /*!< PORT1 PDISC: PDIS15 (Bit 15) */ 13954 #define PORT1_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT1 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 13955 13956 /* ---------------------------------- PORT1_PPS --------------------------------- */ 13957 #define PORT1_PPS_PPS0_Pos (0UL) /*!< PORT1 PPS: PPS0 (Bit 0) */ 13958 #define PORT1_PPS_PPS0_Msk (0x1UL) /*!< PORT1 PPS: PPS0 (Bitfield-Mask: 0x01) */ 13959 #define PORT1_PPS_PPS1_Pos (1UL) /*!< PORT1 PPS: PPS1 (Bit 1) */ 13960 #define PORT1_PPS_PPS1_Msk (0x2UL) /*!< PORT1 PPS: PPS1 (Bitfield-Mask: 0x01) */ 13961 #define PORT1_PPS_PPS2_Pos (2UL) /*!< PORT1 PPS: PPS2 (Bit 2) */ 13962 #define PORT1_PPS_PPS2_Msk (0x4UL) /*!< PORT1 PPS: PPS2 (Bitfield-Mask: 0x01) */ 13963 #define PORT1_PPS_PPS3_Pos (3UL) /*!< PORT1 PPS: PPS3 (Bit 3) */ 13964 #define PORT1_PPS_PPS3_Msk (0x8UL) /*!< PORT1 PPS: PPS3 (Bitfield-Mask: 0x01) */ 13965 #define PORT1_PPS_PPS4_Pos (4UL) /*!< PORT1 PPS: PPS4 (Bit 4) */ 13966 #define PORT1_PPS_PPS4_Msk (0x10UL) /*!< PORT1 PPS: PPS4 (Bitfield-Mask: 0x01) */ 13967 #define PORT1_PPS_PPS5_Pos (5UL) /*!< PORT1 PPS: PPS5 (Bit 5) */ 13968 #define PORT1_PPS_PPS5_Msk (0x20UL) /*!< PORT1 PPS: PPS5 (Bitfield-Mask: 0x01) */ 13969 #define PORT1_PPS_PPS6_Pos (6UL) /*!< PORT1 PPS: PPS6 (Bit 6) */ 13970 #define PORT1_PPS_PPS6_Msk (0x40UL) /*!< PORT1 PPS: PPS6 (Bitfield-Mask: 0x01) */ 13971 #define PORT1_PPS_PPS7_Pos (7UL) /*!< PORT1 PPS: PPS7 (Bit 7) */ 13972 #define PORT1_PPS_PPS7_Msk (0x80UL) /*!< PORT1 PPS: PPS7 (Bitfield-Mask: 0x01) */ 13973 #define PORT1_PPS_PPS8_Pos (8UL) /*!< PORT1 PPS: PPS8 (Bit 8) */ 13974 #define PORT1_PPS_PPS8_Msk (0x100UL) /*!< PORT1 PPS: PPS8 (Bitfield-Mask: 0x01) */ 13975 #define PORT1_PPS_PPS9_Pos (9UL) /*!< PORT1 PPS: PPS9 (Bit 9) */ 13976 #define PORT1_PPS_PPS9_Msk (0x200UL) /*!< PORT1 PPS: PPS9 (Bitfield-Mask: 0x01) */ 13977 #define PORT1_PPS_PPS10_Pos (10UL) /*!< PORT1 PPS: PPS10 (Bit 10) */ 13978 #define PORT1_PPS_PPS10_Msk (0x400UL) /*!< PORT1 PPS: PPS10 (Bitfield-Mask: 0x01) */ 13979 #define PORT1_PPS_PPS11_Pos (11UL) /*!< PORT1 PPS: PPS11 (Bit 11) */ 13980 #define PORT1_PPS_PPS11_Msk (0x800UL) /*!< PORT1 PPS: PPS11 (Bitfield-Mask: 0x01) */ 13981 #define PORT1_PPS_PPS12_Pos (12UL) /*!< PORT1 PPS: PPS12 (Bit 12) */ 13982 #define PORT1_PPS_PPS12_Msk (0x1000UL) /*!< PORT1 PPS: PPS12 (Bitfield-Mask: 0x01) */ 13983 #define PORT1_PPS_PPS13_Pos (13UL) /*!< PORT1 PPS: PPS13 (Bit 13) */ 13984 #define PORT1_PPS_PPS13_Msk (0x2000UL) /*!< PORT1 PPS: PPS13 (Bitfield-Mask: 0x01) */ 13985 #define PORT1_PPS_PPS14_Pos (14UL) /*!< PORT1 PPS: PPS14 (Bit 14) */ 13986 #define PORT1_PPS_PPS14_Msk (0x4000UL) /*!< PORT1 PPS: PPS14 (Bitfield-Mask: 0x01) */ 13987 #define PORT1_PPS_PPS15_Pos (15UL) /*!< PORT1 PPS: PPS15 (Bit 15) */ 13988 #define PORT1_PPS_PPS15_Msk (0x8000UL) /*!< PORT1 PPS: PPS15 (Bitfield-Mask: 0x01) */ 13989 13990 /* --------------------------------- PORT1_HWSEL -------------------------------- */ 13991 #define PORT1_HWSEL_HW0_Pos (0UL) /*!< PORT1 HWSEL: HW0 (Bit 0) */ 13992 #define PORT1_HWSEL_HW0_Msk (0x3UL) /*!< PORT1 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 13993 #define PORT1_HWSEL_HW1_Pos (2UL) /*!< PORT1 HWSEL: HW1 (Bit 2) */ 13994 #define PORT1_HWSEL_HW1_Msk (0xcUL) /*!< PORT1 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 13995 #define PORT1_HWSEL_HW2_Pos (4UL) /*!< PORT1 HWSEL: HW2 (Bit 4) */ 13996 #define PORT1_HWSEL_HW2_Msk (0x30UL) /*!< PORT1 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 13997 #define PORT1_HWSEL_HW3_Pos (6UL) /*!< PORT1 HWSEL: HW3 (Bit 6) */ 13998 #define PORT1_HWSEL_HW3_Msk (0xc0UL) /*!< PORT1 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 13999 #define PORT1_HWSEL_HW4_Pos (8UL) /*!< PORT1 HWSEL: HW4 (Bit 8) */ 14000 #define PORT1_HWSEL_HW4_Msk (0x300UL) /*!< PORT1 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 14001 #define PORT1_HWSEL_HW5_Pos (10UL) /*!< PORT1 HWSEL: HW5 (Bit 10) */ 14002 #define PORT1_HWSEL_HW5_Msk (0xc00UL) /*!< PORT1 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 14003 #define PORT1_HWSEL_HW6_Pos (12UL) /*!< PORT1 HWSEL: HW6 (Bit 12) */ 14004 #define PORT1_HWSEL_HW6_Msk (0x3000UL) /*!< PORT1 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 14005 #define PORT1_HWSEL_HW7_Pos (14UL) /*!< PORT1 HWSEL: HW7 (Bit 14) */ 14006 #define PORT1_HWSEL_HW7_Msk (0xc000UL) /*!< PORT1 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 14007 #define PORT1_HWSEL_HW8_Pos (16UL) /*!< PORT1 HWSEL: HW8 (Bit 16) */ 14008 #define PORT1_HWSEL_HW8_Msk (0x30000UL) /*!< PORT1 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 14009 #define PORT1_HWSEL_HW9_Pos (18UL) /*!< PORT1 HWSEL: HW9 (Bit 18) */ 14010 #define PORT1_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT1 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 14011 #define PORT1_HWSEL_HW10_Pos (20UL) /*!< PORT1 HWSEL: HW10 (Bit 20) */ 14012 #define PORT1_HWSEL_HW10_Msk (0x300000UL) /*!< PORT1 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 14013 #define PORT1_HWSEL_HW11_Pos (22UL) /*!< PORT1 HWSEL: HW11 (Bit 22) */ 14014 #define PORT1_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT1 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 14015 #define PORT1_HWSEL_HW12_Pos (24UL) /*!< PORT1 HWSEL: HW12 (Bit 24) */ 14016 #define PORT1_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT1 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 14017 #define PORT1_HWSEL_HW13_Pos (26UL) /*!< PORT1 HWSEL: HW13 (Bit 26) */ 14018 #define PORT1_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT1 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 14019 #define PORT1_HWSEL_HW14_Pos (28UL) /*!< PORT1 HWSEL: HW14 (Bit 28) */ 14020 #define PORT1_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT1 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 14021 #define PORT1_HWSEL_HW15_Pos (30UL) /*!< PORT1 HWSEL: HW15 (Bit 30) */ 14022 #define PORT1_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT1 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 14023 14024 14025 /* ================================================================================ */ 14026 /* ================ struct 'PORT2' Position & Mask ================ */ 14027 /* ================================================================================ */ 14028 14029 14030 /* ---------------------------------- PORT2_OUT --------------------------------- */ 14031 #define PORT2_OUT_P0_Pos (0UL) /*!< PORT2 OUT: P0 (Bit 0) */ 14032 #define PORT2_OUT_P0_Msk (0x1UL) /*!< PORT2 OUT: P0 (Bitfield-Mask: 0x01) */ 14033 #define PORT2_OUT_P1_Pos (1UL) /*!< PORT2 OUT: P1 (Bit 1) */ 14034 #define PORT2_OUT_P1_Msk (0x2UL) /*!< PORT2 OUT: P1 (Bitfield-Mask: 0x01) */ 14035 #define PORT2_OUT_P2_Pos (2UL) /*!< PORT2 OUT: P2 (Bit 2) */ 14036 #define PORT2_OUT_P2_Msk (0x4UL) /*!< PORT2 OUT: P2 (Bitfield-Mask: 0x01) */ 14037 #define PORT2_OUT_P3_Pos (3UL) /*!< PORT2 OUT: P3 (Bit 3) */ 14038 #define PORT2_OUT_P3_Msk (0x8UL) /*!< PORT2 OUT: P3 (Bitfield-Mask: 0x01) */ 14039 #define PORT2_OUT_P4_Pos (4UL) /*!< PORT2 OUT: P4 (Bit 4) */ 14040 #define PORT2_OUT_P4_Msk (0x10UL) /*!< PORT2 OUT: P4 (Bitfield-Mask: 0x01) */ 14041 #define PORT2_OUT_P5_Pos (5UL) /*!< PORT2 OUT: P5 (Bit 5) */ 14042 #define PORT2_OUT_P5_Msk (0x20UL) /*!< PORT2 OUT: P5 (Bitfield-Mask: 0x01) */ 14043 #define PORT2_OUT_P6_Pos (6UL) /*!< PORT2 OUT: P6 (Bit 6) */ 14044 #define PORT2_OUT_P6_Msk (0x40UL) /*!< PORT2 OUT: P6 (Bitfield-Mask: 0x01) */ 14045 #define PORT2_OUT_P7_Pos (7UL) /*!< PORT2 OUT: P7 (Bit 7) */ 14046 #define PORT2_OUT_P7_Msk (0x80UL) /*!< PORT2 OUT: P7 (Bitfield-Mask: 0x01) */ 14047 #define PORT2_OUT_P8_Pos (8UL) /*!< PORT2 OUT: P8 (Bit 8) */ 14048 #define PORT2_OUT_P8_Msk (0x100UL) /*!< PORT2 OUT: P8 (Bitfield-Mask: 0x01) */ 14049 #define PORT2_OUT_P9_Pos (9UL) /*!< PORT2 OUT: P9 (Bit 9) */ 14050 #define PORT2_OUT_P9_Msk (0x200UL) /*!< PORT2 OUT: P9 (Bitfield-Mask: 0x01) */ 14051 #define PORT2_OUT_P10_Pos (10UL) /*!< PORT2 OUT: P10 (Bit 10) */ 14052 #define PORT2_OUT_P10_Msk (0x400UL) /*!< PORT2 OUT: P10 (Bitfield-Mask: 0x01) */ 14053 #define PORT2_OUT_P11_Pos (11UL) /*!< PORT2 OUT: P11 (Bit 11) */ 14054 #define PORT2_OUT_P11_Msk (0x800UL) /*!< PORT2 OUT: P11 (Bitfield-Mask: 0x01) */ 14055 #define PORT2_OUT_P12_Pos (12UL) /*!< PORT2 OUT: P12 (Bit 12) */ 14056 #define PORT2_OUT_P12_Msk (0x1000UL) /*!< PORT2 OUT: P12 (Bitfield-Mask: 0x01) */ 14057 #define PORT2_OUT_P13_Pos (13UL) /*!< PORT2 OUT: P13 (Bit 13) */ 14058 #define PORT2_OUT_P13_Msk (0x2000UL) /*!< PORT2 OUT: P13 (Bitfield-Mask: 0x01) */ 14059 #define PORT2_OUT_P14_Pos (14UL) /*!< PORT2 OUT: P14 (Bit 14) */ 14060 #define PORT2_OUT_P14_Msk (0x4000UL) /*!< PORT2 OUT: P14 (Bitfield-Mask: 0x01) */ 14061 #define PORT2_OUT_P15_Pos (15UL) /*!< PORT2 OUT: P15 (Bit 15) */ 14062 #define PORT2_OUT_P15_Msk (0x8000UL) /*!< PORT2 OUT: P15 (Bitfield-Mask: 0x01) */ 14063 14064 /* ---------------------------------- PORT2_OMR --------------------------------- */ 14065 #define PORT2_OMR_PS0_Pos (0UL) /*!< PORT2 OMR: PS0 (Bit 0) */ 14066 #define PORT2_OMR_PS0_Msk (0x1UL) /*!< PORT2 OMR: PS0 (Bitfield-Mask: 0x01) */ 14067 #define PORT2_OMR_PS1_Pos (1UL) /*!< PORT2 OMR: PS1 (Bit 1) */ 14068 #define PORT2_OMR_PS1_Msk (0x2UL) /*!< PORT2 OMR: PS1 (Bitfield-Mask: 0x01) */ 14069 #define PORT2_OMR_PS2_Pos (2UL) /*!< PORT2 OMR: PS2 (Bit 2) */ 14070 #define PORT2_OMR_PS2_Msk (0x4UL) /*!< PORT2 OMR: PS2 (Bitfield-Mask: 0x01) */ 14071 #define PORT2_OMR_PS3_Pos (3UL) /*!< PORT2 OMR: PS3 (Bit 3) */ 14072 #define PORT2_OMR_PS3_Msk (0x8UL) /*!< PORT2 OMR: PS3 (Bitfield-Mask: 0x01) */ 14073 #define PORT2_OMR_PS4_Pos (4UL) /*!< PORT2 OMR: PS4 (Bit 4) */ 14074 #define PORT2_OMR_PS4_Msk (0x10UL) /*!< PORT2 OMR: PS4 (Bitfield-Mask: 0x01) */ 14075 #define PORT2_OMR_PS5_Pos (5UL) /*!< PORT2 OMR: PS5 (Bit 5) */ 14076 #define PORT2_OMR_PS5_Msk (0x20UL) /*!< PORT2 OMR: PS5 (Bitfield-Mask: 0x01) */ 14077 #define PORT2_OMR_PS6_Pos (6UL) /*!< PORT2 OMR: PS6 (Bit 6) */ 14078 #define PORT2_OMR_PS6_Msk (0x40UL) /*!< PORT2 OMR: PS6 (Bitfield-Mask: 0x01) */ 14079 #define PORT2_OMR_PS7_Pos (7UL) /*!< PORT2 OMR: PS7 (Bit 7) */ 14080 #define PORT2_OMR_PS7_Msk (0x80UL) /*!< PORT2 OMR: PS7 (Bitfield-Mask: 0x01) */ 14081 #define PORT2_OMR_PS8_Pos (8UL) /*!< PORT2 OMR: PS8 (Bit 8) */ 14082 #define PORT2_OMR_PS8_Msk (0x100UL) /*!< PORT2 OMR: PS8 (Bitfield-Mask: 0x01) */ 14083 #define PORT2_OMR_PS9_Pos (9UL) /*!< PORT2 OMR: PS9 (Bit 9) */ 14084 #define PORT2_OMR_PS9_Msk (0x200UL) /*!< PORT2 OMR: PS9 (Bitfield-Mask: 0x01) */ 14085 #define PORT2_OMR_PS10_Pos (10UL) /*!< PORT2 OMR: PS10 (Bit 10) */ 14086 #define PORT2_OMR_PS10_Msk (0x400UL) /*!< PORT2 OMR: PS10 (Bitfield-Mask: 0x01) */ 14087 #define PORT2_OMR_PS11_Pos (11UL) /*!< PORT2 OMR: PS11 (Bit 11) */ 14088 #define PORT2_OMR_PS11_Msk (0x800UL) /*!< PORT2 OMR: PS11 (Bitfield-Mask: 0x01) */ 14089 #define PORT2_OMR_PS12_Pos (12UL) /*!< PORT2 OMR: PS12 (Bit 12) */ 14090 #define PORT2_OMR_PS12_Msk (0x1000UL) /*!< PORT2 OMR: PS12 (Bitfield-Mask: 0x01) */ 14091 #define PORT2_OMR_PS13_Pos (13UL) /*!< PORT2 OMR: PS13 (Bit 13) */ 14092 #define PORT2_OMR_PS13_Msk (0x2000UL) /*!< PORT2 OMR: PS13 (Bitfield-Mask: 0x01) */ 14093 #define PORT2_OMR_PS14_Pos (14UL) /*!< PORT2 OMR: PS14 (Bit 14) */ 14094 #define PORT2_OMR_PS14_Msk (0x4000UL) /*!< PORT2 OMR: PS14 (Bitfield-Mask: 0x01) */ 14095 #define PORT2_OMR_PS15_Pos (15UL) /*!< PORT2 OMR: PS15 (Bit 15) */ 14096 #define PORT2_OMR_PS15_Msk (0x8000UL) /*!< PORT2 OMR: PS15 (Bitfield-Mask: 0x01) */ 14097 #define PORT2_OMR_PR0_Pos (16UL) /*!< PORT2 OMR: PR0 (Bit 16) */ 14098 #define PORT2_OMR_PR0_Msk (0x10000UL) /*!< PORT2 OMR: PR0 (Bitfield-Mask: 0x01) */ 14099 #define PORT2_OMR_PR1_Pos (17UL) /*!< PORT2 OMR: PR1 (Bit 17) */ 14100 #define PORT2_OMR_PR1_Msk (0x20000UL) /*!< PORT2 OMR: PR1 (Bitfield-Mask: 0x01) */ 14101 #define PORT2_OMR_PR2_Pos (18UL) /*!< PORT2 OMR: PR2 (Bit 18) */ 14102 #define PORT2_OMR_PR2_Msk (0x40000UL) /*!< PORT2 OMR: PR2 (Bitfield-Mask: 0x01) */ 14103 #define PORT2_OMR_PR3_Pos (19UL) /*!< PORT2 OMR: PR3 (Bit 19) */ 14104 #define PORT2_OMR_PR3_Msk (0x80000UL) /*!< PORT2 OMR: PR3 (Bitfield-Mask: 0x01) */ 14105 #define PORT2_OMR_PR4_Pos (20UL) /*!< PORT2 OMR: PR4 (Bit 20) */ 14106 #define PORT2_OMR_PR4_Msk (0x100000UL) /*!< PORT2 OMR: PR4 (Bitfield-Mask: 0x01) */ 14107 #define PORT2_OMR_PR5_Pos (21UL) /*!< PORT2 OMR: PR5 (Bit 21) */ 14108 #define PORT2_OMR_PR5_Msk (0x200000UL) /*!< PORT2 OMR: PR5 (Bitfield-Mask: 0x01) */ 14109 #define PORT2_OMR_PR6_Pos (22UL) /*!< PORT2 OMR: PR6 (Bit 22) */ 14110 #define PORT2_OMR_PR6_Msk (0x400000UL) /*!< PORT2 OMR: PR6 (Bitfield-Mask: 0x01) */ 14111 #define PORT2_OMR_PR7_Pos (23UL) /*!< PORT2 OMR: PR7 (Bit 23) */ 14112 #define PORT2_OMR_PR7_Msk (0x800000UL) /*!< PORT2 OMR: PR7 (Bitfield-Mask: 0x01) */ 14113 #define PORT2_OMR_PR8_Pos (24UL) /*!< PORT2 OMR: PR8 (Bit 24) */ 14114 #define PORT2_OMR_PR8_Msk (0x1000000UL) /*!< PORT2 OMR: PR8 (Bitfield-Mask: 0x01) */ 14115 #define PORT2_OMR_PR9_Pos (25UL) /*!< PORT2 OMR: PR9 (Bit 25) */ 14116 #define PORT2_OMR_PR9_Msk (0x2000000UL) /*!< PORT2 OMR: PR9 (Bitfield-Mask: 0x01) */ 14117 #define PORT2_OMR_PR10_Pos (26UL) /*!< PORT2 OMR: PR10 (Bit 26) */ 14118 #define PORT2_OMR_PR10_Msk (0x4000000UL) /*!< PORT2 OMR: PR10 (Bitfield-Mask: 0x01) */ 14119 #define PORT2_OMR_PR11_Pos (27UL) /*!< PORT2 OMR: PR11 (Bit 27) */ 14120 #define PORT2_OMR_PR11_Msk (0x8000000UL) /*!< PORT2 OMR: PR11 (Bitfield-Mask: 0x01) */ 14121 #define PORT2_OMR_PR12_Pos (28UL) /*!< PORT2 OMR: PR12 (Bit 28) */ 14122 #define PORT2_OMR_PR12_Msk (0x10000000UL) /*!< PORT2 OMR: PR12 (Bitfield-Mask: 0x01) */ 14123 #define PORT2_OMR_PR13_Pos (29UL) /*!< PORT2 OMR: PR13 (Bit 29) */ 14124 #define PORT2_OMR_PR13_Msk (0x20000000UL) /*!< PORT2 OMR: PR13 (Bitfield-Mask: 0x01) */ 14125 #define PORT2_OMR_PR14_Pos (30UL) /*!< PORT2 OMR: PR14 (Bit 30) */ 14126 #define PORT2_OMR_PR14_Msk (0x40000000UL) /*!< PORT2 OMR: PR14 (Bitfield-Mask: 0x01) */ 14127 #define PORT2_OMR_PR15_Pos (31UL) /*!< PORT2 OMR: PR15 (Bit 31) */ 14128 #define PORT2_OMR_PR15_Msk (0x80000000UL) /*!< PORT2 OMR: PR15 (Bitfield-Mask: 0x01) */ 14129 14130 /* --------------------------------- PORT2_IOCR0 -------------------------------- */ 14131 #define PORT2_IOCR0_PC0_Pos (3UL) /*!< PORT2 IOCR0: PC0 (Bit 3) */ 14132 #define PORT2_IOCR0_PC0_Msk (0xf8UL) /*!< PORT2 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 14133 #define PORT2_IOCR0_PC1_Pos (11UL) /*!< PORT2 IOCR0: PC1 (Bit 11) */ 14134 #define PORT2_IOCR0_PC1_Msk (0xf800UL) /*!< PORT2 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 14135 #define PORT2_IOCR0_PC2_Pos (19UL) /*!< PORT2 IOCR0: PC2 (Bit 19) */ 14136 #define PORT2_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT2 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 14137 #define PORT2_IOCR0_PC3_Pos (27UL) /*!< PORT2 IOCR0: PC3 (Bit 27) */ 14138 #define PORT2_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT2 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 14139 14140 /* --------------------------------- PORT2_IOCR4 -------------------------------- */ 14141 #define PORT2_IOCR4_PC4_Pos (3UL) /*!< PORT2 IOCR4: PC4 (Bit 3) */ 14142 #define PORT2_IOCR4_PC4_Msk (0xf8UL) /*!< PORT2 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 14143 #define PORT2_IOCR4_PC5_Pos (11UL) /*!< PORT2 IOCR4: PC5 (Bit 11) */ 14144 #define PORT2_IOCR4_PC5_Msk (0xf800UL) /*!< PORT2 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 14145 #define PORT2_IOCR4_PC6_Pos (19UL) /*!< PORT2 IOCR4: PC6 (Bit 19) */ 14146 #define PORT2_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT2 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 14147 #define PORT2_IOCR4_PC7_Pos (27UL) /*!< PORT2 IOCR4: PC7 (Bit 27) */ 14148 #define PORT2_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT2 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 14149 14150 /* --------------------------------- PORT2_IOCR8 -------------------------------- */ 14151 #define PORT2_IOCR8_PC8_Pos (3UL) /*!< PORT2 IOCR8: PC8 (Bit 3) */ 14152 #define PORT2_IOCR8_PC8_Msk (0xf8UL) /*!< PORT2 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ 14153 #define PORT2_IOCR8_PC9_Pos (11UL) /*!< PORT2 IOCR8: PC9 (Bit 11) */ 14154 #define PORT2_IOCR8_PC9_Msk (0xf800UL) /*!< PORT2 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ 14155 #define PORT2_IOCR8_PC10_Pos (19UL) /*!< PORT2 IOCR8: PC10 (Bit 19) */ 14156 #define PORT2_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT2 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ 14157 #define PORT2_IOCR8_PC11_Pos (27UL) /*!< PORT2 IOCR8: PC11 (Bit 27) */ 14158 #define PORT2_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT2 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ 14159 14160 /* -------------------------------- PORT2_IOCR12 -------------------------------- */ 14161 #define PORT2_IOCR12_PC12_Pos (3UL) /*!< PORT2 IOCR12: PC12 (Bit 3) */ 14162 #define PORT2_IOCR12_PC12_Msk (0xf8UL) /*!< PORT2 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ 14163 #define PORT2_IOCR12_PC13_Pos (11UL) /*!< PORT2 IOCR12: PC13 (Bit 11) */ 14164 #define PORT2_IOCR12_PC13_Msk (0xf800UL) /*!< PORT2 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ 14165 #define PORT2_IOCR12_PC14_Pos (19UL) /*!< PORT2 IOCR12: PC14 (Bit 19) */ 14166 #define PORT2_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT2 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ 14167 #define PORT2_IOCR12_PC15_Pos (27UL) /*!< PORT2 IOCR12: PC15 (Bit 27) */ 14168 #define PORT2_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT2 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ 14169 14170 /* ---------------------------------- PORT2_IN ---------------------------------- */ 14171 #define PORT2_IN_P0_Pos (0UL) /*!< PORT2 IN: P0 (Bit 0) */ 14172 #define PORT2_IN_P0_Msk (0x1UL) /*!< PORT2 IN: P0 (Bitfield-Mask: 0x01) */ 14173 #define PORT2_IN_P1_Pos (1UL) /*!< PORT2 IN: P1 (Bit 1) */ 14174 #define PORT2_IN_P1_Msk (0x2UL) /*!< PORT2 IN: P1 (Bitfield-Mask: 0x01) */ 14175 #define PORT2_IN_P2_Pos (2UL) /*!< PORT2 IN: P2 (Bit 2) */ 14176 #define PORT2_IN_P2_Msk (0x4UL) /*!< PORT2 IN: P2 (Bitfield-Mask: 0x01) */ 14177 #define PORT2_IN_P3_Pos (3UL) /*!< PORT2 IN: P3 (Bit 3) */ 14178 #define PORT2_IN_P3_Msk (0x8UL) /*!< PORT2 IN: P3 (Bitfield-Mask: 0x01) */ 14179 #define PORT2_IN_P4_Pos (4UL) /*!< PORT2 IN: P4 (Bit 4) */ 14180 #define PORT2_IN_P4_Msk (0x10UL) /*!< PORT2 IN: P4 (Bitfield-Mask: 0x01) */ 14181 #define PORT2_IN_P5_Pos (5UL) /*!< PORT2 IN: P5 (Bit 5) */ 14182 #define PORT2_IN_P5_Msk (0x20UL) /*!< PORT2 IN: P5 (Bitfield-Mask: 0x01) */ 14183 #define PORT2_IN_P6_Pos (6UL) /*!< PORT2 IN: P6 (Bit 6) */ 14184 #define PORT2_IN_P6_Msk (0x40UL) /*!< PORT2 IN: P6 (Bitfield-Mask: 0x01) */ 14185 #define PORT2_IN_P7_Pos (7UL) /*!< PORT2 IN: P7 (Bit 7) */ 14186 #define PORT2_IN_P7_Msk (0x80UL) /*!< PORT2 IN: P7 (Bitfield-Mask: 0x01) */ 14187 #define PORT2_IN_P8_Pos (8UL) /*!< PORT2 IN: P8 (Bit 8) */ 14188 #define PORT2_IN_P8_Msk (0x100UL) /*!< PORT2 IN: P8 (Bitfield-Mask: 0x01) */ 14189 #define PORT2_IN_P9_Pos (9UL) /*!< PORT2 IN: P9 (Bit 9) */ 14190 #define PORT2_IN_P9_Msk (0x200UL) /*!< PORT2 IN: P9 (Bitfield-Mask: 0x01) */ 14191 #define PORT2_IN_P10_Pos (10UL) /*!< PORT2 IN: P10 (Bit 10) */ 14192 #define PORT2_IN_P10_Msk (0x400UL) /*!< PORT2 IN: P10 (Bitfield-Mask: 0x01) */ 14193 #define PORT2_IN_P11_Pos (11UL) /*!< PORT2 IN: P11 (Bit 11) */ 14194 #define PORT2_IN_P11_Msk (0x800UL) /*!< PORT2 IN: P11 (Bitfield-Mask: 0x01) */ 14195 #define PORT2_IN_P12_Pos (12UL) /*!< PORT2 IN: P12 (Bit 12) */ 14196 #define PORT2_IN_P12_Msk (0x1000UL) /*!< PORT2 IN: P12 (Bitfield-Mask: 0x01) */ 14197 #define PORT2_IN_P13_Pos (13UL) /*!< PORT2 IN: P13 (Bit 13) */ 14198 #define PORT2_IN_P13_Msk (0x2000UL) /*!< PORT2 IN: P13 (Bitfield-Mask: 0x01) */ 14199 #define PORT2_IN_P14_Pos (14UL) /*!< PORT2 IN: P14 (Bit 14) */ 14200 #define PORT2_IN_P14_Msk (0x4000UL) /*!< PORT2 IN: P14 (Bitfield-Mask: 0x01) */ 14201 #define PORT2_IN_P15_Pos (15UL) /*!< PORT2 IN: P15 (Bit 15) */ 14202 #define PORT2_IN_P15_Msk (0x8000UL) /*!< PORT2 IN: P15 (Bitfield-Mask: 0x01) */ 14203 14204 /* --------------------------------- PORT2_PDR0 --------------------------------- */ 14205 #define PORT2_PDR0_PD0_Pos (0UL) /*!< PORT2 PDR0: PD0 (Bit 0) */ 14206 #define PORT2_PDR0_PD0_Msk (0x7UL) /*!< PORT2 PDR0: PD0 (Bitfield-Mask: 0x07) */ 14207 #define PORT2_PDR0_PD1_Pos (4UL) /*!< PORT2 PDR0: PD1 (Bit 4) */ 14208 #define PORT2_PDR0_PD1_Msk (0x70UL) /*!< PORT2 PDR0: PD1 (Bitfield-Mask: 0x07) */ 14209 #define PORT2_PDR0_PD2_Pos (8UL) /*!< PORT2 PDR0: PD2 (Bit 8) */ 14210 #define PORT2_PDR0_PD2_Msk (0x700UL) /*!< PORT2 PDR0: PD2 (Bitfield-Mask: 0x07) */ 14211 #define PORT2_PDR0_PD3_Pos (12UL) /*!< PORT2 PDR0: PD3 (Bit 12) */ 14212 #define PORT2_PDR0_PD3_Msk (0x7000UL) /*!< PORT2 PDR0: PD3 (Bitfield-Mask: 0x07) */ 14213 #define PORT2_PDR0_PD4_Pos (16UL) /*!< PORT2 PDR0: PD4 (Bit 16) */ 14214 #define PORT2_PDR0_PD4_Msk (0x70000UL) /*!< PORT2 PDR0: PD4 (Bitfield-Mask: 0x07) */ 14215 #define PORT2_PDR0_PD5_Pos (20UL) /*!< PORT2 PDR0: PD5 (Bit 20) */ 14216 #define PORT2_PDR0_PD5_Msk (0x700000UL) /*!< PORT2 PDR0: PD5 (Bitfield-Mask: 0x07) */ 14217 #define PORT2_PDR0_PD6_Pos (24UL) /*!< PORT2 PDR0: PD6 (Bit 24) */ 14218 #define PORT2_PDR0_PD6_Msk (0x7000000UL) /*!< PORT2 PDR0: PD6 (Bitfield-Mask: 0x07) */ 14219 #define PORT2_PDR0_PD7_Pos (28UL) /*!< PORT2 PDR0: PD7 (Bit 28) */ 14220 #define PORT2_PDR0_PD7_Msk (0x70000000UL) /*!< PORT2 PDR0: PD7 (Bitfield-Mask: 0x07) */ 14221 14222 /* --------------------------------- PORT2_PDR1 --------------------------------- */ 14223 #define PORT2_PDR1_PD8_Pos (0UL) /*!< PORT2 PDR1: PD8 (Bit 0) */ 14224 #define PORT2_PDR1_PD8_Msk (0x7UL) /*!< PORT2 PDR1: PD8 (Bitfield-Mask: 0x07) */ 14225 #define PORT2_PDR1_PD9_Pos (4UL) /*!< PORT2 PDR1: PD9 (Bit 4) */ 14226 #define PORT2_PDR1_PD9_Msk (0x70UL) /*!< PORT2 PDR1: PD9 (Bitfield-Mask: 0x07) */ 14227 #define PORT2_PDR1_PD10_Pos (8UL) /*!< PORT2 PDR1: PD10 (Bit 8) */ 14228 #define PORT2_PDR1_PD10_Msk (0x700UL) /*!< PORT2 PDR1: PD10 (Bitfield-Mask: 0x07) */ 14229 #define PORT2_PDR1_PD11_Pos (12UL) /*!< PORT2 PDR1: PD11 (Bit 12) */ 14230 #define PORT2_PDR1_PD11_Msk (0x7000UL) /*!< PORT2 PDR1: PD11 (Bitfield-Mask: 0x07) */ 14231 #define PORT2_PDR1_PD12_Pos (16UL) /*!< PORT2 PDR1: PD12 (Bit 16) */ 14232 #define PORT2_PDR1_PD12_Msk (0x70000UL) /*!< PORT2 PDR1: PD12 (Bitfield-Mask: 0x07) */ 14233 #define PORT2_PDR1_PD13_Pos (20UL) /*!< PORT2 PDR1: PD13 (Bit 20) */ 14234 #define PORT2_PDR1_PD13_Msk (0x700000UL) /*!< PORT2 PDR1: PD13 (Bitfield-Mask: 0x07) */ 14235 #define PORT2_PDR1_PD14_Pos (24UL) /*!< PORT2 PDR1: PD14 (Bit 24) */ 14236 #define PORT2_PDR1_PD14_Msk (0x7000000UL) /*!< PORT2 PDR1: PD14 (Bitfield-Mask: 0x07) */ 14237 #define PORT2_PDR1_PD15_Pos (28UL) /*!< PORT2 PDR1: PD15 (Bit 28) */ 14238 #define PORT2_PDR1_PD15_Msk (0x70000000UL) /*!< PORT2 PDR1: PD15 (Bitfield-Mask: 0x07) */ 14239 14240 /* --------------------------------- PORT2_PDISC -------------------------------- */ 14241 #define PORT2_PDISC_PDIS0_Pos (0UL) /*!< PORT2 PDISC: PDIS0 (Bit 0) */ 14242 #define PORT2_PDISC_PDIS0_Msk (0x1UL) /*!< PORT2 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ 14243 #define PORT2_PDISC_PDIS1_Pos (1UL) /*!< PORT2 PDISC: PDIS1 (Bit 1) */ 14244 #define PORT2_PDISC_PDIS1_Msk (0x2UL) /*!< PORT2 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ 14245 #define PORT2_PDISC_PDIS2_Pos (2UL) /*!< PORT2 PDISC: PDIS2 (Bit 2) */ 14246 #define PORT2_PDISC_PDIS2_Msk (0x4UL) /*!< PORT2 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 14247 #define PORT2_PDISC_PDIS3_Pos (3UL) /*!< PORT2 PDISC: PDIS3 (Bit 3) */ 14248 #define PORT2_PDISC_PDIS3_Msk (0x8UL) /*!< PORT2 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 14249 #define PORT2_PDISC_PDIS4_Pos (4UL) /*!< PORT2 PDISC: PDIS4 (Bit 4) */ 14250 #define PORT2_PDISC_PDIS4_Msk (0x10UL) /*!< PORT2 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 14251 #define PORT2_PDISC_PDIS5_Pos (5UL) /*!< PORT2 PDISC: PDIS5 (Bit 5) */ 14252 #define PORT2_PDISC_PDIS5_Msk (0x20UL) /*!< PORT2 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 14253 #define PORT2_PDISC_PDIS6_Pos (6UL) /*!< PORT2 PDISC: PDIS6 (Bit 6) */ 14254 #define PORT2_PDISC_PDIS6_Msk (0x40UL) /*!< PORT2 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 14255 #define PORT2_PDISC_PDIS7_Pos (7UL) /*!< PORT2 PDISC: PDIS7 (Bit 7) */ 14256 #define PORT2_PDISC_PDIS7_Msk (0x80UL) /*!< PORT2 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 14257 #define PORT2_PDISC_PDIS8_Pos (8UL) /*!< PORT2 PDISC: PDIS8 (Bit 8) */ 14258 #define PORT2_PDISC_PDIS8_Msk (0x100UL) /*!< PORT2 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 14259 #define PORT2_PDISC_PDIS9_Pos (9UL) /*!< PORT2 PDISC: PDIS9 (Bit 9) */ 14260 #define PORT2_PDISC_PDIS9_Msk (0x200UL) /*!< PORT2 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 14261 #define PORT2_PDISC_PDIS10_Pos (10UL) /*!< PORT2 PDISC: PDIS10 (Bit 10) */ 14262 #define PORT2_PDISC_PDIS10_Msk (0x400UL) /*!< PORT2 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ 14263 #define PORT2_PDISC_PDIS11_Pos (11UL) /*!< PORT2 PDISC: PDIS11 (Bit 11) */ 14264 #define PORT2_PDISC_PDIS11_Msk (0x800UL) /*!< PORT2 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ 14265 #define PORT2_PDISC_PDIS12_Pos (12UL) /*!< PORT2 PDISC: PDIS12 (Bit 12) */ 14266 #define PORT2_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT2 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 14267 #define PORT2_PDISC_PDIS13_Pos (13UL) /*!< PORT2 PDISC: PDIS13 (Bit 13) */ 14268 #define PORT2_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT2 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 14269 #define PORT2_PDISC_PDIS14_Pos (14UL) /*!< PORT2 PDISC: PDIS14 (Bit 14) */ 14270 #define PORT2_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT2 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 14271 #define PORT2_PDISC_PDIS15_Pos (15UL) /*!< PORT2 PDISC: PDIS15 (Bit 15) */ 14272 #define PORT2_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT2 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 14273 14274 /* ---------------------------------- PORT2_PPS --------------------------------- */ 14275 #define PORT2_PPS_PPS0_Pos (0UL) /*!< PORT2 PPS: PPS0 (Bit 0) */ 14276 #define PORT2_PPS_PPS0_Msk (0x1UL) /*!< PORT2 PPS: PPS0 (Bitfield-Mask: 0x01) */ 14277 #define PORT2_PPS_PPS1_Pos (1UL) /*!< PORT2 PPS: PPS1 (Bit 1) */ 14278 #define PORT2_PPS_PPS1_Msk (0x2UL) /*!< PORT2 PPS: PPS1 (Bitfield-Mask: 0x01) */ 14279 #define PORT2_PPS_PPS2_Pos (2UL) /*!< PORT2 PPS: PPS2 (Bit 2) */ 14280 #define PORT2_PPS_PPS2_Msk (0x4UL) /*!< PORT2 PPS: PPS2 (Bitfield-Mask: 0x01) */ 14281 #define PORT2_PPS_PPS3_Pos (3UL) /*!< PORT2 PPS: PPS3 (Bit 3) */ 14282 #define PORT2_PPS_PPS3_Msk (0x8UL) /*!< PORT2 PPS: PPS3 (Bitfield-Mask: 0x01) */ 14283 #define PORT2_PPS_PPS4_Pos (4UL) /*!< PORT2 PPS: PPS4 (Bit 4) */ 14284 #define PORT2_PPS_PPS4_Msk (0x10UL) /*!< PORT2 PPS: PPS4 (Bitfield-Mask: 0x01) */ 14285 #define PORT2_PPS_PPS5_Pos (5UL) /*!< PORT2 PPS: PPS5 (Bit 5) */ 14286 #define PORT2_PPS_PPS5_Msk (0x20UL) /*!< PORT2 PPS: PPS5 (Bitfield-Mask: 0x01) */ 14287 #define PORT2_PPS_PPS6_Pos (6UL) /*!< PORT2 PPS: PPS6 (Bit 6) */ 14288 #define PORT2_PPS_PPS6_Msk (0x40UL) /*!< PORT2 PPS: PPS6 (Bitfield-Mask: 0x01) */ 14289 #define PORT2_PPS_PPS7_Pos (7UL) /*!< PORT2 PPS: PPS7 (Bit 7) */ 14290 #define PORT2_PPS_PPS7_Msk (0x80UL) /*!< PORT2 PPS: PPS7 (Bitfield-Mask: 0x01) */ 14291 #define PORT2_PPS_PPS8_Pos (8UL) /*!< PORT2 PPS: PPS8 (Bit 8) */ 14292 #define PORT2_PPS_PPS8_Msk (0x100UL) /*!< PORT2 PPS: PPS8 (Bitfield-Mask: 0x01) */ 14293 #define PORT2_PPS_PPS9_Pos (9UL) /*!< PORT2 PPS: PPS9 (Bit 9) */ 14294 #define PORT2_PPS_PPS9_Msk (0x200UL) /*!< PORT2 PPS: PPS9 (Bitfield-Mask: 0x01) */ 14295 #define PORT2_PPS_PPS10_Pos (10UL) /*!< PORT2 PPS: PPS10 (Bit 10) */ 14296 #define PORT2_PPS_PPS10_Msk (0x400UL) /*!< PORT2 PPS: PPS10 (Bitfield-Mask: 0x01) */ 14297 #define PORT2_PPS_PPS11_Pos (11UL) /*!< PORT2 PPS: PPS11 (Bit 11) */ 14298 #define PORT2_PPS_PPS11_Msk (0x800UL) /*!< PORT2 PPS: PPS11 (Bitfield-Mask: 0x01) */ 14299 #define PORT2_PPS_PPS12_Pos (12UL) /*!< PORT2 PPS: PPS12 (Bit 12) */ 14300 #define PORT2_PPS_PPS12_Msk (0x1000UL) /*!< PORT2 PPS: PPS12 (Bitfield-Mask: 0x01) */ 14301 #define PORT2_PPS_PPS13_Pos (13UL) /*!< PORT2 PPS: PPS13 (Bit 13) */ 14302 #define PORT2_PPS_PPS13_Msk (0x2000UL) /*!< PORT2 PPS: PPS13 (Bitfield-Mask: 0x01) */ 14303 #define PORT2_PPS_PPS14_Pos (14UL) /*!< PORT2 PPS: PPS14 (Bit 14) */ 14304 #define PORT2_PPS_PPS14_Msk (0x4000UL) /*!< PORT2 PPS: PPS14 (Bitfield-Mask: 0x01) */ 14305 #define PORT2_PPS_PPS15_Pos (15UL) /*!< PORT2 PPS: PPS15 (Bit 15) */ 14306 #define PORT2_PPS_PPS15_Msk (0x8000UL) /*!< PORT2 PPS: PPS15 (Bitfield-Mask: 0x01) */ 14307 14308 /* --------------------------------- PORT2_HWSEL -------------------------------- */ 14309 #define PORT2_HWSEL_HW0_Pos (0UL) /*!< PORT2 HWSEL: HW0 (Bit 0) */ 14310 #define PORT2_HWSEL_HW0_Msk (0x3UL) /*!< PORT2 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 14311 #define PORT2_HWSEL_HW1_Pos (2UL) /*!< PORT2 HWSEL: HW1 (Bit 2) */ 14312 #define PORT2_HWSEL_HW1_Msk (0xcUL) /*!< PORT2 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 14313 #define PORT2_HWSEL_HW2_Pos (4UL) /*!< PORT2 HWSEL: HW2 (Bit 4) */ 14314 #define PORT2_HWSEL_HW2_Msk (0x30UL) /*!< PORT2 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 14315 #define PORT2_HWSEL_HW3_Pos (6UL) /*!< PORT2 HWSEL: HW3 (Bit 6) */ 14316 #define PORT2_HWSEL_HW3_Msk (0xc0UL) /*!< PORT2 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 14317 #define PORT2_HWSEL_HW4_Pos (8UL) /*!< PORT2 HWSEL: HW4 (Bit 8) */ 14318 #define PORT2_HWSEL_HW4_Msk (0x300UL) /*!< PORT2 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 14319 #define PORT2_HWSEL_HW5_Pos (10UL) /*!< PORT2 HWSEL: HW5 (Bit 10) */ 14320 #define PORT2_HWSEL_HW5_Msk (0xc00UL) /*!< PORT2 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 14321 #define PORT2_HWSEL_HW6_Pos (12UL) /*!< PORT2 HWSEL: HW6 (Bit 12) */ 14322 #define PORT2_HWSEL_HW6_Msk (0x3000UL) /*!< PORT2 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 14323 #define PORT2_HWSEL_HW7_Pos (14UL) /*!< PORT2 HWSEL: HW7 (Bit 14) */ 14324 #define PORT2_HWSEL_HW7_Msk (0xc000UL) /*!< PORT2 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 14325 #define PORT2_HWSEL_HW8_Pos (16UL) /*!< PORT2 HWSEL: HW8 (Bit 16) */ 14326 #define PORT2_HWSEL_HW8_Msk (0x30000UL) /*!< PORT2 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 14327 #define PORT2_HWSEL_HW9_Pos (18UL) /*!< PORT2 HWSEL: HW9 (Bit 18) */ 14328 #define PORT2_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT2 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 14329 #define PORT2_HWSEL_HW10_Pos (20UL) /*!< PORT2 HWSEL: HW10 (Bit 20) */ 14330 #define PORT2_HWSEL_HW10_Msk (0x300000UL) /*!< PORT2 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 14331 #define PORT2_HWSEL_HW11_Pos (22UL) /*!< PORT2 HWSEL: HW11 (Bit 22) */ 14332 #define PORT2_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT2 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 14333 #define PORT2_HWSEL_HW12_Pos (24UL) /*!< PORT2 HWSEL: HW12 (Bit 24) */ 14334 #define PORT2_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT2 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 14335 #define PORT2_HWSEL_HW13_Pos (26UL) /*!< PORT2 HWSEL: HW13 (Bit 26) */ 14336 #define PORT2_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT2 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 14337 #define PORT2_HWSEL_HW14_Pos (28UL) /*!< PORT2 HWSEL: HW14 (Bit 28) */ 14338 #define PORT2_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT2 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 14339 #define PORT2_HWSEL_HW15_Pos (30UL) /*!< PORT2 HWSEL: HW15 (Bit 30) */ 14340 #define PORT2_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT2 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 14341 14342 14343 /* ================================================================================ */ 14344 /* ================ struct 'PORT3' Position & Mask ================ */ 14345 /* ================================================================================ */ 14346 14347 14348 /* ---------------------------------- PORT3_OUT --------------------------------- */ 14349 #define PORT3_OUT_P0_Pos (0UL) /*!< PORT3 OUT: P0 (Bit 0) */ 14350 #define PORT3_OUT_P0_Msk (0x1UL) /*!< PORT3 OUT: P0 (Bitfield-Mask: 0x01) */ 14351 #define PORT3_OUT_P1_Pos (1UL) /*!< PORT3 OUT: P1 (Bit 1) */ 14352 #define PORT3_OUT_P1_Msk (0x2UL) /*!< PORT3 OUT: P1 (Bitfield-Mask: 0x01) */ 14353 #define PORT3_OUT_P2_Pos (2UL) /*!< PORT3 OUT: P2 (Bit 2) */ 14354 #define PORT3_OUT_P2_Msk (0x4UL) /*!< PORT3 OUT: P2 (Bitfield-Mask: 0x01) */ 14355 #define PORT3_OUT_P3_Pos (3UL) /*!< PORT3 OUT: P3 (Bit 3) */ 14356 #define PORT3_OUT_P3_Msk (0x8UL) /*!< PORT3 OUT: P3 (Bitfield-Mask: 0x01) */ 14357 #define PORT3_OUT_P4_Pos (4UL) /*!< PORT3 OUT: P4 (Bit 4) */ 14358 #define PORT3_OUT_P4_Msk (0x10UL) /*!< PORT3 OUT: P4 (Bitfield-Mask: 0x01) */ 14359 #define PORT3_OUT_P5_Pos (5UL) /*!< PORT3 OUT: P5 (Bit 5) */ 14360 #define PORT3_OUT_P5_Msk (0x20UL) /*!< PORT3 OUT: P5 (Bitfield-Mask: 0x01) */ 14361 #define PORT3_OUT_P6_Pos (6UL) /*!< PORT3 OUT: P6 (Bit 6) */ 14362 #define PORT3_OUT_P6_Msk (0x40UL) /*!< PORT3 OUT: P6 (Bitfield-Mask: 0x01) */ 14363 #define PORT3_OUT_P7_Pos (7UL) /*!< PORT3 OUT: P7 (Bit 7) */ 14364 #define PORT3_OUT_P7_Msk (0x80UL) /*!< PORT3 OUT: P7 (Bitfield-Mask: 0x01) */ 14365 #define PORT3_OUT_P8_Pos (8UL) /*!< PORT3 OUT: P8 (Bit 8) */ 14366 #define PORT3_OUT_P8_Msk (0x100UL) /*!< PORT3 OUT: P8 (Bitfield-Mask: 0x01) */ 14367 #define PORT3_OUT_P9_Pos (9UL) /*!< PORT3 OUT: P9 (Bit 9) */ 14368 #define PORT3_OUT_P9_Msk (0x200UL) /*!< PORT3 OUT: P9 (Bitfield-Mask: 0x01) */ 14369 #define PORT3_OUT_P10_Pos (10UL) /*!< PORT3 OUT: P10 (Bit 10) */ 14370 #define PORT3_OUT_P10_Msk (0x400UL) /*!< PORT3 OUT: P10 (Bitfield-Mask: 0x01) */ 14371 #define PORT3_OUT_P11_Pos (11UL) /*!< PORT3 OUT: P11 (Bit 11) */ 14372 #define PORT3_OUT_P11_Msk (0x800UL) /*!< PORT3 OUT: P11 (Bitfield-Mask: 0x01) */ 14373 #define PORT3_OUT_P12_Pos (12UL) /*!< PORT3 OUT: P12 (Bit 12) */ 14374 #define PORT3_OUT_P12_Msk (0x1000UL) /*!< PORT3 OUT: P12 (Bitfield-Mask: 0x01) */ 14375 #define PORT3_OUT_P13_Pos (13UL) /*!< PORT3 OUT: P13 (Bit 13) */ 14376 #define PORT3_OUT_P13_Msk (0x2000UL) /*!< PORT3 OUT: P13 (Bitfield-Mask: 0x01) */ 14377 #define PORT3_OUT_P14_Pos (14UL) /*!< PORT3 OUT: P14 (Bit 14) */ 14378 #define PORT3_OUT_P14_Msk (0x4000UL) /*!< PORT3 OUT: P14 (Bitfield-Mask: 0x01) */ 14379 #define PORT3_OUT_P15_Pos (15UL) /*!< PORT3 OUT: P15 (Bit 15) */ 14380 #define PORT3_OUT_P15_Msk (0x8000UL) /*!< PORT3 OUT: P15 (Bitfield-Mask: 0x01) */ 14381 14382 /* ---------------------------------- PORT3_OMR --------------------------------- */ 14383 #define PORT3_OMR_PS0_Pos (0UL) /*!< PORT3 OMR: PS0 (Bit 0) */ 14384 #define PORT3_OMR_PS0_Msk (0x1UL) /*!< PORT3 OMR: PS0 (Bitfield-Mask: 0x01) */ 14385 #define PORT3_OMR_PS1_Pos (1UL) /*!< PORT3 OMR: PS1 (Bit 1) */ 14386 #define PORT3_OMR_PS1_Msk (0x2UL) /*!< PORT3 OMR: PS1 (Bitfield-Mask: 0x01) */ 14387 #define PORT3_OMR_PS2_Pos (2UL) /*!< PORT3 OMR: PS2 (Bit 2) */ 14388 #define PORT3_OMR_PS2_Msk (0x4UL) /*!< PORT3 OMR: PS2 (Bitfield-Mask: 0x01) */ 14389 #define PORT3_OMR_PS3_Pos (3UL) /*!< PORT3 OMR: PS3 (Bit 3) */ 14390 #define PORT3_OMR_PS3_Msk (0x8UL) /*!< PORT3 OMR: PS3 (Bitfield-Mask: 0x01) */ 14391 #define PORT3_OMR_PS4_Pos (4UL) /*!< PORT3 OMR: PS4 (Bit 4) */ 14392 #define PORT3_OMR_PS4_Msk (0x10UL) /*!< PORT3 OMR: PS4 (Bitfield-Mask: 0x01) */ 14393 #define PORT3_OMR_PS5_Pos (5UL) /*!< PORT3 OMR: PS5 (Bit 5) */ 14394 #define PORT3_OMR_PS5_Msk (0x20UL) /*!< PORT3 OMR: PS5 (Bitfield-Mask: 0x01) */ 14395 #define PORT3_OMR_PS6_Pos (6UL) /*!< PORT3 OMR: PS6 (Bit 6) */ 14396 #define PORT3_OMR_PS6_Msk (0x40UL) /*!< PORT3 OMR: PS6 (Bitfield-Mask: 0x01) */ 14397 #define PORT3_OMR_PS7_Pos (7UL) /*!< PORT3 OMR: PS7 (Bit 7) */ 14398 #define PORT3_OMR_PS7_Msk (0x80UL) /*!< PORT3 OMR: PS7 (Bitfield-Mask: 0x01) */ 14399 #define PORT3_OMR_PS8_Pos (8UL) /*!< PORT3 OMR: PS8 (Bit 8) */ 14400 #define PORT3_OMR_PS8_Msk (0x100UL) /*!< PORT3 OMR: PS8 (Bitfield-Mask: 0x01) */ 14401 #define PORT3_OMR_PS9_Pos (9UL) /*!< PORT3 OMR: PS9 (Bit 9) */ 14402 #define PORT3_OMR_PS9_Msk (0x200UL) /*!< PORT3 OMR: PS9 (Bitfield-Mask: 0x01) */ 14403 #define PORT3_OMR_PS10_Pos (10UL) /*!< PORT3 OMR: PS10 (Bit 10) */ 14404 #define PORT3_OMR_PS10_Msk (0x400UL) /*!< PORT3 OMR: PS10 (Bitfield-Mask: 0x01) */ 14405 #define PORT3_OMR_PS11_Pos (11UL) /*!< PORT3 OMR: PS11 (Bit 11) */ 14406 #define PORT3_OMR_PS11_Msk (0x800UL) /*!< PORT3 OMR: PS11 (Bitfield-Mask: 0x01) */ 14407 #define PORT3_OMR_PS12_Pos (12UL) /*!< PORT3 OMR: PS12 (Bit 12) */ 14408 #define PORT3_OMR_PS12_Msk (0x1000UL) /*!< PORT3 OMR: PS12 (Bitfield-Mask: 0x01) */ 14409 #define PORT3_OMR_PS13_Pos (13UL) /*!< PORT3 OMR: PS13 (Bit 13) */ 14410 #define PORT3_OMR_PS13_Msk (0x2000UL) /*!< PORT3 OMR: PS13 (Bitfield-Mask: 0x01) */ 14411 #define PORT3_OMR_PS14_Pos (14UL) /*!< PORT3 OMR: PS14 (Bit 14) */ 14412 #define PORT3_OMR_PS14_Msk (0x4000UL) /*!< PORT3 OMR: PS14 (Bitfield-Mask: 0x01) */ 14413 #define PORT3_OMR_PS15_Pos (15UL) /*!< PORT3 OMR: PS15 (Bit 15) */ 14414 #define PORT3_OMR_PS15_Msk (0x8000UL) /*!< PORT3 OMR: PS15 (Bitfield-Mask: 0x01) */ 14415 #define PORT3_OMR_PR0_Pos (16UL) /*!< PORT3 OMR: PR0 (Bit 16) */ 14416 #define PORT3_OMR_PR0_Msk (0x10000UL) /*!< PORT3 OMR: PR0 (Bitfield-Mask: 0x01) */ 14417 #define PORT3_OMR_PR1_Pos (17UL) /*!< PORT3 OMR: PR1 (Bit 17) */ 14418 #define PORT3_OMR_PR1_Msk (0x20000UL) /*!< PORT3 OMR: PR1 (Bitfield-Mask: 0x01) */ 14419 #define PORT3_OMR_PR2_Pos (18UL) /*!< PORT3 OMR: PR2 (Bit 18) */ 14420 #define PORT3_OMR_PR2_Msk (0x40000UL) /*!< PORT3 OMR: PR2 (Bitfield-Mask: 0x01) */ 14421 #define PORT3_OMR_PR3_Pos (19UL) /*!< PORT3 OMR: PR3 (Bit 19) */ 14422 #define PORT3_OMR_PR3_Msk (0x80000UL) /*!< PORT3 OMR: PR3 (Bitfield-Mask: 0x01) */ 14423 #define PORT3_OMR_PR4_Pos (20UL) /*!< PORT3 OMR: PR4 (Bit 20) */ 14424 #define PORT3_OMR_PR4_Msk (0x100000UL) /*!< PORT3 OMR: PR4 (Bitfield-Mask: 0x01) */ 14425 #define PORT3_OMR_PR5_Pos (21UL) /*!< PORT3 OMR: PR5 (Bit 21) */ 14426 #define PORT3_OMR_PR5_Msk (0x200000UL) /*!< PORT3 OMR: PR5 (Bitfield-Mask: 0x01) */ 14427 #define PORT3_OMR_PR6_Pos (22UL) /*!< PORT3 OMR: PR6 (Bit 22) */ 14428 #define PORT3_OMR_PR6_Msk (0x400000UL) /*!< PORT3 OMR: PR6 (Bitfield-Mask: 0x01) */ 14429 #define PORT3_OMR_PR7_Pos (23UL) /*!< PORT3 OMR: PR7 (Bit 23) */ 14430 #define PORT3_OMR_PR7_Msk (0x800000UL) /*!< PORT3 OMR: PR7 (Bitfield-Mask: 0x01) */ 14431 #define PORT3_OMR_PR8_Pos (24UL) /*!< PORT3 OMR: PR8 (Bit 24) */ 14432 #define PORT3_OMR_PR8_Msk (0x1000000UL) /*!< PORT3 OMR: PR8 (Bitfield-Mask: 0x01) */ 14433 #define PORT3_OMR_PR9_Pos (25UL) /*!< PORT3 OMR: PR9 (Bit 25) */ 14434 #define PORT3_OMR_PR9_Msk (0x2000000UL) /*!< PORT3 OMR: PR9 (Bitfield-Mask: 0x01) */ 14435 #define PORT3_OMR_PR10_Pos (26UL) /*!< PORT3 OMR: PR10 (Bit 26) */ 14436 #define PORT3_OMR_PR10_Msk (0x4000000UL) /*!< PORT3 OMR: PR10 (Bitfield-Mask: 0x01) */ 14437 #define PORT3_OMR_PR11_Pos (27UL) /*!< PORT3 OMR: PR11 (Bit 27) */ 14438 #define PORT3_OMR_PR11_Msk (0x8000000UL) /*!< PORT3 OMR: PR11 (Bitfield-Mask: 0x01) */ 14439 #define PORT3_OMR_PR12_Pos (28UL) /*!< PORT3 OMR: PR12 (Bit 28) */ 14440 #define PORT3_OMR_PR12_Msk (0x10000000UL) /*!< PORT3 OMR: PR12 (Bitfield-Mask: 0x01) */ 14441 #define PORT3_OMR_PR13_Pos (29UL) /*!< PORT3 OMR: PR13 (Bit 29) */ 14442 #define PORT3_OMR_PR13_Msk (0x20000000UL) /*!< PORT3 OMR: PR13 (Bitfield-Mask: 0x01) */ 14443 #define PORT3_OMR_PR14_Pos (30UL) /*!< PORT3 OMR: PR14 (Bit 30) */ 14444 #define PORT3_OMR_PR14_Msk (0x40000000UL) /*!< PORT3 OMR: PR14 (Bitfield-Mask: 0x01) */ 14445 #define PORT3_OMR_PR15_Pos (31UL) /*!< PORT3 OMR: PR15 (Bit 31) */ 14446 #define PORT3_OMR_PR15_Msk (0x80000000UL) /*!< PORT3 OMR: PR15 (Bitfield-Mask: 0x01) */ 14447 14448 /* --------------------------------- PORT3_IOCR0 -------------------------------- */ 14449 #define PORT3_IOCR0_PC0_Pos (3UL) /*!< PORT3 IOCR0: PC0 (Bit 3) */ 14450 #define PORT3_IOCR0_PC0_Msk (0xf8UL) /*!< PORT3 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 14451 #define PORT3_IOCR0_PC1_Pos (11UL) /*!< PORT3 IOCR0: PC1 (Bit 11) */ 14452 #define PORT3_IOCR0_PC1_Msk (0xf800UL) /*!< PORT3 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 14453 #define PORT3_IOCR0_PC2_Pos (19UL) /*!< PORT3 IOCR0: PC2 (Bit 19) */ 14454 #define PORT3_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT3 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 14455 #define PORT3_IOCR0_PC3_Pos (27UL) /*!< PORT3 IOCR0: PC3 (Bit 27) */ 14456 #define PORT3_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT3 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 14457 14458 /* --------------------------------- PORT3_IOCR4 -------------------------------- */ 14459 #define PORT3_IOCR4_PC4_Pos (3UL) /*!< PORT3 IOCR4: PC4 (Bit 3) */ 14460 #define PORT3_IOCR4_PC4_Msk (0xf8UL) /*!< PORT3 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 14461 #define PORT3_IOCR4_PC5_Pos (11UL) /*!< PORT3 IOCR4: PC5 (Bit 11) */ 14462 #define PORT3_IOCR4_PC5_Msk (0xf800UL) /*!< PORT3 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 14463 #define PORT3_IOCR4_PC6_Pos (19UL) /*!< PORT3 IOCR4: PC6 (Bit 19) */ 14464 #define PORT3_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT3 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 14465 #define PORT3_IOCR4_PC7_Pos (27UL) /*!< PORT3 IOCR4: PC7 (Bit 27) */ 14466 #define PORT3_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT3 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 14467 14468 /* --------------------------------- PORT3_IOCR8 -------------------------------- */ 14469 #define PORT3_IOCR8_PC8_Pos (3UL) /*!< PORT3 IOCR8: PC8 (Bit 3) */ 14470 #define PORT3_IOCR8_PC8_Msk (0xf8UL) /*!< PORT3 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ 14471 #define PORT3_IOCR8_PC9_Pos (11UL) /*!< PORT3 IOCR8: PC9 (Bit 11) */ 14472 #define PORT3_IOCR8_PC9_Msk (0xf800UL) /*!< PORT3 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ 14473 #define PORT3_IOCR8_PC10_Pos (19UL) /*!< PORT3 IOCR8: PC10 (Bit 19) */ 14474 #define PORT3_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT3 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ 14475 #define PORT3_IOCR8_PC11_Pos (27UL) /*!< PORT3 IOCR8: PC11 (Bit 27) */ 14476 #define PORT3_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT3 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ 14477 14478 /* -------------------------------- PORT3_IOCR12 -------------------------------- */ 14479 #define PORT3_IOCR12_PC12_Pos (3UL) /*!< PORT3 IOCR12: PC12 (Bit 3) */ 14480 #define PORT3_IOCR12_PC12_Msk (0xf8UL) /*!< PORT3 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ 14481 #define PORT3_IOCR12_PC13_Pos (11UL) /*!< PORT3 IOCR12: PC13 (Bit 11) */ 14482 #define PORT3_IOCR12_PC13_Msk (0xf800UL) /*!< PORT3 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ 14483 #define PORT3_IOCR12_PC14_Pos (19UL) /*!< PORT3 IOCR12: PC14 (Bit 19) */ 14484 #define PORT3_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT3 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ 14485 #define PORT3_IOCR12_PC15_Pos (27UL) /*!< PORT3 IOCR12: PC15 (Bit 27) */ 14486 #define PORT3_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT3 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ 14487 14488 /* ---------------------------------- PORT3_IN ---------------------------------- */ 14489 #define PORT3_IN_P0_Pos (0UL) /*!< PORT3 IN: P0 (Bit 0) */ 14490 #define PORT3_IN_P0_Msk (0x1UL) /*!< PORT3 IN: P0 (Bitfield-Mask: 0x01) */ 14491 #define PORT3_IN_P1_Pos (1UL) /*!< PORT3 IN: P1 (Bit 1) */ 14492 #define PORT3_IN_P1_Msk (0x2UL) /*!< PORT3 IN: P1 (Bitfield-Mask: 0x01) */ 14493 #define PORT3_IN_P2_Pos (2UL) /*!< PORT3 IN: P2 (Bit 2) */ 14494 #define PORT3_IN_P2_Msk (0x4UL) /*!< PORT3 IN: P2 (Bitfield-Mask: 0x01) */ 14495 #define PORT3_IN_P3_Pos (3UL) /*!< PORT3 IN: P3 (Bit 3) */ 14496 #define PORT3_IN_P3_Msk (0x8UL) /*!< PORT3 IN: P3 (Bitfield-Mask: 0x01) */ 14497 #define PORT3_IN_P4_Pos (4UL) /*!< PORT3 IN: P4 (Bit 4) */ 14498 #define PORT3_IN_P4_Msk (0x10UL) /*!< PORT3 IN: P4 (Bitfield-Mask: 0x01) */ 14499 #define PORT3_IN_P5_Pos (5UL) /*!< PORT3 IN: P5 (Bit 5) */ 14500 #define PORT3_IN_P5_Msk (0x20UL) /*!< PORT3 IN: P5 (Bitfield-Mask: 0x01) */ 14501 #define PORT3_IN_P6_Pos (6UL) /*!< PORT3 IN: P6 (Bit 6) */ 14502 #define PORT3_IN_P6_Msk (0x40UL) /*!< PORT3 IN: P6 (Bitfield-Mask: 0x01) */ 14503 #define PORT3_IN_P7_Pos (7UL) /*!< PORT3 IN: P7 (Bit 7) */ 14504 #define PORT3_IN_P7_Msk (0x80UL) /*!< PORT3 IN: P7 (Bitfield-Mask: 0x01) */ 14505 #define PORT3_IN_P8_Pos (8UL) /*!< PORT3 IN: P8 (Bit 8) */ 14506 #define PORT3_IN_P8_Msk (0x100UL) /*!< PORT3 IN: P8 (Bitfield-Mask: 0x01) */ 14507 #define PORT3_IN_P9_Pos (9UL) /*!< PORT3 IN: P9 (Bit 9) */ 14508 #define PORT3_IN_P9_Msk (0x200UL) /*!< PORT3 IN: P9 (Bitfield-Mask: 0x01) */ 14509 #define PORT3_IN_P10_Pos (10UL) /*!< PORT3 IN: P10 (Bit 10) */ 14510 #define PORT3_IN_P10_Msk (0x400UL) /*!< PORT3 IN: P10 (Bitfield-Mask: 0x01) */ 14511 #define PORT3_IN_P11_Pos (11UL) /*!< PORT3 IN: P11 (Bit 11) */ 14512 #define PORT3_IN_P11_Msk (0x800UL) /*!< PORT3 IN: P11 (Bitfield-Mask: 0x01) */ 14513 #define PORT3_IN_P12_Pos (12UL) /*!< PORT3 IN: P12 (Bit 12) */ 14514 #define PORT3_IN_P12_Msk (0x1000UL) /*!< PORT3 IN: P12 (Bitfield-Mask: 0x01) */ 14515 #define PORT3_IN_P13_Pos (13UL) /*!< PORT3 IN: P13 (Bit 13) */ 14516 #define PORT3_IN_P13_Msk (0x2000UL) /*!< PORT3 IN: P13 (Bitfield-Mask: 0x01) */ 14517 #define PORT3_IN_P14_Pos (14UL) /*!< PORT3 IN: P14 (Bit 14) */ 14518 #define PORT3_IN_P14_Msk (0x4000UL) /*!< PORT3 IN: P14 (Bitfield-Mask: 0x01) */ 14519 #define PORT3_IN_P15_Pos (15UL) /*!< PORT3 IN: P15 (Bit 15) */ 14520 #define PORT3_IN_P15_Msk (0x8000UL) /*!< PORT3 IN: P15 (Bitfield-Mask: 0x01) */ 14521 14522 /* --------------------------------- PORT3_PDR0 --------------------------------- */ 14523 #define PORT3_PDR0_PD0_Pos (0UL) /*!< PORT3 PDR0: PD0 (Bit 0) */ 14524 #define PORT3_PDR0_PD0_Msk (0x7UL) /*!< PORT3 PDR0: PD0 (Bitfield-Mask: 0x07) */ 14525 #define PORT3_PDR0_PD1_Pos (4UL) /*!< PORT3 PDR0: PD1 (Bit 4) */ 14526 #define PORT3_PDR0_PD1_Msk (0x70UL) /*!< PORT3 PDR0: PD1 (Bitfield-Mask: 0x07) */ 14527 #define PORT3_PDR0_PD2_Pos (8UL) /*!< PORT3 PDR0: PD2 (Bit 8) */ 14528 #define PORT3_PDR0_PD2_Msk (0x700UL) /*!< PORT3 PDR0: PD2 (Bitfield-Mask: 0x07) */ 14529 #define PORT3_PDR0_PD3_Pos (12UL) /*!< PORT3 PDR0: PD3 (Bit 12) */ 14530 #define PORT3_PDR0_PD3_Msk (0x7000UL) /*!< PORT3 PDR0: PD3 (Bitfield-Mask: 0x07) */ 14531 #define PORT3_PDR0_PD4_Pos (16UL) /*!< PORT3 PDR0: PD4 (Bit 16) */ 14532 #define PORT3_PDR0_PD4_Msk (0x70000UL) /*!< PORT3 PDR0: PD4 (Bitfield-Mask: 0x07) */ 14533 #define PORT3_PDR0_PD5_Pos (20UL) /*!< PORT3 PDR0: PD5 (Bit 20) */ 14534 #define PORT3_PDR0_PD5_Msk (0x700000UL) /*!< PORT3 PDR0: PD5 (Bitfield-Mask: 0x07) */ 14535 #define PORT3_PDR0_PD6_Pos (24UL) /*!< PORT3 PDR0: PD6 (Bit 24) */ 14536 #define PORT3_PDR0_PD6_Msk (0x7000000UL) /*!< PORT3 PDR0: PD6 (Bitfield-Mask: 0x07) */ 14537 #define PORT3_PDR0_PD7_Pos (28UL) /*!< PORT3 PDR0: PD7 (Bit 28) */ 14538 #define PORT3_PDR0_PD7_Msk (0x70000000UL) /*!< PORT3 PDR0: PD7 (Bitfield-Mask: 0x07) */ 14539 14540 /* --------------------------------- PORT3_PDR1 --------------------------------- */ 14541 #define PORT3_PDR1_PD8_Pos (0UL) /*!< PORT3 PDR1: PD8 (Bit 0) */ 14542 #define PORT3_PDR1_PD8_Msk (0x7UL) /*!< PORT3 PDR1: PD8 (Bitfield-Mask: 0x07) */ 14543 #define PORT3_PDR1_PD9_Pos (4UL) /*!< PORT3 PDR1: PD9 (Bit 4) */ 14544 #define PORT3_PDR1_PD9_Msk (0x70UL) /*!< PORT3 PDR1: PD9 (Bitfield-Mask: 0x07) */ 14545 #define PORT3_PDR1_PD10_Pos (8UL) /*!< PORT3 PDR1: PD10 (Bit 8) */ 14546 #define PORT3_PDR1_PD10_Msk (0x700UL) /*!< PORT3 PDR1: PD10 (Bitfield-Mask: 0x07) */ 14547 #define PORT3_PDR1_PD11_Pos (12UL) /*!< PORT3 PDR1: PD11 (Bit 12) */ 14548 #define PORT3_PDR1_PD11_Msk (0x7000UL) /*!< PORT3 PDR1: PD11 (Bitfield-Mask: 0x07) */ 14549 #define PORT3_PDR1_PD12_Pos (16UL) /*!< PORT3 PDR1: PD12 (Bit 16) */ 14550 #define PORT3_PDR1_PD12_Msk (0x70000UL) /*!< PORT3 PDR1: PD12 (Bitfield-Mask: 0x07) */ 14551 #define PORT3_PDR1_PD13_Pos (20UL) /*!< PORT3 PDR1: PD13 (Bit 20) */ 14552 #define PORT3_PDR1_PD13_Msk (0x700000UL) /*!< PORT3 PDR1: PD13 (Bitfield-Mask: 0x07) */ 14553 #define PORT3_PDR1_PD14_Pos (24UL) /*!< PORT3 PDR1: PD14 (Bit 24) */ 14554 #define PORT3_PDR1_PD14_Msk (0x7000000UL) /*!< PORT3 PDR1: PD14 (Bitfield-Mask: 0x07) */ 14555 #define PORT3_PDR1_PD15_Pos (28UL) /*!< PORT3 PDR1: PD15 (Bit 28) */ 14556 #define PORT3_PDR1_PD15_Msk (0x70000000UL) /*!< PORT3 PDR1: PD15 (Bitfield-Mask: 0x07) */ 14557 14558 /* --------------------------------- PORT3_PDISC -------------------------------- */ 14559 #define PORT3_PDISC_PDIS0_Pos (0UL) /*!< PORT3 PDISC: PDIS0 (Bit 0) */ 14560 #define PORT3_PDISC_PDIS0_Msk (0x1UL) /*!< PORT3 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ 14561 #define PORT3_PDISC_PDIS1_Pos (1UL) /*!< PORT3 PDISC: PDIS1 (Bit 1) */ 14562 #define PORT3_PDISC_PDIS1_Msk (0x2UL) /*!< PORT3 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ 14563 #define PORT3_PDISC_PDIS2_Pos (2UL) /*!< PORT3 PDISC: PDIS2 (Bit 2) */ 14564 #define PORT3_PDISC_PDIS2_Msk (0x4UL) /*!< PORT3 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 14565 #define PORT3_PDISC_PDIS3_Pos (3UL) /*!< PORT3 PDISC: PDIS3 (Bit 3) */ 14566 #define PORT3_PDISC_PDIS3_Msk (0x8UL) /*!< PORT3 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 14567 #define PORT3_PDISC_PDIS4_Pos (4UL) /*!< PORT3 PDISC: PDIS4 (Bit 4) */ 14568 #define PORT3_PDISC_PDIS4_Msk (0x10UL) /*!< PORT3 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 14569 #define PORT3_PDISC_PDIS5_Pos (5UL) /*!< PORT3 PDISC: PDIS5 (Bit 5) */ 14570 #define PORT3_PDISC_PDIS5_Msk (0x20UL) /*!< PORT3 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 14571 #define PORT3_PDISC_PDIS6_Pos (6UL) /*!< PORT3 PDISC: PDIS6 (Bit 6) */ 14572 #define PORT3_PDISC_PDIS6_Msk (0x40UL) /*!< PORT3 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 14573 #define PORT3_PDISC_PDIS7_Pos (7UL) /*!< PORT3 PDISC: PDIS7 (Bit 7) */ 14574 #define PORT3_PDISC_PDIS7_Msk (0x80UL) /*!< PORT3 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 14575 #define PORT3_PDISC_PDIS8_Pos (8UL) /*!< PORT3 PDISC: PDIS8 (Bit 8) */ 14576 #define PORT3_PDISC_PDIS8_Msk (0x100UL) /*!< PORT3 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 14577 #define PORT3_PDISC_PDIS9_Pos (9UL) /*!< PORT3 PDISC: PDIS9 (Bit 9) */ 14578 #define PORT3_PDISC_PDIS9_Msk (0x200UL) /*!< PORT3 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 14579 #define PORT3_PDISC_PDIS10_Pos (10UL) /*!< PORT3 PDISC: PDIS10 (Bit 10) */ 14580 #define PORT3_PDISC_PDIS10_Msk (0x400UL) /*!< PORT3 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ 14581 #define PORT3_PDISC_PDIS11_Pos (11UL) /*!< PORT3 PDISC: PDIS11 (Bit 11) */ 14582 #define PORT3_PDISC_PDIS11_Msk (0x800UL) /*!< PORT3 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ 14583 #define PORT3_PDISC_PDIS12_Pos (12UL) /*!< PORT3 PDISC: PDIS12 (Bit 12) */ 14584 #define PORT3_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT3 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 14585 #define PORT3_PDISC_PDIS13_Pos (13UL) /*!< PORT3 PDISC: PDIS13 (Bit 13) */ 14586 #define PORT3_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT3 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 14587 #define PORT3_PDISC_PDIS14_Pos (14UL) /*!< PORT3 PDISC: PDIS14 (Bit 14) */ 14588 #define PORT3_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT3 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 14589 #define PORT3_PDISC_PDIS15_Pos (15UL) /*!< PORT3 PDISC: PDIS15 (Bit 15) */ 14590 #define PORT3_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT3 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 14591 14592 /* ---------------------------------- PORT3_PPS --------------------------------- */ 14593 #define PORT3_PPS_PPS0_Pos (0UL) /*!< PORT3 PPS: PPS0 (Bit 0) */ 14594 #define PORT3_PPS_PPS0_Msk (0x1UL) /*!< PORT3 PPS: PPS0 (Bitfield-Mask: 0x01) */ 14595 #define PORT3_PPS_PPS1_Pos (1UL) /*!< PORT3 PPS: PPS1 (Bit 1) */ 14596 #define PORT3_PPS_PPS1_Msk (0x2UL) /*!< PORT3 PPS: PPS1 (Bitfield-Mask: 0x01) */ 14597 #define PORT3_PPS_PPS2_Pos (2UL) /*!< PORT3 PPS: PPS2 (Bit 2) */ 14598 #define PORT3_PPS_PPS2_Msk (0x4UL) /*!< PORT3 PPS: PPS2 (Bitfield-Mask: 0x01) */ 14599 #define PORT3_PPS_PPS3_Pos (3UL) /*!< PORT3 PPS: PPS3 (Bit 3) */ 14600 #define PORT3_PPS_PPS3_Msk (0x8UL) /*!< PORT3 PPS: PPS3 (Bitfield-Mask: 0x01) */ 14601 #define PORT3_PPS_PPS4_Pos (4UL) /*!< PORT3 PPS: PPS4 (Bit 4) */ 14602 #define PORT3_PPS_PPS4_Msk (0x10UL) /*!< PORT3 PPS: PPS4 (Bitfield-Mask: 0x01) */ 14603 #define PORT3_PPS_PPS5_Pos (5UL) /*!< PORT3 PPS: PPS5 (Bit 5) */ 14604 #define PORT3_PPS_PPS5_Msk (0x20UL) /*!< PORT3 PPS: PPS5 (Bitfield-Mask: 0x01) */ 14605 #define PORT3_PPS_PPS6_Pos (6UL) /*!< PORT3 PPS: PPS6 (Bit 6) */ 14606 #define PORT3_PPS_PPS6_Msk (0x40UL) /*!< PORT3 PPS: PPS6 (Bitfield-Mask: 0x01) */ 14607 #define PORT3_PPS_PPS7_Pos (7UL) /*!< PORT3 PPS: PPS7 (Bit 7) */ 14608 #define PORT3_PPS_PPS7_Msk (0x80UL) /*!< PORT3 PPS: PPS7 (Bitfield-Mask: 0x01) */ 14609 #define PORT3_PPS_PPS8_Pos (8UL) /*!< PORT3 PPS: PPS8 (Bit 8) */ 14610 #define PORT3_PPS_PPS8_Msk (0x100UL) /*!< PORT3 PPS: PPS8 (Bitfield-Mask: 0x01) */ 14611 #define PORT3_PPS_PPS9_Pos (9UL) /*!< PORT3 PPS: PPS9 (Bit 9) */ 14612 #define PORT3_PPS_PPS9_Msk (0x200UL) /*!< PORT3 PPS: PPS9 (Bitfield-Mask: 0x01) */ 14613 #define PORT3_PPS_PPS10_Pos (10UL) /*!< PORT3 PPS: PPS10 (Bit 10) */ 14614 #define PORT3_PPS_PPS10_Msk (0x400UL) /*!< PORT3 PPS: PPS10 (Bitfield-Mask: 0x01) */ 14615 #define PORT3_PPS_PPS11_Pos (11UL) /*!< PORT3 PPS: PPS11 (Bit 11) */ 14616 #define PORT3_PPS_PPS11_Msk (0x800UL) /*!< PORT3 PPS: PPS11 (Bitfield-Mask: 0x01) */ 14617 #define PORT3_PPS_PPS12_Pos (12UL) /*!< PORT3 PPS: PPS12 (Bit 12) */ 14618 #define PORT3_PPS_PPS12_Msk (0x1000UL) /*!< PORT3 PPS: PPS12 (Bitfield-Mask: 0x01) */ 14619 #define PORT3_PPS_PPS13_Pos (13UL) /*!< PORT3 PPS: PPS13 (Bit 13) */ 14620 #define PORT3_PPS_PPS13_Msk (0x2000UL) /*!< PORT3 PPS: PPS13 (Bitfield-Mask: 0x01) */ 14621 #define PORT3_PPS_PPS14_Pos (14UL) /*!< PORT3 PPS: PPS14 (Bit 14) */ 14622 #define PORT3_PPS_PPS14_Msk (0x4000UL) /*!< PORT3 PPS: PPS14 (Bitfield-Mask: 0x01) */ 14623 #define PORT3_PPS_PPS15_Pos (15UL) /*!< PORT3 PPS: PPS15 (Bit 15) */ 14624 #define PORT3_PPS_PPS15_Msk (0x8000UL) /*!< PORT3 PPS: PPS15 (Bitfield-Mask: 0x01) */ 14625 14626 /* --------------------------------- PORT3_HWSEL -------------------------------- */ 14627 #define PORT3_HWSEL_HW0_Pos (0UL) /*!< PORT3 HWSEL: HW0 (Bit 0) */ 14628 #define PORT3_HWSEL_HW0_Msk (0x3UL) /*!< PORT3 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 14629 #define PORT3_HWSEL_HW1_Pos (2UL) /*!< PORT3 HWSEL: HW1 (Bit 2) */ 14630 #define PORT3_HWSEL_HW1_Msk (0xcUL) /*!< PORT3 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 14631 #define PORT3_HWSEL_HW2_Pos (4UL) /*!< PORT3 HWSEL: HW2 (Bit 4) */ 14632 #define PORT3_HWSEL_HW2_Msk (0x30UL) /*!< PORT3 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 14633 #define PORT3_HWSEL_HW3_Pos (6UL) /*!< PORT3 HWSEL: HW3 (Bit 6) */ 14634 #define PORT3_HWSEL_HW3_Msk (0xc0UL) /*!< PORT3 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 14635 #define PORT3_HWSEL_HW4_Pos (8UL) /*!< PORT3 HWSEL: HW4 (Bit 8) */ 14636 #define PORT3_HWSEL_HW4_Msk (0x300UL) /*!< PORT3 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 14637 #define PORT3_HWSEL_HW5_Pos (10UL) /*!< PORT3 HWSEL: HW5 (Bit 10) */ 14638 #define PORT3_HWSEL_HW5_Msk (0xc00UL) /*!< PORT3 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 14639 #define PORT3_HWSEL_HW6_Pos (12UL) /*!< PORT3 HWSEL: HW6 (Bit 12) */ 14640 #define PORT3_HWSEL_HW6_Msk (0x3000UL) /*!< PORT3 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 14641 #define PORT3_HWSEL_HW7_Pos (14UL) /*!< PORT3 HWSEL: HW7 (Bit 14) */ 14642 #define PORT3_HWSEL_HW7_Msk (0xc000UL) /*!< PORT3 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 14643 #define PORT3_HWSEL_HW8_Pos (16UL) /*!< PORT3 HWSEL: HW8 (Bit 16) */ 14644 #define PORT3_HWSEL_HW8_Msk (0x30000UL) /*!< PORT3 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 14645 #define PORT3_HWSEL_HW9_Pos (18UL) /*!< PORT3 HWSEL: HW9 (Bit 18) */ 14646 #define PORT3_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT3 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 14647 #define PORT3_HWSEL_HW10_Pos (20UL) /*!< PORT3 HWSEL: HW10 (Bit 20) */ 14648 #define PORT3_HWSEL_HW10_Msk (0x300000UL) /*!< PORT3 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 14649 #define PORT3_HWSEL_HW11_Pos (22UL) /*!< PORT3 HWSEL: HW11 (Bit 22) */ 14650 #define PORT3_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT3 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 14651 #define PORT3_HWSEL_HW12_Pos (24UL) /*!< PORT3 HWSEL: HW12 (Bit 24) */ 14652 #define PORT3_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT3 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 14653 #define PORT3_HWSEL_HW13_Pos (26UL) /*!< PORT3 HWSEL: HW13 (Bit 26) */ 14654 #define PORT3_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT3 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 14655 #define PORT3_HWSEL_HW14_Pos (28UL) /*!< PORT3 HWSEL: HW14 (Bit 28) */ 14656 #define PORT3_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT3 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 14657 #define PORT3_HWSEL_HW15_Pos (30UL) /*!< PORT3 HWSEL: HW15 (Bit 30) */ 14658 #define PORT3_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT3 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 14659 14660 14661 /* ================================================================================ */ 14662 /* ================ struct 'PORT4' Position & Mask ================ */ 14663 /* ================================================================================ */ 14664 14665 14666 /* ---------------------------------- PORT4_OUT --------------------------------- */ 14667 #define PORT4_OUT_P0_Pos (0UL) /*!< PORT4 OUT: P0 (Bit 0) */ 14668 #define PORT4_OUT_P0_Msk (0x1UL) /*!< PORT4 OUT: P0 (Bitfield-Mask: 0x01) */ 14669 #define PORT4_OUT_P1_Pos (1UL) /*!< PORT4 OUT: P1 (Bit 1) */ 14670 #define PORT4_OUT_P1_Msk (0x2UL) /*!< PORT4 OUT: P1 (Bitfield-Mask: 0x01) */ 14671 #define PORT4_OUT_P2_Pos (2UL) /*!< PORT4 OUT: P2 (Bit 2) */ 14672 #define PORT4_OUT_P2_Msk (0x4UL) /*!< PORT4 OUT: P2 (Bitfield-Mask: 0x01) */ 14673 #define PORT4_OUT_P3_Pos (3UL) /*!< PORT4 OUT: P3 (Bit 3) */ 14674 #define PORT4_OUT_P3_Msk (0x8UL) /*!< PORT4 OUT: P3 (Bitfield-Mask: 0x01) */ 14675 #define PORT4_OUT_P4_Pos (4UL) /*!< PORT4 OUT: P4 (Bit 4) */ 14676 #define PORT4_OUT_P4_Msk (0x10UL) /*!< PORT4 OUT: P4 (Bitfield-Mask: 0x01) */ 14677 #define PORT4_OUT_P5_Pos (5UL) /*!< PORT4 OUT: P5 (Bit 5) */ 14678 #define PORT4_OUT_P5_Msk (0x20UL) /*!< PORT4 OUT: P5 (Bitfield-Mask: 0x01) */ 14679 #define PORT4_OUT_P6_Pos (6UL) /*!< PORT4 OUT: P6 (Bit 6) */ 14680 #define PORT4_OUT_P6_Msk (0x40UL) /*!< PORT4 OUT: P6 (Bitfield-Mask: 0x01) */ 14681 #define PORT4_OUT_P7_Pos (7UL) /*!< PORT4 OUT: P7 (Bit 7) */ 14682 #define PORT4_OUT_P7_Msk (0x80UL) /*!< PORT4 OUT: P7 (Bitfield-Mask: 0x01) */ 14683 #define PORT4_OUT_P8_Pos (8UL) /*!< PORT4 OUT: P8 (Bit 8) */ 14684 #define PORT4_OUT_P8_Msk (0x100UL) /*!< PORT4 OUT: P8 (Bitfield-Mask: 0x01) */ 14685 #define PORT4_OUT_P9_Pos (9UL) /*!< PORT4 OUT: P9 (Bit 9) */ 14686 #define PORT4_OUT_P9_Msk (0x200UL) /*!< PORT4 OUT: P9 (Bitfield-Mask: 0x01) */ 14687 #define PORT4_OUT_P10_Pos (10UL) /*!< PORT4 OUT: P10 (Bit 10) */ 14688 #define PORT4_OUT_P10_Msk (0x400UL) /*!< PORT4 OUT: P10 (Bitfield-Mask: 0x01) */ 14689 #define PORT4_OUT_P11_Pos (11UL) /*!< PORT4 OUT: P11 (Bit 11) */ 14690 #define PORT4_OUT_P11_Msk (0x800UL) /*!< PORT4 OUT: P11 (Bitfield-Mask: 0x01) */ 14691 #define PORT4_OUT_P12_Pos (12UL) /*!< PORT4 OUT: P12 (Bit 12) */ 14692 #define PORT4_OUT_P12_Msk (0x1000UL) /*!< PORT4 OUT: P12 (Bitfield-Mask: 0x01) */ 14693 #define PORT4_OUT_P13_Pos (13UL) /*!< PORT4 OUT: P13 (Bit 13) */ 14694 #define PORT4_OUT_P13_Msk (0x2000UL) /*!< PORT4 OUT: P13 (Bitfield-Mask: 0x01) */ 14695 #define PORT4_OUT_P14_Pos (14UL) /*!< PORT4 OUT: P14 (Bit 14) */ 14696 #define PORT4_OUT_P14_Msk (0x4000UL) /*!< PORT4 OUT: P14 (Bitfield-Mask: 0x01) */ 14697 #define PORT4_OUT_P15_Pos (15UL) /*!< PORT4 OUT: P15 (Bit 15) */ 14698 #define PORT4_OUT_P15_Msk (0x8000UL) /*!< PORT4 OUT: P15 (Bitfield-Mask: 0x01) */ 14699 14700 /* ---------------------------------- PORT4_OMR --------------------------------- */ 14701 #define PORT4_OMR_PS0_Pos (0UL) /*!< PORT4 OMR: PS0 (Bit 0) */ 14702 #define PORT4_OMR_PS0_Msk (0x1UL) /*!< PORT4 OMR: PS0 (Bitfield-Mask: 0x01) */ 14703 #define PORT4_OMR_PS1_Pos (1UL) /*!< PORT4 OMR: PS1 (Bit 1) */ 14704 #define PORT4_OMR_PS1_Msk (0x2UL) /*!< PORT4 OMR: PS1 (Bitfield-Mask: 0x01) */ 14705 #define PORT4_OMR_PS2_Pos (2UL) /*!< PORT4 OMR: PS2 (Bit 2) */ 14706 #define PORT4_OMR_PS2_Msk (0x4UL) /*!< PORT4 OMR: PS2 (Bitfield-Mask: 0x01) */ 14707 #define PORT4_OMR_PS3_Pos (3UL) /*!< PORT4 OMR: PS3 (Bit 3) */ 14708 #define PORT4_OMR_PS3_Msk (0x8UL) /*!< PORT4 OMR: PS3 (Bitfield-Mask: 0x01) */ 14709 #define PORT4_OMR_PS4_Pos (4UL) /*!< PORT4 OMR: PS4 (Bit 4) */ 14710 #define PORT4_OMR_PS4_Msk (0x10UL) /*!< PORT4 OMR: PS4 (Bitfield-Mask: 0x01) */ 14711 #define PORT4_OMR_PS5_Pos (5UL) /*!< PORT4 OMR: PS5 (Bit 5) */ 14712 #define PORT4_OMR_PS5_Msk (0x20UL) /*!< PORT4 OMR: PS5 (Bitfield-Mask: 0x01) */ 14713 #define PORT4_OMR_PS6_Pos (6UL) /*!< PORT4 OMR: PS6 (Bit 6) */ 14714 #define PORT4_OMR_PS6_Msk (0x40UL) /*!< PORT4 OMR: PS6 (Bitfield-Mask: 0x01) */ 14715 #define PORT4_OMR_PS7_Pos (7UL) /*!< PORT4 OMR: PS7 (Bit 7) */ 14716 #define PORT4_OMR_PS7_Msk (0x80UL) /*!< PORT4 OMR: PS7 (Bitfield-Mask: 0x01) */ 14717 #define PORT4_OMR_PS8_Pos (8UL) /*!< PORT4 OMR: PS8 (Bit 8) */ 14718 #define PORT4_OMR_PS8_Msk (0x100UL) /*!< PORT4 OMR: PS8 (Bitfield-Mask: 0x01) */ 14719 #define PORT4_OMR_PS9_Pos (9UL) /*!< PORT4 OMR: PS9 (Bit 9) */ 14720 #define PORT4_OMR_PS9_Msk (0x200UL) /*!< PORT4 OMR: PS9 (Bitfield-Mask: 0x01) */ 14721 #define PORT4_OMR_PS10_Pos (10UL) /*!< PORT4 OMR: PS10 (Bit 10) */ 14722 #define PORT4_OMR_PS10_Msk (0x400UL) /*!< PORT4 OMR: PS10 (Bitfield-Mask: 0x01) */ 14723 #define PORT4_OMR_PS11_Pos (11UL) /*!< PORT4 OMR: PS11 (Bit 11) */ 14724 #define PORT4_OMR_PS11_Msk (0x800UL) /*!< PORT4 OMR: PS11 (Bitfield-Mask: 0x01) */ 14725 #define PORT4_OMR_PS12_Pos (12UL) /*!< PORT4 OMR: PS12 (Bit 12) */ 14726 #define PORT4_OMR_PS12_Msk (0x1000UL) /*!< PORT4 OMR: PS12 (Bitfield-Mask: 0x01) */ 14727 #define PORT4_OMR_PS13_Pos (13UL) /*!< PORT4 OMR: PS13 (Bit 13) */ 14728 #define PORT4_OMR_PS13_Msk (0x2000UL) /*!< PORT4 OMR: PS13 (Bitfield-Mask: 0x01) */ 14729 #define PORT4_OMR_PS14_Pos (14UL) /*!< PORT4 OMR: PS14 (Bit 14) */ 14730 #define PORT4_OMR_PS14_Msk (0x4000UL) /*!< PORT4 OMR: PS14 (Bitfield-Mask: 0x01) */ 14731 #define PORT4_OMR_PS15_Pos (15UL) /*!< PORT4 OMR: PS15 (Bit 15) */ 14732 #define PORT4_OMR_PS15_Msk (0x8000UL) /*!< PORT4 OMR: PS15 (Bitfield-Mask: 0x01) */ 14733 #define PORT4_OMR_PR0_Pos (16UL) /*!< PORT4 OMR: PR0 (Bit 16) */ 14734 #define PORT4_OMR_PR0_Msk (0x10000UL) /*!< PORT4 OMR: PR0 (Bitfield-Mask: 0x01) */ 14735 #define PORT4_OMR_PR1_Pos (17UL) /*!< PORT4 OMR: PR1 (Bit 17) */ 14736 #define PORT4_OMR_PR1_Msk (0x20000UL) /*!< PORT4 OMR: PR1 (Bitfield-Mask: 0x01) */ 14737 #define PORT4_OMR_PR2_Pos (18UL) /*!< PORT4 OMR: PR2 (Bit 18) */ 14738 #define PORT4_OMR_PR2_Msk (0x40000UL) /*!< PORT4 OMR: PR2 (Bitfield-Mask: 0x01) */ 14739 #define PORT4_OMR_PR3_Pos (19UL) /*!< PORT4 OMR: PR3 (Bit 19) */ 14740 #define PORT4_OMR_PR3_Msk (0x80000UL) /*!< PORT4 OMR: PR3 (Bitfield-Mask: 0x01) */ 14741 #define PORT4_OMR_PR4_Pos (20UL) /*!< PORT4 OMR: PR4 (Bit 20) */ 14742 #define PORT4_OMR_PR4_Msk (0x100000UL) /*!< PORT4 OMR: PR4 (Bitfield-Mask: 0x01) */ 14743 #define PORT4_OMR_PR5_Pos (21UL) /*!< PORT4 OMR: PR5 (Bit 21) */ 14744 #define PORT4_OMR_PR5_Msk (0x200000UL) /*!< PORT4 OMR: PR5 (Bitfield-Mask: 0x01) */ 14745 #define PORT4_OMR_PR6_Pos (22UL) /*!< PORT4 OMR: PR6 (Bit 22) */ 14746 #define PORT4_OMR_PR6_Msk (0x400000UL) /*!< PORT4 OMR: PR6 (Bitfield-Mask: 0x01) */ 14747 #define PORT4_OMR_PR7_Pos (23UL) /*!< PORT4 OMR: PR7 (Bit 23) */ 14748 #define PORT4_OMR_PR7_Msk (0x800000UL) /*!< PORT4 OMR: PR7 (Bitfield-Mask: 0x01) */ 14749 #define PORT4_OMR_PR8_Pos (24UL) /*!< PORT4 OMR: PR8 (Bit 24) */ 14750 #define PORT4_OMR_PR8_Msk (0x1000000UL) /*!< PORT4 OMR: PR8 (Bitfield-Mask: 0x01) */ 14751 #define PORT4_OMR_PR9_Pos (25UL) /*!< PORT4 OMR: PR9 (Bit 25) */ 14752 #define PORT4_OMR_PR9_Msk (0x2000000UL) /*!< PORT4 OMR: PR9 (Bitfield-Mask: 0x01) */ 14753 #define PORT4_OMR_PR10_Pos (26UL) /*!< PORT4 OMR: PR10 (Bit 26) */ 14754 #define PORT4_OMR_PR10_Msk (0x4000000UL) /*!< PORT4 OMR: PR10 (Bitfield-Mask: 0x01) */ 14755 #define PORT4_OMR_PR11_Pos (27UL) /*!< PORT4 OMR: PR11 (Bit 27) */ 14756 #define PORT4_OMR_PR11_Msk (0x8000000UL) /*!< PORT4 OMR: PR11 (Bitfield-Mask: 0x01) */ 14757 #define PORT4_OMR_PR12_Pos (28UL) /*!< PORT4 OMR: PR12 (Bit 28) */ 14758 #define PORT4_OMR_PR12_Msk (0x10000000UL) /*!< PORT4 OMR: PR12 (Bitfield-Mask: 0x01) */ 14759 #define PORT4_OMR_PR13_Pos (29UL) /*!< PORT4 OMR: PR13 (Bit 29) */ 14760 #define PORT4_OMR_PR13_Msk (0x20000000UL) /*!< PORT4 OMR: PR13 (Bitfield-Mask: 0x01) */ 14761 #define PORT4_OMR_PR14_Pos (30UL) /*!< PORT4 OMR: PR14 (Bit 30) */ 14762 #define PORT4_OMR_PR14_Msk (0x40000000UL) /*!< PORT4 OMR: PR14 (Bitfield-Mask: 0x01) */ 14763 #define PORT4_OMR_PR15_Pos (31UL) /*!< PORT4 OMR: PR15 (Bit 31) */ 14764 #define PORT4_OMR_PR15_Msk (0x80000000UL) /*!< PORT4 OMR: PR15 (Bitfield-Mask: 0x01) */ 14765 14766 /* --------------------------------- PORT4_IOCR0 -------------------------------- */ 14767 #define PORT4_IOCR0_PC0_Pos (3UL) /*!< PORT4 IOCR0: PC0 (Bit 3) */ 14768 #define PORT4_IOCR0_PC0_Msk (0xf8UL) /*!< PORT4 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 14769 #define PORT4_IOCR0_PC1_Pos (11UL) /*!< PORT4 IOCR0: PC1 (Bit 11) */ 14770 #define PORT4_IOCR0_PC1_Msk (0xf800UL) /*!< PORT4 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 14771 #define PORT4_IOCR0_PC2_Pos (19UL) /*!< PORT4 IOCR0: PC2 (Bit 19) */ 14772 #define PORT4_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT4 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 14773 #define PORT4_IOCR0_PC3_Pos (27UL) /*!< PORT4 IOCR0: PC3 (Bit 27) */ 14774 #define PORT4_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT4 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 14775 14776 /* --------------------------------- PORT4_IOCR4 -------------------------------- */ 14777 #define PORT4_IOCR4_PC4_Pos (3UL) /*!< PORT4 IOCR4: PC4 (Bit 3) */ 14778 #define PORT4_IOCR4_PC4_Msk (0xf8UL) /*!< PORT4 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 14779 #define PORT4_IOCR4_PC5_Pos (11UL) /*!< PORT4 IOCR4: PC5 (Bit 11) */ 14780 #define PORT4_IOCR4_PC5_Msk (0xf800UL) /*!< PORT4 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 14781 #define PORT4_IOCR4_PC6_Pos (19UL) /*!< PORT4 IOCR4: PC6 (Bit 19) */ 14782 #define PORT4_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT4 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 14783 #define PORT4_IOCR4_PC7_Pos (27UL) /*!< PORT4 IOCR4: PC7 (Bit 27) */ 14784 #define PORT4_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT4 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 14785 14786 /* ---------------------------------- PORT4_IN ---------------------------------- */ 14787 #define PORT4_IN_P0_Pos (0UL) /*!< PORT4 IN: P0 (Bit 0) */ 14788 #define PORT4_IN_P0_Msk (0x1UL) /*!< PORT4 IN: P0 (Bitfield-Mask: 0x01) */ 14789 #define PORT4_IN_P1_Pos (1UL) /*!< PORT4 IN: P1 (Bit 1) */ 14790 #define PORT4_IN_P1_Msk (0x2UL) /*!< PORT4 IN: P1 (Bitfield-Mask: 0x01) */ 14791 #define PORT4_IN_P2_Pos (2UL) /*!< PORT4 IN: P2 (Bit 2) */ 14792 #define PORT4_IN_P2_Msk (0x4UL) /*!< PORT4 IN: P2 (Bitfield-Mask: 0x01) */ 14793 #define PORT4_IN_P3_Pos (3UL) /*!< PORT4 IN: P3 (Bit 3) */ 14794 #define PORT4_IN_P3_Msk (0x8UL) /*!< PORT4 IN: P3 (Bitfield-Mask: 0x01) */ 14795 #define PORT4_IN_P4_Pos (4UL) /*!< PORT4 IN: P4 (Bit 4) */ 14796 #define PORT4_IN_P4_Msk (0x10UL) /*!< PORT4 IN: P4 (Bitfield-Mask: 0x01) */ 14797 #define PORT4_IN_P5_Pos (5UL) /*!< PORT4 IN: P5 (Bit 5) */ 14798 #define PORT4_IN_P5_Msk (0x20UL) /*!< PORT4 IN: P5 (Bitfield-Mask: 0x01) */ 14799 #define PORT4_IN_P6_Pos (6UL) /*!< PORT4 IN: P6 (Bit 6) */ 14800 #define PORT4_IN_P6_Msk (0x40UL) /*!< PORT4 IN: P6 (Bitfield-Mask: 0x01) */ 14801 #define PORT4_IN_P7_Pos (7UL) /*!< PORT4 IN: P7 (Bit 7) */ 14802 #define PORT4_IN_P7_Msk (0x80UL) /*!< PORT4 IN: P7 (Bitfield-Mask: 0x01) */ 14803 #define PORT4_IN_P8_Pos (8UL) /*!< PORT4 IN: P8 (Bit 8) */ 14804 #define PORT4_IN_P8_Msk (0x100UL) /*!< PORT4 IN: P8 (Bitfield-Mask: 0x01) */ 14805 #define PORT4_IN_P9_Pos (9UL) /*!< PORT4 IN: P9 (Bit 9) */ 14806 #define PORT4_IN_P9_Msk (0x200UL) /*!< PORT4 IN: P9 (Bitfield-Mask: 0x01) */ 14807 #define PORT4_IN_P10_Pos (10UL) /*!< PORT4 IN: P10 (Bit 10) */ 14808 #define PORT4_IN_P10_Msk (0x400UL) /*!< PORT4 IN: P10 (Bitfield-Mask: 0x01) */ 14809 #define PORT4_IN_P11_Pos (11UL) /*!< PORT4 IN: P11 (Bit 11) */ 14810 #define PORT4_IN_P11_Msk (0x800UL) /*!< PORT4 IN: P11 (Bitfield-Mask: 0x01) */ 14811 #define PORT4_IN_P12_Pos (12UL) /*!< PORT4 IN: P12 (Bit 12) */ 14812 #define PORT4_IN_P12_Msk (0x1000UL) /*!< PORT4 IN: P12 (Bitfield-Mask: 0x01) */ 14813 #define PORT4_IN_P13_Pos (13UL) /*!< PORT4 IN: P13 (Bit 13) */ 14814 #define PORT4_IN_P13_Msk (0x2000UL) /*!< PORT4 IN: P13 (Bitfield-Mask: 0x01) */ 14815 #define PORT4_IN_P14_Pos (14UL) /*!< PORT4 IN: P14 (Bit 14) */ 14816 #define PORT4_IN_P14_Msk (0x4000UL) /*!< PORT4 IN: P14 (Bitfield-Mask: 0x01) */ 14817 #define PORT4_IN_P15_Pos (15UL) /*!< PORT4 IN: P15 (Bit 15) */ 14818 #define PORT4_IN_P15_Msk (0x8000UL) /*!< PORT4 IN: P15 (Bitfield-Mask: 0x01) */ 14819 14820 /* --------------------------------- PORT4_PDR0 --------------------------------- */ 14821 #define PORT4_PDR0_PD0_Pos (0UL) /*!< PORT4 PDR0: PD0 (Bit 0) */ 14822 #define PORT4_PDR0_PD0_Msk (0x7UL) /*!< PORT4 PDR0: PD0 (Bitfield-Mask: 0x07) */ 14823 #define PORT4_PDR0_PD1_Pos (4UL) /*!< PORT4 PDR0: PD1 (Bit 4) */ 14824 #define PORT4_PDR0_PD1_Msk (0x70UL) /*!< PORT4 PDR0: PD1 (Bitfield-Mask: 0x07) */ 14825 #define PORT4_PDR0_PD2_Pos (8UL) /*!< PORT4 PDR0: PD2 (Bit 8) */ 14826 #define PORT4_PDR0_PD2_Msk (0x700UL) /*!< PORT4 PDR0: PD2 (Bitfield-Mask: 0x07) */ 14827 #define PORT4_PDR0_PD3_Pos (12UL) /*!< PORT4 PDR0: PD3 (Bit 12) */ 14828 #define PORT4_PDR0_PD3_Msk (0x7000UL) /*!< PORT4 PDR0: PD3 (Bitfield-Mask: 0x07) */ 14829 #define PORT4_PDR0_PD4_Pos (16UL) /*!< PORT4 PDR0: PD4 (Bit 16) */ 14830 #define PORT4_PDR0_PD4_Msk (0x70000UL) /*!< PORT4 PDR0: PD4 (Bitfield-Mask: 0x07) */ 14831 #define PORT4_PDR0_PD5_Pos (20UL) /*!< PORT4 PDR0: PD5 (Bit 20) */ 14832 #define PORT4_PDR0_PD5_Msk (0x700000UL) /*!< PORT4 PDR0: PD5 (Bitfield-Mask: 0x07) */ 14833 #define PORT4_PDR0_PD6_Pos (24UL) /*!< PORT4 PDR0: PD6 (Bit 24) */ 14834 #define PORT4_PDR0_PD6_Msk (0x7000000UL) /*!< PORT4 PDR0: PD6 (Bitfield-Mask: 0x07) */ 14835 #define PORT4_PDR0_PD7_Pos (28UL) /*!< PORT4 PDR0: PD7 (Bit 28) */ 14836 #define PORT4_PDR0_PD7_Msk (0x70000000UL) /*!< PORT4 PDR0: PD7 (Bitfield-Mask: 0x07) */ 14837 14838 /* --------------------------------- PORT4_PDISC -------------------------------- */ 14839 #define PORT4_PDISC_PDIS0_Pos (0UL) /*!< PORT4 PDISC: PDIS0 (Bit 0) */ 14840 #define PORT4_PDISC_PDIS0_Msk (0x1UL) /*!< PORT4 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ 14841 #define PORT4_PDISC_PDIS1_Pos (1UL) /*!< PORT4 PDISC: PDIS1 (Bit 1) */ 14842 #define PORT4_PDISC_PDIS1_Msk (0x2UL) /*!< PORT4 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ 14843 #define PORT4_PDISC_PDIS2_Pos (2UL) /*!< PORT4 PDISC: PDIS2 (Bit 2) */ 14844 #define PORT4_PDISC_PDIS2_Msk (0x4UL) /*!< PORT4 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 14845 #define PORT4_PDISC_PDIS3_Pos (3UL) /*!< PORT4 PDISC: PDIS3 (Bit 3) */ 14846 #define PORT4_PDISC_PDIS3_Msk (0x8UL) /*!< PORT4 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 14847 #define PORT4_PDISC_PDIS4_Pos (4UL) /*!< PORT4 PDISC: PDIS4 (Bit 4) */ 14848 #define PORT4_PDISC_PDIS4_Msk (0x10UL) /*!< PORT4 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 14849 #define PORT4_PDISC_PDIS5_Pos (5UL) /*!< PORT4 PDISC: PDIS5 (Bit 5) */ 14850 #define PORT4_PDISC_PDIS5_Msk (0x20UL) /*!< PORT4 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 14851 #define PORT4_PDISC_PDIS6_Pos (6UL) /*!< PORT4 PDISC: PDIS6 (Bit 6) */ 14852 #define PORT4_PDISC_PDIS6_Msk (0x40UL) /*!< PORT4 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 14853 #define PORT4_PDISC_PDIS7_Pos (7UL) /*!< PORT4 PDISC: PDIS7 (Bit 7) */ 14854 #define PORT4_PDISC_PDIS7_Msk (0x80UL) /*!< PORT4 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 14855 #define PORT4_PDISC_PDIS8_Pos (8UL) /*!< PORT4 PDISC: PDIS8 (Bit 8) */ 14856 #define PORT4_PDISC_PDIS8_Msk (0x100UL) /*!< PORT4 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 14857 #define PORT4_PDISC_PDIS9_Pos (9UL) /*!< PORT4 PDISC: PDIS9 (Bit 9) */ 14858 #define PORT4_PDISC_PDIS9_Msk (0x200UL) /*!< PORT4 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 14859 #define PORT4_PDISC_PDIS10_Pos (10UL) /*!< PORT4 PDISC: PDIS10 (Bit 10) */ 14860 #define PORT4_PDISC_PDIS10_Msk (0x400UL) /*!< PORT4 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ 14861 #define PORT4_PDISC_PDIS11_Pos (11UL) /*!< PORT4 PDISC: PDIS11 (Bit 11) */ 14862 #define PORT4_PDISC_PDIS11_Msk (0x800UL) /*!< PORT4 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ 14863 #define PORT4_PDISC_PDIS12_Pos (12UL) /*!< PORT4 PDISC: PDIS12 (Bit 12) */ 14864 #define PORT4_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT4 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 14865 #define PORT4_PDISC_PDIS13_Pos (13UL) /*!< PORT4 PDISC: PDIS13 (Bit 13) */ 14866 #define PORT4_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT4 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 14867 #define PORT4_PDISC_PDIS14_Pos (14UL) /*!< PORT4 PDISC: PDIS14 (Bit 14) */ 14868 #define PORT4_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT4 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 14869 #define PORT4_PDISC_PDIS15_Pos (15UL) /*!< PORT4 PDISC: PDIS15 (Bit 15) */ 14870 #define PORT4_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT4 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 14871 14872 /* ---------------------------------- PORT4_PPS --------------------------------- */ 14873 #define PORT4_PPS_PPS0_Pos (0UL) /*!< PORT4 PPS: PPS0 (Bit 0) */ 14874 #define PORT4_PPS_PPS0_Msk (0x1UL) /*!< PORT4 PPS: PPS0 (Bitfield-Mask: 0x01) */ 14875 #define PORT4_PPS_PPS1_Pos (1UL) /*!< PORT4 PPS: PPS1 (Bit 1) */ 14876 #define PORT4_PPS_PPS1_Msk (0x2UL) /*!< PORT4 PPS: PPS1 (Bitfield-Mask: 0x01) */ 14877 #define PORT4_PPS_PPS2_Pos (2UL) /*!< PORT4 PPS: PPS2 (Bit 2) */ 14878 #define PORT4_PPS_PPS2_Msk (0x4UL) /*!< PORT4 PPS: PPS2 (Bitfield-Mask: 0x01) */ 14879 #define PORT4_PPS_PPS3_Pos (3UL) /*!< PORT4 PPS: PPS3 (Bit 3) */ 14880 #define PORT4_PPS_PPS3_Msk (0x8UL) /*!< PORT4 PPS: PPS3 (Bitfield-Mask: 0x01) */ 14881 #define PORT4_PPS_PPS4_Pos (4UL) /*!< PORT4 PPS: PPS4 (Bit 4) */ 14882 #define PORT4_PPS_PPS4_Msk (0x10UL) /*!< PORT4 PPS: PPS4 (Bitfield-Mask: 0x01) */ 14883 #define PORT4_PPS_PPS5_Pos (5UL) /*!< PORT4 PPS: PPS5 (Bit 5) */ 14884 #define PORT4_PPS_PPS5_Msk (0x20UL) /*!< PORT4 PPS: PPS5 (Bitfield-Mask: 0x01) */ 14885 #define PORT4_PPS_PPS6_Pos (6UL) /*!< PORT4 PPS: PPS6 (Bit 6) */ 14886 #define PORT4_PPS_PPS6_Msk (0x40UL) /*!< PORT4 PPS: PPS6 (Bitfield-Mask: 0x01) */ 14887 #define PORT4_PPS_PPS7_Pos (7UL) /*!< PORT4 PPS: PPS7 (Bit 7) */ 14888 #define PORT4_PPS_PPS7_Msk (0x80UL) /*!< PORT4 PPS: PPS7 (Bitfield-Mask: 0x01) */ 14889 #define PORT4_PPS_PPS8_Pos (8UL) /*!< PORT4 PPS: PPS8 (Bit 8) */ 14890 #define PORT4_PPS_PPS8_Msk (0x100UL) /*!< PORT4 PPS: PPS8 (Bitfield-Mask: 0x01) */ 14891 #define PORT4_PPS_PPS9_Pos (9UL) /*!< PORT4 PPS: PPS9 (Bit 9) */ 14892 #define PORT4_PPS_PPS9_Msk (0x200UL) /*!< PORT4 PPS: PPS9 (Bitfield-Mask: 0x01) */ 14893 #define PORT4_PPS_PPS10_Pos (10UL) /*!< PORT4 PPS: PPS10 (Bit 10) */ 14894 #define PORT4_PPS_PPS10_Msk (0x400UL) /*!< PORT4 PPS: PPS10 (Bitfield-Mask: 0x01) */ 14895 #define PORT4_PPS_PPS11_Pos (11UL) /*!< PORT4 PPS: PPS11 (Bit 11) */ 14896 #define PORT4_PPS_PPS11_Msk (0x800UL) /*!< PORT4 PPS: PPS11 (Bitfield-Mask: 0x01) */ 14897 #define PORT4_PPS_PPS12_Pos (12UL) /*!< PORT4 PPS: PPS12 (Bit 12) */ 14898 #define PORT4_PPS_PPS12_Msk (0x1000UL) /*!< PORT4 PPS: PPS12 (Bitfield-Mask: 0x01) */ 14899 #define PORT4_PPS_PPS13_Pos (13UL) /*!< PORT4 PPS: PPS13 (Bit 13) */ 14900 #define PORT4_PPS_PPS13_Msk (0x2000UL) /*!< PORT4 PPS: PPS13 (Bitfield-Mask: 0x01) */ 14901 #define PORT4_PPS_PPS14_Pos (14UL) /*!< PORT4 PPS: PPS14 (Bit 14) */ 14902 #define PORT4_PPS_PPS14_Msk (0x4000UL) /*!< PORT4 PPS: PPS14 (Bitfield-Mask: 0x01) */ 14903 #define PORT4_PPS_PPS15_Pos (15UL) /*!< PORT4 PPS: PPS15 (Bit 15) */ 14904 #define PORT4_PPS_PPS15_Msk (0x8000UL) /*!< PORT4 PPS: PPS15 (Bitfield-Mask: 0x01) */ 14905 14906 /* --------------------------------- PORT4_HWSEL -------------------------------- */ 14907 #define PORT4_HWSEL_HW0_Pos (0UL) /*!< PORT4 HWSEL: HW0 (Bit 0) */ 14908 #define PORT4_HWSEL_HW0_Msk (0x3UL) /*!< PORT4 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 14909 #define PORT4_HWSEL_HW1_Pos (2UL) /*!< PORT4 HWSEL: HW1 (Bit 2) */ 14910 #define PORT4_HWSEL_HW1_Msk (0xcUL) /*!< PORT4 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 14911 #define PORT4_HWSEL_HW2_Pos (4UL) /*!< PORT4 HWSEL: HW2 (Bit 4) */ 14912 #define PORT4_HWSEL_HW2_Msk (0x30UL) /*!< PORT4 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 14913 #define PORT4_HWSEL_HW3_Pos (6UL) /*!< PORT4 HWSEL: HW3 (Bit 6) */ 14914 #define PORT4_HWSEL_HW3_Msk (0xc0UL) /*!< PORT4 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 14915 #define PORT4_HWSEL_HW4_Pos (8UL) /*!< PORT4 HWSEL: HW4 (Bit 8) */ 14916 #define PORT4_HWSEL_HW4_Msk (0x300UL) /*!< PORT4 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 14917 #define PORT4_HWSEL_HW5_Pos (10UL) /*!< PORT4 HWSEL: HW5 (Bit 10) */ 14918 #define PORT4_HWSEL_HW5_Msk (0xc00UL) /*!< PORT4 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 14919 #define PORT4_HWSEL_HW6_Pos (12UL) /*!< PORT4 HWSEL: HW6 (Bit 12) */ 14920 #define PORT4_HWSEL_HW6_Msk (0x3000UL) /*!< PORT4 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 14921 #define PORT4_HWSEL_HW7_Pos (14UL) /*!< PORT4 HWSEL: HW7 (Bit 14) */ 14922 #define PORT4_HWSEL_HW7_Msk (0xc000UL) /*!< PORT4 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 14923 #define PORT4_HWSEL_HW8_Pos (16UL) /*!< PORT4 HWSEL: HW8 (Bit 16) */ 14924 #define PORT4_HWSEL_HW8_Msk (0x30000UL) /*!< PORT4 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 14925 #define PORT4_HWSEL_HW9_Pos (18UL) /*!< PORT4 HWSEL: HW9 (Bit 18) */ 14926 #define PORT4_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT4 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 14927 #define PORT4_HWSEL_HW10_Pos (20UL) /*!< PORT4 HWSEL: HW10 (Bit 20) */ 14928 #define PORT4_HWSEL_HW10_Msk (0x300000UL) /*!< PORT4 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 14929 #define PORT4_HWSEL_HW11_Pos (22UL) /*!< PORT4 HWSEL: HW11 (Bit 22) */ 14930 #define PORT4_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT4 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 14931 #define PORT4_HWSEL_HW12_Pos (24UL) /*!< PORT4 HWSEL: HW12 (Bit 24) */ 14932 #define PORT4_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT4 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 14933 #define PORT4_HWSEL_HW13_Pos (26UL) /*!< PORT4 HWSEL: HW13 (Bit 26) */ 14934 #define PORT4_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT4 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 14935 #define PORT4_HWSEL_HW14_Pos (28UL) /*!< PORT4 HWSEL: HW14 (Bit 28) */ 14936 #define PORT4_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT4 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 14937 #define PORT4_HWSEL_HW15_Pos (30UL) /*!< PORT4 HWSEL: HW15 (Bit 30) */ 14938 #define PORT4_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT4 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 14939 14940 14941 /* ================================================================================ */ 14942 /* ================ struct 'PORT5' Position & Mask ================ */ 14943 /* ================================================================================ */ 14944 14945 14946 /* ---------------------------------- PORT5_OUT --------------------------------- */ 14947 #define PORT5_OUT_P0_Pos (0UL) /*!< PORT5 OUT: P0 (Bit 0) */ 14948 #define PORT5_OUT_P0_Msk (0x1UL) /*!< PORT5 OUT: P0 (Bitfield-Mask: 0x01) */ 14949 #define PORT5_OUT_P1_Pos (1UL) /*!< PORT5 OUT: P1 (Bit 1) */ 14950 #define PORT5_OUT_P1_Msk (0x2UL) /*!< PORT5 OUT: P1 (Bitfield-Mask: 0x01) */ 14951 #define PORT5_OUT_P2_Pos (2UL) /*!< PORT5 OUT: P2 (Bit 2) */ 14952 #define PORT5_OUT_P2_Msk (0x4UL) /*!< PORT5 OUT: P2 (Bitfield-Mask: 0x01) */ 14953 #define PORT5_OUT_P3_Pos (3UL) /*!< PORT5 OUT: P3 (Bit 3) */ 14954 #define PORT5_OUT_P3_Msk (0x8UL) /*!< PORT5 OUT: P3 (Bitfield-Mask: 0x01) */ 14955 #define PORT5_OUT_P4_Pos (4UL) /*!< PORT5 OUT: P4 (Bit 4) */ 14956 #define PORT5_OUT_P4_Msk (0x10UL) /*!< PORT5 OUT: P4 (Bitfield-Mask: 0x01) */ 14957 #define PORT5_OUT_P5_Pos (5UL) /*!< PORT5 OUT: P5 (Bit 5) */ 14958 #define PORT5_OUT_P5_Msk (0x20UL) /*!< PORT5 OUT: P5 (Bitfield-Mask: 0x01) */ 14959 #define PORT5_OUT_P6_Pos (6UL) /*!< PORT5 OUT: P6 (Bit 6) */ 14960 #define PORT5_OUT_P6_Msk (0x40UL) /*!< PORT5 OUT: P6 (Bitfield-Mask: 0x01) */ 14961 #define PORT5_OUT_P7_Pos (7UL) /*!< PORT5 OUT: P7 (Bit 7) */ 14962 #define PORT5_OUT_P7_Msk (0x80UL) /*!< PORT5 OUT: P7 (Bitfield-Mask: 0x01) */ 14963 #define PORT5_OUT_P8_Pos (8UL) /*!< PORT5 OUT: P8 (Bit 8) */ 14964 #define PORT5_OUT_P8_Msk (0x100UL) /*!< PORT5 OUT: P8 (Bitfield-Mask: 0x01) */ 14965 #define PORT5_OUT_P9_Pos (9UL) /*!< PORT5 OUT: P9 (Bit 9) */ 14966 #define PORT5_OUT_P9_Msk (0x200UL) /*!< PORT5 OUT: P9 (Bitfield-Mask: 0x01) */ 14967 #define PORT5_OUT_P10_Pos (10UL) /*!< PORT5 OUT: P10 (Bit 10) */ 14968 #define PORT5_OUT_P10_Msk (0x400UL) /*!< PORT5 OUT: P10 (Bitfield-Mask: 0x01) */ 14969 #define PORT5_OUT_P11_Pos (11UL) /*!< PORT5 OUT: P11 (Bit 11) */ 14970 #define PORT5_OUT_P11_Msk (0x800UL) /*!< PORT5 OUT: P11 (Bitfield-Mask: 0x01) */ 14971 #define PORT5_OUT_P12_Pos (12UL) /*!< PORT5 OUT: P12 (Bit 12) */ 14972 #define PORT5_OUT_P12_Msk (0x1000UL) /*!< PORT5 OUT: P12 (Bitfield-Mask: 0x01) */ 14973 #define PORT5_OUT_P13_Pos (13UL) /*!< PORT5 OUT: P13 (Bit 13) */ 14974 #define PORT5_OUT_P13_Msk (0x2000UL) /*!< PORT5 OUT: P13 (Bitfield-Mask: 0x01) */ 14975 #define PORT5_OUT_P14_Pos (14UL) /*!< PORT5 OUT: P14 (Bit 14) */ 14976 #define PORT5_OUT_P14_Msk (0x4000UL) /*!< PORT5 OUT: P14 (Bitfield-Mask: 0x01) */ 14977 #define PORT5_OUT_P15_Pos (15UL) /*!< PORT5 OUT: P15 (Bit 15) */ 14978 #define PORT5_OUT_P15_Msk (0x8000UL) /*!< PORT5 OUT: P15 (Bitfield-Mask: 0x01) */ 14979 14980 /* ---------------------------------- PORT5_OMR --------------------------------- */ 14981 #define PORT5_OMR_PS0_Pos (0UL) /*!< PORT5 OMR: PS0 (Bit 0) */ 14982 #define PORT5_OMR_PS0_Msk (0x1UL) /*!< PORT5 OMR: PS0 (Bitfield-Mask: 0x01) */ 14983 #define PORT5_OMR_PS1_Pos (1UL) /*!< PORT5 OMR: PS1 (Bit 1) */ 14984 #define PORT5_OMR_PS1_Msk (0x2UL) /*!< PORT5 OMR: PS1 (Bitfield-Mask: 0x01) */ 14985 #define PORT5_OMR_PS2_Pos (2UL) /*!< PORT5 OMR: PS2 (Bit 2) */ 14986 #define PORT5_OMR_PS2_Msk (0x4UL) /*!< PORT5 OMR: PS2 (Bitfield-Mask: 0x01) */ 14987 #define PORT5_OMR_PS3_Pos (3UL) /*!< PORT5 OMR: PS3 (Bit 3) */ 14988 #define PORT5_OMR_PS3_Msk (0x8UL) /*!< PORT5 OMR: PS3 (Bitfield-Mask: 0x01) */ 14989 #define PORT5_OMR_PS4_Pos (4UL) /*!< PORT5 OMR: PS4 (Bit 4) */ 14990 #define PORT5_OMR_PS4_Msk (0x10UL) /*!< PORT5 OMR: PS4 (Bitfield-Mask: 0x01) */ 14991 #define PORT5_OMR_PS5_Pos (5UL) /*!< PORT5 OMR: PS5 (Bit 5) */ 14992 #define PORT5_OMR_PS5_Msk (0x20UL) /*!< PORT5 OMR: PS5 (Bitfield-Mask: 0x01) */ 14993 #define PORT5_OMR_PS6_Pos (6UL) /*!< PORT5 OMR: PS6 (Bit 6) */ 14994 #define PORT5_OMR_PS6_Msk (0x40UL) /*!< PORT5 OMR: PS6 (Bitfield-Mask: 0x01) */ 14995 #define PORT5_OMR_PS7_Pos (7UL) /*!< PORT5 OMR: PS7 (Bit 7) */ 14996 #define PORT5_OMR_PS7_Msk (0x80UL) /*!< PORT5 OMR: PS7 (Bitfield-Mask: 0x01) */ 14997 #define PORT5_OMR_PS8_Pos (8UL) /*!< PORT5 OMR: PS8 (Bit 8) */ 14998 #define PORT5_OMR_PS8_Msk (0x100UL) /*!< PORT5 OMR: PS8 (Bitfield-Mask: 0x01) */ 14999 #define PORT5_OMR_PS9_Pos (9UL) /*!< PORT5 OMR: PS9 (Bit 9) */ 15000 #define PORT5_OMR_PS9_Msk (0x200UL) /*!< PORT5 OMR: PS9 (Bitfield-Mask: 0x01) */ 15001 #define PORT5_OMR_PS10_Pos (10UL) /*!< PORT5 OMR: PS10 (Bit 10) */ 15002 #define PORT5_OMR_PS10_Msk (0x400UL) /*!< PORT5 OMR: PS10 (Bitfield-Mask: 0x01) */ 15003 #define PORT5_OMR_PS11_Pos (11UL) /*!< PORT5 OMR: PS11 (Bit 11) */ 15004 #define PORT5_OMR_PS11_Msk (0x800UL) /*!< PORT5 OMR: PS11 (Bitfield-Mask: 0x01) */ 15005 #define PORT5_OMR_PS12_Pos (12UL) /*!< PORT5 OMR: PS12 (Bit 12) */ 15006 #define PORT5_OMR_PS12_Msk (0x1000UL) /*!< PORT5 OMR: PS12 (Bitfield-Mask: 0x01) */ 15007 #define PORT5_OMR_PS13_Pos (13UL) /*!< PORT5 OMR: PS13 (Bit 13) */ 15008 #define PORT5_OMR_PS13_Msk (0x2000UL) /*!< PORT5 OMR: PS13 (Bitfield-Mask: 0x01) */ 15009 #define PORT5_OMR_PS14_Pos (14UL) /*!< PORT5 OMR: PS14 (Bit 14) */ 15010 #define PORT5_OMR_PS14_Msk (0x4000UL) /*!< PORT5 OMR: PS14 (Bitfield-Mask: 0x01) */ 15011 #define PORT5_OMR_PS15_Pos (15UL) /*!< PORT5 OMR: PS15 (Bit 15) */ 15012 #define PORT5_OMR_PS15_Msk (0x8000UL) /*!< PORT5 OMR: PS15 (Bitfield-Mask: 0x01) */ 15013 #define PORT5_OMR_PR0_Pos (16UL) /*!< PORT5 OMR: PR0 (Bit 16) */ 15014 #define PORT5_OMR_PR0_Msk (0x10000UL) /*!< PORT5 OMR: PR0 (Bitfield-Mask: 0x01) */ 15015 #define PORT5_OMR_PR1_Pos (17UL) /*!< PORT5 OMR: PR1 (Bit 17) */ 15016 #define PORT5_OMR_PR1_Msk (0x20000UL) /*!< PORT5 OMR: PR1 (Bitfield-Mask: 0x01) */ 15017 #define PORT5_OMR_PR2_Pos (18UL) /*!< PORT5 OMR: PR2 (Bit 18) */ 15018 #define PORT5_OMR_PR2_Msk (0x40000UL) /*!< PORT5 OMR: PR2 (Bitfield-Mask: 0x01) */ 15019 #define PORT5_OMR_PR3_Pos (19UL) /*!< PORT5 OMR: PR3 (Bit 19) */ 15020 #define PORT5_OMR_PR3_Msk (0x80000UL) /*!< PORT5 OMR: PR3 (Bitfield-Mask: 0x01) */ 15021 #define PORT5_OMR_PR4_Pos (20UL) /*!< PORT5 OMR: PR4 (Bit 20) */ 15022 #define PORT5_OMR_PR4_Msk (0x100000UL) /*!< PORT5 OMR: PR4 (Bitfield-Mask: 0x01) */ 15023 #define PORT5_OMR_PR5_Pos (21UL) /*!< PORT5 OMR: PR5 (Bit 21) */ 15024 #define PORT5_OMR_PR5_Msk (0x200000UL) /*!< PORT5 OMR: PR5 (Bitfield-Mask: 0x01) */ 15025 #define PORT5_OMR_PR6_Pos (22UL) /*!< PORT5 OMR: PR6 (Bit 22) */ 15026 #define PORT5_OMR_PR6_Msk (0x400000UL) /*!< PORT5 OMR: PR6 (Bitfield-Mask: 0x01) */ 15027 #define PORT5_OMR_PR7_Pos (23UL) /*!< PORT5 OMR: PR7 (Bit 23) */ 15028 #define PORT5_OMR_PR7_Msk (0x800000UL) /*!< PORT5 OMR: PR7 (Bitfield-Mask: 0x01) */ 15029 #define PORT5_OMR_PR8_Pos (24UL) /*!< PORT5 OMR: PR8 (Bit 24) */ 15030 #define PORT5_OMR_PR8_Msk (0x1000000UL) /*!< PORT5 OMR: PR8 (Bitfield-Mask: 0x01) */ 15031 #define PORT5_OMR_PR9_Pos (25UL) /*!< PORT5 OMR: PR9 (Bit 25) */ 15032 #define PORT5_OMR_PR9_Msk (0x2000000UL) /*!< PORT5 OMR: PR9 (Bitfield-Mask: 0x01) */ 15033 #define PORT5_OMR_PR10_Pos (26UL) /*!< PORT5 OMR: PR10 (Bit 26) */ 15034 #define PORT5_OMR_PR10_Msk (0x4000000UL) /*!< PORT5 OMR: PR10 (Bitfield-Mask: 0x01) */ 15035 #define PORT5_OMR_PR11_Pos (27UL) /*!< PORT5 OMR: PR11 (Bit 27) */ 15036 #define PORT5_OMR_PR11_Msk (0x8000000UL) /*!< PORT5 OMR: PR11 (Bitfield-Mask: 0x01) */ 15037 #define PORT5_OMR_PR12_Pos (28UL) /*!< PORT5 OMR: PR12 (Bit 28) */ 15038 #define PORT5_OMR_PR12_Msk (0x10000000UL) /*!< PORT5 OMR: PR12 (Bitfield-Mask: 0x01) */ 15039 #define PORT5_OMR_PR13_Pos (29UL) /*!< PORT5 OMR: PR13 (Bit 29) */ 15040 #define PORT5_OMR_PR13_Msk (0x20000000UL) /*!< PORT5 OMR: PR13 (Bitfield-Mask: 0x01) */ 15041 #define PORT5_OMR_PR14_Pos (30UL) /*!< PORT5 OMR: PR14 (Bit 30) */ 15042 #define PORT5_OMR_PR14_Msk (0x40000000UL) /*!< PORT5 OMR: PR14 (Bitfield-Mask: 0x01) */ 15043 #define PORT5_OMR_PR15_Pos (31UL) /*!< PORT5 OMR: PR15 (Bit 31) */ 15044 #define PORT5_OMR_PR15_Msk (0x80000000UL) /*!< PORT5 OMR: PR15 (Bitfield-Mask: 0x01) */ 15045 15046 /* --------------------------------- PORT5_IOCR0 -------------------------------- */ 15047 #define PORT5_IOCR0_PC0_Pos (3UL) /*!< PORT5 IOCR0: PC0 (Bit 3) */ 15048 #define PORT5_IOCR0_PC0_Msk (0xf8UL) /*!< PORT5 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 15049 #define PORT5_IOCR0_PC1_Pos (11UL) /*!< PORT5 IOCR0: PC1 (Bit 11) */ 15050 #define PORT5_IOCR0_PC1_Msk (0xf800UL) /*!< PORT5 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 15051 #define PORT5_IOCR0_PC2_Pos (19UL) /*!< PORT5 IOCR0: PC2 (Bit 19) */ 15052 #define PORT5_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT5 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 15053 #define PORT5_IOCR0_PC3_Pos (27UL) /*!< PORT5 IOCR0: PC3 (Bit 27) */ 15054 #define PORT5_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT5 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 15055 15056 /* --------------------------------- PORT5_IOCR4 -------------------------------- */ 15057 #define PORT5_IOCR4_PC4_Pos (3UL) /*!< PORT5 IOCR4: PC4 (Bit 3) */ 15058 #define PORT5_IOCR4_PC4_Msk (0xf8UL) /*!< PORT5 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 15059 #define PORT5_IOCR4_PC5_Pos (11UL) /*!< PORT5 IOCR4: PC5 (Bit 11) */ 15060 #define PORT5_IOCR4_PC5_Msk (0xf800UL) /*!< PORT5 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 15061 #define PORT5_IOCR4_PC6_Pos (19UL) /*!< PORT5 IOCR4: PC6 (Bit 19) */ 15062 #define PORT5_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT5 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 15063 #define PORT5_IOCR4_PC7_Pos (27UL) /*!< PORT5 IOCR4: PC7 (Bit 27) */ 15064 #define PORT5_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT5 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 15065 15066 /* --------------------------------- PORT5_IOCR8 -------------------------------- */ 15067 #define PORT5_IOCR8_PC8_Pos (3UL) /*!< PORT5 IOCR8: PC8 (Bit 3) */ 15068 #define PORT5_IOCR8_PC8_Msk (0xf8UL) /*!< PORT5 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ 15069 #define PORT5_IOCR8_PC9_Pos (11UL) /*!< PORT5 IOCR8: PC9 (Bit 11) */ 15070 #define PORT5_IOCR8_PC9_Msk (0xf800UL) /*!< PORT5 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ 15071 #define PORT5_IOCR8_PC10_Pos (19UL) /*!< PORT5 IOCR8: PC10 (Bit 19) */ 15072 #define PORT5_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT5 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ 15073 #define PORT5_IOCR8_PC11_Pos (27UL) /*!< PORT5 IOCR8: PC11 (Bit 27) */ 15074 #define PORT5_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT5 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ 15075 15076 /* ---------------------------------- PORT5_IN ---------------------------------- */ 15077 #define PORT5_IN_P0_Pos (0UL) /*!< PORT5 IN: P0 (Bit 0) */ 15078 #define PORT5_IN_P0_Msk (0x1UL) /*!< PORT5 IN: P0 (Bitfield-Mask: 0x01) */ 15079 #define PORT5_IN_P1_Pos (1UL) /*!< PORT5 IN: P1 (Bit 1) */ 15080 #define PORT5_IN_P1_Msk (0x2UL) /*!< PORT5 IN: P1 (Bitfield-Mask: 0x01) */ 15081 #define PORT5_IN_P2_Pos (2UL) /*!< PORT5 IN: P2 (Bit 2) */ 15082 #define PORT5_IN_P2_Msk (0x4UL) /*!< PORT5 IN: P2 (Bitfield-Mask: 0x01) */ 15083 #define PORT5_IN_P3_Pos (3UL) /*!< PORT5 IN: P3 (Bit 3) */ 15084 #define PORT5_IN_P3_Msk (0x8UL) /*!< PORT5 IN: P3 (Bitfield-Mask: 0x01) */ 15085 #define PORT5_IN_P4_Pos (4UL) /*!< PORT5 IN: P4 (Bit 4) */ 15086 #define PORT5_IN_P4_Msk (0x10UL) /*!< PORT5 IN: P4 (Bitfield-Mask: 0x01) */ 15087 #define PORT5_IN_P5_Pos (5UL) /*!< PORT5 IN: P5 (Bit 5) */ 15088 #define PORT5_IN_P5_Msk (0x20UL) /*!< PORT5 IN: P5 (Bitfield-Mask: 0x01) */ 15089 #define PORT5_IN_P6_Pos (6UL) /*!< PORT5 IN: P6 (Bit 6) */ 15090 #define PORT5_IN_P6_Msk (0x40UL) /*!< PORT5 IN: P6 (Bitfield-Mask: 0x01) */ 15091 #define PORT5_IN_P7_Pos (7UL) /*!< PORT5 IN: P7 (Bit 7) */ 15092 #define PORT5_IN_P7_Msk (0x80UL) /*!< PORT5 IN: P7 (Bitfield-Mask: 0x01) */ 15093 #define PORT5_IN_P8_Pos (8UL) /*!< PORT5 IN: P8 (Bit 8) */ 15094 #define PORT5_IN_P8_Msk (0x100UL) /*!< PORT5 IN: P8 (Bitfield-Mask: 0x01) */ 15095 #define PORT5_IN_P9_Pos (9UL) /*!< PORT5 IN: P9 (Bit 9) */ 15096 #define PORT5_IN_P9_Msk (0x200UL) /*!< PORT5 IN: P9 (Bitfield-Mask: 0x01) */ 15097 #define PORT5_IN_P10_Pos (10UL) /*!< PORT5 IN: P10 (Bit 10) */ 15098 #define PORT5_IN_P10_Msk (0x400UL) /*!< PORT5 IN: P10 (Bitfield-Mask: 0x01) */ 15099 #define PORT5_IN_P11_Pos (11UL) /*!< PORT5 IN: P11 (Bit 11) */ 15100 #define PORT5_IN_P11_Msk (0x800UL) /*!< PORT5 IN: P11 (Bitfield-Mask: 0x01) */ 15101 #define PORT5_IN_P12_Pos (12UL) /*!< PORT5 IN: P12 (Bit 12) */ 15102 #define PORT5_IN_P12_Msk (0x1000UL) /*!< PORT5 IN: P12 (Bitfield-Mask: 0x01) */ 15103 #define PORT5_IN_P13_Pos (13UL) /*!< PORT5 IN: P13 (Bit 13) */ 15104 #define PORT5_IN_P13_Msk (0x2000UL) /*!< PORT5 IN: P13 (Bitfield-Mask: 0x01) */ 15105 #define PORT5_IN_P14_Pos (14UL) /*!< PORT5 IN: P14 (Bit 14) */ 15106 #define PORT5_IN_P14_Msk (0x4000UL) /*!< PORT5 IN: P14 (Bitfield-Mask: 0x01) */ 15107 #define PORT5_IN_P15_Pos (15UL) /*!< PORT5 IN: P15 (Bit 15) */ 15108 #define PORT5_IN_P15_Msk (0x8000UL) /*!< PORT5 IN: P15 (Bitfield-Mask: 0x01) */ 15109 15110 /* --------------------------------- PORT5_PDR0 --------------------------------- */ 15111 #define PORT5_PDR0_PD0_Pos (0UL) /*!< PORT5 PDR0: PD0 (Bit 0) */ 15112 #define PORT5_PDR0_PD0_Msk (0x7UL) /*!< PORT5 PDR0: PD0 (Bitfield-Mask: 0x07) */ 15113 #define PORT5_PDR0_PD1_Pos (4UL) /*!< PORT5 PDR0: PD1 (Bit 4) */ 15114 #define PORT5_PDR0_PD1_Msk (0x70UL) /*!< PORT5 PDR0: PD1 (Bitfield-Mask: 0x07) */ 15115 #define PORT5_PDR0_PD2_Pos (8UL) /*!< PORT5 PDR0: PD2 (Bit 8) */ 15116 #define PORT5_PDR0_PD2_Msk (0x700UL) /*!< PORT5 PDR0: PD2 (Bitfield-Mask: 0x07) */ 15117 #define PORT5_PDR0_PD3_Pos (12UL) /*!< PORT5 PDR0: PD3 (Bit 12) */ 15118 #define PORT5_PDR0_PD3_Msk (0x7000UL) /*!< PORT5 PDR0: PD3 (Bitfield-Mask: 0x07) */ 15119 #define PORT5_PDR0_PD4_Pos (16UL) /*!< PORT5 PDR0: PD4 (Bit 16) */ 15120 #define PORT5_PDR0_PD4_Msk (0x70000UL) /*!< PORT5 PDR0: PD4 (Bitfield-Mask: 0x07) */ 15121 #define PORT5_PDR0_PD5_Pos (20UL) /*!< PORT5 PDR0: PD5 (Bit 20) */ 15122 #define PORT5_PDR0_PD5_Msk (0x700000UL) /*!< PORT5 PDR0: PD5 (Bitfield-Mask: 0x07) */ 15123 #define PORT5_PDR0_PD6_Pos (24UL) /*!< PORT5 PDR0: PD6 (Bit 24) */ 15124 #define PORT5_PDR0_PD6_Msk (0x7000000UL) /*!< PORT5 PDR0: PD6 (Bitfield-Mask: 0x07) */ 15125 #define PORT5_PDR0_PD7_Pos (28UL) /*!< PORT5 PDR0: PD7 (Bit 28) */ 15126 #define PORT5_PDR0_PD7_Msk (0x70000000UL) /*!< PORT5 PDR0: PD7 (Bitfield-Mask: 0x07) */ 15127 15128 /* --------------------------------- PORT5_PDR1 --------------------------------- */ 15129 #define PORT5_PDR1_PD8_Pos (0UL) /*!< PORT5 PDR1: PD8 (Bit 0) */ 15130 #define PORT5_PDR1_PD8_Msk (0x7UL) /*!< PORT5 PDR1: PD8 (Bitfield-Mask: 0x07) */ 15131 #define PORT5_PDR1_PD9_Pos (4UL) /*!< PORT5 PDR1: PD9 (Bit 4) */ 15132 #define PORT5_PDR1_PD9_Msk (0x70UL) /*!< PORT5 PDR1: PD9 (Bitfield-Mask: 0x07) */ 15133 #define PORT5_PDR1_PD10_Pos (8UL) /*!< PORT5 PDR1: PD10 (Bit 8) */ 15134 #define PORT5_PDR1_PD10_Msk (0x700UL) /*!< PORT5 PDR1: PD10 (Bitfield-Mask: 0x07) */ 15135 #define PORT5_PDR1_PD11_Pos (12UL) /*!< PORT5 PDR1: PD11 (Bit 12) */ 15136 #define PORT5_PDR1_PD11_Msk (0x7000UL) /*!< PORT5 PDR1: PD11 (Bitfield-Mask: 0x07) */ 15137 #define PORT5_PDR1_PD12_Pos (16UL) /*!< PORT5 PDR1: PD12 (Bit 16) */ 15138 #define PORT5_PDR1_PD12_Msk (0x70000UL) /*!< PORT5 PDR1: PD12 (Bitfield-Mask: 0x07) */ 15139 #define PORT5_PDR1_PD13_Pos (20UL) /*!< PORT5 PDR1: PD13 (Bit 20) */ 15140 #define PORT5_PDR1_PD13_Msk (0x700000UL) /*!< PORT5 PDR1: PD13 (Bitfield-Mask: 0x07) */ 15141 #define PORT5_PDR1_PD14_Pos (24UL) /*!< PORT5 PDR1: PD14 (Bit 24) */ 15142 #define PORT5_PDR1_PD14_Msk (0x7000000UL) /*!< PORT5 PDR1: PD14 (Bitfield-Mask: 0x07) */ 15143 #define PORT5_PDR1_PD15_Pos (28UL) /*!< PORT5 PDR1: PD15 (Bit 28) */ 15144 #define PORT5_PDR1_PD15_Msk (0x70000000UL) /*!< PORT5 PDR1: PD15 (Bitfield-Mask: 0x07) */ 15145 15146 /* --------------------------------- PORT5_PDISC -------------------------------- */ 15147 #define PORT5_PDISC_PDIS0_Pos (0UL) /*!< PORT5 PDISC: PDIS0 (Bit 0) */ 15148 #define PORT5_PDISC_PDIS0_Msk (0x1UL) /*!< PORT5 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ 15149 #define PORT5_PDISC_PDIS1_Pos (1UL) /*!< PORT5 PDISC: PDIS1 (Bit 1) */ 15150 #define PORT5_PDISC_PDIS1_Msk (0x2UL) /*!< PORT5 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ 15151 #define PORT5_PDISC_PDIS2_Pos (2UL) /*!< PORT5 PDISC: PDIS2 (Bit 2) */ 15152 #define PORT5_PDISC_PDIS2_Msk (0x4UL) /*!< PORT5 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 15153 #define PORT5_PDISC_PDIS3_Pos (3UL) /*!< PORT5 PDISC: PDIS3 (Bit 3) */ 15154 #define PORT5_PDISC_PDIS3_Msk (0x8UL) /*!< PORT5 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 15155 #define PORT5_PDISC_PDIS4_Pos (4UL) /*!< PORT5 PDISC: PDIS4 (Bit 4) */ 15156 #define PORT5_PDISC_PDIS4_Msk (0x10UL) /*!< PORT5 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 15157 #define PORT5_PDISC_PDIS5_Pos (5UL) /*!< PORT5 PDISC: PDIS5 (Bit 5) */ 15158 #define PORT5_PDISC_PDIS5_Msk (0x20UL) /*!< PORT5 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 15159 #define PORT5_PDISC_PDIS6_Pos (6UL) /*!< PORT5 PDISC: PDIS6 (Bit 6) */ 15160 #define PORT5_PDISC_PDIS6_Msk (0x40UL) /*!< PORT5 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 15161 #define PORT5_PDISC_PDIS7_Pos (7UL) /*!< PORT5 PDISC: PDIS7 (Bit 7) */ 15162 #define PORT5_PDISC_PDIS7_Msk (0x80UL) /*!< PORT5 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 15163 #define PORT5_PDISC_PDIS8_Pos (8UL) /*!< PORT5 PDISC: PDIS8 (Bit 8) */ 15164 #define PORT5_PDISC_PDIS8_Msk (0x100UL) /*!< PORT5 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 15165 #define PORT5_PDISC_PDIS9_Pos (9UL) /*!< PORT5 PDISC: PDIS9 (Bit 9) */ 15166 #define PORT5_PDISC_PDIS9_Msk (0x200UL) /*!< PORT5 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 15167 #define PORT5_PDISC_PDIS10_Pos (10UL) /*!< PORT5 PDISC: PDIS10 (Bit 10) */ 15168 #define PORT5_PDISC_PDIS10_Msk (0x400UL) /*!< PORT5 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ 15169 #define PORT5_PDISC_PDIS11_Pos (11UL) /*!< PORT5 PDISC: PDIS11 (Bit 11) */ 15170 #define PORT5_PDISC_PDIS11_Msk (0x800UL) /*!< PORT5 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ 15171 #define PORT5_PDISC_PDIS12_Pos (12UL) /*!< PORT5 PDISC: PDIS12 (Bit 12) */ 15172 #define PORT5_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT5 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 15173 #define PORT5_PDISC_PDIS13_Pos (13UL) /*!< PORT5 PDISC: PDIS13 (Bit 13) */ 15174 #define PORT5_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT5 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 15175 #define PORT5_PDISC_PDIS14_Pos (14UL) /*!< PORT5 PDISC: PDIS14 (Bit 14) */ 15176 #define PORT5_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT5 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 15177 #define PORT5_PDISC_PDIS15_Pos (15UL) /*!< PORT5 PDISC: PDIS15 (Bit 15) */ 15178 #define PORT5_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT5 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 15179 15180 /* ---------------------------------- PORT5_PPS --------------------------------- */ 15181 #define PORT5_PPS_PPS0_Pos (0UL) /*!< PORT5 PPS: PPS0 (Bit 0) */ 15182 #define PORT5_PPS_PPS0_Msk (0x1UL) /*!< PORT5 PPS: PPS0 (Bitfield-Mask: 0x01) */ 15183 #define PORT5_PPS_PPS1_Pos (1UL) /*!< PORT5 PPS: PPS1 (Bit 1) */ 15184 #define PORT5_PPS_PPS1_Msk (0x2UL) /*!< PORT5 PPS: PPS1 (Bitfield-Mask: 0x01) */ 15185 #define PORT5_PPS_PPS2_Pos (2UL) /*!< PORT5 PPS: PPS2 (Bit 2) */ 15186 #define PORT5_PPS_PPS2_Msk (0x4UL) /*!< PORT5 PPS: PPS2 (Bitfield-Mask: 0x01) */ 15187 #define PORT5_PPS_PPS3_Pos (3UL) /*!< PORT5 PPS: PPS3 (Bit 3) */ 15188 #define PORT5_PPS_PPS3_Msk (0x8UL) /*!< PORT5 PPS: PPS3 (Bitfield-Mask: 0x01) */ 15189 #define PORT5_PPS_PPS4_Pos (4UL) /*!< PORT5 PPS: PPS4 (Bit 4) */ 15190 #define PORT5_PPS_PPS4_Msk (0x10UL) /*!< PORT5 PPS: PPS4 (Bitfield-Mask: 0x01) */ 15191 #define PORT5_PPS_PPS5_Pos (5UL) /*!< PORT5 PPS: PPS5 (Bit 5) */ 15192 #define PORT5_PPS_PPS5_Msk (0x20UL) /*!< PORT5 PPS: PPS5 (Bitfield-Mask: 0x01) */ 15193 #define PORT5_PPS_PPS6_Pos (6UL) /*!< PORT5 PPS: PPS6 (Bit 6) */ 15194 #define PORT5_PPS_PPS6_Msk (0x40UL) /*!< PORT5 PPS: PPS6 (Bitfield-Mask: 0x01) */ 15195 #define PORT5_PPS_PPS7_Pos (7UL) /*!< PORT5 PPS: PPS7 (Bit 7) */ 15196 #define PORT5_PPS_PPS7_Msk (0x80UL) /*!< PORT5 PPS: PPS7 (Bitfield-Mask: 0x01) */ 15197 #define PORT5_PPS_PPS8_Pos (8UL) /*!< PORT5 PPS: PPS8 (Bit 8) */ 15198 #define PORT5_PPS_PPS8_Msk (0x100UL) /*!< PORT5 PPS: PPS8 (Bitfield-Mask: 0x01) */ 15199 #define PORT5_PPS_PPS9_Pos (9UL) /*!< PORT5 PPS: PPS9 (Bit 9) */ 15200 #define PORT5_PPS_PPS9_Msk (0x200UL) /*!< PORT5 PPS: PPS9 (Bitfield-Mask: 0x01) */ 15201 #define PORT5_PPS_PPS10_Pos (10UL) /*!< PORT5 PPS: PPS10 (Bit 10) */ 15202 #define PORT5_PPS_PPS10_Msk (0x400UL) /*!< PORT5 PPS: PPS10 (Bitfield-Mask: 0x01) */ 15203 #define PORT5_PPS_PPS11_Pos (11UL) /*!< PORT5 PPS: PPS11 (Bit 11) */ 15204 #define PORT5_PPS_PPS11_Msk (0x800UL) /*!< PORT5 PPS: PPS11 (Bitfield-Mask: 0x01) */ 15205 #define PORT5_PPS_PPS12_Pos (12UL) /*!< PORT5 PPS: PPS12 (Bit 12) */ 15206 #define PORT5_PPS_PPS12_Msk (0x1000UL) /*!< PORT5 PPS: PPS12 (Bitfield-Mask: 0x01) */ 15207 #define PORT5_PPS_PPS13_Pos (13UL) /*!< PORT5 PPS: PPS13 (Bit 13) */ 15208 #define PORT5_PPS_PPS13_Msk (0x2000UL) /*!< PORT5 PPS: PPS13 (Bitfield-Mask: 0x01) */ 15209 #define PORT5_PPS_PPS14_Pos (14UL) /*!< PORT5 PPS: PPS14 (Bit 14) */ 15210 #define PORT5_PPS_PPS14_Msk (0x4000UL) /*!< PORT5 PPS: PPS14 (Bitfield-Mask: 0x01) */ 15211 #define PORT5_PPS_PPS15_Pos (15UL) /*!< PORT5 PPS: PPS15 (Bit 15) */ 15212 #define PORT5_PPS_PPS15_Msk (0x8000UL) /*!< PORT5 PPS: PPS15 (Bitfield-Mask: 0x01) */ 15213 15214 /* --------------------------------- PORT5_HWSEL -------------------------------- */ 15215 #define PORT5_HWSEL_HW0_Pos (0UL) /*!< PORT5 HWSEL: HW0 (Bit 0) */ 15216 #define PORT5_HWSEL_HW0_Msk (0x3UL) /*!< PORT5 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 15217 #define PORT5_HWSEL_HW1_Pos (2UL) /*!< PORT5 HWSEL: HW1 (Bit 2) */ 15218 #define PORT5_HWSEL_HW1_Msk (0xcUL) /*!< PORT5 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 15219 #define PORT5_HWSEL_HW2_Pos (4UL) /*!< PORT5 HWSEL: HW2 (Bit 4) */ 15220 #define PORT5_HWSEL_HW2_Msk (0x30UL) /*!< PORT5 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 15221 #define PORT5_HWSEL_HW3_Pos (6UL) /*!< PORT5 HWSEL: HW3 (Bit 6) */ 15222 #define PORT5_HWSEL_HW3_Msk (0xc0UL) /*!< PORT5 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 15223 #define PORT5_HWSEL_HW4_Pos (8UL) /*!< PORT5 HWSEL: HW4 (Bit 8) */ 15224 #define PORT5_HWSEL_HW4_Msk (0x300UL) /*!< PORT5 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 15225 #define PORT5_HWSEL_HW5_Pos (10UL) /*!< PORT5 HWSEL: HW5 (Bit 10) */ 15226 #define PORT5_HWSEL_HW5_Msk (0xc00UL) /*!< PORT5 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 15227 #define PORT5_HWSEL_HW6_Pos (12UL) /*!< PORT5 HWSEL: HW6 (Bit 12) */ 15228 #define PORT5_HWSEL_HW6_Msk (0x3000UL) /*!< PORT5 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 15229 #define PORT5_HWSEL_HW7_Pos (14UL) /*!< PORT5 HWSEL: HW7 (Bit 14) */ 15230 #define PORT5_HWSEL_HW7_Msk (0xc000UL) /*!< PORT5 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 15231 #define PORT5_HWSEL_HW8_Pos (16UL) /*!< PORT5 HWSEL: HW8 (Bit 16) */ 15232 #define PORT5_HWSEL_HW8_Msk (0x30000UL) /*!< PORT5 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 15233 #define PORT5_HWSEL_HW9_Pos (18UL) /*!< PORT5 HWSEL: HW9 (Bit 18) */ 15234 #define PORT5_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT5 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 15235 #define PORT5_HWSEL_HW10_Pos (20UL) /*!< PORT5 HWSEL: HW10 (Bit 20) */ 15236 #define PORT5_HWSEL_HW10_Msk (0x300000UL) /*!< PORT5 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 15237 #define PORT5_HWSEL_HW11_Pos (22UL) /*!< PORT5 HWSEL: HW11 (Bit 22) */ 15238 #define PORT5_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT5 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 15239 #define PORT5_HWSEL_HW12_Pos (24UL) /*!< PORT5 HWSEL: HW12 (Bit 24) */ 15240 #define PORT5_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT5 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 15241 #define PORT5_HWSEL_HW13_Pos (26UL) /*!< PORT5 HWSEL: HW13 (Bit 26) */ 15242 #define PORT5_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT5 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 15243 #define PORT5_HWSEL_HW14_Pos (28UL) /*!< PORT5 HWSEL: HW14 (Bit 28) */ 15244 #define PORT5_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT5 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 15245 #define PORT5_HWSEL_HW15_Pos (30UL) /*!< PORT5 HWSEL: HW15 (Bit 30) */ 15246 #define PORT5_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT5 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 15247 15248 15249 /* ================================================================================ */ 15250 /* ================ struct 'PORT6' Position & Mask ================ */ 15251 /* ================================================================================ */ 15252 15253 15254 /* ---------------------------------- PORT6_OUT --------------------------------- */ 15255 #define PORT6_OUT_P0_Pos (0UL) /*!< PORT6 OUT: P0 (Bit 0) */ 15256 #define PORT6_OUT_P0_Msk (0x1UL) /*!< PORT6 OUT: P0 (Bitfield-Mask: 0x01) */ 15257 #define PORT6_OUT_P1_Pos (1UL) /*!< PORT6 OUT: P1 (Bit 1) */ 15258 #define PORT6_OUT_P1_Msk (0x2UL) /*!< PORT6 OUT: P1 (Bitfield-Mask: 0x01) */ 15259 #define PORT6_OUT_P2_Pos (2UL) /*!< PORT6 OUT: P2 (Bit 2) */ 15260 #define PORT6_OUT_P2_Msk (0x4UL) /*!< PORT6 OUT: P2 (Bitfield-Mask: 0x01) */ 15261 #define PORT6_OUT_P3_Pos (3UL) /*!< PORT6 OUT: P3 (Bit 3) */ 15262 #define PORT6_OUT_P3_Msk (0x8UL) /*!< PORT6 OUT: P3 (Bitfield-Mask: 0x01) */ 15263 #define PORT6_OUT_P4_Pos (4UL) /*!< PORT6 OUT: P4 (Bit 4) */ 15264 #define PORT6_OUT_P4_Msk (0x10UL) /*!< PORT6 OUT: P4 (Bitfield-Mask: 0x01) */ 15265 #define PORT6_OUT_P5_Pos (5UL) /*!< PORT6 OUT: P5 (Bit 5) */ 15266 #define PORT6_OUT_P5_Msk (0x20UL) /*!< PORT6 OUT: P5 (Bitfield-Mask: 0x01) */ 15267 #define PORT6_OUT_P6_Pos (6UL) /*!< PORT6 OUT: P6 (Bit 6) */ 15268 #define PORT6_OUT_P6_Msk (0x40UL) /*!< PORT6 OUT: P6 (Bitfield-Mask: 0x01) */ 15269 #define PORT6_OUT_P7_Pos (7UL) /*!< PORT6 OUT: P7 (Bit 7) */ 15270 #define PORT6_OUT_P7_Msk (0x80UL) /*!< PORT6 OUT: P7 (Bitfield-Mask: 0x01) */ 15271 #define PORT6_OUT_P8_Pos (8UL) /*!< PORT6 OUT: P8 (Bit 8) */ 15272 #define PORT6_OUT_P8_Msk (0x100UL) /*!< PORT6 OUT: P8 (Bitfield-Mask: 0x01) */ 15273 #define PORT6_OUT_P9_Pos (9UL) /*!< PORT6 OUT: P9 (Bit 9) */ 15274 #define PORT6_OUT_P9_Msk (0x200UL) /*!< PORT6 OUT: P9 (Bitfield-Mask: 0x01) */ 15275 #define PORT6_OUT_P10_Pos (10UL) /*!< PORT6 OUT: P10 (Bit 10) */ 15276 #define PORT6_OUT_P10_Msk (0x400UL) /*!< PORT6 OUT: P10 (Bitfield-Mask: 0x01) */ 15277 #define PORT6_OUT_P11_Pos (11UL) /*!< PORT6 OUT: P11 (Bit 11) */ 15278 #define PORT6_OUT_P11_Msk (0x800UL) /*!< PORT6 OUT: P11 (Bitfield-Mask: 0x01) */ 15279 #define PORT6_OUT_P12_Pos (12UL) /*!< PORT6 OUT: P12 (Bit 12) */ 15280 #define PORT6_OUT_P12_Msk (0x1000UL) /*!< PORT6 OUT: P12 (Bitfield-Mask: 0x01) */ 15281 #define PORT6_OUT_P13_Pos (13UL) /*!< PORT6 OUT: P13 (Bit 13) */ 15282 #define PORT6_OUT_P13_Msk (0x2000UL) /*!< PORT6 OUT: P13 (Bitfield-Mask: 0x01) */ 15283 #define PORT6_OUT_P14_Pos (14UL) /*!< PORT6 OUT: P14 (Bit 14) */ 15284 #define PORT6_OUT_P14_Msk (0x4000UL) /*!< PORT6 OUT: P14 (Bitfield-Mask: 0x01) */ 15285 #define PORT6_OUT_P15_Pos (15UL) /*!< PORT6 OUT: P15 (Bit 15) */ 15286 #define PORT6_OUT_P15_Msk (0x8000UL) /*!< PORT6 OUT: P15 (Bitfield-Mask: 0x01) */ 15287 15288 /* ---------------------------------- PORT6_OMR --------------------------------- */ 15289 #define PORT6_OMR_PS0_Pos (0UL) /*!< PORT6 OMR: PS0 (Bit 0) */ 15290 #define PORT6_OMR_PS0_Msk (0x1UL) /*!< PORT6 OMR: PS0 (Bitfield-Mask: 0x01) */ 15291 #define PORT6_OMR_PS1_Pos (1UL) /*!< PORT6 OMR: PS1 (Bit 1) */ 15292 #define PORT6_OMR_PS1_Msk (0x2UL) /*!< PORT6 OMR: PS1 (Bitfield-Mask: 0x01) */ 15293 #define PORT6_OMR_PS2_Pos (2UL) /*!< PORT6 OMR: PS2 (Bit 2) */ 15294 #define PORT6_OMR_PS2_Msk (0x4UL) /*!< PORT6 OMR: PS2 (Bitfield-Mask: 0x01) */ 15295 #define PORT6_OMR_PS3_Pos (3UL) /*!< PORT6 OMR: PS3 (Bit 3) */ 15296 #define PORT6_OMR_PS3_Msk (0x8UL) /*!< PORT6 OMR: PS3 (Bitfield-Mask: 0x01) */ 15297 #define PORT6_OMR_PS4_Pos (4UL) /*!< PORT6 OMR: PS4 (Bit 4) */ 15298 #define PORT6_OMR_PS4_Msk (0x10UL) /*!< PORT6 OMR: PS4 (Bitfield-Mask: 0x01) */ 15299 #define PORT6_OMR_PS5_Pos (5UL) /*!< PORT6 OMR: PS5 (Bit 5) */ 15300 #define PORT6_OMR_PS5_Msk (0x20UL) /*!< PORT6 OMR: PS5 (Bitfield-Mask: 0x01) */ 15301 #define PORT6_OMR_PS6_Pos (6UL) /*!< PORT6 OMR: PS6 (Bit 6) */ 15302 #define PORT6_OMR_PS6_Msk (0x40UL) /*!< PORT6 OMR: PS6 (Bitfield-Mask: 0x01) */ 15303 #define PORT6_OMR_PS7_Pos (7UL) /*!< PORT6 OMR: PS7 (Bit 7) */ 15304 #define PORT6_OMR_PS7_Msk (0x80UL) /*!< PORT6 OMR: PS7 (Bitfield-Mask: 0x01) */ 15305 #define PORT6_OMR_PS8_Pos (8UL) /*!< PORT6 OMR: PS8 (Bit 8) */ 15306 #define PORT6_OMR_PS8_Msk (0x100UL) /*!< PORT6 OMR: PS8 (Bitfield-Mask: 0x01) */ 15307 #define PORT6_OMR_PS9_Pos (9UL) /*!< PORT6 OMR: PS9 (Bit 9) */ 15308 #define PORT6_OMR_PS9_Msk (0x200UL) /*!< PORT6 OMR: PS9 (Bitfield-Mask: 0x01) */ 15309 #define PORT6_OMR_PS10_Pos (10UL) /*!< PORT6 OMR: PS10 (Bit 10) */ 15310 #define PORT6_OMR_PS10_Msk (0x400UL) /*!< PORT6 OMR: PS10 (Bitfield-Mask: 0x01) */ 15311 #define PORT6_OMR_PS11_Pos (11UL) /*!< PORT6 OMR: PS11 (Bit 11) */ 15312 #define PORT6_OMR_PS11_Msk (0x800UL) /*!< PORT6 OMR: PS11 (Bitfield-Mask: 0x01) */ 15313 #define PORT6_OMR_PS12_Pos (12UL) /*!< PORT6 OMR: PS12 (Bit 12) */ 15314 #define PORT6_OMR_PS12_Msk (0x1000UL) /*!< PORT6 OMR: PS12 (Bitfield-Mask: 0x01) */ 15315 #define PORT6_OMR_PS13_Pos (13UL) /*!< PORT6 OMR: PS13 (Bit 13) */ 15316 #define PORT6_OMR_PS13_Msk (0x2000UL) /*!< PORT6 OMR: PS13 (Bitfield-Mask: 0x01) */ 15317 #define PORT6_OMR_PS14_Pos (14UL) /*!< PORT6 OMR: PS14 (Bit 14) */ 15318 #define PORT6_OMR_PS14_Msk (0x4000UL) /*!< PORT6 OMR: PS14 (Bitfield-Mask: 0x01) */ 15319 #define PORT6_OMR_PS15_Pos (15UL) /*!< PORT6 OMR: PS15 (Bit 15) */ 15320 #define PORT6_OMR_PS15_Msk (0x8000UL) /*!< PORT6 OMR: PS15 (Bitfield-Mask: 0x01) */ 15321 #define PORT6_OMR_PR0_Pos (16UL) /*!< PORT6 OMR: PR0 (Bit 16) */ 15322 #define PORT6_OMR_PR0_Msk (0x10000UL) /*!< PORT6 OMR: PR0 (Bitfield-Mask: 0x01) */ 15323 #define PORT6_OMR_PR1_Pos (17UL) /*!< PORT6 OMR: PR1 (Bit 17) */ 15324 #define PORT6_OMR_PR1_Msk (0x20000UL) /*!< PORT6 OMR: PR1 (Bitfield-Mask: 0x01) */ 15325 #define PORT6_OMR_PR2_Pos (18UL) /*!< PORT6 OMR: PR2 (Bit 18) */ 15326 #define PORT6_OMR_PR2_Msk (0x40000UL) /*!< PORT6 OMR: PR2 (Bitfield-Mask: 0x01) */ 15327 #define PORT6_OMR_PR3_Pos (19UL) /*!< PORT6 OMR: PR3 (Bit 19) */ 15328 #define PORT6_OMR_PR3_Msk (0x80000UL) /*!< PORT6 OMR: PR3 (Bitfield-Mask: 0x01) */ 15329 #define PORT6_OMR_PR4_Pos (20UL) /*!< PORT6 OMR: PR4 (Bit 20) */ 15330 #define PORT6_OMR_PR4_Msk (0x100000UL) /*!< PORT6 OMR: PR4 (Bitfield-Mask: 0x01) */ 15331 #define PORT6_OMR_PR5_Pos (21UL) /*!< PORT6 OMR: PR5 (Bit 21) */ 15332 #define PORT6_OMR_PR5_Msk (0x200000UL) /*!< PORT6 OMR: PR5 (Bitfield-Mask: 0x01) */ 15333 #define PORT6_OMR_PR6_Pos (22UL) /*!< PORT6 OMR: PR6 (Bit 22) */ 15334 #define PORT6_OMR_PR6_Msk (0x400000UL) /*!< PORT6 OMR: PR6 (Bitfield-Mask: 0x01) */ 15335 #define PORT6_OMR_PR7_Pos (23UL) /*!< PORT6 OMR: PR7 (Bit 23) */ 15336 #define PORT6_OMR_PR7_Msk (0x800000UL) /*!< PORT6 OMR: PR7 (Bitfield-Mask: 0x01) */ 15337 #define PORT6_OMR_PR8_Pos (24UL) /*!< PORT6 OMR: PR8 (Bit 24) */ 15338 #define PORT6_OMR_PR8_Msk (0x1000000UL) /*!< PORT6 OMR: PR8 (Bitfield-Mask: 0x01) */ 15339 #define PORT6_OMR_PR9_Pos (25UL) /*!< PORT6 OMR: PR9 (Bit 25) */ 15340 #define PORT6_OMR_PR9_Msk (0x2000000UL) /*!< PORT6 OMR: PR9 (Bitfield-Mask: 0x01) */ 15341 #define PORT6_OMR_PR10_Pos (26UL) /*!< PORT6 OMR: PR10 (Bit 26) */ 15342 #define PORT6_OMR_PR10_Msk (0x4000000UL) /*!< PORT6 OMR: PR10 (Bitfield-Mask: 0x01) */ 15343 #define PORT6_OMR_PR11_Pos (27UL) /*!< PORT6 OMR: PR11 (Bit 27) */ 15344 #define PORT6_OMR_PR11_Msk (0x8000000UL) /*!< PORT6 OMR: PR11 (Bitfield-Mask: 0x01) */ 15345 #define PORT6_OMR_PR12_Pos (28UL) /*!< PORT6 OMR: PR12 (Bit 28) */ 15346 #define PORT6_OMR_PR12_Msk (0x10000000UL) /*!< PORT6 OMR: PR12 (Bitfield-Mask: 0x01) */ 15347 #define PORT6_OMR_PR13_Pos (29UL) /*!< PORT6 OMR: PR13 (Bit 29) */ 15348 #define PORT6_OMR_PR13_Msk (0x20000000UL) /*!< PORT6 OMR: PR13 (Bitfield-Mask: 0x01) */ 15349 #define PORT6_OMR_PR14_Pos (30UL) /*!< PORT6 OMR: PR14 (Bit 30) */ 15350 #define PORT6_OMR_PR14_Msk (0x40000000UL) /*!< PORT6 OMR: PR14 (Bitfield-Mask: 0x01) */ 15351 #define PORT6_OMR_PR15_Pos (31UL) /*!< PORT6 OMR: PR15 (Bit 31) */ 15352 #define PORT6_OMR_PR15_Msk (0x80000000UL) /*!< PORT6 OMR: PR15 (Bitfield-Mask: 0x01) */ 15353 15354 /* --------------------------------- PORT6_IOCR0 -------------------------------- */ 15355 #define PORT6_IOCR0_PC0_Pos (3UL) /*!< PORT6 IOCR0: PC0 (Bit 3) */ 15356 #define PORT6_IOCR0_PC0_Msk (0xf8UL) /*!< PORT6 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 15357 #define PORT6_IOCR0_PC1_Pos (11UL) /*!< PORT6 IOCR0: PC1 (Bit 11) */ 15358 #define PORT6_IOCR0_PC1_Msk (0xf800UL) /*!< PORT6 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 15359 #define PORT6_IOCR0_PC2_Pos (19UL) /*!< PORT6 IOCR0: PC2 (Bit 19) */ 15360 #define PORT6_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT6 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 15361 #define PORT6_IOCR0_PC3_Pos (27UL) /*!< PORT6 IOCR0: PC3 (Bit 27) */ 15362 #define PORT6_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT6 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 15363 15364 /* --------------------------------- PORT6_IOCR4 -------------------------------- */ 15365 #define PORT6_IOCR4_PC4_Pos (3UL) /*!< PORT6 IOCR4: PC4 (Bit 3) */ 15366 #define PORT6_IOCR4_PC4_Msk (0xf8UL) /*!< PORT6 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 15367 #define PORT6_IOCR4_PC5_Pos (11UL) /*!< PORT6 IOCR4: PC5 (Bit 11) */ 15368 #define PORT6_IOCR4_PC5_Msk (0xf800UL) /*!< PORT6 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 15369 #define PORT6_IOCR4_PC6_Pos (19UL) /*!< PORT6 IOCR4: PC6 (Bit 19) */ 15370 #define PORT6_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT6 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 15371 #define PORT6_IOCR4_PC7_Pos (27UL) /*!< PORT6 IOCR4: PC7 (Bit 27) */ 15372 #define PORT6_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT6 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 15373 15374 /* ---------------------------------- PORT6_IN ---------------------------------- */ 15375 #define PORT6_IN_P0_Pos (0UL) /*!< PORT6 IN: P0 (Bit 0) */ 15376 #define PORT6_IN_P0_Msk (0x1UL) /*!< PORT6 IN: P0 (Bitfield-Mask: 0x01) */ 15377 #define PORT6_IN_P1_Pos (1UL) /*!< PORT6 IN: P1 (Bit 1) */ 15378 #define PORT6_IN_P1_Msk (0x2UL) /*!< PORT6 IN: P1 (Bitfield-Mask: 0x01) */ 15379 #define PORT6_IN_P2_Pos (2UL) /*!< PORT6 IN: P2 (Bit 2) */ 15380 #define PORT6_IN_P2_Msk (0x4UL) /*!< PORT6 IN: P2 (Bitfield-Mask: 0x01) */ 15381 #define PORT6_IN_P3_Pos (3UL) /*!< PORT6 IN: P3 (Bit 3) */ 15382 #define PORT6_IN_P3_Msk (0x8UL) /*!< PORT6 IN: P3 (Bitfield-Mask: 0x01) */ 15383 #define PORT6_IN_P4_Pos (4UL) /*!< PORT6 IN: P4 (Bit 4) */ 15384 #define PORT6_IN_P4_Msk (0x10UL) /*!< PORT6 IN: P4 (Bitfield-Mask: 0x01) */ 15385 #define PORT6_IN_P5_Pos (5UL) /*!< PORT6 IN: P5 (Bit 5) */ 15386 #define PORT6_IN_P5_Msk (0x20UL) /*!< PORT6 IN: P5 (Bitfield-Mask: 0x01) */ 15387 #define PORT6_IN_P6_Pos (6UL) /*!< PORT6 IN: P6 (Bit 6) */ 15388 #define PORT6_IN_P6_Msk (0x40UL) /*!< PORT6 IN: P6 (Bitfield-Mask: 0x01) */ 15389 #define PORT6_IN_P7_Pos (7UL) /*!< PORT6 IN: P7 (Bit 7) */ 15390 #define PORT6_IN_P7_Msk (0x80UL) /*!< PORT6 IN: P7 (Bitfield-Mask: 0x01) */ 15391 #define PORT6_IN_P8_Pos (8UL) /*!< PORT6 IN: P8 (Bit 8) */ 15392 #define PORT6_IN_P8_Msk (0x100UL) /*!< PORT6 IN: P8 (Bitfield-Mask: 0x01) */ 15393 #define PORT6_IN_P9_Pos (9UL) /*!< PORT6 IN: P9 (Bit 9) */ 15394 #define PORT6_IN_P9_Msk (0x200UL) /*!< PORT6 IN: P9 (Bitfield-Mask: 0x01) */ 15395 #define PORT6_IN_P10_Pos (10UL) /*!< PORT6 IN: P10 (Bit 10) */ 15396 #define PORT6_IN_P10_Msk (0x400UL) /*!< PORT6 IN: P10 (Bitfield-Mask: 0x01) */ 15397 #define PORT6_IN_P11_Pos (11UL) /*!< PORT6 IN: P11 (Bit 11) */ 15398 #define PORT6_IN_P11_Msk (0x800UL) /*!< PORT6 IN: P11 (Bitfield-Mask: 0x01) */ 15399 #define PORT6_IN_P12_Pos (12UL) /*!< PORT6 IN: P12 (Bit 12) */ 15400 #define PORT6_IN_P12_Msk (0x1000UL) /*!< PORT6 IN: P12 (Bitfield-Mask: 0x01) */ 15401 #define PORT6_IN_P13_Pos (13UL) /*!< PORT6 IN: P13 (Bit 13) */ 15402 #define PORT6_IN_P13_Msk (0x2000UL) /*!< PORT6 IN: P13 (Bitfield-Mask: 0x01) */ 15403 #define PORT6_IN_P14_Pos (14UL) /*!< PORT6 IN: P14 (Bit 14) */ 15404 #define PORT6_IN_P14_Msk (0x4000UL) /*!< PORT6 IN: P14 (Bitfield-Mask: 0x01) */ 15405 #define PORT6_IN_P15_Pos (15UL) /*!< PORT6 IN: P15 (Bit 15) */ 15406 #define PORT6_IN_P15_Msk (0x8000UL) /*!< PORT6 IN: P15 (Bitfield-Mask: 0x01) */ 15407 15408 /* --------------------------------- PORT6_PDR0 --------------------------------- */ 15409 #define PORT6_PDR0_PD0_Pos (0UL) /*!< PORT6 PDR0: PD0 (Bit 0) */ 15410 #define PORT6_PDR0_PD0_Msk (0x7UL) /*!< PORT6 PDR0: PD0 (Bitfield-Mask: 0x07) */ 15411 #define PORT6_PDR0_PD1_Pos (4UL) /*!< PORT6 PDR0: PD1 (Bit 4) */ 15412 #define PORT6_PDR0_PD1_Msk (0x70UL) /*!< PORT6 PDR0: PD1 (Bitfield-Mask: 0x07) */ 15413 #define PORT6_PDR0_PD2_Pos (8UL) /*!< PORT6 PDR0: PD2 (Bit 8) */ 15414 #define PORT6_PDR0_PD2_Msk (0x700UL) /*!< PORT6 PDR0: PD2 (Bitfield-Mask: 0x07) */ 15415 #define PORT6_PDR0_PD3_Pos (12UL) /*!< PORT6 PDR0: PD3 (Bit 12) */ 15416 #define PORT6_PDR0_PD3_Msk (0x7000UL) /*!< PORT6 PDR0: PD3 (Bitfield-Mask: 0x07) */ 15417 #define PORT6_PDR0_PD4_Pos (16UL) /*!< PORT6 PDR0: PD4 (Bit 16) */ 15418 #define PORT6_PDR0_PD4_Msk (0x70000UL) /*!< PORT6 PDR0: PD4 (Bitfield-Mask: 0x07) */ 15419 #define PORT6_PDR0_PD5_Pos (20UL) /*!< PORT6 PDR0: PD5 (Bit 20) */ 15420 #define PORT6_PDR0_PD5_Msk (0x700000UL) /*!< PORT6 PDR0: PD5 (Bitfield-Mask: 0x07) */ 15421 #define PORT6_PDR0_PD6_Pos (24UL) /*!< PORT6 PDR0: PD6 (Bit 24) */ 15422 #define PORT6_PDR0_PD6_Msk (0x7000000UL) /*!< PORT6 PDR0: PD6 (Bitfield-Mask: 0x07) */ 15423 #define PORT6_PDR0_PD7_Pos (28UL) /*!< PORT6 PDR0: PD7 (Bit 28) */ 15424 #define PORT6_PDR0_PD7_Msk (0x70000000UL) /*!< PORT6 PDR0: PD7 (Bitfield-Mask: 0x07) */ 15425 15426 /* --------------------------------- PORT6_PDISC -------------------------------- */ 15427 #define PORT6_PDISC_PDIS0_Pos (0UL) /*!< PORT6 PDISC: PDIS0 (Bit 0) */ 15428 #define PORT6_PDISC_PDIS0_Msk (0x1UL) /*!< PORT6 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ 15429 #define PORT6_PDISC_PDIS1_Pos (1UL) /*!< PORT6 PDISC: PDIS1 (Bit 1) */ 15430 #define PORT6_PDISC_PDIS1_Msk (0x2UL) /*!< PORT6 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ 15431 #define PORT6_PDISC_PDIS2_Pos (2UL) /*!< PORT6 PDISC: PDIS2 (Bit 2) */ 15432 #define PORT6_PDISC_PDIS2_Msk (0x4UL) /*!< PORT6 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 15433 #define PORT6_PDISC_PDIS3_Pos (3UL) /*!< PORT6 PDISC: PDIS3 (Bit 3) */ 15434 #define PORT6_PDISC_PDIS3_Msk (0x8UL) /*!< PORT6 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 15435 #define PORT6_PDISC_PDIS4_Pos (4UL) /*!< PORT6 PDISC: PDIS4 (Bit 4) */ 15436 #define PORT6_PDISC_PDIS4_Msk (0x10UL) /*!< PORT6 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 15437 #define PORT6_PDISC_PDIS5_Pos (5UL) /*!< PORT6 PDISC: PDIS5 (Bit 5) */ 15438 #define PORT6_PDISC_PDIS5_Msk (0x20UL) /*!< PORT6 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 15439 #define PORT6_PDISC_PDIS6_Pos (6UL) /*!< PORT6 PDISC: PDIS6 (Bit 6) */ 15440 #define PORT6_PDISC_PDIS6_Msk (0x40UL) /*!< PORT6 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 15441 #define PORT6_PDISC_PDIS7_Pos (7UL) /*!< PORT6 PDISC: PDIS7 (Bit 7) */ 15442 #define PORT6_PDISC_PDIS7_Msk (0x80UL) /*!< PORT6 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 15443 #define PORT6_PDISC_PDIS8_Pos (8UL) /*!< PORT6 PDISC: PDIS8 (Bit 8) */ 15444 #define PORT6_PDISC_PDIS8_Msk (0x100UL) /*!< PORT6 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 15445 #define PORT6_PDISC_PDIS9_Pos (9UL) /*!< PORT6 PDISC: PDIS9 (Bit 9) */ 15446 #define PORT6_PDISC_PDIS9_Msk (0x200UL) /*!< PORT6 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 15447 #define PORT6_PDISC_PDIS10_Pos (10UL) /*!< PORT6 PDISC: PDIS10 (Bit 10) */ 15448 #define PORT6_PDISC_PDIS10_Msk (0x400UL) /*!< PORT6 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ 15449 #define PORT6_PDISC_PDIS11_Pos (11UL) /*!< PORT6 PDISC: PDIS11 (Bit 11) */ 15450 #define PORT6_PDISC_PDIS11_Msk (0x800UL) /*!< PORT6 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ 15451 #define PORT6_PDISC_PDIS12_Pos (12UL) /*!< PORT6 PDISC: PDIS12 (Bit 12) */ 15452 #define PORT6_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT6 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 15453 #define PORT6_PDISC_PDIS13_Pos (13UL) /*!< PORT6 PDISC: PDIS13 (Bit 13) */ 15454 #define PORT6_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT6 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 15455 #define PORT6_PDISC_PDIS14_Pos (14UL) /*!< PORT6 PDISC: PDIS14 (Bit 14) */ 15456 #define PORT6_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT6 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 15457 #define PORT6_PDISC_PDIS15_Pos (15UL) /*!< PORT6 PDISC: PDIS15 (Bit 15) */ 15458 #define PORT6_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT6 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 15459 15460 /* ---------------------------------- PORT6_PPS --------------------------------- */ 15461 #define PORT6_PPS_PPS0_Pos (0UL) /*!< PORT6 PPS: PPS0 (Bit 0) */ 15462 #define PORT6_PPS_PPS0_Msk (0x1UL) /*!< PORT6 PPS: PPS0 (Bitfield-Mask: 0x01) */ 15463 #define PORT6_PPS_PPS1_Pos (1UL) /*!< PORT6 PPS: PPS1 (Bit 1) */ 15464 #define PORT6_PPS_PPS1_Msk (0x2UL) /*!< PORT6 PPS: PPS1 (Bitfield-Mask: 0x01) */ 15465 #define PORT6_PPS_PPS2_Pos (2UL) /*!< PORT6 PPS: PPS2 (Bit 2) */ 15466 #define PORT6_PPS_PPS2_Msk (0x4UL) /*!< PORT6 PPS: PPS2 (Bitfield-Mask: 0x01) */ 15467 #define PORT6_PPS_PPS3_Pos (3UL) /*!< PORT6 PPS: PPS3 (Bit 3) */ 15468 #define PORT6_PPS_PPS3_Msk (0x8UL) /*!< PORT6 PPS: PPS3 (Bitfield-Mask: 0x01) */ 15469 #define PORT6_PPS_PPS4_Pos (4UL) /*!< PORT6 PPS: PPS4 (Bit 4) */ 15470 #define PORT6_PPS_PPS4_Msk (0x10UL) /*!< PORT6 PPS: PPS4 (Bitfield-Mask: 0x01) */ 15471 #define PORT6_PPS_PPS5_Pos (5UL) /*!< PORT6 PPS: PPS5 (Bit 5) */ 15472 #define PORT6_PPS_PPS5_Msk (0x20UL) /*!< PORT6 PPS: PPS5 (Bitfield-Mask: 0x01) */ 15473 #define PORT6_PPS_PPS6_Pos (6UL) /*!< PORT6 PPS: PPS6 (Bit 6) */ 15474 #define PORT6_PPS_PPS6_Msk (0x40UL) /*!< PORT6 PPS: PPS6 (Bitfield-Mask: 0x01) */ 15475 #define PORT6_PPS_PPS7_Pos (7UL) /*!< PORT6 PPS: PPS7 (Bit 7) */ 15476 #define PORT6_PPS_PPS7_Msk (0x80UL) /*!< PORT6 PPS: PPS7 (Bitfield-Mask: 0x01) */ 15477 #define PORT6_PPS_PPS8_Pos (8UL) /*!< PORT6 PPS: PPS8 (Bit 8) */ 15478 #define PORT6_PPS_PPS8_Msk (0x100UL) /*!< PORT6 PPS: PPS8 (Bitfield-Mask: 0x01) */ 15479 #define PORT6_PPS_PPS9_Pos (9UL) /*!< PORT6 PPS: PPS9 (Bit 9) */ 15480 #define PORT6_PPS_PPS9_Msk (0x200UL) /*!< PORT6 PPS: PPS9 (Bitfield-Mask: 0x01) */ 15481 #define PORT6_PPS_PPS10_Pos (10UL) /*!< PORT6 PPS: PPS10 (Bit 10) */ 15482 #define PORT6_PPS_PPS10_Msk (0x400UL) /*!< PORT6 PPS: PPS10 (Bitfield-Mask: 0x01) */ 15483 #define PORT6_PPS_PPS11_Pos (11UL) /*!< PORT6 PPS: PPS11 (Bit 11) */ 15484 #define PORT6_PPS_PPS11_Msk (0x800UL) /*!< PORT6 PPS: PPS11 (Bitfield-Mask: 0x01) */ 15485 #define PORT6_PPS_PPS12_Pos (12UL) /*!< PORT6 PPS: PPS12 (Bit 12) */ 15486 #define PORT6_PPS_PPS12_Msk (0x1000UL) /*!< PORT6 PPS: PPS12 (Bitfield-Mask: 0x01) */ 15487 #define PORT6_PPS_PPS13_Pos (13UL) /*!< PORT6 PPS: PPS13 (Bit 13) */ 15488 #define PORT6_PPS_PPS13_Msk (0x2000UL) /*!< PORT6 PPS: PPS13 (Bitfield-Mask: 0x01) */ 15489 #define PORT6_PPS_PPS14_Pos (14UL) /*!< PORT6 PPS: PPS14 (Bit 14) */ 15490 #define PORT6_PPS_PPS14_Msk (0x4000UL) /*!< PORT6 PPS: PPS14 (Bitfield-Mask: 0x01) */ 15491 #define PORT6_PPS_PPS15_Pos (15UL) /*!< PORT6 PPS: PPS15 (Bit 15) */ 15492 #define PORT6_PPS_PPS15_Msk (0x8000UL) /*!< PORT6 PPS: PPS15 (Bitfield-Mask: 0x01) */ 15493 15494 /* --------------------------------- PORT6_HWSEL -------------------------------- */ 15495 #define PORT6_HWSEL_HW0_Pos (0UL) /*!< PORT6 HWSEL: HW0 (Bit 0) */ 15496 #define PORT6_HWSEL_HW0_Msk (0x3UL) /*!< PORT6 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 15497 #define PORT6_HWSEL_HW1_Pos (2UL) /*!< PORT6 HWSEL: HW1 (Bit 2) */ 15498 #define PORT6_HWSEL_HW1_Msk (0xcUL) /*!< PORT6 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 15499 #define PORT6_HWSEL_HW2_Pos (4UL) /*!< PORT6 HWSEL: HW2 (Bit 4) */ 15500 #define PORT6_HWSEL_HW2_Msk (0x30UL) /*!< PORT6 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 15501 #define PORT6_HWSEL_HW3_Pos (6UL) /*!< PORT6 HWSEL: HW3 (Bit 6) */ 15502 #define PORT6_HWSEL_HW3_Msk (0xc0UL) /*!< PORT6 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 15503 #define PORT6_HWSEL_HW4_Pos (8UL) /*!< PORT6 HWSEL: HW4 (Bit 8) */ 15504 #define PORT6_HWSEL_HW4_Msk (0x300UL) /*!< PORT6 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 15505 #define PORT6_HWSEL_HW5_Pos (10UL) /*!< PORT6 HWSEL: HW5 (Bit 10) */ 15506 #define PORT6_HWSEL_HW5_Msk (0xc00UL) /*!< PORT6 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 15507 #define PORT6_HWSEL_HW6_Pos (12UL) /*!< PORT6 HWSEL: HW6 (Bit 12) */ 15508 #define PORT6_HWSEL_HW6_Msk (0x3000UL) /*!< PORT6 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 15509 #define PORT6_HWSEL_HW7_Pos (14UL) /*!< PORT6 HWSEL: HW7 (Bit 14) */ 15510 #define PORT6_HWSEL_HW7_Msk (0xc000UL) /*!< PORT6 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 15511 #define PORT6_HWSEL_HW8_Pos (16UL) /*!< PORT6 HWSEL: HW8 (Bit 16) */ 15512 #define PORT6_HWSEL_HW8_Msk (0x30000UL) /*!< PORT6 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 15513 #define PORT6_HWSEL_HW9_Pos (18UL) /*!< PORT6 HWSEL: HW9 (Bit 18) */ 15514 #define PORT6_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT6 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 15515 #define PORT6_HWSEL_HW10_Pos (20UL) /*!< PORT6 HWSEL: HW10 (Bit 20) */ 15516 #define PORT6_HWSEL_HW10_Msk (0x300000UL) /*!< PORT6 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 15517 #define PORT6_HWSEL_HW11_Pos (22UL) /*!< PORT6 HWSEL: HW11 (Bit 22) */ 15518 #define PORT6_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT6 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 15519 #define PORT6_HWSEL_HW12_Pos (24UL) /*!< PORT6 HWSEL: HW12 (Bit 24) */ 15520 #define PORT6_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT6 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 15521 #define PORT6_HWSEL_HW13_Pos (26UL) /*!< PORT6 HWSEL: HW13 (Bit 26) */ 15522 #define PORT6_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT6 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 15523 #define PORT6_HWSEL_HW14_Pos (28UL) /*!< PORT6 HWSEL: HW14 (Bit 28) */ 15524 #define PORT6_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT6 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 15525 #define PORT6_HWSEL_HW15_Pos (30UL) /*!< PORT6 HWSEL: HW15 (Bit 30) */ 15526 #define PORT6_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT6 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 15527 15528 15529 /* ================================================================================ */ 15530 /* ================ struct 'PORT14' Position & Mask ================ */ 15531 /* ================================================================================ */ 15532 15533 15534 /* --------------------------------- PORT14_OUT --------------------------------- */ 15535 #define PORT14_OUT_P0_Pos (0UL) /*!< PORT14 OUT: P0 (Bit 0) */ 15536 #define PORT14_OUT_P0_Msk (0x1UL) /*!< PORT14 OUT: P0 (Bitfield-Mask: 0x01) */ 15537 #define PORT14_OUT_P1_Pos (1UL) /*!< PORT14 OUT: P1 (Bit 1) */ 15538 #define PORT14_OUT_P1_Msk (0x2UL) /*!< PORT14 OUT: P1 (Bitfield-Mask: 0x01) */ 15539 #define PORT14_OUT_P2_Pos (2UL) /*!< PORT14 OUT: P2 (Bit 2) */ 15540 #define PORT14_OUT_P2_Msk (0x4UL) /*!< PORT14 OUT: P2 (Bitfield-Mask: 0x01) */ 15541 #define PORT14_OUT_P3_Pos (3UL) /*!< PORT14 OUT: P3 (Bit 3) */ 15542 #define PORT14_OUT_P3_Msk (0x8UL) /*!< PORT14 OUT: P3 (Bitfield-Mask: 0x01) */ 15543 #define PORT14_OUT_P4_Pos (4UL) /*!< PORT14 OUT: P4 (Bit 4) */ 15544 #define PORT14_OUT_P4_Msk (0x10UL) /*!< PORT14 OUT: P4 (Bitfield-Mask: 0x01) */ 15545 #define PORT14_OUT_P5_Pos (5UL) /*!< PORT14 OUT: P5 (Bit 5) */ 15546 #define PORT14_OUT_P5_Msk (0x20UL) /*!< PORT14 OUT: P5 (Bitfield-Mask: 0x01) */ 15547 #define PORT14_OUT_P6_Pos (6UL) /*!< PORT14 OUT: P6 (Bit 6) */ 15548 #define PORT14_OUT_P6_Msk (0x40UL) /*!< PORT14 OUT: P6 (Bitfield-Mask: 0x01) */ 15549 #define PORT14_OUT_P7_Pos (7UL) /*!< PORT14 OUT: P7 (Bit 7) */ 15550 #define PORT14_OUT_P7_Msk (0x80UL) /*!< PORT14 OUT: P7 (Bitfield-Mask: 0x01) */ 15551 #define PORT14_OUT_P8_Pos (8UL) /*!< PORT14 OUT: P8 (Bit 8) */ 15552 #define PORT14_OUT_P8_Msk (0x100UL) /*!< PORT14 OUT: P8 (Bitfield-Mask: 0x01) */ 15553 #define PORT14_OUT_P9_Pos (9UL) /*!< PORT14 OUT: P9 (Bit 9) */ 15554 #define PORT14_OUT_P9_Msk (0x200UL) /*!< PORT14 OUT: P9 (Bitfield-Mask: 0x01) */ 15555 #define PORT14_OUT_P10_Pos (10UL) /*!< PORT14 OUT: P10 (Bit 10) */ 15556 #define PORT14_OUT_P10_Msk (0x400UL) /*!< PORT14 OUT: P10 (Bitfield-Mask: 0x01) */ 15557 #define PORT14_OUT_P11_Pos (11UL) /*!< PORT14 OUT: P11 (Bit 11) */ 15558 #define PORT14_OUT_P11_Msk (0x800UL) /*!< PORT14 OUT: P11 (Bitfield-Mask: 0x01) */ 15559 #define PORT14_OUT_P12_Pos (12UL) /*!< PORT14 OUT: P12 (Bit 12) */ 15560 #define PORT14_OUT_P12_Msk (0x1000UL) /*!< PORT14 OUT: P12 (Bitfield-Mask: 0x01) */ 15561 #define PORT14_OUT_P13_Pos (13UL) /*!< PORT14 OUT: P13 (Bit 13) */ 15562 #define PORT14_OUT_P13_Msk (0x2000UL) /*!< PORT14 OUT: P13 (Bitfield-Mask: 0x01) */ 15563 #define PORT14_OUT_P14_Pos (14UL) /*!< PORT14 OUT: P14 (Bit 14) */ 15564 #define PORT14_OUT_P14_Msk (0x4000UL) /*!< PORT14 OUT: P14 (Bitfield-Mask: 0x01) */ 15565 #define PORT14_OUT_P15_Pos (15UL) /*!< PORT14 OUT: P15 (Bit 15) */ 15566 #define PORT14_OUT_P15_Msk (0x8000UL) /*!< PORT14 OUT: P15 (Bitfield-Mask: 0x01) */ 15567 15568 /* --------------------------------- PORT14_OMR --------------------------------- */ 15569 #define PORT14_OMR_PS0_Pos (0UL) /*!< PORT14 OMR: PS0 (Bit 0) */ 15570 #define PORT14_OMR_PS0_Msk (0x1UL) /*!< PORT14 OMR: PS0 (Bitfield-Mask: 0x01) */ 15571 #define PORT14_OMR_PS1_Pos (1UL) /*!< PORT14 OMR: PS1 (Bit 1) */ 15572 #define PORT14_OMR_PS1_Msk (0x2UL) /*!< PORT14 OMR: PS1 (Bitfield-Mask: 0x01) */ 15573 #define PORT14_OMR_PS2_Pos (2UL) /*!< PORT14 OMR: PS2 (Bit 2) */ 15574 #define PORT14_OMR_PS2_Msk (0x4UL) /*!< PORT14 OMR: PS2 (Bitfield-Mask: 0x01) */ 15575 #define PORT14_OMR_PS3_Pos (3UL) /*!< PORT14 OMR: PS3 (Bit 3) */ 15576 #define PORT14_OMR_PS3_Msk (0x8UL) /*!< PORT14 OMR: PS3 (Bitfield-Mask: 0x01) */ 15577 #define PORT14_OMR_PS4_Pos (4UL) /*!< PORT14 OMR: PS4 (Bit 4) */ 15578 #define PORT14_OMR_PS4_Msk (0x10UL) /*!< PORT14 OMR: PS4 (Bitfield-Mask: 0x01) */ 15579 #define PORT14_OMR_PS5_Pos (5UL) /*!< PORT14 OMR: PS5 (Bit 5) */ 15580 #define PORT14_OMR_PS5_Msk (0x20UL) /*!< PORT14 OMR: PS5 (Bitfield-Mask: 0x01) */ 15581 #define PORT14_OMR_PS6_Pos (6UL) /*!< PORT14 OMR: PS6 (Bit 6) */ 15582 #define PORT14_OMR_PS6_Msk (0x40UL) /*!< PORT14 OMR: PS6 (Bitfield-Mask: 0x01) */ 15583 #define PORT14_OMR_PS7_Pos (7UL) /*!< PORT14 OMR: PS7 (Bit 7) */ 15584 #define PORT14_OMR_PS7_Msk (0x80UL) /*!< PORT14 OMR: PS7 (Bitfield-Mask: 0x01) */ 15585 #define PORT14_OMR_PS8_Pos (8UL) /*!< PORT14 OMR: PS8 (Bit 8) */ 15586 #define PORT14_OMR_PS8_Msk (0x100UL) /*!< PORT14 OMR: PS8 (Bitfield-Mask: 0x01) */ 15587 #define PORT14_OMR_PS9_Pos (9UL) /*!< PORT14 OMR: PS9 (Bit 9) */ 15588 #define PORT14_OMR_PS9_Msk (0x200UL) /*!< PORT14 OMR: PS9 (Bitfield-Mask: 0x01) */ 15589 #define PORT14_OMR_PS10_Pos (10UL) /*!< PORT14 OMR: PS10 (Bit 10) */ 15590 #define PORT14_OMR_PS10_Msk (0x400UL) /*!< PORT14 OMR: PS10 (Bitfield-Mask: 0x01) */ 15591 #define PORT14_OMR_PS11_Pos (11UL) /*!< PORT14 OMR: PS11 (Bit 11) */ 15592 #define PORT14_OMR_PS11_Msk (0x800UL) /*!< PORT14 OMR: PS11 (Bitfield-Mask: 0x01) */ 15593 #define PORT14_OMR_PS12_Pos (12UL) /*!< PORT14 OMR: PS12 (Bit 12) */ 15594 #define PORT14_OMR_PS12_Msk (0x1000UL) /*!< PORT14 OMR: PS12 (Bitfield-Mask: 0x01) */ 15595 #define PORT14_OMR_PS13_Pos (13UL) /*!< PORT14 OMR: PS13 (Bit 13) */ 15596 #define PORT14_OMR_PS13_Msk (0x2000UL) /*!< PORT14 OMR: PS13 (Bitfield-Mask: 0x01) */ 15597 #define PORT14_OMR_PS14_Pos (14UL) /*!< PORT14 OMR: PS14 (Bit 14) */ 15598 #define PORT14_OMR_PS14_Msk (0x4000UL) /*!< PORT14 OMR: PS14 (Bitfield-Mask: 0x01) */ 15599 #define PORT14_OMR_PS15_Pos (15UL) /*!< PORT14 OMR: PS15 (Bit 15) */ 15600 #define PORT14_OMR_PS15_Msk (0x8000UL) /*!< PORT14 OMR: PS15 (Bitfield-Mask: 0x01) */ 15601 #define PORT14_OMR_PR0_Pos (16UL) /*!< PORT14 OMR: PR0 (Bit 16) */ 15602 #define PORT14_OMR_PR0_Msk (0x10000UL) /*!< PORT14 OMR: PR0 (Bitfield-Mask: 0x01) */ 15603 #define PORT14_OMR_PR1_Pos (17UL) /*!< PORT14 OMR: PR1 (Bit 17) */ 15604 #define PORT14_OMR_PR1_Msk (0x20000UL) /*!< PORT14 OMR: PR1 (Bitfield-Mask: 0x01) */ 15605 #define PORT14_OMR_PR2_Pos (18UL) /*!< PORT14 OMR: PR2 (Bit 18) */ 15606 #define PORT14_OMR_PR2_Msk (0x40000UL) /*!< PORT14 OMR: PR2 (Bitfield-Mask: 0x01) */ 15607 #define PORT14_OMR_PR3_Pos (19UL) /*!< PORT14 OMR: PR3 (Bit 19) */ 15608 #define PORT14_OMR_PR3_Msk (0x80000UL) /*!< PORT14 OMR: PR3 (Bitfield-Mask: 0x01) */ 15609 #define PORT14_OMR_PR4_Pos (20UL) /*!< PORT14 OMR: PR4 (Bit 20) */ 15610 #define PORT14_OMR_PR4_Msk (0x100000UL) /*!< PORT14 OMR: PR4 (Bitfield-Mask: 0x01) */ 15611 #define PORT14_OMR_PR5_Pos (21UL) /*!< PORT14 OMR: PR5 (Bit 21) */ 15612 #define PORT14_OMR_PR5_Msk (0x200000UL) /*!< PORT14 OMR: PR5 (Bitfield-Mask: 0x01) */ 15613 #define PORT14_OMR_PR6_Pos (22UL) /*!< PORT14 OMR: PR6 (Bit 22) */ 15614 #define PORT14_OMR_PR6_Msk (0x400000UL) /*!< PORT14 OMR: PR6 (Bitfield-Mask: 0x01) */ 15615 #define PORT14_OMR_PR7_Pos (23UL) /*!< PORT14 OMR: PR7 (Bit 23) */ 15616 #define PORT14_OMR_PR7_Msk (0x800000UL) /*!< PORT14 OMR: PR7 (Bitfield-Mask: 0x01) */ 15617 #define PORT14_OMR_PR8_Pos (24UL) /*!< PORT14 OMR: PR8 (Bit 24) */ 15618 #define PORT14_OMR_PR8_Msk (0x1000000UL) /*!< PORT14 OMR: PR8 (Bitfield-Mask: 0x01) */ 15619 #define PORT14_OMR_PR9_Pos (25UL) /*!< PORT14 OMR: PR9 (Bit 25) */ 15620 #define PORT14_OMR_PR9_Msk (0x2000000UL) /*!< PORT14 OMR: PR9 (Bitfield-Mask: 0x01) */ 15621 #define PORT14_OMR_PR10_Pos (26UL) /*!< PORT14 OMR: PR10 (Bit 26) */ 15622 #define PORT14_OMR_PR10_Msk (0x4000000UL) /*!< PORT14 OMR: PR10 (Bitfield-Mask: 0x01) */ 15623 #define PORT14_OMR_PR11_Pos (27UL) /*!< PORT14 OMR: PR11 (Bit 27) */ 15624 #define PORT14_OMR_PR11_Msk (0x8000000UL) /*!< PORT14 OMR: PR11 (Bitfield-Mask: 0x01) */ 15625 #define PORT14_OMR_PR12_Pos (28UL) /*!< PORT14 OMR: PR12 (Bit 28) */ 15626 #define PORT14_OMR_PR12_Msk (0x10000000UL) /*!< PORT14 OMR: PR12 (Bitfield-Mask: 0x01) */ 15627 #define PORT14_OMR_PR13_Pos (29UL) /*!< PORT14 OMR: PR13 (Bit 29) */ 15628 #define PORT14_OMR_PR13_Msk (0x20000000UL) /*!< PORT14 OMR: PR13 (Bitfield-Mask: 0x01) */ 15629 #define PORT14_OMR_PR14_Pos (30UL) /*!< PORT14 OMR: PR14 (Bit 30) */ 15630 #define PORT14_OMR_PR14_Msk (0x40000000UL) /*!< PORT14 OMR: PR14 (Bitfield-Mask: 0x01) */ 15631 #define PORT14_OMR_PR15_Pos (31UL) /*!< PORT14 OMR: PR15 (Bit 31) */ 15632 #define PORT14_OMR_PR15_Msk (0x80000000UL) /*!< PORT14 OMR: PR15 (Bitfield-Mask: 0x01) */ 15633 15634 /* -------------------------------- PORT14_IOCR0 -------------------------------- */ 15635 #define PORT14_IOCR0_PC0_Pos (3UL) /*!< PORT14 IOCR0: PC0 (Bit 3) */ 15636 #define PORT14_IOCR0_PC0_Msk (0xf8UL) /*!< PORT14 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 15637 #define PORT14_IOCR0_PC1_Pos (11UL) /*!< PORT14 IOCR0: PC1 (Bit 11) */ 15638 #define PORT14_IOCR0_PC1_Msk (0xf800UL) /*!< PORT14 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 15639 #define PORT14_IOCR0_PC2_Pos (19UL) /*!< PORT14 IOCR0: PC2 (Bit 19) */ 15640 #define PORT14_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT14 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 15641 #define PORT14_IOCR0_PC3_Pos (27UL) /*!< PORT14 IOCR0: PC3 (Bit 27) */ 15642 #define PORT14_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT14 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 15643 15644 /* -------------------------------- PORT14_IOCR4 -------------------------------- */ 15645 #define PORT14_IOCR4_PC4_Pos (3UL) /*!< PORT14 IOCR4: PC4 (Bit 3) */ 15646 #define PORT14_IOCR4_PC4_Msk (0xf8UL) /*!< PORT14 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 15647 #define PORT14_IOCR4_PC5_Pos (11UL) /*!< PORT14 IOCR4: PC5 (Bit 11) */ 15648 #define PORT14_IOCR4_PC5_Msk (0xf800UL) /*!< PORT14 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 15649 #define PORT14_IOCR4_PC6_Pos (19UL) /*!< PORT14 IOCR4: PC6 (Bit 19) */ 15650 #define PORT14_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT14 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 15651 #define PORT14_IOCR4_PC7_Pos (27UL) /*!< PORT14 IOCR4: PC7 (Bit 27) */ 15652 #define PORT14_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT14 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 15653 15654 /* -------------------------------- PORT14_IOCR8 -------------------------------- */ 15655 #define PORT14_IOCR8_PC8_Pos (3UL) /*!< PORT14 IOCR8: PC8 (Bit 3) */ 15656 #define PORT14_IOCR8_PC8_Msk (0xf8UL) /*!< PORT14 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ 15657 #define PORT14_IOCR8_PC9_Pos (11UL) /*!< PORT14 IOCR8: PC9 (Bit 11) */ 15658 #define PORT14_IOCR8_PC9_Msk (0xf800UL) /*!< PORT14 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ 15659 #define PORT14_IOCR8_PC10_Pos (19UL) /*!< PORT14 IOCR8: PC10 (Bit 19) */ 15660 #define PORT14_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT14 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ 15661 #define PORT14_IOCR8_PC11_Pos (27UL) /*!< PORT14 IOCR8: PC11 (Bit 27) */ 15662 #define PORT14_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT14 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ 15663 15664 /* -------------------------------- PORT14_IOCR12 ------------------------------- */ 15665 #define PORT14_IOCR12_PC12_Pos (3UL) /*!< PORT14 IOCR12: PC12 (Bit 3) */ 15666 #define PORT14_IOCR12_PC12_Msk (0xf8UL) /*!< PORT14 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ 15667 #define PORT14_IOCR12_PC13_Pos (11UL) /*!< PORT14 IOCR12: PC13 (Bit 11) */ 15668 #define PORT14_IOCR12_PC13_Msk (0xf800UL) /*!< PORT14 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ 15669 #define PORT14_IOCR12_PC14_Pos (19UL) /*!< PORT14 IOCR12: PC14 (Bit 19) */ 15670 #define PORT14_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT14 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ 15671 #define PORT14_IOCR12_PC15_Pos (27UL) /*!< PORT14 IOCR12: PC15 (Bit 27) */ 15672 #define PORT14_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT14 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ 15673 15674 /* ---------------------------------- PORT14_IN --------------------------------- */ 15675 #define PORT14_IN_P0_Pos (0UL) /*!< PORT14 IN: P0 (Bit 0) */ 15676 #define PORT14_IN_P0_Msk (0x1UL) /*!< PORT14 IN: P0 (Bitfield-Mask: 0x01) */ 15677 #define PORT14_IN_P1_Pos (1UL) /*!< PORT14 IN: P1 (Bit 1) */ 15678 #define PORT14_IN_P1_Msk (0x2UL) /*!< PORT14 IN: P1 (Bitfield-Mask: 0x01) */ 15679 #define PORT14_IN_P2_Pos (2UL) /*!< PORT14 IN: P2 (Bit 2) */ 15680 #define PORT14_IN_P2_Msk (0x4UL) /*!< PORT14 IN: P2 (Bitfield-Mask: 0x01) */ 15681 #define PORT14_IN_P3_Pos (3UL) /*!< PORT14 IN: P3 (Bit 3) */ 15682 #define PORT14_IN_P3_Msk (0x8UL) /*!< PORT14 IN: P3 (Bitfield-Mask: 0x01) */ 15683 #define PORT14_IN_P4_Pos (4UL) /*!< PORT14 IN: P4 (Bit 4) */ 15684 #define PORT14_IN_P4_Msk (0x10UL) /*!< PORT14 IN: P4 (Bitfield-Mask: 0x01) */ 15685 #define PORT14_IN_P5_Pos (5UL) /*!< PORT14 IN: P5 (Bit 5) */ 15686 #define PORT14_IN_P5_Msk (0x20UL) /*!< PORT14 IN: P5 (Bitfield-Mask: 0x01) */ 15687 #define PORT14_IN_P6_Pos (6UL) /*!< PORT14 IN: P6 (Bit 6) */ 15688 #define PORT14_IN_P6_Msk (0x40UL) /*!< PORT14 IN: P6 (Bitfield-Mask: 0x01) */ 15689 #define PORT14_IN_P7_Pos (7UL) /*!< PORT14 IN: P7 (Bit 7) */ 15690 #define PORT14_IN_P7_Msk (0x80UL) /*!< PORT14 IN: P7 (Bitfield-Mask: 0x01) */ 15691 #define PORT14_IN_P8_Pos (8UL) /*!< PORT14 IN: P8 (Bit 8) */ 15692 #define PORT14_IN_P8_Msk (0x100UL) /*!< PORT14 IN: P8 (Bitfield-Mask: 0x01) */ 15693 #define PORT14_IN_P9_Pos (9UL) /*!< PORT14 IN: P9 (Bit 9) */ 15694 #define PORT14_IN_P9_Msk (0x200UL) /*!< PORT14 IN: P9 (Bitfield-Mask: 0x01) */ 15695 #define PORT14_IN_P10_Pos (10UL) /*!< PORT14 IN: P10 (Bit 10) */ 15696 #define PORT14_IN_P10_Msk (0x400UL) /*!< PORT14 IN: P10 (Bitfield-Mask: 0x01) */ 15697 #define PORT14_IN_P11_Pos (11UL) /*!< PORT14 IN: P11 (Bit 11) */ 15698 #define PORT14_IN_P11_Msk (0x800UL) /*!< PORT14 IN: P11 (Bitfield-Mask: 0x01) */ 15699 #define PORT14_IN_P12_Pos (12UL) /*!< PORT14 IN: P12 (Bit 12) */ 15700 #define PORT14_IN_P12_Msk (0x1000UL) /*!< PORT14 IN: P12 (Bitfield-Mask: 0x01) */ 15701 #define PORT14_IN_P13_Pos (13UL) /*!< PORT14 IN: P13 (Bit 13) */ 15702 #define PORT14_IN_P13_Msk (0x2000UL) /*!< PORT14 IN: P13 (Bitfield-Mask: 0x01) */ 15703 #define PORT14_IN_P14_Pos (14UL) /*!< PORT14 IN: P14 (Bit 14) */ 15704 #define PORT14_IN_P14_Msk (0x4000UL) /*!< PORT14 IN: P14 (Bitfield-Mask: 0x01) */ 15705 #define PORT14_IN_P15_Pos (15UL) /*!< PORT14 IN: P15 (Bit 15) */ 15706 #define PORT14_IN_P15_Msk (0x8000UL) /*!< PORT14 IN: P15 (Bitfield-Mask: 0x01) */ 15707 15708 /* -------------------------------- PORT14_PDISC -------------------------------- */ 15709 #define PORT14_PDISC_PDIS0_Pos (0UL) /*!< PORT14 PDISC: PDIS0 (Bit 0) */ 15710 #define PORT14_PDISC_PDIS0_Msk (0x1UL) /*!< PORT14 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ 15711 #define PORT14_PDISC_PDIS1_Pos (1UL) /*!< PORT14 PDISC: PDIS1 (Bit 1) */ 15712 #define PORT14_PDISC_PDIS1_Msk (0x2UL) /*!< PORT14 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ 15713 #define PORT14_PDISC_PDIS2_Pos (2UL) /*!< PORT14 PDISC: PDIS2 (Bit 2) */ 15714 #define PORT14_PDISC_PDIS2_Msk (0x4UL) /*!< PORT14 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 15715 #define PORT14_PDISC_PDIS3_Pos (3UL) /*!< PORT14 PDISC: PDIS3 (Bit 3) */ 15716 #define PORT14_PDISC_PDIS3_Msk (0x8UL) /*!< PORT14 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 15717 #define PORT14_PDISC_PDIS4_Pos (4UL) /*!< PORT14 PDISC: PDIS4 (Bit 4) */ 15718 #define PORT14_PDISC_PDIS4_Msk (0x10UL) /*!< PORT14 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 15719 #define PORT14_PDISC_PDIS5_Pos (5UL) /*!< PORT14 PDISC: PDIS5 (Bit 5) */ 15720 #define PORT14_PDISC_PDIS5_Msk (0x20UL) /*!< PORT14 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 15721 #define PORT14_PDISC_PDIS6_Pos (6UL) /*!< PORT14 PDISC: PDIS6 (Bit 6) */ 15722 #define PORT14_PDISC_PDIS6_Msk (0x40UL) /*!< PORT14 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 15723 #define PORT14_PDISC_PDIS7_Pos (7UL) /*!< PORT14 PDISC: PDIS7 (Bit 7) */ 15724 #define PORT14_PDISC_PDIS7_Msk (0x80UL) /*!< PORT14 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 15725 #define PORT14_PDISC_PDIS8_Pos (8UL) /*!< PORT14 PDISC: PDIS8 (Bit 8) */ 15726 #define PORT14_PDISC_PDIS8_Msk (0x100UL) /*!< PORT14 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 15727 #define PORT14_PDISC_PDIS9_Pos (9UL) /*!< PORT14 PDISC: PDIS9 (Bit 9) */ 15728 #define PORT14_PDISC_PDIS9_Msk (0x200UL) /*!< PORT14 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 15729 #define PORT14_PDISC_PDIS12_Pos (12UL) /*!< PORT14 PDISC: PDIS12 (Bit 12) */ 15730 #define PORT14_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT14 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 15731 #define PORT14_PDISC_PDIS13_Pos (13UL) /*!< PORT14 PDISC: PDIS13 (Bit 13) */ 15732 #define PORT14_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT14 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 15733 #define PORT14_PDISC_PDIS14_Pos (14UL) /*!< PORT14 PDISC: PDIS14 (Bit 14) */ 15734 #define PORT14_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT14 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 15735 #define PORT14_PDISC_PDIS15_Pos (15UL) /*!< PORT14 PDISC: PDIS15 (Bit 15) */ 15736 #define PORT14_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT14 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 15737 15738 /* --------------------------------- PORT14_PPS --------------------------------- */ 15739 #define PORT14_PPS_PPS0_Pos (0UL) /*!< PORT14 PPS: PPS0 (Bit 0) */ 15740 #define PORT14_PPS_PPS0_Msk (0x1UL) /*!< PORT14 PPS: PPS0 (Bitfield-Mask: 0x01) */ 15741 #define PORT14_PPS_PPS1_Pos (1UL) /*!< PORT14 PPS: PPS1 (Bit 1) */ 15742 #define PORT14_PPS_PPS1_Msk (0x2UL) /*!< PORT14 PPS: PPS1 (Bitfield-Mask: 0x01) */ 15743 #define PORT14_PPS_PPS2_Pos (2UL) /*!< PORT14 PPS: PPS2 (Bit 2) */ 15744 #define PORT14_PPS_PPS2_Msk (0x4UL) /*!< PORT14 PPS: PPS2 (Bitfield-Mask: 0x01) */ 15745 #define PORT14_PPS_PPS3_Pos (3UL) /*!< PORT14 PPS: PPS3 (Bit 3) */ 15746 #define PORT14_PPS_PPS3_Msk (0x8UL) /*!< PORT14 PPS: PPS3 (Bitfield-Mask: 0x01) */ 15747 #define PORT14_PPS_PPS4_Pos (4UL) /*!< PORT14 PPS: PPS4 (Bit 4) */ 15748 #define PORT14_PPS_PPS4_Msk (0x10UL) /*!< PORT14 PPS: PPS4 (Bitfield-Mask: 0x01) */ 15749 #define PORT14_PPS_PPS5_Pos (5UL) /*!< PORT14 PPS: PPS5 (Bit 5) */ 15750 #define PORT14_PPS_PPS5_Msk (0x20UL) /*!< PORT14 PPS: PPS5 (Bitfield-Mask: 0x01) */ 15751 #define PORT14_PPS_PPS6_Pos (6UL) /*!< PORT14 PPS: PPS6 (Bit 6) */ 15752 #define PORT14_PPS_PPS6_Msk (0x40UL) /*!< PORT14 PPS: PPS6 (Bitfield-Mask: 0x01) */ 15753 #define PORT14_PPS_PPS7_Pos (7UL) /*!< PORT14 PPS: PPS7 (Bit 7) */ 15754 #define PORT14_PPS_PPS7_Msk (0x80UL) /*!< PORT14 PPS: PPS7 (Bitfield-Mask: 0x01) */ 15755 #define PORT14_PPS_PPS8_Pos (8UL) /*!< PORT14 PPS: PPS8 (Bit 8) */ 15756 #define PORT14_PPS_PPS8_Msk (0x100UL) /*!< PORT14 PPS: PPS8 (Bitfield-Mask: 0x01) */ 15757 #define PORT14_PPS_PPS9_Pos (9UL) /*!< PORT14 PPS: PPS9 (Bit 9) */ 15758 #define PORT14_PPS_PPS9_Msk (0x200UL) /*!< PORT14 PPS: PPS9 (Bitfield-Mask: 0x01) */ 15759 #define PORT14_PPS_PPS10_Pos (10UL) /*!< PORT14 PPS: PPS10 (Bit 10) */ 15760 #define PORT14_PPS_PPS10_Msk (0x400UL) /*!< PORT14 PPS: PPS10 (Bitfield-Mask: 0x01) */ 15761 #define PORT14_PPS_PPS11_Pos (11UL) /*!< PORT14 PPS: PPS11 (Bit 11) */ 15762 #define PORT14_PPS_PPS11_Msk (0x800UL) /*!< PORT14 PPS: PPS11 (Bitfield-Mask: 0x01) */ 15763 #define PORT14_PPS_PPS12_Pos (12UL) /*!< PORT14 PPS: PPS12 (Bit 12) */ 15764 #define PORT14_PPS_PPS12_Msk (0x1000UL) /*!< PORT14 PPS: PPS12 (Bitfield-Mask: 0x01) */ 15765 #define PORT14_PPS_PPS13_Pos (13UL) /*!< PORT14 PPS: PPS13 (Bit 13) */ 15766 #define PORT14_PPS_PPS13_Msk (0x2000UL) /*!< PORT14 PPS: PPS13 (Bitfield-Mask: 0x01) */ 15767 #define PORT14_PPS_PPS14_Pos (14UL) /*!< PORT14 PPS: PPS14 (Bit 14) */ 15768 #define PORT14_PPS_PPS14_Msk (0x4000UL) /*!< PORT14 PPS: PPS14 (Bitfield-Mask: 0x01) */ 15769 #define PORT14_PPS_PPS15_Pos (15UL) /*!< PORT14 PPS: PPS15 (Bit 15) */ 15770 #define PORT14_PPS_PPS15_Msk (0x8000UL) /*!< PORT14 PPS: PPS15 (Bitfield-Mask: 0x01) */ 15771 15772 /* -------------------------------- PORT14_HWSEL -------------------------------- */ 15773 #define PORT14_HWSEL_HW0_Pos (0UL) /*!< PORT14 HWSEL: HW0 (Bit 0) */ 15774 #define PORT14_HWSEL_HW0_Msk (0x3UL) /*!< PORT14 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 15775 #define PORT14_HWSEL_HW1_Pos (2UL) /*!< PORT14 HWSEL: HW1 (Bit 2) */ 15776 #define PORT14_HWSEL_HW1_Msk (0xcUL) /*!< PORT14 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 15777 #define PORT14_HWSEL_HW2_Pos (4UL) /*!< PORT14 HWSEL: HW2 (Bit 4) */ 15778 #define PORT14_HWSEL_HW2_Msk (0x30UL) /*!< PORT14 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 15779 #define PORT14_HWSEL_HW3_Pos (6UL) /*!< PORT14 HWSEL: HW3 (Bit 6) */ 15780 #define PORT14_HWSEL_HW3_Msk (0xc0UL) /*!< PORT14 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 15781 #define PORT14_HWSEL_HW4_Pos (8UL) /*!< PORT14 HWSEL: HW4 (Bit 8) */ 15782 #define PORT14_HWSEL_HW4_Msk (0x300UL) /*!< PORT14 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 15783 #define PORT14_HWSEL_HW5_Pos (10UL) /*!< PORT14 HWSEL: HW5 (Bit 10) */ 15784 #define PORT14_HWSEL_HW5_Msk (0xc00UL) /*!< PORT14 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 15785 #define PORT14_HWSEL_HW6_Pos (12UL) /*!< PORT14 HWSEL: HW6 (Bit 12) */ 15786 #define PORT14_HWSEL_HW6_Msk (0x3000UL) /*!< PORT14 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 15787 #define PORT14_HWSEL_HW7_Pos (14UL) /*!< PORT14 HWSEL: HW7 (Bit 14) */ 15788 #define PORT14_HWSEL_HW7_Msk (0xc000UL) /*!< PORT14 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 15789 #define PORT14_HWSEL_HW8_Pos (16UL) /*!< PORT14 HWSEL: HW8 (Bit 16) */ 15790 #define PORT14_HWSEL_HW8_Msk (0x30000UL) /*!< PORT14 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 15791 #define PORT14_HWSEL_HW9_Pos (18UL) /*!< PORT14 HWSEL: HW9 (Bit 18) */ 15792 #define PORT14_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT14 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 15793 #define PORT14_HWSEL_HW10_Pos (20UL) /*!< PORT14 HWSEL: HW10 (Bit 20) */ 15794 #define PORT14_HWSEL_HW10_Msk (0x300000UL) /*!< PORT14 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 15795 #define PORT14_HWSEL_HW11_Pos (22UL) /*!< PORT14 HWSEL: HW11 (Bit 22) */ 15796 #define PORT14_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT14 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 15797 #define PORT14_HWSEL_HW12_Pos (24UL) /*!< PORT14 HWSEL: HW12 (Bit 24) */ 15798 #define PORT14_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT14 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 15799 #define PORT14_HWSEL_HW13_Pos (26UL) /*!< PORT14 HWSEL: HW13 (Bit 26) */ 15800 #define PORT14_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT14 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 15801 #define PORT14_HWSEL_HW14_Pos (28UL) /*!< PORT14 HWSEL: HW14 (Bit 28) */ 15802 #define PORT14_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT14 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 15803 #define PORT14_HWSEL_HW15_Pos (30UL) /*!< PORT14 HWSEL: HW15 (Bit 30) */ 15804 #define PORT14_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT14 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 15805 15806 15807 /* ================================================================================ */ 15808 /* ================ struct 'PORT15' Position & Mask ================ */ 15809 /* ================================================================================ */ 15810 15811 15812 /* --------------------------------- PORT15_OUT --------------------------------- */ 15813 #define PORT15_OUT_P0_Pos (0UL) /*!< PORT15 OUT: P0 (Bit 0) */ 15814 #define PORT15_OUT_P0_Msk (0x1UL) /*!< PORT15 OUT: P0 (Bitfield-Mask: 0x01) */ 15815 #define PORT15_OUT_P1_Pos (1UL) /*!< PORT15 OUT: P1 (Bit 1) */ 15816 #define PORT15_OUT_P1_Msk (0x2UL) /*!< PORT15 OUT: P1 (Bitfield-Mask: 0x01) */ 15817 #define PORT15_OUT_P2_Pos (2UL) /*!< PORT15 OUT: P2 (Bit 2) */ 15818 #define PORT15_OUT_P2_Msk (0x4UL) /*!< PORT15 OUT: P2 (Bitfield-Mask: 0x01) */ 15819 #define PORT15_OUT_P3_Pos (3UL) /*!< PORT15 OUT: P3 (Bit 3) */ 15820 #define PORT15_OUT_P3_Msk (0x8UL) /*!< PORT15 OUT: P3 (Bitfield-Mask: 0x01) */ 15821 #define PORT15_OUT_P4_Pos (4UL) /*!< PORT15 OUT: P4 (Bit 4) */ 15822 #define PORT15_OUT_P4_Msk (0x10UL) /*!< PORT15 OUT: P4 (Bitfield-Mask: 0x01) */ 15823 #define PORT15_OUT_P5_Pos (5UL) /*!< PORT15 OUT: P5 (Bit 5) */ 15824 #define PORT15_OUT_P5_Msk (0x20UL) /*!< PORT15 OUT: P5 (Bitfield-Mask: 0x01) */ 15825 #define PORT15_OUT_P6_Pos (6UL) /*!< PORT15 OUT: P6 (Bit 6) */ 15826 #define PORT15_OUT_P6_Msk (0x40UL) /*!< PORT15 OUT: P6 (Bitfield-Mask: 0x01) */ 15827 #define PORT15_OUT_P7_Pos (7UL) /*!< PORT15 OUT: P7 (Bit 7) */ 15828 #define PORT15_OUT_P7_Msk (0x80UL) /*!< PORT15 OUT: P7 (Bitfield-Mask: 0x01) */ 15829 #define PORT15_OUT_P8_Pos (8UL) /*!< PORT15 OUT: P8 (Bit 8) */ 15830 #define PORT15_OUT_P8_Msk (0x100UL) /*!< PORT15 OUT: P8 (Bitfield-Mask: 0x01) */ 15831 #define PORT15_OUT_P9_Pos (9UL) /*!< PORT15 OUT: P9 (Bit 9) */ 15832 #define PORT15_OUT_P9_Msk (0x200UL) /*!< PORT15 OUT: P9 (Bitfield-Mask: 0x01) */ 15833 #define PORT15_OUT_P10_Pos (10UL) /*!< PORT15 OUT: P10 (Bit 10) */ 15834 #define PORT15_OUT_P10_Msk (0x400UL) /*!< PORT15 OUT: P10 (Bitfield-Mask: 0x01) */ 15835 #define PORT15_OUT_P11_Pos (11UL) /*!< PORT15 OUT: P11 (Bit 11) */ 15836 #define PORT15_OUT_P11_Msk (0x800UL) /*!< PORT15 OUT: P11 (Bitfield-Mask: 0x01) */ 15837 #define PORT15_OUT_P12_Pos (12UL) /*!< PORT15 OUT: P12 (Bit 12) */ 15838 #define PORT15_OUT_P12_Msk (0x1000UL) /*!< PORT15 OUT: P12 (Bitfield-Mask: 0x01) */ 15839 #define PORT15_OUT_P13_Pos (13UL) /*!< PORT15 OUT: P13 (Bit 13) */ 15840 #define PORT15_OUT_P13_Msk (0x2000UL) /*!< PORT15 OUT: P13 (Bitfield-Mask: 0x01) */ 15841 #define PORT15_OUT_P14_Pos (14UL) /*!< PORT15 OUT: P14 (Bit 14) */ 15842 #define PORT15_OUT_P14_Msk (0x4000UL) /*!< PORT15 OUT: P14 (Bitfield-Mask: 0x01) */ 15843 #define PORT15_OUT_P15_Pos (15UL) /*!< PORT15 OUT: P15 (Bit 15) */ 15844 #define PORT15_OUT_P15_Msk (0x8000UL) /*!< PORT15 OUT: P15 (Bitfield-Mask: 0x01) */ 15845 15846 /* --------------------------------- PORT15_OMR --------------------------------- */ 15847 #define PORT15_OMR_PS0_Pos (0UL) /*!< PORT15 OMR: PS0 (Bit 0) */ 15848 #define PORT15_OMR_PS0_Msk (0x1UL) /*!< PORT15 OMR: PS0 (Bitfield-Mask: 0x01) */ 15849 #define PORT15_OMR_PS1_Pos (1UL) /*!< PORT15 OMR: PS1 (Bit 1) */ 15850 #define PORT15_OMR_PS1_Msk (0x2UL) /*!< PORT15 OMR: PS1 (Bitfield-Mask: 0x01) */ 15851 #define PORT15_OMR_PS2_Pos (2UL) /*!< PORT15 OMR: PS2 (Bit 2) */ 15852 #define PORT15_OMR_PS2_Msk (0x4UL) /*!< PORT15 OMR: PS2 (Bitfield-Mask: 0x01) */ 15853 #define PORT15_OMR_PS3_Pos (3UL) /*!< PORT15 OMR: PS3 (Bit 3) */ 15854 #define PORT15_OMR_PS3_Msk (0x8UL) /*!< PORT15 OMR: PS3 (Bitfield-Mask: 0x01) */ 15855 #define PORT15_OMR_PS4_Pos (4UL) /*!< PORT15 OMR: PS4 (Bit 4) */ 15856 #define PORT15_OMR_PS4_Msk (0x10UL) /*!< PORT15 OMR: PS4 (Bitfield-Mask: 0x01) */ 15857 #define PORT15_OMR_PS5_Pos (5UL) /*!< PORT15 OMR: PS5 (Bit 5) */ 15858 #define PORT15_OMR_PS5_Msk (0x20UL) /*!< PORT15 OMR: PS5 (Bitfield-Mask: 0x01) */ 15859 #define PORT15_OMR_PS6_Pos (6UL) /*!< PORT15 OMR: PS6 (Bit 6) */ 15860 #define PORT15_OMR_PS6_Msk (0x40UL) /*!< PORT15 OMR: PS6 (Bitfield-Mask: 0x01) */ 15861 #define PORT15_OMR_PS7_Pos (7UL) /*!< PORT15 OMR: PS7 (Bit 7) */ 15862 #define PORT15_OMR_PS7_Msk (0x80UL) /*!< PORT15 OMR: PS7 (Bitfield-Mask: 0x01) */ 15863 #define PORT15_OMR_PS8_Pos (8UL) /*!< PORT15 OMR: PS8 (Bit 8) */ 15864 #define PORT15_OMR_PS8_Msk (0x100UL) /*!< PORT15 OMR: PS8 (Bitfield-Mask: 0x01) */ 15865 #define PORT15_OMR_PS9_Pos (9UL) /*!< PORT15 OMR: PS9 (Bit 9) */ 15866 #define PORT15_OMR_PS9_Msk (0x200UL) /*!< PORT15 OMR: PS9 (Bitfield-Mask: 0x01) */ 15867 #define PORT15_OMR_PS10_Pos (10UL) /*!< PORT15 OMR: PS10 (Bit 10) */ 15868 #define PORT15_OMR_PS10_Msk (0x400UL) /*!< PORT15 OMR: PS10 (Bitfield-Mask: 0x01) */ 15869 #define PORT15_OMR_PS11_Pos (11UL) /*!< PORT15 OMR: PS11 (Bit 11) */ 15870 #define PORT15_OMR_PS11_Msk (0x800UL) /*!< PORT15 OMR: PS11 (Bitfield-Mask: 0x01) */ 15871 #define PORT15_OMR_PS12_Pos (12UL) /*!< PORT15 OMR: PS12 (Bit 12) */ 15872 #define PORT15_OMR_PS12_Msk (0x1000UL) /*!< PORT15 OMR: PS12 (Bitfield-Mask: 0x01) */ 15873 #define PORT15_OMR_PS13_Pos (13UL) /*!< PORT15 OMR: PS13 (Bit 13) */ 15874 #define PORT15_OMR_PS13_Msk (0x2000UL) /*!< PORT15 OMR: PS13 (Bitfield-Mask: 0x01) */ 15875 #define PORT15_OMR_PS14_Pos (14UL) /*!< PORT15 OMR: PS14 (Bit 14) */ 15876 #define PORT15_OMR_PS14_Msk (0x4000UL) /*!< PORT15 OMR: PS14 (Bitfield-Mask: 0x01) */ 15877 #define PORT15_OMR_PS15_Pos (15UL) /*!< PORT15 OMR: PS15 (Bit 15) */ 15878 #define PORT15_OMR_PS15_Msk (0x8000UL) /*!< PORT15 OMR: PS15 (Bitfield-Mask: 0x01) */ 15879 #define PORT15_OMR_PR0_Pos (16UL) /*!< PORT15 OMR: PR0 (Bit 16) */ 15880 #define PORT15_OMR_PR0_Msk (0x10000UL) /*!< PORT15 OMR: PR0 (Bitfield-Mask: 0x01) */ 15881 #define PORT15_OMR_PR1_Pos (17UL) /*!< PORT15 OMR: PR1 (Bit 17) */ 15882 #define PORT15_OMR_PR1_Msk (0x20000UL) /*!< PORT15 OMR: PR1 (Bitfield-Mask: 0x01) */ 15883 #define PORT15_OMR_PR2_Pos (18UL) /*!< PORT15 OMR: PR2 (Bit 18) */ 15884 #define PORT15_OMR_PR2_Msk (0x40000UL) /*!< PORT15 OMR: PR2 (Bitfield-Mask: 0x01) */ 15885 #define PORT15_OMR_PR3_Pos (19UL) /*!< PORT15 OMR: PR3 (Bit 19) */ 15886 #define PORT15_OMR_PR3_Msk (0x80000UL) /*!< PORT15 OMR: PR3 (Bitfield-Mask: 0x01) */ 15887 #define PORT15_OMR_PR4_Pos (20UL) /*!< PORT15 OMR: PR4 (Bit 20) */ 15888 #define PORT15_OMR_PR4_Msk (0x100000UL) /*!< PORT15 OMR: PR4 (Bitfield-Mask: 0x01) */ 15889 #define PORT15_OMR_PR5_Pos (21UL) /*!< PORT15 OMR: PR5 (Bit 21) */ 15890 #define PORT15_OMR_PR5_Msk (0x200000UL) /*!< PORT15 OMR: PR5 (Bitfield-Mask: 0x01) */ 15891 #define PORT15_OMR_PR6_Pos (22UL) /*!< PORT15 OMR: PR6 (Bit 22) */ 15892 #define PORT15_OMR_PR6_Msk (0x400000UL) /*!< PORT15 OMR: PR6 (Bitfield-Mask: 0x01) */ 15893 #define PORT15_OMR_PR7_Pos (23UL) /*!< PORT15 OMR: PR7 (Bit 23) */ 15894 #define PORT15_OMR_PR7_Msk (0x800000UL) /*!< PORT15 OMR: PR7 (Bitfield-Mask: 0x01) */ 15895 #define PORT15_OMR_PR8_Pos (24UL) /*!< PORT15 OMR: PR8 (Bit 24) */ 15896 #define PORT15_OMR_PR8_Msk (0x1000000UL) /*!< PORT15 OMR: PR8 (Bitfield-Mask: 0x01) */ 15897 #define PORT15_OMR_PR9_Pos (25UL) /*!< PORT15 OMR: PR9 (Bit 25) */ 15898 #define PORT15_OMR_PR9_Msk (0x2000000UL) /*!< PORT15 OMR: PR9 (Bitfield-Mask: 0x01) */ 15899 #define PORT15_OMR_PR10_Pos (26UL) /*!< PORT15 OMR: PR10 (Bit 26) */ 15900 #define PORT15_OMR_PR10_Msk (0x4000000UL) /*!< PORT15 OMR: PR10 (Bitfield-Mask: 0x01) */ 15901 #define PORT15_OMR_PR11_Pos (27UL) /*!< PORT15 OMR: PR11 (Bit 27) */ 15902 #define PORT15_OMR_PR11_Msk (0x8000000UL) /*!< PORT15 OMR: PR11 (Bitfield-Mask: 0x01) */ 15903 #define PORT15_OMR_PR12_Pos (28UL) /*!< PORT15 OMR: PR12 (Bit 28) */ 15904 #define PORT15_OMR_PR12_Msk (0x10000000UL) /*!< PORT15 OMR: PR12 (Bitfield-Mask: 0x01) */ 15905 #define PORT15_OMR_PR13_Pos (29UL) /*!< PORT15 OMR: PR13 (Bit 29) */ 15906 #define PORT15_OMR_PR13_Msk (0x20000000UL) /*!< PORT15 OMR: PR13 (Bitfield-Mask: 0x01) */ 15907 #define PORT15_OMR_PR14_Pos (30UL) /*!< PORT15 OMR: PR14 (Bit 30) */ 15908 #define PORT15_OMR_PR14_Msk (0x40000000UL) /*!< PORT15 OMR: PR14 (Bitfield-Mask: 0x01) */ 15909 #define PORT15_OMR_PR15_Pos (31UL) /*!< PORT15 OMR: PR15 (Bit 31) */ 15910 #define PORT15_OMR_PR15_Msk (0x80000000UL) /*!< PORT15 OMR: PR15 (Bitfield-Mask: 0x01) */ 15911 15912 /* -------------------------------- PORT15_IOCR0 -------------------------------- */ 15913 #define PORT15_IOCR0_PC0_Pos (3UL) /*!< PORT15 IOCR0: PC0 (Bit 3) */ 15914 #define PORT15_IOCR0_PC0_Msk (0xf8UL) /*!< PORT15 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ 15915 #define PORT15_IOCR0_PC1_Pos (11UL) /*!< PORT15 IOCR0: PC1 (Bit 11) */ 15916 #define PORT15_IOCR0_PC1_Msk (0xf800UL) /*!< PORT15 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ 15917 #define PORT15_IOCR0_PC2_Pos (19UL) /*!< PORT15 IOCR0: PC2 (Bit 19) */ 15918 #define PORT15_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT15 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ 15919 #define PORT15_IOCR0_PC3_Pos (27UL) /*!< PORT15 IOCR0: PC3 (Bit 27) */ 15920 #define PORT15_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT15 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ 15921 15922 /* -------------------------------- PORT15_IOCR4 -------------------------------- */ 15923 #define PORT15_IOCR4_PC4_Pos (3UL) /*!< PORT15 IOCR4: PC4 (Bit 3) */ 15924 #define PORT15_IOCR4_PC4_Msk (0xf8UL) /*!< PORT15 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ 15925 #define PORT15_IOCR4_PC5_Pos (11UL) /*!< PORT15 IOCR4: PC5 (Bit 11) */ 15926 #define PORT15_IOCR4_PC5_Msk (0xf800UL) /*!< PORT15 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ 15927 #define PORT15_IOCR4_PC6_Pos (19UL) /*!< PORT15 IOCR4: PC6 (Bit 19) */ 15928 #define PORT15_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT15 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ 15929 #define PORT15_IOCR4_PC7_Pos (27UL) /*!< PORT15 IOCR4: PC7 (Bit 27) */ 15930 #define PORT15_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT15 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ 15931 15932 /* -------------------------------- PORT15_IOCR8 -------------------------------- */ 15933 #define PORT15_IOCR8_PC8_Pos (3UL) /*!< PORT15 IOCR8: PC8 (Bit 3) */ 15934 #define PORT15_IOCR8_PC8_Msk (0xf8UL) /*!< PORT15 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ 15935 #define PORT15_IOCR8_PC9_Pos (11UL) /*!< PORT15 IOCR8: PC9 (Bit 11) */ 15936 #define PORT15_IOCR8_PC9_Msk (0xf800UL) /*!< PORT15 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ 15937 #define PORT15_IOCR8_PC10_Pos (19UL) /*!< PORT15 IOCR8: PC10 (Bit 19) */ 15938 #define PORT15_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT15 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ 15939 #define PORT15_IOCR8_PC11_Pos (27UL) /*!< PORT15 IOCR8: PC11 (Bit 27) */ 15940 #define PORT15_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT15 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ 15941 15942 /* -------------------------------- PORT15_IOCR12 ------------------------------- */ 15943 #define PORT15_IOCR12_PC12_Pos (3UL) /*!< PORT15 IOCR12: PC12 (Bit 3) */ 15944 #define PORT15_IOCR12_PC12_Msk (0xf8UL) /*!< PORT15 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ 15945 #define PORT15_IOCR12_PC13_Pos (11UL) /*!< PORT15 IOCR12: PC13 (Bit 11) */ 15946 #define PORT15_IOCR12_PC13_Msk (0xf800UL) /*!< PORT15 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ 15947 #define PORT15_IOCR12_PC14_Pos (19UL) /*!< PORT15 IOCR12: PC14 (Bit 19) */ 15948 #define PORT15_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT15 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ 15949 #define PORT15_IOCR12_PC15_Pos (27UL) /*!< PORT15 IOCR12: PC15 (Bit 27) */ 15950 #define PORT15_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT15 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ 15951 15952 /* ---------------------------------- PORT15_IN --------------------------------- */ 15953 #define PORT15_IN_P0_Pos (0UL) /*!< PORT15 IN: P0 (Bit 0) */ 15954 #define PORT15_IN_P0_Msk (0x1UL) /*!< PORT15 IN: P0 (Bitfield-Mask: 0x01) */ 15955 #define PORT15_IN_P1_Pos (1UL) /*!< PORT15 IN: P1 (Bit 1) */ 15956 #define PORT15_IN_P1_Msk (0x2UL) /*!< PORT15 IN: P1 (Bitfield-Mask: 0x01) */ 15957 #define PORT15_IN_P2_Pos (2UL) /*!< PORT15 IN: P2 (Bit 2) */ 15958 #define PORT15_IN_P2_Msk (0x4UL) /*!< PORT15 IN: P2 (Bitfield-Mask: 0x01) */ 15959 #define PORT15_IN_P3_Pos (3UL) /*!< PORT15 IN: P3 (Bit 3) */ 15960 #define PORT15_IN_P3_Msk (0x8UL) /*!< PORT15 IN: P3 (Bitfield-Mask: 0x01) */ 15961 #define PORT15_IN_P4_Pos (4UL) /*!< PORT15 IN: P4 (Bit 4) */ 15962 #define PORT15_IN_P4_Msk (0x10UL) /*!< PORT15 IN: P4 (Bitfield-Mask: 0x01) */ 15963 #define PORT15_IN_P5_Pos (5UL) /*!< PORT15 IN: P5 (Bit 5) */ 15964 #define PORT15_IN_P5_Msk (0x20UL) /*!< PORT15 IN: P5 (Bitfield-Mask: 0x01) */ 15965 #define PORT15_IN_P6_Pos (6UL) /*!< PORT15 IN: P6 (Bit 6) */ 15966 #define PORT15_IN_P6_Msk (0x40UL) /*!< PORT15 IN: P6 (Bitfield-Mask: 0x01) */ 15967 #define PORT15_IN_P7_Pos (7UL) /*!< PORT15 IN: P7 (Bit 7) */ 15968 #define PORT15_IN_P7_Msk (0x80UL) /*!< PORT15 IN: P7 (Bitfield-Mask: 0x01) */ 15969 #define PORT15_IN_P8_Pos (8UL) /*!< PORT15 IN: P8 (Bit 8) */ 15970 #define PORT15_IN_P8_Msk (0x100UL) /*!< PORT15 IN: P8 (Bitfield-Mask: 0x01) */ 15971 #define PORT15_IN_P9_Pos (9UL) /*!< PORT15 IN: P9 (Bit 9) */ 15972 #define PORT15_IN_P9_Msk (0x200UL) /*!< PORT15 IN: P9 (Bitfield-Mask: 0x01) */ 15973 #define PORT15_IN_P10_Pos (10UL) /*!< PORT15 IN: P10 (Bit 10) */ 15974 #define PORT15_IN_P10_Msk (0x400UL) /*!< PORT15 IN: P10 (Bitfield-Mask: 0x01) */ 15975 #define PORT15_IN_P11_Pos (11UL) /*!< PORT15 IN: P11 (Bit 11) */ 15976 #define PORT15_IN_P11_Msk (0x800UL) /*!< PORT15 IN: P11 (Bitfield-Mask: 0x01) */ 15977 #define PORT15_IN_P12_Pos (12UL) /*!< PORT15 IN: P12 (Bit 12) */ 15978 #define PORT15_IN_P12_Msk (0x1000UL) /*!< PORT15 IN: P12 (Bitfield-Mask: 0x01) */ 15979 #define PORT15_IN_P13_Pos (13UL) /*!< PORT15 IN: P13 (Bit 13) */ 15980 #define PORT15_IN_P13_Msk (0x2000UL) /*!< PORT15 IN: P13 (Bitfield-Mask: 0x01) */ 15981 #define PORT15_IN_P14_Pos (14UL) /*!< PORT15 IN: P14 (Bit 14) */ 15982 #define PORT15_IN_P14_Msk (0x4000UL) /*!< PORT15 IN: P14 (Bitfield-Mask: 0x01) */ 15983 #define PORT15_IN_P15_Pos (15UL) /*!< PORT15 IN: P15 (Bit 15) */ 15984 #define PORT15_IN_P15_Msk (0x8000UL) /*!< PORT15 IN: P15 (Bitfield-Mask: 0x01) */ 15985 15986 /* -------------------------------- PORT15_PDISC -------------------------------- */ 15987 #define PORT15_PDISC_PDIS2_Pos (2UL) /*!< PORT15 PDISC: PDIS2 (Bit 2) */ 15988 #define PORT15_PDISC_PDIS2_Msk (0x4UL) /*!< PORT15 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ 15989 #define PORT15_PDISC_PDIS3_Pos (3UL) /*!< PORT15 PDISC: PDIS3 (Bit 3) */ 15990 #define PORT15_PDISC_PDIS3_Msk (0x8UL) /*!< PORT15 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ 15991 #define PORT15_PDISC_PDIS4_Pos (4UL) /*!< PORT15 PDISC: PDIS4 (Bit 4) */ 15992 #define PORT15_PDISC_PDIS4_Msk (0x10UL) /*!< PORT15 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ 15993 #define PORT15_PDISC_PDIS5_Pos (5UL) /*!< PORT15 PDISC: PDIS5 (Bit 5) */ 15994 #define PORT15_PDISC_PDIS5_Msk (0x20UL) /*!< PORT15 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ 15995 #define PORT15_PDISC_PDIS6_Pos (6UL) /*!< PORT15 PDISC: PDIS6 (Bit 6) */ 15996 #define PORT15_PDISC_PDIS6_Msk (0x40UL) /*!< PORT15 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ 15997 #define PORT15_PDISC_PDIS7_Pos (7UL) /*!< PORT15 PDISC: PDIS7 (Bit 7) */ 15998 #define PORT15_PDISC_PDIS7_Msk (0x80UL) /*!< PORT15 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ 15999 #define PORT15_PDISC_PDIS8_Pos (8UL) /*!< PORT15 PDISC: PDIS8 (Bit 8) */ 16000 #define PORT15_PDISC_PDIS8_Msk (0x100UL) /*!< PORT15 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ 16001 #define PORT15_PDISC_PDIS9_Pos (9UL) /*!< PORT15 PDISC: PDIS9 (Bit 9) */ 16002 #define PORT15_PDISC_PDIS9_Msk (0x200UL) /*!< PORT15 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ 16003 #define PORT15_PDISC_PDIS12_Pos (12UL) /*!< PORT15 PDISC: PDIS12 (Bit 12) */ 16004 #define PORT15_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT15 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ 16005 #define PORT15_PDISC_PDIS13_Pos (13UL) /*!< PORT15 PDISC: PDIS13 (Bit 13) */ 16006 #define PORT15_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT15 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ 16007 #define PORT15_PDISC_PDIS14_Pos (14UL) /*!< PORT15 PDISC: PDIS14 (Bit 14) */ 16008 #define PORT15_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT15 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ 16009 #define PORT15_PDISC_PDIS15_Pos (15UL) /*!< PORT15 PDISC: PDIS15 (Bit 15) */ 16010 #define PORT15_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT15 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ 16011 16012 /* --------------------------------- PORT15_PPS --------------------------------- */ 16013 #define PORT15_PPS_PPS0_Pos (0UL) /*!< PORT15 PPS: PPS0 (Bit 0) */ 16014 #define PORT15_PPS_PPS0_Msk (0x1UL) /*!< PORT15 PPS: PPS0 (Bitfield-Mask: 0x01) */ 16015 #define PORT15_PPS_PPS1_Pos (1UL) /*!< PORT15 PPS: PPS1 (Bit 1) */ 16016 #define PORT15_PPS_PPS1_Msk (0x2UL) /*!< PORT15 PPS: PPS1 (Bitfield-Mask: 0x01) */ 16017 #define PORT15_PPS_PPS2_Pos (2UL) /*!< PORT15 PPS: PPS2 (Bit 2) */ 16018 #define PORT15_PPS_PPS2_Msk (0x4UL) /*!< PORT15 PPS: PPS2 (Bitfield-Mask: 0x01) */ 16019 #define PORT15_PPS_PPS3_Pos (3UL) /*!< PORT15 PPS: PPS3 (Bit 3) */ 16020 #define PORT15_PPS_PPS3_Msk (0x8UL) /*!< PORT15 PPS: PPS3 (Bitfield-Mask: 0x01) */ 16021 #define PORT15_PPS_PPS4_Pos (4UL) /*!< PORT15 PPS: PPS4 (Bit 4) */ 16022 #define PORT15_PPS_PPS4_Msk (0x10UL) /*!< PORT15 PPS: PPS4 (Bitfield-Mask: 0x01) */ 16023 #define PORT15_PPS_PPS5_Pos (5UL) /*!< PORT15 PPS: PPS5 (Bit 5) */ 16024 #define PORT15_PPS_PPS5_Msk (0x20UL) /*!< PORT15 PPS: PPS5 (Bitfield-Mask: 0x01) */ 16025 #define PORT15_PPS_PPS6_Pos (6UL) /*!< PORT15 PPS: PPS6 (Bit 6) */ 16026 #define PORT15_PPS_PPS6_Msk (0x40UL) /*!< PORT15 PPS: PPS6 (Bitfield-Mask: 0x01) */ 16027 #define PORT15_PPS_PPS7_Pos (7UL) /*!< PORT15 PPS: PPS7 (Bit 7) */ 16028 #define PORT15_PPS_PPS7_Msk (0x80UL) /*!< PORT15 PPS: PPS7 (Bitfield-Mask: 0x01) */ 16029 #define PORT15_PPS_PPS8_Pos (8UL) /*!< PORT15 PPS: PPS8 (Bit 8) */ 16030 #define PORT15_PPS_PPS8_Msk (0x100UL) /*!< PORT15 PPS: PPS8 (Bitfield-Mask: 0x01) */ 16031 #define PORT15_PPS_PPS9_Pos (9UL) /*!< PORT15 PPS: PPS9 (Bit 9) */ 16032 #define PORT15_PPS_PPS9_Msk (0x200UL) /*!< PORT15 PPS: PPS9 (Bitfield-Mask: 0x01) */ 16033 #define PORT15_PPS_PPS10_Pos (10UL) /*!< PORT15 PPS: PPS10 (Bit 10) */ 16034 #define PORT15_PPS_PPS10_Msk (0x400UL) /*!< PORT15 PPS: PPS10 (Bitfield-Mask: 0x01) */ 16035 #define PORT15_PPS_PPS11_Pos (11UL) /*!< PORT15 PPS: PPS11 (Bit 11) */ 16036 #define PORT15_PPS_PPS11_Msk (0x800UL) /*!< PORT15 PPS: PPS11 (Bitfield-Mask: 0x01) */ 16037 #define PORT15_PPS_PPS12_Pos (12UL) /*!< PORT15 PPS: PPS12 (Bit 12) */ 16038 #define PORT15_PPS_PPS12_Msk (0x1000UL) /*!< PORT15 PPS: PPS12 (Bitfield-Mask: 0x01) */ 16039 #define PORT15_PPS_PPS13_Pos (13UL) /*!< PORT15 PPS: PPS13 (Bit 13) */ 16040 #define PORT15_PPS_PPS13_Msk (0x2000UL) /*!< PORT15 PPS: PPS13 (Bitfield-Mask: 0x01) */ 16041 #define PORT15_PPS_PPS14_Pos (14UL) /*!< PORT15 PPS: PPS14 (Bit 14) */ 16042 #define PORT15_PPS_PPS14_Msk (0x4000UL) /*!< PORT15 PPS: PPS14 (Bitfield-Mask: 0x01) */ 16043 #define PORT15_PPS_PPS15_Pos (15UL) /*!< PORT15 PPS: PPS15 (Bit 15) */ 16044 #define PORT15_PPS_PPS15_Msk (0x8000UL) /*!< PORT15 PPS: PPS15 (Bitfield-Mask: 0x01) */ 16045 16046 /* -------------------------------- PORT15_HWSEL -------------------------------- */ 16047 #define PORT15_HWSEL_HW0_Pos (0UL) /*!< PORT15 HWSEL: HW0 (Bit 0) */ 16048 #define PORT15_HWSEL_HW0_Msk (0x3UL) /*!< PORT15 HWSEL: HW0 (Bitfield-Mask: 0x03) */ 16049 #define PORT15_HWSEL_HW1_Pos (2UL) /*!< PORT15 HWSEL: HW1 (Bit 2) */ 16050 #define PORT15_HWSEL_HW1_Msk (0xcUL) /*!< PORT15 HWSEL: HW1 (Bitfield-Mask: 0x03) */ 16051 #define PORT15_HWSEL_HW2_Pos (4UL) /*!< PORT15 HWSEL: HW2 (Bit 4) */ 16052 #define PORT15_HWSEL_HW2_Msk (0x30UL) /*!< PORT15 HWSEL: HW2 (Bitfield-Mask: 0x03) */ 16053 #define PORT15_HWSEL_HW3_Pos (6UL) /*!< PORT15 HWSEL: HW3 (Bit 6) */ 16054 #define PORT15_HWSEL_HW3_Msk (0xc0UL) /*!< PORT15 HWSEL: HW3 (Bitfield-Mask: 0x03) */ 16055 #define PORT15_HWSEL_HW4_Pos (8UL) /*!< PORT15 HWSEL: HW4 (Bit 8) */ 16056 #define PORT15_HWSEL_HW4_Msk (0x300UL) /*!< PORT15 HWSEL: HW4 (Bitfield-Mask: 0x03) */ 16057 #define PORT15_HWSEL_HW5_Pos (10UL) /*!< PORT15 HWSEL: HW5 (Bit 10) */ 16058 #define PORT15_HWSEL_HW5_Msk (0xc00UL) /*!< PORT15 HWSEL: HW5 (Bitfield-Mask: 0x03) */ 16059 #define PORT15_HWSEL_HW6_Pos (12UL) /*!< PORT15 HWSEL: HW6 (Bit 12) */ 16060 #define PORT15_HWSEL_HW6_Msk (0x3000UL) /*!< PORT15 HWSEL: HW6 (Bitfield-Mask: 0x03) */ 16061 #define PORT15_HWSEL_HW7_Pos (14UL) /*!< PORT15 HWSEL: HW7 (Bit 14) */ 16062 #define PORT15_HWSEL_HW7_Msk (0xc000UL) /*!< PORT15 HWSEL: HW7 (Bitfield-Mask: 0x03) */ 16063 #define PORT15_HWSEL_HW8_Pos (16UL) /*!< PORT15 HWSEL: HW8 (Bit 16) */ 16064 #define PORT15_HWSEL_HW8_Msk (0x30000UL) /*!< PORT15 HWSEL: HW8 (Bitfield-Mask: 0x03) */ 16065 #define PORT15_HWSEL_HW9_Pos (18UL) /*!< PORT15 HWSEL: HW9 (Bit 18) */ 16066 #define PORT15_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT15 HWSEL: HW9 (Bitfield-Mask: 0x03) */ 16067 #define PORT15_HWSEL_HW10_Pos (20UL) /*!< PORT15 HWSEL: HW10 (Bit 20) */ 16068 #define PORT15_HWSEL_HW10_Msk (0x300000UL) /*!< PORT15 HWSEL: HW10 (Bitfield-Mask: 0x03) */ 16069 #define PORT15_HWSEL_HW11_Pos (22UL) /*!< PORT15 HWSEL: HW11 (Bit 22) */ 16070 #define PORT15_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT15 HWSEL: HW11 (Bitfield-Mask: 0x03) */ 16071 #define PORT15_HWSEL_HW12_Pos (24UL) /*!< PORT15 HWSEL: HW12 (Bit 24) */ 16072 #define PORT15_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT15 HWSEL: HW12 (Bitfield-Mask: 0x03) */ 16073 #define PORT15_HWSEL_HW13_Pos (26UL) /*!< PORT15 HWSEL: HW13 (Bit 26) */ 16074 #define PORT15_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT15 HWSEL: HW13 (Bitfield-Mask: 0x03) */ 16075 #define PORT15_HWSEL_HW14_Pos (28UL) /*!< PORT15 HWSEL: HW14 (Bit 28) */ 16076 #define PORT15_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT15 HWSEL: HW14 (Bitfield-Mask: 0x03) */ 16077 #define PORT15_HWSEL_HW15_Pos (30UL) /*!< PORT15 HWSEL: HW15 (Bit 30) */ 16078 #define PORT15_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT15 HWSEL: HW15 (Bitfield-Mask: 0x03) */ 16079 16080 16081 16082 /* ================================================================================ */ 16083 /* ================ Peripheral memory map ================ */ 16084 /* ================================================================================ */ 16085 16086 #define PPB_BASE 0xE000E000UL 16087 #define DLR_BASE 0x50004900UL 16088 #define ERU0_BASE 0x50004800UL 16089 #define ERU1_BASE 0x40044000UL 16090 #define GPDMA0_BASE 0x500142C0UL 16091 #define GPDMA0_CH0_BASE 0x50014000UL 16092 #define GPDMA0_CH1_BASE 0x50014058UL 16093 #define GPDMA0_CH2_BASE 0x500140B0UL 16094 #define GPDMA0_CH3_BASE 0x50014108UL 16095 #define GPDMA0_CH4_BASE 0x50014160UL 16096 #define GPDMA0_CH5_BASE 0x500141B8UL 16097 #define GPDMA0_CH6_BASE 0x50014210UL 16098 #define GPDMA0_CH7_BASE 0x50014268UL 16099 #define GPDMA1_BASE 0x500182C0UL 16100 #define GPDMA1_CH0_BASE 0x50018000UL 16101 #define GPDMA1_CH1_BASE 0x50018058UL 16102 #define GPDMA1_CH2_BASE 0x500180B0UL 16103 #define GPDMA1_CH3_BASE 0x50018108UL 16104 #define FCE_BASE 0x50020000UL 16105 #define FCE_KE0_BASE 0x50020020UL 16106 #define FCE_KE1_BASE 0x50020040UL 16107 #define FCE_KE2_BASE 0x50020060UL 16108 #define FCE_KE3_BASE 0x50020080UL 16109 #define PBA0_BASE 0x40000000UL 16110 #define PBA1_BASE 0x48000000UL 16111 #define FLASH0_BASE 0x58001000UL 16112 #define PREF_BASE 0x58004000UL 16113 #define PMU0_BASE 0x58000508UL 16114 #define WDT_BASE 0x50008000UL 16115 #define RTC_BASE 0x50004A00UL 16116 #define SCU_CLK_BASE 0x50004600UL 16117 #define SCU_OSC_BASE 0x50004700UL 16118 #define SCU_PLL_BASE 0x50004710UL 16119 #define SCU_GENERAL_BASE 0x50004000UL 16120 #define SCU_INTERRUPT_BASE 0x50004074UL 16121 #define SCU_PARITY_BASE 0x5000413CUL 16122 #define SCU_TRAP_BASE 0x50004160UL 16123 #define SCU_HIBERNATE_BASE 0x50004300UL 16124 #define SCU_POWER_BASE 0x50004200UL 16125 #define SCU_RESET_BASE 0x50004400UL 16126 #define LEDTS0_BASE 0x48010000UL 16127 #define SDMMC_BASE 0x4801C000UL 16128 #define EBU_BASE 0x58008000UL 16129 #define ETH0_CON_BASE 0x50004040UL 16130 #define ETH0_BASE 0x5000C000UL 16131 #define USB0_BASE 0x50040000UL 16132 #define USB_EP_BASE 0x50040900UL 16133 #define USB0_EP1_BASE 0x50040920UL 16134 #define USB0_EP2_BASE 0x50040940UL 16135 #define USB0_EP3_BASE 0x50040960UL 16136 #define USB0_EP4_BASE 0x50040980UL 16137 #define USB0_EP5_BASE 0x500409A0UL 16138 #define USB0_EP6_BASE 0x500409C0UL 16139 #define USB0_CH0_BASE 0x50040500UL 16140 #define USB0_CH1_BASE 0x50040520UL 16141 #define USB0_CH2_BASE 0x50040540UL 16142 #define USB0_CH3_BASE 0x50040560UL 16143 #define USB0_CH4_BASE 0x50040580UL 16144 #define USB0_CH5_BASE 0x500405A0UL 16145 #define USB0_CH6_BASE 0x500405C0UL 16146 #define USB0_CH7_BASE 0x500405E0UL 16147 #define USB0_CH8_BASE 0x50040600UL 16148 #define USB0_CH9_BASE 0x50040620UL 16149 #define USB0_CH10_BASE 0x50040640UL 16150 #define USB0_CH11_BASE 0x50040660UL 16151 #define USB0_CH12_BASE 0x50040680UL 16152 #define USB0_CH13_BASE 0x500406A0UL 16153 #define USIC0_BASE 0x40030008UL 16154 #define USIC1_BASE 0x48020008UL 16155 #define USIC2_BASE 0x48024008UL 16156 #define USIC0_CH0_BASE 0x40030000UL 16157 #define USIC0_CH1_BASE 0x40030200UL 16158 #define USIC1_CH0_BASE 0x48020000UL 16159 #define USIC1_CH1_BASE 0x48020200UL 16160 #define USIC2_CH0_BASE 0x48024000UL 16161 #define USIC2_CH1_BASE 0x48024200UL 16162 #define CAN_BASE 0x48014000UL 16163 #define CAN_NODE0_BASE 0x48014200UL 16164 #define CAN_NODE1_BASE 0x48014300UL 16165 #define CAN_NODE2_BASE 0x48014400UL 16166 #define CAN_MO0_BASE 0x48015000UL 16167 #define CAN_MO1_BASE 0x48015020UL 16168 #define CAN_MO2_BASE 0x48015040UL 16169 #define CAN_MO3_BASE 0x48015060UL 16170 #define CAN_MO4_BASE 0x48015080UL 16171 #define CAN_MO5_BASE 0x480150A0UL 16172 #define CAN_MO6_BASE 0x480150C0UL 16173 #define CAN_MO7_BASE 0x480150E0UL 16174 #define CAN_MO8_BASE 0x48015100UL 16175 #define CAN_MO9_BASE 0x48015120UL 16176 #define CAN_MO10_BASE 0x48015140UL 16177 #define CAN_MO11_BASE 0x48015160UL 16178 #define CAN_MO12_BASE 0x48015180UL 16179 #define CAN_MO13_BASE 0x480151A0UL 16180 #define CAN_MO14_BASE 0x480151C0UL 16181 #define CAN_MO15_BASE 0x480151E0UL 16182 #define CAN_MO16_BASE 0x48015200UL 16183 #define CAN_MO17_BASE 0x48015220UL 16184 #define CAN_MO18_BASE 0x48015240UL 16185 #define CAN_MO19_BASE 0x48015260UL 16186 #define CAN_MO20_BASE 0x48015280UL 16187 #define CAN_MO21_BASE 0x480152A0UL 16188 #define CAN_MO22_BASE 0x480152C0UL 16189 #define CAN_MO23_BASE 0x480152E0UL 16190 #define CAN_MO24_BASE 0x48015300UL 16191 #define CAN_MO25_BASE 0x48015320UL 16192 #define CAN_MO26_BASE 0x48015340UL 16193 #define CAN_MO27_BASE 0x48015360UL 16194 #define CAN_MO28_BASE 0x48015380UL 16195 #define CAN_MO29_BASE 0x480153A0UL 16196 #define CAN_MO30_BASE 0x480153C0UL 16197 #define CAN_MO31_BASE 0x480153E0UL 16198 #define CAN_MO32_BASE 0x48015400UL 16199 #define CAN_MO33_BASE 0x48015420UL 16200 #define CAN_MO34_BASE 0x48015440UL 16201 #define CAN_MO35_BASE 0x48015460UL 16202 #define CAN_MO36_BASE 0x48015480UL 16203 #define CAN_MO37_BASE 0x480154A0UL 16204 #define CAN_MO38_BASE 0x480154C0UL 16205 #define CAN_MO39_BASE 0x480154E0UL 16206 #define CAN_MO40_BASE 0x48015500UL 16207 #define CAN_MO41_BASE 0x48015520UL 16208 #define CAN_MO42_BASE 0x48015540UL 16209 #define CAN_MO43_BASE 0x48015560UL 16210 #define CAN_MO44_BASE 0x48015580UL 16211 #define CAN_MO45_BASE 0x480155A0UL 16212 #define CAN_MO46_BASE 0x480155C0UL 16213 #define CAN_MO47_BASE 0x480155E0UL 16214 #define CAN_MO48_BASE 0x48015600UL 16215 #define CAN_MO49_BASE 0x48015620UL 16216 #define CAN_MO50_BASE 0x48015640UL 16217 #define CAN_MO51_BASE 0x48015660UL 16218 #define CAN_MO52_BASE 0x48015680UL 16219 #define CAN_MO53_BASE 0x480156A0UL 16220 #define CAN_MO54_BASE 0x480156C0UL 16221 #define CAN_MO55_BASE 0x480156E0UL 16222 #define CAN_MO56_BASE 0x48015700UL 16223 #define CAN_MO57_BASE 0x48015720UL 16224 #define CAN_MO58_BASE 0x48015740UL 16225 #define CAN_MO59_BASE 0x48015760UL 16226 #define CAN_MO60_BASE 0x48015780UL 16227 #define CAN_MO61_BASE 0x480157A0UL 16228 #define CAN_MO62_BASE 0x480157C0UL 16229 #define CAN_MO63_BASE 0x480157E0UL 16230 #define VADC_BASE 0x40004000UL 16231 #define VADC_G0_BASE 0x40004400UL 16232 #define VADC_G1_BASE 0x40004800UL 16233 #define VADC_G2_BASE 0x40004C00UL 16234 #define VADC_G3_BASE 0x40005000UL 16235 #define DSD_BASE 0x40008000UL 16236 #define DSD_CH0_BASE 0x40008100UL 16237 #define DSD_CH1_BASE 0x40008200UL 16238 #define DSD_CH2_BASE 0x40008300UL 16239 #define DSD_CH3_BASE 0x40008400UL 16240 #define DAC_BASE 0x48018000UL 16241 #define CCU40_BASE 0x4000C000UL 16242 #define CCU41_BASE 0x40010000UL 16243 #define CCU42_BASE 0x40014000UL 16244 #define CCU43_BASE 0x48004000UL 16245 #define CCU40_CC40_BASE 0x4000C100UL 16246 #define CCU40_CC41_BASE 0x4000C200UL 16247 #define CCU40_CC42_BASE 0x4000C300UL 16248 #define CCU40_CC43_BASE 0x4000C400UL 16249 #define CCU41_CC40_BASE 0x40010100UL 16250 #define CCU41_CC41_BASE 0x40010200UL 16251 #define CCU41_CC42_BASE 0x40010300UL 16252 #define CCU41_CC43_BASE 0x40010400UL 16253 #define CCU42_CC40_BASE 0x40014100UL 16254 #define CCU42_CC41_BASE 0x40014200UL 16255 #define CCU42_CC42_BASE 0x40014300UL 16256 #define CCU42_CC43_BASE 0x40014400UL 16257 #define CCU43_CC40_BASE 0x48004100UL 16258 #define CCU43_CC41_BASE 0x48004200UL 16259 #define CCU43_CC42_BASE 0x48004300UL 16260 #define CCU43_CC43_BASE 0x48004400UL 16261 #define CCU80_BASE 0x40020000UL 16262 #define CCU81_BASE 0x40024000UL 16263 #define CCU80_CC80_BASE 0x40020100UL 16264 #define CCU80_CC81_BASE 0x40020200UL 16265 #define CCU80_CC82_BASE 0x40020300UL 16266 #define CCU80_CC83_BASE 0x40020400UL 16267 #define CCU81_CC80_BASE 0x40024100UL 16268 #define CCU81_CC81_BASE 0x40024200UL 16269 #define CCU81_CC82_BASE 0x40024300UL 16270 #define CCU81_CC83_BASE 0x40024400UL 16271 #define POSIF0_BASE 0x40028000UL 16272 #define POSIF1_BASE 0x4002C000UL 16273 #define PORT0_BASE 0x48028000UL 16274 #define PORT1_BASE 0x48028100UL 16275 #define PORT2_BASE 0x48028200UL 16276 #define PORT3_BASE 0x48028300UL 16277 #define PORT4_BASE 0x48028400UL 16278 #define PORT5_BASE 0x48028500UL 16279 #define PORT6_BASE 0x48028600UL 16280 #define PORT14_BASE 0x48028E00UL 16281 #define PORT15_BASE 0x48028F00UL 16282 16283 16284 /* ================================================================================ */ 16285 /* ================ Peripheral declaration ================ */ 16286 /* ================================================================================ */ 16287 16288 #define PPB ((PPB_Type *) PPB_BASE) 16289 #define DLR ((DLR_GLOBAL_TypeDef *) DLR_BASE) 16290 #define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE) 16291 #define ERU1 ((ERU_GLOBAL_TypeDef *) ERU1_BASE) 16292 #define GPDMA0 ((GPDMA0_GLOBAL_TypeDef *) GPDMA0_BASE) 16293 #define GPDMA0_CH0 ((GPDMA0_CH_TypeDef *) GPDMA0_CH0_BASE) 16294 #define GPDMA0_CH1 ((GPDMA0_CH_TypeDef *) GPDMA0_CH1_BASE) 16295 #define GPDMA0_CH2 ((GPDMA0_CH_TypeDef *) GPDMA0_CH2_BASE) 16296 #define GPDMA0_CH3 ((GPDMA0_CH_TypeDef *) GPDMA0_CH3_BASE) 16297 #define GPDMA0_CH4 ((GPDMA0_CH_TypeDef *) GPDMA0_CH4_BASE) 16298 #define GPDMA0_CH5 ((GPDMA0_CH_TypeDef *) GPDMA0_CH5_BASE) 16299 #define GPDMA0_CH6 ((GPDMA0_CH_TypeDef *) GPDMA0_CH6_BASE) 16300 #define GPDMA0_CH7 ((GPDMA0_CH_TypeDef *) GPDMA0_CH7_BASE) 16301 #define GPDMA1 ((GPDMA1_GLOBAL_TypeDef *) GPDMA1_BASE) 16302 #define GPDMA1_CH0 ((GPDMA1_CH_TypeDef *) GPDMA1_CH0_BASE) 16303 #define GPDMA1_CH1 ((GPDMA1_CH_TypeDef *) GPDMA1_CH1_BASE) 16304 #define GPDMA1_CH2 ((GPDMA1_CH_TypeDef *) GPDMA1_CH2_BASE) 16305 #define GPDMA1_CH3 ((GPDMA1_CH_TypeDef *) GPDMA1_CH3_BASE) 16306 #define FCE ((FCE_GLOBAL_TypeDef *) FCE_BASE) 16307 #define FCE_KE0 ((FCE_KE_TypeDef *) FCE_KE0_BASE) 16308 #define FCE_KE1 ((FCE_KE_TypeDef *) FCE_KE1_BASE) 16309 #define FCE_KE2 ((FCE_KE_TypeDef *) FCE_KE2_BASE) 16310 #define FCE_KE3 ((FCE_KE_TypeDef *) FCE_KE3_BASE) 16311 #define PBA0 ((PBA_GLOBAL_TypeDef *) PBA0_BASE) 16312 #define PBA1 ((PBA_GLOBAL_TypeDef *) PBA1_BASE) 16313 #define FLASH0 ((FLASH0_GLOBAL_TypeDef *) FLASH0_BASE) 16314 #define PREF ((PREF_GLOBAL_TypeDef *) PREF_BASE) 16315 #define PMU0 ((PMU0_GLOBAL_TypeDef *) PMU0_BASE) 16316 #define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE) 16317 #define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE) 16318 #define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE) 16319 #define SCU_OSC ((SCU_OSC_TypeDef *) SCU_OSC_BASE) 16320 #define SCU_PLL ((SCU_PLL_TypeDef *) SCU_PLL_BASE) 16321 #define SCU_GENERAL ((SCU_GENERAL_TypeDef *) SCU_GENERAL_BASE) 16322 #define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE) 16323 #define SCU_PARITY ((SCU_PARITY_TypeDef *) SCU_PARITY_BASE) 16324 #define SCU_TRAP ((SCU_TRAP_TypeDef *) SCU_TRAP_BASE) 16325 #define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *) SCU_HIBERNATE_BASE) 16326 #define SCU_POWER ((SCU_POWER_TypeDef *) SCU_POWER_BASE) 16327 #define SCU_RESET ((SCU_RESET_TypeDef *) SCU_RESET_BASE) 16328 #define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *) LEDTS0_BASE) 16329 #define SDMMC ((SDMMC_GLOBAL_TypeDef *) SDMMC_BASE) 16330 #define EBU ((EBU_Type *) EBU_BASE) 16331 #if UC_DEVICE == XMC4500 16332 #define ETH0_CON ((ETH0_CON_GLOBAL_TypeDef *) ETH0_CON_BASE) 16333 #define ETH0 ((ETH_GLOBAL_TypeDef *) ETH0_BASE) 16334 #endif 16335 #if UC_DEVICE == XMC4500 || UC_DEVICE == XMC4502 16336 #define USB0 ((USB0_GLOBAL_TypeDef *) USB0_BASE) 16337 #define USB0_EP0 ((USB0_EP0_TypeDef *) USB_EP_BASE) 16338 #define USB0_EP1 ((USB0_EP_TypeDef *) USB0_EP1_BASE) 16339 #define USB0_EP2 ((USB0_EP_TypeDef *) USB0_EP2_BASE) 16340 #define USB0_EP3 ((USB0_EP_TypeDef *) USB0_EP3_BASE) 16341 #define USB0_EP4 ((USB0_EP_TypeDef *) USB0_EP4_BASE) 16342 #define USB0_EP5 ((USB0_EP_TypeDef *) USB0_EP5_BASE) 16343 #define USB0_EP6 ((USB0_EP_TypeDef *) USB0_EP6_BASE) 16344 #define USB0_CH0 ((USB0_CH_TypeDef *) USB0_CH0_BASE) 16345 #define USB0_CH1 ((USB0_CH_TypeDef *) USB0_CH1_BASE) 16346 #define USB0_CH2 ((USB0_CH_TypeDef *) USB0_CH2_BASE) 16347 #define USB0_CH3 ((USB0_CH_TypeDef *) USB0_CH3_BASE) 16348 #define USB0_CH4 ((USB0_CH_TypeDef *) USB0_CH4_BASE) 16349 #define USB0_CH5 ((USB0_CH_TypeDef *) USB0_CH5_BASE) 16350 #define USB0_CH6 ((USB0_CH_TypeDef *) USB0_CH6_BASE) 16351 #define USB0_CH7 ((USB0_CH_TypeDef *) USB0_CH7_BASE) 16352 #define USB0_CH8 ((USB0_CH_TypeDef *) USB0_CH8_BASE) 16353 #define USB0_CH9 ((USB0_CH_TypeDef *) USB0_CH9_BASE) 16354 #define USB0_CH10 ((USB0_CH_TypeDef *) USB0_CH10_BASE) 16355 #define USB0_CH11 ((USB0_CH_TypeDef *) USB0_CH11_BASE) 16356 #define USB0_CH12 ((USB0_CH_TypeDef *) USB0_CH12_BASE) 16357 #define USB0_CH13 ((USB0_CH_TypeDef *) USB0_CH13_BASE) 16358 #endif 16359 #define USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE) 16360 #define USIC1 ((USIC_GLOBAL_TypeDef *) USIC1_BASE) 16361 #define USIC2 ((USIC_GLOBAL_TypeDef *) USIC2_BASE) 16362 #define USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE) 16363 #define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE) 16364 #define USIC1_CH0 ((USIC_CH_TypeDef *) USIC1_CH0_BASE) 16365 #define USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE) 16366 #define USIC2_CH0 ((USIC_CH_TypeDef *) USIC2_CH0_BASE) 16367 #define USIC2_CH1 ((USIC_CH_TypeDef *) USIC2_CH1_BASE) 16368 #if UC_DEVICE == XMC4500 || UC_DEVICE == XMC4502 16369 #define CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE) 16370 #define CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE) 16371 #define CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE) 16372 #define CAN_NODE2 ((CAN_NODE_TypeDef *) CAN_NODE2_BASE) 16373 #define CAN_MO0 ((CAN_MO_TypeDef *) CAN_MO0_BASE) 16374 #define CAN_MO1 ((CAN_MO_TypeDef *) CAN_MO1_BASE) 16375 #define CAN_MO2 ((CAN_MO_TypeDef *) CAN_MO2_BASE) 16376 #define CAN_MO3 ((CAN_MO_TypeDef *) CAN_MO3_BASE) 16377 #define CAN_MO4 ((CAN_MO_TypeDef *) CAN_MO4_BASE) 16378 #define CAN_MO5 ((CAN_MO_TypeDef *) CAN_MO5_BASE) 16379 #define CAN_MO6 ((CAN_MO_TypeDef *) CAN_MO6_BASE) 16380 #define CAN_MO7 ((CAN_MO_TypeDef *) CAN_MO7_BASE) 16381 #define CAN_MO8 ((CAN_MO_TypeDef *) CAN_MO8_BASE) 16382 #define CAN_MO9 ((CAN_MO_TypeDef *) CAN_MO9_BASE) 16383 #define CAN_MO10 ((CAN_MO_TypeDef *) CAN_MO10_BASE) 16384 #define CAN_MO11 ((CAN_MO_TypeDef *) CAN_MO11_BASE) 16385 #define CAN_MO12 ((CAN_MO_TypeDef *) CAN_MO12_BASE) 16386 #define CAN_MO13 ((CAN_MO_TypeDef *) CAN_MO13_BASE) 16387 #define CAN_MO14 ((CAN_MO_TypeDef *) CAN_MO14_BASE) 16388 #define CAN_MO15 ((CAN_MO_TypeDef *) CAN_MO15_BASE) 16389 #define CAN_MO16 ((CAN_MO_TypeDef *) CAN_MO16_BASE) 16390 #define CAN_MO17 ((CAN_MO_TypeDef *) CAN_MO17_BASE) 16391 #define CAN_MO18 ((CAN_MO_TypeDef *) CAN_MO18_BASE) 16392 #define CAN_MO19 ((CAN_MO_TypeDef *) CAN_MO19_BASE) 16393 #define CAN_MO20 ((CAN_MO_TypeDef *) CAN_MO20_BASE) 16394 #define CAN_MO21 ((CAN_MO_TypeDef *) CAN_MO21_BASE) 16395 #define CAN_MO22 ((CAN_MO_TypeDef *) CAN_MO22_BASE) 16396 #define CAN_MO23 ((CAN_MO_TypeDef *) CAN_MO23_BASE) 16397 #define CAN_MO24 ((CAN_MO_TypeDef *) CAN_MO24_BASE) 16398 #define CAN_MO25 ((CAN_MO_TypeDef *) CAN_MO25_BASE) 16399 #define CAN_MO26 ((CAN_MO_TypeDef *) CAN_MO26_BASE) 16400 #define CAN_MO27 ((CAN_MO_TypeDef *) CAN_MO27_BASE) 16401 #define CAN_MO28 ((CAN_MO_TypeDef *) CAN_MO28_BASE) 16402 #define CAN_MO29 ((CAN_MO_TypeDef *) CAN_MO29_BASE) 16403 #define CAN_MO30 ((CAN_MO_TypeDef *) CAN_MO30_BASE) 16404 #define CAN_MO31 ((CAN_MO_TypeDef *) CAN_MO31_BASE) 16405 #define CAN_MO32 ((CAN_MO_TypeDef *) CAN_MO32_BASE) 16406 #define CAN_MO33 ((CAN_MO_TypeDef *) CAN_MO33_BASE) 16407 #define CAN_MO34 ((CAN_MO_TypeDef *) CAN_MO34_BASE) 16408 #define CAN_MO35 ((CAN_MO_TypeDef *) CAN_MO35_BASE) 16409 #define CAN_MO36 ((CAN_MO_TypeDef *) CAN_MO36_BASE) 16410 #define CAN_MO37 ((CAN_MO_TypeDef *) CAN_MO37_BASE) 16411 #define CAN_MO38 ((CAN_MO_TypeDef *) CAN_MO38_BASE) 16412 #define CAN_MO39 ((CAN_MO_TypeDef *) CAN_MO39_BASE) 16413 #define CAN_MO40 ((CAN_MO_TypeDef *) CAN_MO40_BASE) 16414 #define CAN_MO41 ((CAN_MO_TypeDef *) CAN_MO41_BASE) 16415 #define CAN_MO42 ((CAN_MO_TypeDef *) CAN_MO42_BASE) 16416 #define CAN_MO43 ((CAN_MO_TypeDef *) CAN_MO43_BASE) 16417 #define CAN_MO44 ((CAN_MO_TypeDef *) CAN_MO44_BASE) 16418 #define CAN_MO45 ((CAN_MO_TypeDef *) CAN_MO45_BASE) 16419 #define CAN_MO46 ((CAN_MO_TypeDef *) CAN_MO46_BASE) 16420 #define CAN_MO47 ((CAN_MO_TypeDef *) CAN_MO47_BASE) 16421 #define CAN_MO48 ((CAN_MO_TypeDef *) CAN_MO48_BASE) 16422 #define CAN_MO49 ((CAN_MO_TypeDef *) CAN_MO49_BASE) 16423 #define CAN_MO50 ((CAN_MO_TypeDef *) CAN_MO50_BASE) 16424 #define CAN_MO51 ((CAN_MO_TypeDef *) CAN_MO51_BASE) 16425 #define CAN_MO52 ((CAN_MO_TypeDef *) CAN_MO52_BASE) 16426 #define CAN_MO53 ((CAN_MO_TypeDef *) CAN_MO53_BASE) 16427 #define CAN_MO54 ((CAN_MO_TypeDef *) CAN_MO54_BASE) 16428 #define CAN_MO55 ((CAN_MO_TypeDef *) CAN_MO55_BASE) 16429 #define CAN_MO56 ((CAN_MO_TypeDef *) CAN_MO56_BASE) 16430 #define CAN_MO57 ((CAN_MO_TypeDef *) CAN_MO57_BASE) 16431 #define CAN_MO58 ((CAN_MO_TypeDef *) CAN_MO58_BASE) 16432 #define CAN_MO59 ((CAN_MO_TypeDef *) CAN_MO59_BASE) 16433 #define CAN_MO60 ((CAN_MO_TypeDef *) CAN_MO60_BASE) 16434 #define CAN_MO61 ((CAN_MO_TypeDef *) CAN_MO61_BASE) 16435 #define CAN_MO62 ((CAN_MO_TypeDef *) CAN_MO62_BASE) 16436 #define CAN_MO63 ((CAN_MO_TypeDef *) CAN_MO63_BASE) 16437 #endif /* UC_DEVICE == XMC4500 || UC_DEVICE == XMC4502 */ 16438 #define VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE) 16439 #define VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE) 16440 #define VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE) 16441 #define VADC_G2 ((VADC_G_TypeDef *) VADC_G2_BASE) 16442 #define VADC_G3 ((VADC_G_TypeDef *) VADC_G3_BASE) 16443 #define DSD ((DSD_GLOBAL_TypeDef *) DSD_BASE) 16444 #define DSD_CH0 ((DSD_CH_TypeDef *) DSD_CH0_BASE) 16445 #define DSD_CH1 ((DSD_CH_TypeDef *) DSD_CH1_BASE) 16446 #define DSD_CH2 ((DSD_CH_TypeDef *) DSD_CH2_BASE) 16447 #define DSD_CH3 ((DSD_CH_TypeDef *) DSD_CH3_BASE) 16448 #define DAC ((DAC_GLOBAL_TypeDef *) DAC_BASE) 16449 #define CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE) 16450 #define CCU41 ((CCU4_GLOBAL_TypeDef *) CCU41_BASE) 16451 #define CCU42 ((CCU4_GLOBAL_TypeDef *) CCU42_BASE) 16452 #define CCU43 ((CCU4_GLOBAL_TypeDef *) CCU43_BASE) 16453 #define CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE) 16454 #define CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE) 16455 #define CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE) 16456 #define CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE) 16457 #define CCU41_CC40 ((CCU4_CC4_TypeDef *) CCU41_CC40_BASE) 16458 #define CCU41_CC41 ((CCU4_CC4_TypeDef *) CCU41_CC41_BASE) 16459 #define CCU41_CC42 ((CCU4_CC4_TypeDef *) CCU41_CC42_BASE) 16460 #define CCU41_CC43 ((CCU4_CC4_TypeDef *) CCU41_CC43_BASE) 16461 #define CCU42_CC40 ((CCU4_CC4_TypeDef *) CCU42_CC40_BASE) 16462 #define CCU42_CC41 ((CCU4_CC4_TypeDef *) CCU42_CC41_BASE) 16463 #define CCU42_CC42 ((CCU4_CC4_TypeDef *) CCU42_CC42_BASE) 16464 #define CCU42_CC43 ((CCU4_CC4_TypeDef *) CCU42_CC43_BASE) 16465 #define CCU43_CC40 ((CCU4_CC4_TypeDef *) CCU43_CC40_BASE) 16466 #define CCU43_CC41 ((CCU4_CC4_TypeDef *) CCU43_CC41_BASE) 16467 #define CCU43_CC42 ((CCU4_CC4_TypeDef *) CCU43_CC42_BASE) 16468 #define CCU43_CC43 ((CCU4_CC4_TypeDef *) CCU43_CC43_BASE) 16469 #define CCU80 ((CCU8_GLOBAL_TypeDef *) CCU80_BASE) 16470 #define CCU81 ((CCU8_GLOBAL_TypeDef *) CCU81_BASE) 16471 #define CCU80_CC80 ((CCU8_CC8_TypeDef *) CCU80_CC80_BASE) 16472 #define CCU80_CC81 ((CCU8_CC8_TypeDef *) CCU80_CC81_BASE) 16473 #define CCU80_CC82 ((CCU8_CC8_TypeDef *) CCU80_CC82_BASE) 16474 #define CCU80_CC83 ((CCU8_CC8_TypeDef *) CCU80_CC83_BASE) 16475 #define CCU81_CC80 ((CCU8_CC8_TypeDef *) CCU81_CC80_BASE) 16476 #define CCU81_CC81 ((CCU8_CC8_TypeDef *) CCU81_CC81_BASE) 16477 #define CCU81_CC82 ((CCU8_CC8_TypeDef *) CCU81_CC82_BASE) 16478 #define CCU81_CC83 ((CCU8_CC8_TypeDef *) CCU81_CC83_BASE) 16479 #define POSIF0 ((POSIF_GLOBAL_TypeDef *) POSIF0_BASE) 16480 #define POSIF1 ((POSIF_GLOBAL_TypeDef *) POSIF1_BASE) 16481 #define PORT0 ((PORT0_Type *) PORT0_BASE) 16482 #define PORT1 ((PORT1_Type *) PORT1_BASE) 16483 #define PORT2 ((PORT2_Type *) PORT2_BASE) 16484 #define PORT3 ((PORT3_Type *) PORT3_BASE) 16485 #define PORT4 ((PORT4_Type *) PORT4_BASE) 16486 #define PORT5 ((PORT5_Type *) PORT5_BASE) 16487 #define PORT6 ((PORT6_Type *) PORT6_BASE) 16488 #define PORT14 ((PORT14_Type *) PORT14_BASE) 16489 #define PORT15 ((PORT15_Type *) PORT15_BASE) 16490 16491 16492 /** @} */ /* End of group Device_Peripheral_Registers */ 16493 /** @} */ /* End of group XMC4500 */ 16494 /** @} */ /* End of group Infineon */ 16495 16496 #ifdef __cplusplus 16497 } 16498 #endif 16499 16500 16501 #endif /* XMC4500_H */ 16502 16503