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Searched refs:write_timing (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_exmc.c109 exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
110 exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
111 exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
112 exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
113 exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; in exmc_norsram_struct_para_init()
177 …snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_… in exmc_norsram_init()
178 …(((exmc_norsram_init_struct->write_timing->asyn_address_holdtime -1U ) << SNWTCFG_WAHLD_OFFSET ) &… in exmc_norsram_init()
179 …(((exmc_norsram_init_struct->write_timing->asyn_data_setuptime -1U ) << SNWTCFG_WDSET_OFFSET ) & E… in exmc_norsram_init()
180 …(((exmc_norsram_init_struct->write_timing->bus_latency - 1U ) << SNWTCFG_WBUSLAT_OFFSET ) & EXMC_S… in exmc_norsram_init()
181 exmc_norsram_init_struct->write_timing->asyn_access_mode; in exmc_norsram_init()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_exmc.c145 exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
146 exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
147 exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
148 exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
149 exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; in exmc_norsram_struct_para_init()
228 …snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_… in exmc_norsram_init()
229 …(((exmc_norsram_init_struct->write_timing->asyn_address_holdtime -1U ) << SNWTCFG_WAHLD_OFFSET ) &… in exmc_norsram_init()
230 …(((exmc_norsram_init_struct->write_timing->asyn_data_setuptime -1U ) << SNWTCFG_WDSET_OFFSET ) & E… in exmc_norsram_init()
231 …(((exmc_norsram_init_struct->write_timing->bus_latency - 1U ) << SNWTCFG_WBUSLAT_OFFSET ) & EXMC_S… in exmc_norsram_init()
232 exmc_norsram_init_struct->write_timing->asyn_access_mode; in exmc_norsram_init()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_exmc.c145 exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
146 exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
147 exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
148 exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
149 exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; in exmc_norsram_struct_para_init()
214 …snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_… in exmc_norsram_init()
215 …(((exmc_norsram_init_struct->write_timing->asyn_address_holdtime -1U ) << SNWTCFG_WAHLD_OFFSET ) &… in exmc_norsram_init()
216 …(((exmc_norsram_init_struct->write_timing->asyn_data_setuptime -1U ) << SNWTCFG_WDSET_OFFSET ) & E… in exmc_norsram_init()
217 …(((exmc_norsram_init_struct->write_timing->bus_latency - 1U ) << SNWTCFG_WBUSLAT_OFFSET ) & EXMC_S… in exmc_norsram_init()
218 exmc_norsram_init_struct->write_timing->asyn_access_mode; in exmc_norsram_init()
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_exmc.c173 exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
174 exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
175 exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
176 exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
177 exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; in exmc_norsram_struct_para_init()
256 snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | in exmc_norsram_init()
257 … (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | in exmc_norsram_init()
258 … (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | in exmc_norsram_init()
259 (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | in exmc_norsram_init()
260 exmc_norsram_init_struct->write_timing->asyn_access_mode; in exmc_norsram_init()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_exmc.h116 …exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for wri… member
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_exmc.h187 …exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for wri… member
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_exmc.h187 …exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for wri… member
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_exmc.h279 …exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for wri… member