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Searched refs:read_write_timing (Results 1 – 10 of 10) sorted by relevance

/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_exmc.c100 exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
101 exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
102 exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
103 exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
104 exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; in exmc_norsram_struct_para_init()
105 exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; in exmc_norsram_struct_para_init()
106 exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; in exmc_norsram_struct_para_init()
162 …sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & … in exmc_norsram_init()
163 …(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET… in exmc_norsram_init()
164 …(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET )… in exmc_norsram_init()
[all …]
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_exmc.c88 exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
89 exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
90 exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
91 exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
128 …sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & … in exmc_norsram_init()
129 …(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET… in exmc_norsram_init()
130 …(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET )… in exmc_norsram_init()
131 …(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXM… in exmc_norsram_init()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_exmc.c136 exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
137 exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
138 exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
139 exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
140 exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; in exmc_norsram_struct_para_init()
141 exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; in exmc_norsram_struct_para_init()
142 exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; in exmc_norsram_struct_para_init()
213 …sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & … in exmc_norsram_init()
214 …(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET… in exmc_norsram_init()
215 …(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET )… in exmc_norsram_init()
[all …]
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_exmc.c136 exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
137 exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
138 exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
139 exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
140 exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; in exmc_norsram_struct_para_init()
141 exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; in exmc_norsram_struct_para_init()
142 exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; in exmc_norsram_struct_para_init()
199 …sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & … in exmc_norsram_init()
200 …(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET… in exmc_norsram_init()
201 …(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET )… in exmc_norsram_init()
[all …]
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_exmc.c164 exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; in exmc_norsram_struct_para_init()
165 exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; in exmc_norsram_struct_para_init()
166 exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; in exmc_norsram_struct_para_init()
167 exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; in exmc_norsram_struct_para_init()
168 exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; in exmc_norsram_struct_para_init()
169 exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; in exmc_norsram_struct_para_init()
170 exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; in exmc_norsram_struct_para_init()
241 sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | in exmc_norsram_init()
242 … (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | in exmc_norsram_init()
243 … (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | in exmc_norsram_init()
[all …]
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_exmc.h90 …exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for rea… member
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_exmc.h114 …exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for rea… member
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_exmc.h185 …exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for rea… member
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_exmc.h185 …exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for rea… member
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_exmc.h277 …exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for rea… member