Home
last modified time | relevance | path

Searched refs:USART5_CTL1_CLEN (Results 1 – 2 of 2) sorted by relevance

/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_usart.c695 ctl &= ~(USART5_CTL1_CLEN | USART5_CTL1_CPH | USART5_CTL1_CPL); in usart_synchronous_clock_config()
697 ctl |= (USART5_CTL1_CLEN & clen) | (USART5_CTL1_CPH & cph) | (USART5_CTL1_CPL & cpl); in usart_synchronous_clock_config()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_usart.h196 #define USART5_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ macro