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Searched refs:SPI_CTL1_NSSP (Results 1 – 14 of 14) sorted by relevance

/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_spi.c581 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
592 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_spi.c542 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
553 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_spi.c583 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
594 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_spi.c588 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
599 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_spi.c605 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
616 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_spi.c595 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
606 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_spi.c645 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
656 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_spi.h78 #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse … macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_spi.h80 #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse … macro
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_spi.h79 #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse … macro
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_spi.h83 #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse … macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_spi.h95 #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse … macro
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_spi.h88 #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse … macro
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_spi.h78 #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse … macro