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Searched refs:SPI_CTL1_ERRIE (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_spi.c621 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; in spi_i2s_interrupt_enable()
653 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); in spi_i2s_interrupt_disable()
694 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
699 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
704 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
709 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
714 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_spi.c647 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; in spi_i2s_interrupt_enable()
679 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); in spi_i2s_interrupt_disable()
720 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
725 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
730 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
735 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
740 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_spi.c693 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; in spi_i2s_interrupt_enable()
725 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); in spi_i2s_interrupt_disable()
766 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
771 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
776 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
781 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
786 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_spi.c700 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; in spi_i2s_interrupt_enable()
732 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); in spi_i2s_interrupt_disable()
773 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
778 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
783 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
788 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
793 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_spi.c733 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; in spi_i2s_interrupt_enable()
765 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); in spi_i2s_interrupt_disable()
806 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
811 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
816 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
821 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
826 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_spi.c761 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
766 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
771 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
776 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
781 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_spi.c823 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; in spi_i2s_interrupt_enable()
855 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); in spi_i2s_interrupt_disable()
896 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
901 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
906 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
911 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_spi.c808 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
813 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
818 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
823 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
828 reg2 = reg2 & SPI_CTL1_ERRIE; in spi_i2s_interrupt_flag_get()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_spi.h97 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interru… macro
252 #define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrup…
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_spi.h90 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interru… macro
245 #define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrup…
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_spi.h80 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interru… macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_spi.h82 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interru… macro
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_spi.h81 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interru… macro
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_spi.h85 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interru… macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_spi.h101 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interru… macro
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_spi.h80 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interru… macro