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Searched refs:SPI_BASE (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_spi.h45 #define SPI0 (SPI_BASE + 0x0000F800U)
46 #define SPI1 SPI_BASE
47 #define SPI2 (SPI_BASE + 0x00000400U)
48 #define SPI3 (SPI_BASE + 0x0000FC00U)
49 #define SPI4 (SPI_BASE + 0x00011800U)
50 #define SPI5 (SPI_BASE + 0x00011C00U)
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_spi.h42 #define SPI0 (SPI_BASE + 0x0000F800U)
43 #define SPI1 SPI_BASE
44 #define SPI2 (SPI_BASE + 0x00000400U)
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_spi.h43 #define SPI0 (SPI_BASE + 0x0000F800U)
44 #define SPI1 SPI_BASE
45 #define SPI2 (SPI_BASE + 0x00000400U)
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_spi.h46 #define SPI0 (SPI_BASE + 0x0000F800U)
47 #define SPI1 SPI_BASE
48 #define SPI2 (SPI_BASE + 0x00000400U)
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_spi.h43 #define SPI0 (SPI_BASE + 0x0000F800U)
44 #define SPI1 SPI_BASE
45 #define SPI2 (SPI_BASE + 0x00000400U)
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_spi.h43 #define SPI0 (SPI_BASE + 0x0000F800U)
44 #define SPI1 SPI_BASE
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_spi.h40 #define SPI0 (SPI_BASE + 0x0000F800U)
41 #define SPI1 SPI_BASE
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_spi.h41 #define SPI0 (SPI_BASE + 0x0000F800U)
42 #define SPI1 SPI_BASE
/hal_gigadevice-latest/gd32vf103/riscv/include/
Dgd32vf103.h211 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address … macro
/hal_gigadevice-latest/gd32f3x0/cmsis/gd/gd32f3x0/include/
Dgd32f3x0.h207 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ macro
/hal_gigadevice-latest/gd32f403/cmsis/gd/gd32f403/include/
Dgd32f403.h214 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address … macro
/hal_gigadevice-latest/gd32e10x/cmsis/gd/gd32e10x/include/
Dgd32e10x.h223 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address … macro
/hal_gigadevice-latest/gd32l23x/cmsis/gd/gd32l23x/include/
Dgd32l23x.h208 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ macro
/hal_gigadevice-latest/gd32a50x/cmsis/gd/gd32a50x/include/
Dgd32a50x.h214 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ macro
/hal_gigadevice-latest/gd32f4xx/cmsis/gd/gd32f4xx/include/
Dgd32f4xx.h325 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address … macro
/hal_gigadevice-latest/gd32e50x/cmsis/gd/gd32e50x/include/
Dgd32e50x.h495 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ macro