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Searched refs:SDIO_CLKCTL_DIV8 (Results 1 – 6 of 6) sorted by relevance

/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_sdio.c75 …(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL… in sdio_clock_config()
78 clock_config |= SDIO_CLKCTL_DIV8; in sdio_clock_config()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_sdio.c83 …(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL… in sdio_clock_config()
86 clock_config |= SDIO_CLKCTL_DIV8; in sdio_clock_config()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_sdio.c85 …(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL… in sdio_clock_config()
88 clock_config |= SDIO_CLKCTL_DIV8; in sdio_clock_config()
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_sdio.h78 #define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_sdio.h77 #define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_sdio.h77 #define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ macro