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Searched refs:RCU_SCSS_PLLP (Results 1 – 2 of 2) sorted by relevance

/hal_gigadevice-latest/gd32f4xx/cmsis/gd/gd32f4xx/source/
Dsystem_gd32f4xx.c349 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_120m_irc16m()
417 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_120m_8m_hxtal()
485 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_120m_25m_hxtal()
553 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_168m_irc16m()
617 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_168m_8m_hxtal()
685 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_168m_25m_hxtal()
753 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_200m_irc16m()
821 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_200m_8m_hxtal()
889 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_200m_25m_hxtal()
957 while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ in system_clock_240m_irc16m()
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/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_rcu.h825 #define RCU_SCSS_PLLP CFG0_SCSS(2) /*!< system clock source… macro