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Searched refs:RCU_I2C0RST (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_i2c.c57 rcu_periph_reset_enable(RCU_I2C0RST); in i2c_deinit()
58 rcu_periph_reset_disable(RCU_I2C0RST); in i2c_deinit()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_i2c.c61 rcu_periph_reset_enable(RCU_I2C0RST); in i2c_deinit()
62 rcu_periph_reset_disable(RCU_I2C0RST); in i2c_deinit()
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_i2c.c58 rcu_periph_reset_enable(RCU_I2C0RST); in i2c_deinit()
59 rcu_periph_reset_disable(RCU_I2C0RST); in i2c_deinit()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_i2c.c64 rcu_periph_reset_enable(RCU_I2C0RST); in i2c_deinit()
65 rcu_periph_reset_disable(RCU_I2C0RST); in i2c_deinit()
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_i2c.c64 rcu_periph_reset_enable(RCU_I2C0RST); in i2c_deinit()
65 rcu_periph_reset_disable(RCU_I2C0RST); in i2c_deinit()
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_i2c.c60 rcu_periph_reset_enable(RCU_I2C0RST); in i2c_deinit()
61 rcu_periph_reset_disable(RCU_I2C0RST); in i2c_deinit()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_i2c.c60 rcu_periph_reset_enable(RCU_I2C0RST); in i2c_deinit()
61 rcu_periph_reset_disable(RCU_I2C0RST); in i2c_deinit()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_i2c.c72 rcu_periph_reset_enable(RCU_I2C0RST); in i2c_deinit()
73 rcu_periph_reset_disable(RCU_I2C0RST); in i2c_deinit()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_rcu.h330 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ enumerator
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_rcu.h359RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ enumerator
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_rcu.h369 RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */ enumerator
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_rcu.h390 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ enumerator
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_rcu.h394 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ enumerator
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_rcu.h379 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 reset */ enumerator
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_rcu.h699 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ enumerator
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_rcu.h661 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ enumerator