| /hal_gigadevice-latest/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_gpio.c | 60 rcu_periph_reset_enable(RCU_GPIOCRST); in gpio_deinit()
61 rcu_periph_reset_disable(RCU_GPIOCRST); in gpio_deinit()
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_gpio.c | 63 rcu_periph_reset_enable(RCU_GPIOCRST); in gpio_deinit()
64 rcu_periph_reset_disable(RCU_GPIOCRST); in gpio_deinit()
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_gpio.c | 60 rcu_periph_reset_enable(RCU_GPIOCRST); in gpio_deinit()
61 rcu_periph_reset_disable(RCU_GPIOCRST); in gpio_deinit()
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_gpio.c | 62 rcu_periph_reset_enable(RCU_GPIOCRST); in gpio_deinit()
63 rcu_periph_reset_disable(RCU_GPIOCRST); in gpio_deinit()
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_gpio.c | 69 rcu_periph_reset_enable(RCU_GPIOCRST); in gpio_deinit()
70 rcu_periph_reset_disable(RCU_GPIOCRST); in gpio_deinit()
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/source/ |
| D | gd32f403_gpio.c | 70 rcu_periph_reset_enable(RCU_GPIOCRST); in gpio_deinit()
71 rcu_periph_reset_disable(RCU_GPIOCRST); in gpio_deinit()
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_gpio.c | 71 rcu_periph_reset_enable(RCU_GPIOCRST); in gpio_deinit()
72 rcu_periph_reset_disable(RCU_GPIOCRST); in gpio_deinit()
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_gpio.c | 70 rcu_periph_reset_enable(RCU_GPIOCRST); in gpio_deinit()
71 rcu_periph_reset_disable(RCU_GPIOCRST); in gpio_deinit()
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_rcu.h | 341 RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ enumerator
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_rcu.h | 334 … RCU_GPIOCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOC clock reset */ enumerator
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/ |
| D | gd32f3x0_rcu.h | 347 RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */ enumerator
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_rcu.h | 402 … RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ enumerator
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/include/ |
| D | gd32f403_rcu.h | 407 … RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ enumerator
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_rcu.h | 353 RCU_GPIOCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOC reset */ enumerator
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/ |
| D | gd32f4xx_rcu.h | 663 … RCU_GPIOCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 2U), /*!< GPIOC clock reset */ enumerator
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_rcu.h | 683 … RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ enumerator
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