1 /*! 2 \file gd32a50x_rcu.h 3 \brief definitions for the RCU 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_RCU_H 36 #define GD32A50X_RCU_H 37 38 #include "gd32a50x.h" 39 40 /* RCU definitions */ 41 #define RCU RCU_BASE /*!< RCU base address */ 42 43 /* registers definitions */ 44 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register */ 45 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< clock configuration register 0 */ 46 #define RCU_INT REG32(RCU + 0x00000008U) /*!< clock interrupt register */ 47 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ 48 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ 49 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB1 enable register */ 50 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ 51 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ 52 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ 53 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source / clock register */ 54 #define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ 55 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< clock configuration register 1 */ 56 #define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< clock configuration register 2 */ 57 #define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ 58 #define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */ 59 60 /* bits definitions */ 61 /* RCU_CTL */ 62 #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ 63 #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ 64 #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< internal 8M RC oscillator clock trim adjust value */ 65 #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< internal 8M RC oscillator calibration value */ 66 #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ 67 #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ 68 #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ 69 #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ 70 #define RCU_CTL_PLLMEN BIT(20) /*!< PLL clock monitor enable */ 71 #define RCU_CTL_LCKMEN BIT(21) /*!< LXTAL clock monitor enable */ 72 #define RCU_CTL_HXTALSCAL BIT(22) /*!< HXTAL frequency scale select */ 73 #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ 74 #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ 75 76 /* RCU_CFG0 */ 77 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 78 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 79 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 80 #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ 81 #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ 82 #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ 83 #define RCU_CFG0_DPLL BIT(17) /*!< double PLL clock */ 84 #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ 85 #define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CKOUT clock source selection */ 86 #define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ 87 #define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ 88 #define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 for CK_OUT */ 89 90 /* RCU_INT */ 91 #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ 92 #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ 93 #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ 94 #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ 95 #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ 96 #define RCU_INT_LCKMIF BIT(5) /*!< LXTAL clock monitor interrupt flag */ 97 #define RCU_INT_PLLMIF BIT(6) /*!< PLL clock monitor interrupt flag */ 98 #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ 99 #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ 100 #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ 101 #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ 102 #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ 103 #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ 104 #define RCU_INT_LCKMIE BIT(13) /*!< LXTAL clock monitor interrupt enable */ 105 #define RCU_INT_PLLMIE BIT(14) /*!< PLL clock monitor interrupt enable */ 106 #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ 107 #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ 108 #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ 109 #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ 110 #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ 111 #define RCU_INT_LCKMIC BIT(21) /*!< LXTAL clock monitor interrupt clear */ 112 #define RCU_INT_PLLMIC BIT(22) /*!< PLL clock monitor interrupt clear */ 113 #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ 114 115 /* RCU_APB2RST */ 116 #define RCU_APB2RST_CFGRST BIT(0) /*!< system configuration reset */ 117 #define RCU_APB2RST_CMPRST BIT(1) /*!< comparator reset */ 118 #define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ 119 #define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ 120 #define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ 121 #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ 122 #define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ 123 #define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ 124 #define RCU_APB2RST_TIMER19RST BIT(20) /*!< TIMER19 reset */ 125 #define RCU_APB2RST_TIMER20RST BIT(21) /*!< TIMER20 reset */ 126 #define RCU_APB2RST_CAN0RST BIT(30) /*!< CAN0 reset */ 127 #define RCU_APB2RST_CAN1RST BIT(31) /*!< CAN1 reset */ 128 129 /* RCU_APB1RST */ 130 #define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ 131 #define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ 132 #define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ 133 #define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ 134 #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ 135 #define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ 136 #define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ 137 #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ 138 #define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ 139 #define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ 140 #define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ 141 142 /* RCU_AHBEN */ 143 #define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ 144 #define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ 145 #define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ 146 #define RCU_AHBEN_DMAMUXEN BIT(3) /*!< DMAMUX clock enable */ 147 #define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ 148 #define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ 149 #define RCU_AHBEN_MFCOMEN BIT(14) /*!< MFCOM clock enable */ 150 #define RCU_AHBEN_PAEN BIT(17) /*!< GPIOA clock enable */ 151 #define RCU_AHBEN_PBEN BIT(18) /*!< GPIOB clock enable */ 152 #define RCU_AHBEN_PCEN BIT(19) /*!< GPIOC clock enable */ 153 #define RCU_AHBEN_PDEN BIT(20) /*!< GPIOD clock enable */ 154 #define RCU_AHBEN_PEEN BIT(21) /*!< GPIOE clock enable */ 155 #define RCU_AHBEN_PFEN BIT(22) /*!< GPIOF clock enable */ 156 157 /* RCU_APB2EN */ 158 #define RCU_APB2EN_CFGEN BIT(0) /*!< System configuration clock enable */ 159 #define RCU_APB2EN_CMPEN BIT(1) /*!< Comparator clock enable */ 160 #define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ 161 #define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ 162 #define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ 163 #define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ 164 #define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ 165 #define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ 166 #define RCU_APB2EN_TIMER19EN BIT(20) /*!< TIMER19 clock enable */ 167 #define RCU_APB2EN_TIMER20EN BIT(21) /*!< TIMER20 clock enable */ 168 #define RCU_APB2EN_TRIGSELEN BIT(29) /*!< TRIGSEL clock enable */ 169 #define RCU_APB2EN_CAN0EN BIT(30) /*!< CAN0 clock enable */ 170 #define RCU_APB2EN_CAN1EN BIT(31) /*!< CAN1 clock enable */ 171 172 /* RCU_APB1EN */ 173 #define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ 174 #define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ 175 #define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ 176 #define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ 177 #define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ 178 #define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ 179 #define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ 180 #define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ 181 #define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ 182 #define RCU_APB1EN_BKPEN BIT(27) /*!< Back-up interface clock enable */ 183 #define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ 184 #define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ 185 186 /* RCU_BDCTL */ 187 #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ 188 #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ 189 #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ 190 #define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ 191 #define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ 192 #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ 193 #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ 194 195 /* RCU_RSTSCK */ 196 #define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ 197 #define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ 198 #define RCU_RSTSCK_LOCKUPRSTEN BIT(10) /*!< CPU Lock-Up reset enable */ 199 #define RCU_RSTSCK_LVDRSTEN BIT(11) /*!< low voltage detection reset enable */ 200 #define RCU_RSTSCK_ECCRSTEN BIT(12) /*!< ECC 2 bits error reset enable*/ 201 #define RCU_RSTSCK_LOHRSTEN BIT(13) /*!< lost of HXTAL reset enable */ 202 #define RCU_RSTSCK_LOPRSTEN BIT(14) /*!< lost of PLL reset enable */ 203 #define RCU_RSTSCK_BORRSTF BIT(17) /*!< BOR reset flag */ 204 #define RCU_RSTSCK_LOCKUPRSTF BIT(18) /*!< CPU Lock-Up error reset flag */ 205 #define RCU_RSTSCK_LVDRSTF BIT(19) /*!< low Voltage detect error reset flag */ 206 #define RCU_RSTSCK_ECCRSTF BIT(20) /*!< two bit ECC error reset flag */ 207 #define RCU_RSTSCK_LOHRSTF BIT(21) /*!< lost of HXTAL error reset flag */ 208 #define RCU_RSTSCK_LOPRSTF BIT(22) /*!< lost of PLL error reset flag */ 209 #define RCU_RSTSCK_V11RSTF BIT(23) /*!< 1.1V domain power reset flag */ 210 #define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ 211 #define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ 212 #define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ 213 #define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ 214 #define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ 215 #define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ 216 #define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ 217 #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ 218 219 /* RCU_AHBRST */ 220 #define RCU_AHBRST_DMA0RST BIT(0) /*!< DMA0 reset */ 221 #define RCU_AHBRST_DMA1RST BIT(1) /*!< DMA1 reset */ 222 #define RCU_AHBRST_DMAMUXRST BIT(3) /*!< DMAMUX reset */ 223 #define RCU_AHBRST_CRCRST BIT(6) /*!< CRC reset */ 224 #define RCU_AHBRST_MFCOMRST BIT(14) /*!< MFCOM reset */ 225 #define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ 226 #define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ 227 #define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ 228 #define RCU_AHBRST_PDRST BIT(20) /*!< GPIO port D reset */ 229 #define RCU_AHBRST_PERST BIT(21) /*!< GPIO port E reset */ 230 #define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ 231 232 /* RCU_CFG1 */ 233 #define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ 234 235 /* RCU_CFG2 */ 236 #define RCU_CFG2_USART0SEL BITS(0,1) /*!< USART0 clock source selection */ 237 #define RCU_CFG2_USART1SEL BITS(4,5) /*!< USART1 clock source selection */ 238 #define RCU_CFG2_USART2SEL BITS(6,7) /*!< USART2 clock source selection */ 239 #define RCU_CFG2_CAN0SEL BITS(12,13) /*!< CAN0 clock source selection */ 240 #define RCU_CFG2_CAN1SEL BITS(14,15) /*!< CAN1 clock source selection */ 241 #define RCU_CFG2_ADCPSC BITS(27,31) /*!< ADC prescaler selection */ 242 243 /* RCU_VKEY */ 244 #define RCU_VKEY_UNLOCK 0x1A2B3C4DU /*!< the key of RCU_DSV register */ 245 /* RCU_VKEY */ 246 #define RCU_VKEY_KEY BITS(0,31) 247 /* RCU_DSV */ 248 #define RCU_DSV_DSLPVS BITS(0,1) /*!< Deep-sleep mode voltage selection */ 249 250 /* constants definitions */ 251 /* define the peripheral clock enable bit position and its register index offset */ 252 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 253 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) 254 #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) 255 256 /* register offset */ 257 /* peripherals enable */ 258 #define AHBEN_REG_OFFSET 0x00000014U /*!< AHB enable register offset */ 259 #define APB1EN_REG_OFFSET 0x0000001CU /*!< APB1 enable register offset */ 260 #define APB2EN_REG_OFFSET 0x00000018U /*!< APB2 enable register offset */ 261 262 /* peripherals reset */ 263 #define AHBRST_REG_OFFSET 0x00000028U /*!< AHB reset register offset */ 264 #define APB1RST_REG_OFFSET 0x00000010U /*!< APB1 reset register offset */ 265 #define APB2RST_REG_OFFSET 0x0000000CU /*!< APB2 reset register offset */ 266 #define RSTSCK_REG_OFFSET 0x00000024U /*!< reset source/clock register offset */ 267 268 /* clock control */ 269 #define CTL_REG_OFFSET 0x00000000U /*!< control register offset */ 270 #define BDCTL_REG_OFFSET 0x00000020U /*!< backup domain control register offset */ 271 272 /* clock stabilization and stuck interrupt */ 273 #define INT_REG_OFFSET 0x00000008U /*!< clock interrupt register offset */ 274 275 /* configuration register */ 276 #define CFG0_REG_OFFSET 0x00000004U /*!< clock configuration register 0 offset */ 277 #define CFG1_REG_OFFSET 0x0000002CU /*!< clock configuration register 1 offset */ 278 279 /* peripheral clock enable */ 280 typedef enum { 281 /* AHB peripherals */ 282 RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ 283 RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ 284 RCU_DMAMUX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 3U), /*!< DMAMUX clock */ 285 RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ 286 RCU_MFCOM = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< MFCOM clock */ 287 RCU_GPIOA = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 17U), /*!< GPIOA clock */ 288 RCU_GPIOB = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 18U), /*!< GPIOB clock */ 289 RCU_GPIOC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 19U), /*!< GPIOC clock */ 290 RCU_GPIOD = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 20U), /*!< GPIOD clock */ 291 RCU_GPIOE = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 21U), /*!< GPIOE clock */ 292 RCU_GPIOF = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 22U), /*!< GPIOF clock */ 293 /* APB2 peripherals */ 294 RCU_SYSCFG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< SYSCFG clock */ 295 RCU_CMP = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 1U), /*!< CMP clock */ 296 RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ 297 RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ 298 RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ 299 RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ 300 RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ 301 RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ 302 RCU_TIMER19 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER19 clock */ 303 RCU_TIMER20 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER20 clock */ 304 RCU_TRIGSEL = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 29U), /*!< TRIGSEL clock */ 305 RCU_CAN0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 30U), /*!< CAN0 clock */ 306 RCU_CAN1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 31U), /*!< CAN1 clock */ 307 /* APB1 peripherals */ 308 RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ 309 RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ 310 RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ 311 RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ 312 RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ 313 RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ 314 RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ 315 RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ 316 RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ 317 RCU_BKP = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKP clock */ 318 RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ 319 RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ 320 RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ 321 } rcu_periph_enum; 322 323 324 /* peripherals reset */ 325 typedef enum { 326 /* AHB peripherals */ 327 RCU_DMA0RST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 0U), /*!< DMA0 clock reset */ 328 RCU_DMA1RST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 1U), /*!< DMA1 clock reset */ 329 RCU_DMAMUXRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 3U), /*!< DMAMUX clock reset */ 330 RCU_CRCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 6U), /*!< CRC clock reset */ 331 RCU_MFCOMRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< MFCOM clock reset */ 332 RCU_GPIOARST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 17U), /*!< GPIOA clock reset */ 333 RCU_GPIOBRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 18U), /*!< GPIOB clock reset */ 334 RCU_GPIOCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOC clock reset */ 335 RCU_GPIODRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 20U), /*!< GPIOD clock reset */ 336 RCU_GPIOERST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 21U), /*!< GPIOE clock reset */ 337 RCU_GPIOFRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 22U), /*!< GPIOF clock reset */ 338 /* APB2 peripherals */ 339 RCU_SYSCFGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< system configuration reset */ 340 RCU_CMPRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 1U), /*!< Comparator reset */ 341 RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ 342 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ 343 RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ 344 RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ 345 RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ 346 RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ 347 RCU_TIMER19RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER19 clock reset */ 348 RCU_TIMER20RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER20 clock reset */ 349 RCU_CAN0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 30U), /*!< CAN0 clock reset */ 350 RCU_CAN1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 31U), /*!< CAN1 clock reset */ 351 /* APB1 peripherals */ 352 RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ 353 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ 354 RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ 355 RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ 356 RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ 357 RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ 358 RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ 359 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ 360 RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ 361 RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ 362 RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ 363 } rcu_periph_reset_enum; 364 365 /* peripheral clock enable when sleep mode*/ 366 typedef enum { 367 /* AHB peripherals */ 368 RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ 369 RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ 370 } rcu_periph_sleep_enum; 371 372 /* clock stabilization and peripheral reset flags */ 373 typedef enum { 374 /* clock stabilization flags */ 375 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flag */ 376 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flag */ 377 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flag */ 378 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flag */ 379 /* reset source flags */ 380 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flag */ 381 RCU_FLAG_BORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 17U), /*!< BOR reset flag */ 382 RCU_FLAG_LOCKUPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 18U), /*!< CPU LOCK UP error reset flag */ 383 RCU_FLAG_LVDRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 19U), /*!< low voltage detect error reset flag */ 384 RCU_FLAG_ECCRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 20U), /*!< 2 bits ECC error reset flag */ 385 RCU_FLAG_LOHRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 21U), /*!< lost of HXTAL error reset flag */ 386 RCU_FLAG_LOPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 22U), /*!< lost of PLL error reset flag */ 387 RCU_FLAG_V11RST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 23U), /*!< 1.1V domain Power reset flag */ 388 RCU_FLAG_OBLRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 25U), /*!< option byte loader reset flag */ 389 RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flag */ 390 RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flag */ 391 RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flag */ 392 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flag */ 393 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flag */ 394 RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flag */ 395 } rcu_flag_enum; 396 397 /* clock stabilization and ckm interrupt flags */ 398 typedef enum { 399 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ 400 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ 401 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ 402 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ 403 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ 404 RCU_INT_FLAG_LCKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< LXTAL clock monitor interrupt flag */ 405 RCU_INT_FLAG_PLLM = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL clock monitor interrupt flag */ 406 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ 407 } rcu_int_flag_enum; 408 409 /* clock stabilization and stuck interrupt flags clear */ 410 typedef enum { 411 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flag clear */ 412 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flag clear */ 413 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flag clear */ 414 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flag clear */ 415 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flag clear */ 416 RCU_INT_FLAG_LCKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< LXTAL clock monitor interrupt clear */ 417 RCU_INT_FLAG_PLLM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL clock monitor interrupt clear */ 418 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flag clear */ 419 } rcu_int_flag_clear_enum; 420 421 /* clock stabilization interrupt enable or disable */ 422 typedef enum { 423 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt enable */ 424 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt enable */ 425 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt enable */ 426 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt enable */ 427 RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt enable */ 428 RCU_INT_LCKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< LXTAL clock monitor interrupt enable */ 429 RCU_INT_PLLM = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL clock monitor interrupt enable */ 430 } rcu_int_enum; 431 432 /* oscillator types */ 433 typedef enum { 434 RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ 435 RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ 436 RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ 437 RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ 438 RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ 439 } rcu_osci_type_enum; 440 441 /* rcu clock frequency */ 442 typedef enum { 443 CK_SYS = 0, /*!< system clock */ 444 CK_AHB, /*!< AHB clock */ 445 CK_APB1, /*!< APB1 clock */ 446 CK_APB2, /*!< APB2 clock */ 447 CK_USART0, /*!< USART0 clock */ 448 CK_USART1, /*!< USART1 clock */ 449 CK_USART2, /*!< USART2 clock */ 450 } rcu_clock_freq_enum; 451 452 /* HXTAL frequency scale select */ 453 #define HXTAL_SCALE_2M_TO_8M 0x00000000U /*!< HXTAL scale is 2M-8MHz */ 454 #define HXTAL_SCALE_8M_TO_40M RCU_CTL_HXTALSCAL /*!< HXTAL scale is 8M-40MHz */ 455 456 /* RCU_CFG0 register bit define */ 457 /* system clock source select */ 458 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 459 #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ 460 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ 461 #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ 462 463 /* system clock source select status */ 464 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 465 #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ 466 #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ 467 #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ 468 469 /* AHB prescaler selection */ 470 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 471 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ 472 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ 473 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ 474 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ 475 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ 476 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ 477 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ 478 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ 479 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ 480 481 /* APB1 prescaler selection */ 482 #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) 483 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ 484 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ 485 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ 486 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ 487 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ 488 489 /* APB2 prescaler selection */ 490 #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) 491 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ 492 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ 493 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ 494 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ 495 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ 496 497 /* RCU system reset */ 498 #define RCU_SYSRST_LOCKUP RCU_RSTSCK_LOCKUPRSTEN /*!< CPU lock-up reset */ 499 #define RCU_SYSRST_LVD RCU_RSTSCK_LVDRSTEN /*!< low voltage detect reset */ 500 #define RCU_SYSRST_ECC RCU_RSTSCK_ECCRSTEN /*!< ECC 2 bits error reset */ 501 #define RCU_SYSRST_LOH RCU_RSTSCK_LOHRSTEN /*!< lost of HXTAL error reset */ 502 #define RCU_SYSRST_LOP RCU_RSTSCK_LOPRSTEN /*!< lost of PLL reset */ 503 504 /* ADC prescaler select */ 505 #define CFG2_ADCPSC(regval) (BITS(27,31) & ((uint32_t)(regval) << 27)) 506 #define RCU_CKADC_CKAHB_DIV2 CFG2_ADCPSC(0) /*!< ADC prescaler select CK_AHB/2 */ 507 #define RCU_CKADC_CKAHB_DIV3 CFG2_ADCPSC(1) /*!< ADC prescaler select CK_AHB/3 */ 508 #define RCU_CKADC_CKAHB_DIV4 CFG2_ADCPSC(2) /*!< ADC prescaler select CK_AHB/4 */ 509 #define RCU_CKADC_CKAHB_DIV5 CFG2_ADCPSC(3) /*!< ADC prescaler select CK_AHB/5 */ 510 #define RCU_CKADC_CKAHB_DIV6 CFG2_ADCPSC(4) /*!< ADC prescaler select CK_AHB/6 */ 511 #define RCU_CKADC_CKAHB_DIV7 CFG2_ADCPSC(5) /*!< ADC prescaler select CK_AHB/7 */ 512 #define RCU_CKADC_CKAHB_DIV8 CFG2_ADCPSC(6) /*!< ADC prescaler select CK_AHB/8 */ 513 #define RCU_CKADC_CKAHB_DIV9 CFG2_ADCPSC(7) /*!< ADC prescaler select CK_AHB/9 */ 514 #define RCU_CKADC_CKAHB_DIV10 CFG2_ADCPSC(8) /*!< ADC prescaler select CK_AHB/10 */ 515 #define RCU_CKADC_CKAHB_DIV11 CFG2_ADCPSC(9) /*!< ADC prescaler select CK_AHB/11 */ 516 #define RCU_CKADC_CKAHB_DIV12 CFG2_ADCPSC(10) /*!< ADC prescaler select CK_AHB/12 */ 517 #define RCU_CKADC_CKAHB_DIV13 CFG2_ADCPSC(11) /*!< ADC prescaler select CK_AHB/13 */ 518 #define RCU_CKADC_CKAHB_DIV14 CFG2_ADCPSC(12) /*!< ADC prescaler select CK_AHB/14 */ 519 #define RCU_CKADC_CKAHB_DIV15 CFG2_ADCPSC(13) /*!< ADC prescaler select CK_AHB/15 */ 520 #define RCU_CKADC_CKAHB_DIV16 CFG2_ADCPSC(14) /*!< ADC prescaler select CK_AHB/16 */ 521 #define RCU_CKADC_CKAHB_DIV17 CFG2_ADCPSC(15) /*!< ADC prescaler select CK_AHB/17 */ 522 #define RCU_CKADC_CKAHB_DIV18 CFG2_ADCPSC(16) /*!< ADC prescaler select CK_AHB/18 */ 523 #define RCU_CKADC_CKAHB_DIV19 CFG2_ADCPSC(17) /*!< ADC prescaler select CK_AHB/19 */ 524 #define RCU_CKADC_CKAHB_DIV20 CFG2_ADCPSC(18) /*!< ADC prescaler select CK_AHB/20 */ 525 #define RCU_CKADC_CKAHB_DIV21 CFG2_ADCPSC(19) /*!< ADC prescaler select CK_AHB/21 */ 526 #define RCU_CKADC_CKAHB_DIV22 CFG2_ADCPSC(20) /*!< ADC prescaler select CK_AHB/22 */ 527 #define RCU_CKADC_CKAHB_DIV23 CFG2_ADCPSC(21) /*!< ADC prescaler select CK_AHB/23 */ 528 #define RCU_CKADC_CKAHB_DIV24 CFG2_ADCPSC(22) /*!< ADC prescaler select CK_AHB/24 */ 529 #define RCU_CKADC_CKAHB_DIV25 CFG2_ADCPSC(23) /*!< ADC prescaler select CK_AHB/25 */ 530 #define RCU_CKADC_CKAHB_DIV26 CFG2_ADCPSC(24) /*!< ADC prescaler select CK_AHB/26 */ 531 #define RCU_CKADC_CKAHB_DIV27 CFG2_ADCPSC(25) /*!< ADC prescaler select CK_AHB/27 */ 532 #define RCU_CKADC_CKAHB_DIV28 CFG2_ADCPSC(26) /*!< ADC prescaler select CK_AHB/28 */ 533 #define RCU_CKADC_CKAHB_DIV29 CFG2_ADCPSC(27) /*!< ADC prescaler select CK_AHB/29 */ 534 #define RCU_CKADC_CKAHB_DIV30 CFG2_ADCPSC(28) /*!< ADC prescaler select CK_AHB/30 */ 535 #define RCU_CKADC_CKAHB_DIV31 CFG2_ADCPSC(29) /*!< ADC prescaler select CK_AHB/31 */ 536 #define RCU_CKADC_CKAHB_DIV32 CFG2_ADCPSC(30) /*!< ADC prescaler select CK_AHB/32 */ 537 538 /* PLL clock source selection */ 539 #define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock is selected as clock source of PLL */ 540 #define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL is selected as clock source of PLL */ 541 542 /* PLL clock multiplication factor */ 543 #define PLLMF_4 RCU_CFG0_PLLMF_4 /*!< bit 4 of PLLMF */ 544 #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) 545 #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL clock source multiply by 2 */ 546 #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL clock source multiply by 3 */ 547 #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL clock source multiply by 4 */ 548 #define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL clock source multiply by 5 */ 549 #define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL clock source multiply by 6 */ 550 #define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL clock source multiply by 7 */ 551 #define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL clock source multiply by 8 */ 552 #define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL clock source multiply by 9 */ 553 #define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL clock source multiply by 10 */ 554 #define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL clock source multiply by 11 */ 555 #define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL clock source multiply by 12 */ 556 #define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL clock source multiply by 13 */ 557 #define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL clock source multiply by 14 */ 558 #define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL clock source multiply by 15 */ 559 #define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL clock source multiply by 16 */ 560 #define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL clock source multiply by 17 */ 561 #define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL clock source multiply by 18 */ 562 #define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL clock source multiply by 19 */ 563 #define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL clock source multiply by 20 */ 564 #define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL clock source multiply by 21 */ 565 #define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL clock source multiply by 22 */ 566 #define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL clock source multiply by 23 */ 567 #define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL clock source multiply by 24 */ 568 #define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL clock source multiply by 25 */ 569 #define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL clock source multiply by 26 */ 570 #define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL clock source multiply by 27 */ 571 #define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL clock source multiply by 28 */ 572 #define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL clock source multiply by 29 */ 573 #define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL clock source multiply by 30 */ 574 #define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL clock source multiply by 31 */ 575 576 /* CKOUT Clock source selection */ 577 #define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) 578 #define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock is selected */ 579 #define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< IRC40K is selected as CK_OUT clock source */ 580 #define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< LXTAL is selected as CK_OUT clock source */ 581 #define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< system clock is selected as CK_OUT clock source */ 582 #define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< IRC8M is selected as CK_OUT clock source */ 583 #define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< HXTAL is selected as CK_OUT clock source */ 584 #define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_PLL is selected as CK_OUT clock source */ 585 #define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_PLL/2 is selected as CK_OUT clock source */ 586 587 /* CK_OUT divider */ 588 #define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) 589 #define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ 590 #define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ 591 #define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ 592 #define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ 593 #define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ 594 #define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ 595 #define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ 596 #define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ 597 598 /* LXTAL drive capability */ 599 #define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) 600 #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ 601 #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ 602 #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ 603 #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ 604 605 /* RTC clock entry selection */ 606 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) 607 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock is selected */ 608 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL is selected as RTC clock source */ 609 #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K is selected as RTC clock source */ 610 #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< HXTAL/128 is selected as RTC clock source */ 611 612 /* PREDV0 division factor */ 613 #define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) 614 #define RCU_PREDV_DIV1 CFG1_PREDV(0) /*!< PREDV input clock source not divided */ 615 #define RCU_PREDV_DIV2 CFG1_PREDV(1) /*!< PREDV input clock source divided by 2 */ 616 #define RCU_PREDV_DIV3 CFG1_PREDV(2) /*!< PREDV input clock source divided by 3 */ 617 #define RCU_PREDV_DIV4 CFG1_PREDV(3) /*!< PREDV input clock source divided by 4 */ 618 #define RCU_PREDV_DIV5 CFG1_PREDV(4) /*!< PREDV input clock source divided by 5 */ 619 #define RCU_PREDV_DIV6 CFG1_PREDV(5) /*!< PREDV input clock source divided by 6 */ 620 #define RCU_PREDV_DIV7 CFG1_PREDV(6) /*!< PREDV input clock source divided by 7 */ 621 #define RCU_PREDV_DIV8 CFG1_PREDV(7) /*!< PREDV input clock source divided by 8 */ 622 #define RCU_PREDV_DIV9 CFG1_PREDV(8) /*!< PREDV input clock source divided by 9 */ 623 #define RCU_PREDV_DIV10 CFG1_PREDV(9) /*!< PREDV input clock source divided by 10 */ 624 #define RCU_PREDV_DIV11 CFG1_PREDV(10) /*!< PREDV input clock source divided by 11 */ 625 #define RCU_PREDV_DIV12 CFG1_PREDV(11) /*!< PREDV input clock source divided by 12 */ 626 #define RCU_PREDV_DIV13 CFG1_PREDV(12) /*!< PREDV input clock source divided by 13 */ 627 #define RCU_PREDV_DIV14 CFG1_PREDV(13) /*!< PREDV input clock source divided by 14 */ 628 #define RCU_PREDV_DIV15 CFG1_PREDV(14) /*!< PREDV input clock source divided by 15 */ 629 #define RCU_PREDV_DIV16 CFG1_PREDV(15) /*!< PREDV input clock source divided by 16 */ 630 631 /* deep-sleep mode voltage */ 632 #define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 633 #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(0) /*!< core voltage is 0.8V in deep-sleep mode */ 634 #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ 635 #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ 636 #define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(3) /*!< core voltage is 1.1V in deep-sleep mode */ 637 638 /* USART clock source selection */ 639 #define CFG2_USART0SRC(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 640 #define RCU_USARTSRC_HXTAL CFG2_USART0SRC(0) /*!< CK_HXTAL is selected as USART clock source */ 641 #define RCU_USARTSRC_CKSYS CFG2_USART0SRC(1) /*!< CK_SYS is selected as USART clock source */ 642 #define RCU_USARTSRC_LXTAL CFG2_USART0SRC(2) /*!< CK_LXTAL is selected as USART clock source */ 643 #define RCU_USARTSRC_IRC8M CFG2_USART0SRC(3) /*!< CK_IRC8M is selected as USART clock source */ 644 645 /* CAN clock source selection */ 646 #define CFG2_CAN0SRC(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 647 #define RCU_CANSRC_HXTAL CFG2_CAN0SRC(0) /*!< CK_HXTAL is selected as CAN clock source */ 648 #define RCU_CANSRC_PCLK2 CFG2_CAN0SRC(1) /*!< PCLK2 is selected as CAN clock source */ 649 #define RCU_CANSRC_PCLK2_DIV_2 CFG2_CAN0SRC(2) /*!< PCLK2/2 is selected as CAN clock source */ 650 #define RCU_CANSRC_IRC8M CFG2_CAN0SRC(3) /*!< CK_IRC8M is selected as CAN clock source */ 651 652 653 /* function declarations */ 654 /* peripherals clock configure functions */ 655 /* deinitialize the RCU */ 656 void rcu_deinit(void); 657 /* enable the peripherals clock */ 658 void rcu_periph_clock_enable(rcu_periph_enum periph); 659 /* disable the peripherals clock */ 660 void rcu_periph_clock_disable(rcu_periph_enum periph); 661 /* reset the peripherals */ 662 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); 663 /* disable reset the peripheral */ 664 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); 665 /* enable the peripherals clock when in sleep mode */ 666 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); 667 /* disable the peripherals clock when in sleep mode */ 668 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); 669 /* reset the BKP domain control register */ 670 void rcu_bkp_reset_enable(void); 671 /* disable the BKP domain control register reset */ 672 void rcu_bkp_reset_disable(void); 673 674 /* system and peripherals clock source, system reset configure functions */ 675 /* configure the system clock source */ 676 void rcu_system_clock_source_config(uint32_t ck_sys); 677 /* get the system clock source */ 678 uint32_t rcu_system_clock_source_get(void); 679 /* configure the AHB prescaler selection */ 680 void rcu_ahb_clock_config(uint32_t ck_ahb); 681 /* configure the APB1 prescaler selection */ 682 void rcu_apb1_clock_config(uint32_t ck_apb1); 683 /* configure the APB2 prescaler selection */ 684 void rcu_apb2_clock_config(uint32_t ck_apb2); 685 /* configure the CK_OUT clock source and divider */ 686 void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); 687 /* configure the PLL clock source selection and PLL multiply factor */ 688 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); 689 /* enable double PLL clock */ 690 void rcu_double_pll_enable(void); 691 /* disable double PLL clock */ 692 void rcu_double_pll_disable(void); 693 /* enable RCU system reset */ 694 void rcu_system_reset_enable(uint32_t reset_source); 695 /* disable RCU system reset */ 696 void rcu_system_reset_disable(uint32_t reset_source); 697 /* configure the ADC division factor */ 698 void rcu_adc_clock_config(uint32_t adc_psc); 699 /* configure the RTC clock source selection */ 700 void rcu_rtc_clock_config(uint32_t rtc_clock_source); 701 /* configure the USART clock source selection */ 702 void rcu_usart_clock_config(uint32_t usart_periph, uint32_t usart_clock_source); 703 /* configure the CAN clock source selection */ 704 void rcu_can_clock_config(uint32_t can_periph, uint32_t can_clock_source); 705 706 /* LXTAL, IRC8M, PLL and other oscillator configure functions */ 707 /* configure the LXTAL drive capability */ 708 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); 709 /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ 710 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); 711 /* turn on the oscillator */ 712 void rcu_osci_on(rcu_osci_type_enum osci); 713 /* turn off the oscillator */ 714 void rcu_osci_off(rcu_osci_type_enum osci); 715 /* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 716 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); 717 /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 718 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); 719 /* configure the HXTAL frequency scale select */ 720 void rcu_hxtal_frequency_scale_select(uint32_t hxtal_scal); 721 /* configure the HXTAL divider used as input of PLL */ 722 void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); 723 /* set the IRC8M adjust value */ 724 void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); 725 726 /* clock monitor configure functions */ 727 /* enable the HXTAL clock monitor */ 728 void rcu_hxtal_clock_monitor_enable(void); 729 /* disable the HXTAL clock monitor */ 730 void rcu_hxtal_clock_monitor_disable(void); 731 /* enable the LXTAL clock monitor */ 732 void rcu_lxtal_clock_monitor_enable(void); 733 /* disable the LXTAL clock monitor */ 734 void rcu_lxtal_clock_monitor_disable(void); 735 /* enable the PLL clock monitor */ 736 void rcu_pll_clock_monitor_enable(void); 737 /* disable the PLL clock monitor */ 738 void rcu_pll_clock_monitor_disable(void); 739 740 /* voltage configure and clock frequency get functions */ 741 /* unlock the voltage key */ 742 void rcu_voltage_key_unlock(void); 743 /* set the deep sleep mode voltage */ 744 void rcu_deepsleep_voltage_set(uint32_t dsvol); 745 /* get the system clock, bus and peripheral clock frequency */ 746 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); 747 748 /* flag & interrupt functions */ 749 /* get the clock stabilization and peripheral reset flags */ 750 FlagStatus rcu_flag_get(rcu_flag_enum flag); 751 /* clear the reset flag */ 752 void rcu_all_reset_flag_clear(void); 753 /* get the clock stabilization interrupt and ckm flags */ 754 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); 755 /* clear the interrupt flags */ 756 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); 757 /* enable the stabilization interrupt */ 758 void rcu_interrupt_enable(rcu_int_enum interrupt); 759 /* disable the stabilization interrupt */ 760 void rcu_interrupt_disable(rcu_int_enum interrupt); 761 #endif /* GD32A50X_RCU_H */ 762
