Searched refs:RCU_CAN0RST (Results 1 – 10 of 10) sorted by relevance
| /hal_gigadevice-latest/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_can.c | 113 rcu_periph_reset_enable(RCU_CAN0RST); in can_deinit()
114 rcu_periph_reset_disable(RCU_CAN0RST); in can_deinit()
130 rcu_periph_reset_enable(RCU_CAN0RST); in can_deinit()
131 rcu_periph_reset_disable(RCU_CAN0RST); in can_deinit()
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_can.c | 55 rcu_periph_reset_enable(RCU_CAN0RST); in can_deinit()
56 rcu_periph_reset_disable(RCU_CAN0RST); in can_deinit()
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_can.c | 53 rcu_periph_reset_enable(RCU_CAN0RST); in can_deinit()
54 rcu_periph_reset_disable(RCU_CAN0RST); in can_deinit()
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/source/ |
| D | gd32f403_can.c | 53 rcu_periph_reset_enable(RCU_CAN0RST); in can_deinit()
54 rcu_periph_reset_disable(RCU_CAN0RST); in can_deinit()
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_can.c | 59 rcu_periph_reset_enable(RCU_CAN0RST); in can_deinit()
60 rcu_periph_reset_disable(RCU_CAN0RST); in can_deinit()
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_rcu.h | 332 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_rcu.h | 349 … RCU_CAN0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 30U), /*!< CAN0 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/include/ |
| D | gd32f403_rcu.h | 396 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/ |
| D | gd32f4xx_rcu.h | 702 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_rcu.h | 668 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ enumerator
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