1 /*! 2 \file gd32l23x_rcu.h 3 \brief definitions for the RCU 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_RCU_H 36 #define GD32L23X_RCU_H 37 38 #include "gd32l23x.h" 39 40 /* RCU definitions */ 41 #define RCU RCU_BASE 42 43 /* registers definitions */ 44 #define RCU_CTL REG32(RCU + 0x00000000U) /*!< control register 0 */ 45 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */ 46 #define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */ 47 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ 48 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ 49 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */ 50 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ 51 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ 52 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ 53 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock register */ 54 #define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ 55 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */ 56 #define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */ 57 #define RCU_AHB2EN REG32(RCU + 0x00000034U) /*!< AHB2 enable register */ 58 #define RCU_AHB2RST REG32(RCU + 0x00000038U) /*!< AHB2 reset register */ 59 #define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ 60 #define RCU_LPLDO REG32(RCU + 0x00000128U) /*!< Low-Power mode LDO voltage register */ 61 #define RCU_LPB REG32(RCU + 0x0000012CU) /*!< Low-Power bandgap mode register */ 62 63 /* bits definitions */ 64 /* RCU_CTL */ 65 #define RCU_CTL_IRC16MEN BIT(0) /*!< internal high speed oscillator enable */ 66 #define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC16M high speed internal oscillator stabilization flag */ 67 #define RCU_CTL_IRC16MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ 68 #define RCU_CTL_IRC16MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ 69 #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ 70 #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ 71 #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ 72 #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ 73 #define RCU_CTL_IRC48MEN BIT(20) /*!< internal high speed oscillator enable */ 74 #define RCU_CTL_IRC48MSTB BIT(21) /*!< IRC48M high speed internal oscillator stabilization flag */ 75 #define RCU_CTL_LXTALCKMEN BIT(22) /*!< LXTAL clock monitor enable */ 76 #define RCU_CTL_LXTALCKMD BIT(23) /*!< LXTAL clock failure detection */ 77 #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ 78 #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ 79 80 /* RCU_CFG0 */ 81 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 82 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 83 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 84 #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ 85 #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ 86 #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */ 87 #define RCU_CFG0_PLLSEL BITS(16,17) /*!< PLL clock source selection */ 88 #define RCU_CFG0_PLLMF BITS(18,23) /*!< PLL multiply factor */ 89 #define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */ 90 #define RCU_CFG0_PLLMF_6 BIT(27) /*!< bit6 of PLL multiply factor */ 91 #define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ 92 #define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */ 93 94 /* RCU_INT */ 95 #define RCU_INT_IRC32KSTBIF BIT(0) /*!< IRC32K stabilization interrupt flag */ 96 #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ 97 #define RCU_INT_IRC16MSTBIF BIT(2) /*!< IRC16M stabilization interrupt flag */ 98 #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ 99 #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ 100 #define RCU_INT_IRC48MSTBIF BIT(5) /*!< IRC48M stabilization interrupt flag */ 101 #define RCU_INT_LXTALCKMIF BIT(6) /*!< LXTAL clock stuck interrupt flag */ 102 #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ 103 #define RCU_INT_IRC32KSTBIE BIT(8) /*!< IRC32K stabilization interrupt enable */ 104 #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ 105 #define RCU_INT_IRC16MSTBIE BIT(10) /*!< IRC16M stabilization interrupt enable */ 106 #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ 107 #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ 108 #define RCU_INT_IRC48MSTBIE BIT(13) /*!< IRC48M stabilization interrupt enable */ 109 #define RCU_INT_LXTALCKMIE BIT(14) /*!< LXTAL clock stuck interrupt enable */ 110 #define RCU_INT_IRC32KSTBIC BIT(16) /*!< IRC32K stabilization interrupt clear */ 111 #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ 112 #define RCU_INT_IRC16MSTBIC BIT(18) /*!< IRC16M stabilization interrupt clear */ 113 #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ 114 #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ 115 #define RCU_INT_IRC48MSTBIC BIT(21) /*!< IRC48M stabilization interrupt clear */ 116 #define RCU_INT_LXTALCKMIC BIT(22) /*!< LXTAL clock stuck interrupt clear */ 117 #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ 118 119 /* RCU_APB2RST */ 120 #define RCU_APB2RST_SYSCFGRST BIT(0) /*!< system configuration reset */ 121 #define RCU_APB2RST_CMPRST BIT(1) /*!< comparator reset */ 122 #define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */ 123 #define RCU_APB2RST_TIMER8RST BIT(11) /*!< TIMER0 reset */ 124 #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ 125 #define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ 126 127 /* RCU_APB1RST */ 128 #define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 timer reset */ 129 #define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */ 130 #define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */ 131 #define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 timer reset */ 132 #define RCU_APB1RST_TIMER11RST BIT(8) /*!< TIMER11 timer reset */ 133 #define RCU_APB1RST_LPTIMERRST BIT(9) /*!< LPTIMER timer reset */ 134 #define RCU_APB1RST_SLCDRST BIT(10) /*!< SLCD reset */ 135 #define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT(window watchdog timer) reset */ 136 #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ 137 #define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ 138 #define RCU_APB1RST_LPUARTRST BIT(18) /*!< LPUART reset */ 139 #define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ 140 #define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ 141 #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ 142 #define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ 143 #define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ 144 #define RCU_APB1RST_I2C2RST BIT(24) /*!< I2C2 reset */ 145 #define RCU_APB1RST_PMURST BIT(28) /*!< PMU(power management unit) reset */ 146 #define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ 147 #define RCU_APB1RST_CTCRST BIT(30) /*!< CTC reset */ 148 149 /* RCU_AHBEN */ 150 #define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */ 151 #define RCU_AHBEN_SRAM0SPEN BIT(2) /*!< SRAM0 interface clock enable */ 152 #define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */ 153 #define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ 154 #define RCU_AHBEN_SRAM1SPEN BIT(7) /*!< SRAM1 interface clock enable */ 155 #define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */ 156 #define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */ 157 #define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */ 158 #define RCU_AHBEN_PDEN BIT(20) /*!< GPIO port D clock enable */ 159 #define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */ 160 161 /* RCU_APB2EN */ 162 #define RCU_APB2EN_SYSCFGEN BIT(0) /*!< system configuration clock enable */ 163 #define RCU_APB2EN_CMPEN BIT(1) /*!< comparator clock enable */ 164 #define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */ 165 #define RCU_APB2EN_TIMER8EN BIT(11) /*!< TIMER8 timer clock enable */ 166 #define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ 167 #define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ 168 #define RCU_APB2EN_DBGMCUEN BIT(22) /*!< DBGMCU clock enable */ 169 170 /* RCU_APB1EN */ 171 #define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 timer clock enable */ 172 #define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */ 173 #define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */ 174 #define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 timer clock enable */ 175 #define RCU_APB1EN_TIMER11EN BIT(8) /*!< TIMER11 timer clock enable */ 176 #define RCU_APB1EN_LPTIMEREN BIT(9) /*!< LPTIMER timer clock enable */ 177 #define RCU_APB1EN_SLCDEN BIT(10) /*!< SLCD clock enable */ 178 #define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT(window watchdog timer) clock enable */ 179 #define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ 180 #define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ 181 #define RCU_APB1EN_LPUARTEN BIT(18) /*!< LPUART clock enable */ 182 #define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ 183 #define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ 184 #define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ 185 #define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ 186 #define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ 187 #define RCU_APB1EN_I2C2EN BIT(24) /*!< I2C2 clock enable */ 188 #define RCU_APB1EN_PMUEN BIT(28) /*!< PMU(power management unit) clock enable */ 189 #define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ 190 #define RCU_APB1EN_CTCEN BIT(30) /*!< CTC clock enable */ 191 #define RCU_APB1EN_BKPEN BIT(31) /*!< BKP clock enable */ 192 193 /* RCU_BDCTL */ 194 #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ 195 #define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */ 196 #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ 197 #define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ 198 #define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ 199 #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ 200 #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ 201 202 /* RCU_RSTSCK */ 203 #define RCU_RSTSCK_IRC32KEN BIT(0) /*!< IRC32K enable */ 204 #define RCU_RSTSCK_IRC32KSTB BIT(1) /*!< IRC32K stabilization */ 205 #define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */ 206 #define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ 207 #define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ 208 #define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ 209 #define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ 210 #define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ 211 #define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ 212 #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ 213 214 /* RCU_AHBRST */ 215 #define RCU_AHBRST_CRCRST BIT(6) /*!< CRC reset */ 216 #define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ 217 #define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ 218 #define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ 219 #define RCU_AHBRST_PDRST BIT(20) /*!< GPIO port D reset */ 220 #define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ 221 222 /* RCU_CFG1 */ 223 #define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ 224 225 /* RCU_CFG2 */ 226 #define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */ 227 #define RCU_CFG2_I2C0SEL BITS(2,3) /*!< CK_I2C0 clock source selection */ 228 #define RCU_CFG2_I2C1SEL BITS(4,5) /*!< CK_I2C1 clock source selection */ 229 #define RCU_CFG2_I2C2SEL BITS(6,7) /*!< CK_I2C2 clock source selection */ 230 #define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */ 231 #define RCU_CFG2_LPTIMERSEL BITS(9,10) /*!< CK_LPTIMER clock source selection */ 232 #define RCU_CFG2_LPUARTSEL BITS(11,12) /*!< CK_LPUART clock source selection */ 233 #define RCU_CFG2_USBDSEL BIT(13) /*!< CK_USBD clock source selection */ 234 #define RCU_CFG2_USART1SEL BITS(16,17) /*!< CK_USART0 clock source selection */ 235 #define RCU_CFG2_IRC16MDIVSEL BITS(18,20) /*!< CK_IRC16M divided clock selection */ 236 #define RCU_CFG2_ADCPSC2 BITS(30,31) /*!< bits of ADCPSC */ 237 238 /* RCU_AHB2EN */ 239 #define RCU_AHB2EN_CAUEN BIT(1) /*!< CAU clock enable */ 240 #define RCU_AHB2EN_TRNGEN BIT(3) /*!< TRNG clock enable */ 241 242 /* RCU_AHB2RST */ 243 #define RCU_AHB2RST_CAURST BIT(1) /*!< CRU reset */ 244 #define RCU_AHBR2ST_TRNGRST BIT(3) /*!< TRNG reset */ 245 /* RCU_VKEY */ 246 #define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */ 247 248 /* RCU_LPLDO */ 249 #define RCU_LPLDO_LPLDOVOS BIT(0) /*!< Deep-sleep 1/2 mode voltage select */ 250 251 /* RCU_LPB */ 252 #define RCU_LPB_LPBMSEL BITS(0,1) /*!< Low power mode selection signal */ 253 254 /* constants definitions */ 255 /* define the peripheral clock enable bit position and its register index offset */ 256 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos)) 257 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) 258 #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 259 /* define the voltage key unlock value */ 260 #define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4D) 261 262 /* register index */ 263 /* peripherals enable */ 264 #define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ 265 #define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ 266 #define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ 267 #define AHB2_REG_OFFSET 0x34U /*!< AHB2 enable register offset */ 268 269 /* peripherals reset */ 270 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ 271 #define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ 272 #define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ 273 #define AHB2RST_REG_OFFSET 0x38U /*!< AHB2 reset register offset */ 274 #define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ 275 276 /* clock control */ 277 #define CTL_REG_OFFSET 0x00U /*!< control register offset */ 278 #define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ 279 280 /* clock stabilization and stuck interrupt */ 281 #define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ 282 283 /* configuration register */ 284 #define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ 285 #define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ 286 #define CFG2_REG_OFFSET 0x30U /*!< clock configuration register 2 offset */ 287 288 /* peripheral clock enable */ 289 typedef enum { 290 /* AHB peripherals */ 291 RCU_DMA = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA clock */ 292 RCU_CAU = RCU_REGIDX_BIT(AHB2_REG_OFFSET, 1U), /*!< CAU clock */ 293 RCU_TRNG = RCU_REGIDX_BIT(AHB2_REG_OFFSET, 3U), /*!< TRNG clock */ 294 RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ 295 RCU_GPIOA = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 17U), /*!< GPIOA clock */ 296 RCU_GPIOB = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 18U), /*!< GPIOB clock */ 297 RCU_GPIOC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 19U), /*!< GPIOC clock */ 298 RCU_GPIOD = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 20U), /*!< GPIOD clock */ 299 RCU_GPIOF = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 22U), /*!< GPIOF clock */ 300 301 /* APB2 peripherals */ 302 RCU_SYSCFG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< SYSCFG clock */ 303 RCU_CMP = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 1U), /*!< CMP clock */ 304 RCU_ADC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC clock */ 305 RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ 306 RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ 307 RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ 308 RCU_DBGMCU = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 22U), /*!< DBGMCU clock */ 309 310 /* APB1 peripherals */ 311 RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ 312 RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ 313 RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ 314 RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ 315 RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER11 clock */ 316 RCU_LPTIMER = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 9U), /*!< LPTIMER clock */ 317 RCU_SLCD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 10U), /*!< SLCD clock */ 318 RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ 319 RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ 320 RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ 321 RCU_LPUART = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< LPUART clock */ 322 RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ 323 RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ 324 RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ 325 RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ 326 RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ 327 RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 24U), /*!< I2C2 clock */ 328 RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ 329 RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ 330 RCU_CTC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 30U), /*!< CTC clock */ 331 RCU_BKP = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 31U), /*!< BKP clock */ 332 333 /* Backup domain control(BDCTL) */ 334 RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U) /*!< RTC clock */ 335 } rcu_periph_enum; 336 337 /* peripheral clock enable when sleep mode*/ 338 typedef enum { 339 /* AHB peripherals */ 340 RCU_SRAM0_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM0 clock */ 341 RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ 342 RCU_SRAM1_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 7U), /*!< SRAM1 clock */ 343 } rcu_periph_sleep_enum; 344 345 /* peripherals reset */ 346 typedef enum { 347 /* AHB peripherals reset */ 348 RCU_CAURST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 1U), /*!< CAU reset */ 349 RCU_TRNGRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 3U), /*!< TRNG reset */ 350 RCU_CRCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 6U), /*!< CRC reset */ 351 RCU_GPIOARST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 17U), /*!< GPIOA reset */ 352 RCU_GPIOBRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 18U), /*!< GPIOB reset */ 353 RCU_GPIOCRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOC reset */ 354 RCU_GPIODRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 19U), /*!< GPIOD reset */ 355 RCU_GPIOFRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 22U), /*!< GPIOF reset */ 356 357 /* APB2 peripherals reset */ 358 RCU_SYSCFGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< SYSCFG reset */ 359 RCU_CMPRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 1U), /*!< CMP reset */ 360 RCU_ADCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC reset */ 361 RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER8 reset */ 362 RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 reset */ 363 RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 reset */ 364 365 /* APB1 peripherals reset */ 366 RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 reset */ 367 RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 reset */ 368 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 reset */ 369 RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 reset */ 370 RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER11 reset */ 371 RCU_LPTIMERRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 9U), /*!< LPTIMER reset */ 372 RCU_SLCDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 10U), /*!< SLCD reset */ 373 RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT reset */ 374 RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 reset */ 375 RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 reset */ 376 RCU_LPUARTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< LPUART reset */ 377 RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 reset */ 378 RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 reset */ 379 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 reset */ 380 RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 reset */ 381 RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD reset */ 382 RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 24U), /*!< I2C2 reset */ 383 RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU reset */ 384 RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC reset */ 385 RCU_CTCRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 30U), /*!< CTC reset */ 386 } rcu_periph_reset_enum; 387 388 /* clock stabilization and peripheral reset flags */ 389 typedef enum { 390 RCU_FLAG_IRC32KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC32K stabilization flags */ 391 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ 392 RCU_FLAG_IRC16MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC16M stabilization flags */ 393 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ 394 RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 21U), /*!< IRC48M stabilization flags */ 395 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ 396 397 RCU_FLAG_V12RST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 23U), /*!< V12 reset flags */ 398 RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< EPR reset flags */ 399 RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ 400 RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< SW reset flags */ 401 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ 402 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ 403 RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U) /*!< LP reset flags */ 404 } rcu_flag_enum; 405 406 /* clock stabilization and ckm interrupt flags */ 407 typedef enum { 408 RCU_INT_FLAG_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC32K stabilization interrupt flag */ 409 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ 410 RCU_INT_FLAG_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC16M stabilization interrupt flag */ 411 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ 412 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ 413 RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< IRC48M stabilization interrupt flag */ 414 RCU_INT_FLAG_LXTALCKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< LXTAL clock stuck interrupt flag */ 415 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< CKM interrupt flag */ 416 } rcu_int_flag_enum; 417 418 /* clock stabilization and stuck interrupt flags clear */ 419 typedef enum { 420 RCU_INT_FLAG_IRC32KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC32K stabilization interrupt flags clear */ 421 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ 422 RCU_INT_FLAG_IRC16MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC16M stabilization interrupt flags clear */ 423 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ 424 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ 425 RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< IRC48M stabilization interrupt flags clear */ 426 RCU_INT_FLAG_LXTALCKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< LXTAL clock stuck interrupt flag clear */ 427 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ 428 } rcu_int_flag_clear_enum; 429 430 /* clock stabilization interrupt enable or disable */ 431 typedef enum { 432 RCU_INT_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC32K stabilization interrupt */ 433 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ 434 RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC16M stabilization interrupt */ 435 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ 436 RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ 437 RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< IRC48M stabilization interrupt */ 438 RCU_INT_LXTALCKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< LXTAL clock stuck interrupt */ 439 } rcu_int_enum; 440 441 /* oscillator types */ 442 typedef enum { 443 RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ 444 RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ 445 RCU_IRC16M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC16M */ 446 RCU_IRC48M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 20U), /*!< IRC48M */ 447 RCU_IRC32K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC32K */ 448 RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U) /*!< PLL */ 449 } rcu_osci_type_enum; 450 451 /* rcu clock frequency */ 452 typedef enum { 453 CK_SYS = 0U, /*!< system clock */ 454 CK_AHB, /*!< AHB clock */ 455 CK_APB1, /*!< APB1 clock */ 456 CK_APB2, /*!< APB2 clock */ 457 CK_ADC, /*!< ADC clock */ 458 CK_USART0, /*!< USART0 clock */ 459 CK_I2C0, /*!< I2C0 clock */ 460 CK_I2C1, /*!< I2C1 clock */ 461 CK_I2C2, /*!< I2C2 clock */ 462 CK_LPUART, /*!< LPUART clock */ 463 CK_USART1, /*!< USART1 clock */ 464 CK_LPTIMER /*!< LPTIMER clock */ 465 } rcu_clock_freq_enum; 466 467 typedef enum { 468 IDX_USART0 = 0U, /*!< idnex of USART0 */ 469 IDX_USART1 /*!< idnex of USART1 */ 470 } usart_idx_enum; 471 472 typedef enum { 473 IDX_I2C0 = 0U, /*!< idnex of I2C0 */ 474 IDX_I2C1, /*!< idnex of I2C1 */ 475 IDX_I2C2 /*!< idnex of I2C2 */ 476 } i2c_idx_enum; 477 478 /* system clock source select */ 479 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) 480 #define RCU_CKSYSSRC_IRC16M CFG0_SCS(0) /*!< system clock source select IRC16M */ 481 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ 482 #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ 483 #define RCU_CKSYSSRC_IRC48M CFG0_SCS(3) /*!< system clock source select IRC48M */ 484 485 /* system clock source select status */ 486 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U)) 487 #define RCU_SCSS_IRC16M CFG0_SCSS(0) /*!< system clock source select IRC16M */ 488 #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ 489 #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ 490 #define RCU_SCSS_IRC48M CFG0_SCSS(3) /*!< system clock source select IRC48M */ 491 492 /* AHB prescaler selection */ 493 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4U)) 494 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ 495 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ 496 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ 497 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ 498 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ 499 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ 500 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ 501 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ 502 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ 503 504 /* APB1 prescaler selection */ 505 #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) 506 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ 507 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ 508 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ 509 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ 510 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ 511 512 /* APB2 prescaler selection */ 513 #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11U)) 514 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ 515 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ 516 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ 517 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ 518 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ 519 520 /* ADC clock prescaler selection */ 521 #define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14U)) 522 #define CFG2_ADCPSC(regval) (BITS(30,31) & ((uint32_t)(regval) << 30U)) 523 #define CFG_ADCPSC(regval) (BITS(0,4)& ((uint32_t)(regval))) 524 #define RCU_ADCCK_IRC16M CFG_ADCPSC(16) /*!< ADC clock select IRC16M */ 525 #define RCU_ADCCK_APB2_DIV2 CFG_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */ 526 #define RCU_ADCCK_APB2_DIV4 CFG_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */ 527 #define RCU_ADCCK_APB2_DIV6 CFG_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */ 528 #define RCU_ADCCK_APB2_DIV8 CFG_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */ 529 #define RCU_ADCCK_APB2_DIV10 CFG_ADCPSC(4) /*!< ADC clock prescaler select CK_APB2/10 */ 530 #define RCU_ADCCK_APB2_DIV12 CFG_ADCPSC(5) /*!< ADC clock prescaler select CK_APB2/12 */ 531 #define RCU_ADCCK_APB2_DIV14 CFG_ADCPSC(6) /*!< ADC clock prescaler select CK_APB2/14 */ 532 #define RCU_ADCCK_APB2_DIV16 CFG_ADCPSC(7) /*!< ADC clock prescaler select CK_APB2/16 */ 533 #define RCU_ADCCK_AHB_DIV3 CFG_ADCPSC(8) /*!< ADC clock prescaler select CK_AHB/3 */ 534 #define RCU_ADCCK_AHB_DIV5 CFG_ADCPSC(9) /*!< ADC clock prescaler select CK_AHB/5 */ 535 #define RCU_ADCCK_AHB_DIV7 CFG_ADCPSC(10) /*!< ADC clock prescaler select CK_AHB/7 */ 536 #define RCU_ADCCK_AHB_DIV9 CFG_ADCPSC(11) /*!< ADC clock prescaler select CK_AHB/9 */ 537 #define RCU_ADCCK_AHB_DIV11 CFG_ADCPSC(12) /*!< ADC clock prescaler select CK_AHB/11 */ 538 #define RCU_ADCCK_AHB_DIV13 CFG_ADCPSC(13) /*!< ADC clock prescaler select CK_AHB/13 */ 539 #define RCU_ADCCK_AHB_DIV15 CFG_ADCPSC(14) /*!< ADC clock prescaler select CK_AHB/15 */ 540 #define RCU_ADCCK_AHB_DIV17 CFG_ADCPSC(15) /*!< ADC clock prescaler select CK_AHB/17 */ 541 542 /* PLL clock source selection */ 543 #define CFG0_PLLSRC(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) 544 #define RCU_PLLSRC_IRC16M CFG0_PLLSRC(0) /*!< PLL clock source select IRC16M */ 545 #define RCU_PLLSRC_HXTAL CFG0_PLLSRC(1) /*!< PLL clock source select HXTAL */ 546 #define RCU_PLLSRC_IRC48M CFG0_PLLSRC(2) /*!< PLL clock source select IRC48M */ 547 548 /* PLL multiply factor */ 549 #define PLLMF_6 RCU_CFG0_PLLMF_6 /*!< bit 6 of PLLMF */ 550 #define CFG0_PLLMF(regval) (BITS(18,23) & ((uint32_t)(regval) << 18U)) 551 #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ 552 #define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ 553 #define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ 554 #define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ 555 #define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ 556 #define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ 557 #define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ 558 #define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ 559 #define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ 560 #define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ 561 #define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ 562 #define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ 563 #define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ 564 #define RCU_PLL_MUL17 CFG0_PLLMF(16) /*!< PLL source clock multiply by 17 */ 565 #define RCU_PLL_MUL18 CFG0_PLLMF(17) /*!< PLL source clock multiply by 18 */ 566 #define RCU_PLL_MUL19 CFG0_PLLMF(18) /*!< PLL source clock multiply by 19 */ 567 #define RCU_PLL_MUL20 CFG0_PLLMF(19) /*!< PLL source clock multiply by 20 */ 568 #define RCU_PLL_MUL21 CFG0_PLLMF(20) /*!< PLL source clock multiply by 21 */ 569 #define RCU_PLL_MUL22 CFG0_PLLMF(21) /*!< PLL source clock multiply by 22 */ 570 #define RCU_PLL_MUL23 CFG0_PLLMF(22) /*!< PLL source clock multiply by 23 */ 571 #define RCU_PLL_MUL24 CFG0_PLLMF(23) /*!< PLL source clock multiply by 24 */ 572 #define RCU_PLL_MUL25 CFG0_PLLMF(24) /*!< PLL source clock multiply by 25 */ 573 #define RCU_PLL_MUL26 CFG0_PLLMF(25) /*!< PLL source clock multiply by 26 */ 574 #define RCU_PLL_MUL27 CFG0_PLLMF(26) /*!< PLL source clock multiply by 27 */ 575 #define RCU_PLL_MUL28 CFG0_PLLMF(27) /*!< PLL source clock multiply by 28 */ 576 #define RCU_PLL_MUL29 CFG0_PLLMF(28) /*!< PLL source clock multiply by 29 */ 577 #define RCU_PLL_MUL30 CFG0_PLLMF(29) /*!< PLL source clock multiply by 30 */ 578 #define RCU_PLL_MUL31 CFG0_PLLMF(30) /*!< PLL source clock multiply by 31 */ 579 #define RCU_PLL_MUL32 CFG0_PLLMF(31) /*!< PLL source clock multiply by 32 */ 580 #define RCU_PLL_MUL33 CFG0_PLLMF(32) /*!< PLL source clock multiply by 33 */ 581 #define RCU_PLL_MUL34 CFG0_PLLMF(33) /*!< PLL source clock multiply by 34 */ 582 #define RCU_PLL_MUL35 CFG0_PLLMF(34) /*!< PLL source clock multiply by 35 */ 583 #define RCU_PLL_MUL36 CFG0_PLLMF(35) /*!< PLL source clock multiply by 36 */ 584 #define RCU_PLL_MUL37 CFG0_PLLMF(36) /*!< PLL source clock multiply by 37 */ 585 #define RCU_PLL_MUL38 CFG0_PLLMF(37) /*!< PLL source clock multiply by 38 */ 586 #define RCU_PLL_MUL39 CFG0_PLLMF(38) /*!< PLL source clock multiply by 39 */ 587 #define RCU_PLL_MUL40 CFG0_PLLMF(39) /*!< PLL source clock multiply by 40 */ 588 #define RCU_PLL_MUL41 CFG0_PLLMF(40) /*!< PLL source clock multiply by 41 */ 589 #define RCU_PLL_MUL42 CFG0_PLLMF(41) /*!< PLL source clock multiply by 42 */ 590 #define RCU_PLL_MUL43 CFG0_PLLMF(42) /*!< PLL source clock multiply by 43 */ 591 #define RCU_PLL_MUL44 CFG0_PLLMF(43) /*!< PLL source clock multiply by 44 */ 592 #define RCU_PLL_MUL45 CFG0_PLLMF(44) /*!< PLL source clock multiply by 45 */ 593 #define RCU_PLL_MUL46 CFG0_PLLMF(45) /*!< PLL source clock multiply by 46 */ 594 #define RCU_PLL_MUL47 CFG0_PLLMF(46) /*!< PLL source clock multiply by 47 */ 595 #define RCU_PLL_MUL48 CFG0_PLLMF(47) /*!< PLL source clock multiply by 48 */ 596 #define RCU_PLL_MUL49 CFG0_PLLMF(48) /*!< PLL source clock multiply by 49 */ 597 #define RCU_PLL_MUL50 CFG0_PLLMF(49) /*!< PLL source clock multiply by 50 */ 598 #define RCU_PLL_MUL51 CFG0_PLLMF(50) /*!< PLL source clock multiply by 51 */ 599 #define RCU_PLL_MUL52 CFG0_PLLMF(51) /*!< PLL source clock multiply by 52 */ 600 #define RCU_PLL_MUL53 CFG0_PLLMF(52) /*!< PLL source clock multiply by 53 */ 601 #define RCU_PLL_MUL54 CFG0_PLLMF(53) /*!< PLL source clock multiply by 54 */ 602 #define RCU_PLL_MUL55 CFG0_PLLMF(54) /*!< PLL source clock multiply by 55 */ 603 #define RCU_PLL_MUL56 CFG0_PLLMF(55) /*!< PLL source clock multiply by 56 */ 604 #define RCU_PLL_MUL57 CFG0_PLLMF(56) /*!< PLL source clock multiply by 57 */ 605 #define RCU_PLL_MUL58 CFG0_PLLMF(57) /*!< PLL source clock multiply by 58 */ 606 #define RCU_PLL_MUL59 CFG0_PLLMF(58) /*!< PLL source clock multiply by 59 */ 607 #define RCU_PLL_MUL60 CFG0_PLLMF(59) /*!< PLL source clock multiply by 60 */ 608 #define RCU_PLL_MUL61 CFG0_PLLMF(60) /*!< PLL source clock multiply by 61 */ 609 #define RCU_PLL_MUL62 CFG0_PLLMF(61) /*!< PLL source clock multiply by 62 */ 610 #define RCU_PLL_MUL63 CFG0_PLLMF(62) /*!< PLL source clock multiply by 63 */ 611 #define RCU_PLL_MUL64 CFG0_PLLMF(63) /*!< PLL source clock multiply by 64 */ 612 #define RCU_PLL_MUL63 CFG0_PLLMF(62) /*!< PLL source clock multiply by 63 */ 613 #define RCU_PLL_MUL64 CFG0_PLLMF(63) /*!< PLL source clock multiply by 64 */ 614 #define RCU_PLL_MUL65 (PLLMF_6 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 65 */ 615 #define RCU_PLL_MUL66 (PLLMF_6 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 66 */ 616 #define RCU_PLL_MUL67 (PLLMF_6 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 67 */ 617 #define RCU_PLL_MUL68 (PLLMF_6 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 68 */ 618 #define RCU_PLL_MUL69 (PLLMF_6 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 69 */ 619 #define RCU_PLL_MUL70 (PLLMF_6 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 70 */ 620 #define RCU_PLL_MUL71 (PLLMF_6 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 71 */ 621 #define RCU_PLL_MUL72 (PLLMF_6 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 72 */ 622 #define RCU_PLL_MUL73 (PLLMF_6 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 73 */ 623 #define RCU_PLL_MUL74 (PLLMF_6 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 74 */ 624 #define RCU_PLL_MUL75 (PLLMF_6 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 75 */ 625 #define RCU_PLL_MUL76 (PLLMF_6 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 76 */ 626 #define RCU_PLL_MUL77 (PLLMF_6 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 77 */ 627 #define RCU_PLL_MUL78 (PLLMF_6 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 78 */ 628 #define RCU_PLL_MUL79 (PLLMF_6 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 79 */ 629 #define RCU_PLL_MUL80 (PLLMF_6 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 80 */ 630 #define RCU_PLL_MUL81 (PLLMF_6 | CFG0_PLLMF(16)) /*!< PLL source clock multiply by 81 */ 631 #define RCU_PLL_MUL82 (PLLMF_6 | CFG0_PLLMF(17)) /*!< PLL source clock multiply by 82 */ 632 #define RCU_PLL_MUL83 (PLLMF_6 | CFG0_PLLMF(18)) /*!< PLL source clock multiply by 83 */ 633 #define RCU_PLL_MUL84 (PLLMF_6 | CFG0_PLLMF(19)) /*!< PLL source clock multiply by 84 */ 634 #define RCU_PLL_MUL85 (PLLMF_6 | CFG0_PLLMF(20)) /*!< PLL source clock multiply by 85 */ 635 #define RCU_PLL_MUL86 (PLLMF_6 | CFG0_PLLMF(21)) /*!< PLL source clock multiply by 86 */ 636 #define RCU_PLL_MUL87 (PLLMF_6 | CFG0_PLLMF(22)) /*!< PLL source clock multiply by 87 */ 637 #define RCU_PLL_MUL88 (PLLMF_6 | CFG0_PLLMF(23)) /*!< PLL source clock multiply by 88 */ 638 #define RCU_PLL_MUL89 (PLLMF_6 | CFG0_PLLMF(24)) /*!< PLL source clock multiply by 89 */ 639 #define RCU_PLL_MUL90 (PLLMF_6 | CFG0_PLLMF(25)) /*!< PLL source clock multiply by 90 */ 640 #define RCU_PLL_MUL91 (PLLMF_6 | CFG0_PLLMF(26)) /*!< PLL source clock multiply by 91 */ 641 #define RCU_PLL_MUL92 (PLLMF_6 | CFG0_PLLMF(27)) /*!< PLL source clock multiply by 92 */ 642 #define RCU_PLL_MUL93 (PLLMF_6 | CFG0_PLLMF(28)) /*!< PLL source clock multiply by 93 */ 643 #define RCU_PLL_MUL94 (PLLMF_6 | CFG0_PLLMF(29)) /*!< PLL source clock multiply by 94 */ 644 #define RCU_PLL_MUL95 (PLLMF_6 | CFG0_PLLMF(30)) /*!< PLL source clock multiply by 95 */ 645 #define RCU_PLL_MUL96 (PLLMF_6 | CFG0_PLLMF(31)) /*!< PLL source clock multiply by 96 */ 646 #define RCU_PLL_MUL97 (PLLMF_6 | CFG0_PLLMF(32)) /*!< PLL source clock multiply by 97 */ 647 #define RCU_PLL_MUL98 (PLLMF_6 | CFG0_PLLMF(33)) /*!< PLL source clock multiply by 98 */ 648 #define RCU_PLL_MUL99 (PLLMF_6 | CFG0_PLLMF(34)) /*!< PLL source clock multiply by 99 */ 649 #define RCU_PLL_MUL100 (PLLMF_6 | CFG0_PLLMF(35)) /*!< PLL source clock multiply by 100 */ 650 #define RCU_PLL_MUL101 (PLLMF_6 | CFG0_PLLMF(36)) /*!< PLL source clock multiply by 101 */ 651 #define RCU_PLL_MUL102 (PLLMF_6 | CFG0_PLLMF(37)) /*!< PLL source clock multiply by 102 */ 652 #define RCU_PLL_MUL103 (PLLMF_6 | CFG0_PLLMF(38)) /*!< PLL source clock multiply by 103 */ 653 #define RCU_PLL_MUL104 (PLLMF_6 | CFG0_PLLMF(39)) /*!< PLL source clock multiply by 104 */ 654 #define RCU_PLL_MUL105 (PLLMF_6 | CFG0_PLLMF(40)) /*!< PLL source clock multiply by 105 */ 655 #define RCU_PLL_MUL106 (PLLMF_6 | CFG0_PLLMF(41)) /*!< PLL source clock multiply by 106 */ 656 #define RCU_PLL_MUL107 (PLLMF_6 | CFG0_PLLMF(42)) /*!< PLL source clock multiply by 107 */ 657 #define RCU_PLL_MUL108 (PLLMF_6 | CFG0_PLLMF(43)) /*!< PLL source clock multiply by 108 */ 658 #define RCU_PLL_MUL109 (PLLMF_6 | CFG0_PLLMF(44)) /*!< PLL source clock multiply by 109 */ 659 #define RCU_PLL_MUL110 (PLLMF_6 | CFG0_PLLMF(45)) /*!< PLL source clock multiply by 110 */ 660 #define RCU_PLL_MUL111 (PLLMF_6 | CFG0_PLLMF(46)) /*!< PLL source clock multiply by 111 */ 661 #define RCU_PLL_MUL112 (PLLMF_6 | CFG0_PLLMF(47)) /*!< PLL source clock multiply by 112 */ 662 #define RCU_PLL_MUL113 (PLLMF_6 | CFG0_PLLMF(48)) /*!< PLL source clock multiply by 113 */ 663 #define RCU_PLL_MUL114 (PLLMF_6 | CFG0_PLLMF(49)) /*!< PLL source clock multiply by 114 */ 664 #define RCU_PLL_MUL115 (PLLMF_6 | CFG0_PLLMF(50)) /*!< PLL source clock multiply by 115 */ 665 #define RCU_PLL_MUL116 (PLLMF_6 | CFG0_PLLMF(51)) /*!< PLL source clock multiply by 116 */ 666 #define RCU_PLL_MUL117 (PLLMF_6 | CFG0_PLLMF(52)) /*!< PLL source clock multiply by 117 */ 667 #define RCU_PLL_MUL118 (PLLMF_6 | CFG0_PLLMF(53)) /*!< PLL source clock multiply by 118 */ 668 #define RCU_PLL_MUL119 (PLLMF_6 | CFG0_PLLMF(54)) /*!< PLL source clock multiply by 119 */ 669 #define RCU_PLL_MUL120 (PLLMF_6 | CFG0_PLLMF(55)) /*!< PLL source clock multiply by 120 */ 670 #define RCU_PLL_MUL121 (PLLMF_6 | CFG0_PLLMF(56)) /*!< PLL source clock multiply by 121 */ 671 #define RCU_PLL_MUL122 (PLLMF_6 | CFG0_PLLMF(57)) /*!< PLL source clock multiply by 122 */ 672 #define RCU_PLL_MUL123 (PLLMF_6 | CFG0_PLLMF(58)) /*!< PLL source clock multiply by 123 */ 673 #define RCU_PLL_MUL124 (PLLMF_6 | CFG0_PLLMF(59)) /*!< PLL source clock multiply by 124 */ 674 #define RCU_PLL_MUL125 (PLLMF_6 | CFG0_PLLMF(60)) /*!< PLL source clock multiply by 125 */ 675 #define RCU_PLL_MUL126 (PLLMF_6 | CFG0_PLLMF(61)) /*!< PLL source clock multiply by 126 */ 676 #define RCU_PLL_MUL127 (PLLMF_6 | CFG0_PLLMF(62)) /*!< PLL source clock multiply by 127 */ 677 678 /* CK_OUT clock source selection */ 679 #define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24U)) 680 #define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */ 681 #define RCU_CKOUTSRC_IRC48M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC48M */ 682 #define RCU_CKOUTSRC_IRC32K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC32K */ 683 #define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */ 684 #define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */ 685 #define RCU_CKOUTSRC_IRC16M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC16M */ 686 #define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */ 687 #define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */ 688 #define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */ 689 690 /* CK_OUT divider */ 691 #define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28U)) 692 #define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ 693 #define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ 694 #define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ 695 #define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ 696 #define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ 697 #define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ 698 #define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ 699 #define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ 700 701 /* CK_PLL divide by 1 or 2 for CK_OUT */ 702 #define RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U /*!< CK_PLL divide by 2 for CK_OUT */ 703 #define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */ 704 705 /* LXTAL drive capability */ 706 #define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3U)) 707 #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ 708 #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ 709 #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ 710 #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ 711 712 /* RTC clock entry selection */ 713 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U)) 714 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ 715 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */ 716 #define RCU_RTCSRC_IRC32K BDCTL_RTCSRC(2) /*!< IRC32K selected as RTC source clock */ 717 #define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */ 718 719 /* CK_HXTAL divider previous PLL */ 720 #define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0U)) 721 #define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */ 722 #define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */ 723 #define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */ 724 #define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */ 725 #define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */ 726 #define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */ 727 #define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */ 728 #define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */ 729 #define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */ 730 #define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */ 731 #define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */ 732 #define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */ 733 #define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */ 734 #define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */ 735 #define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */ 736 #define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */ 737 738 /* USART0 clock source selection */ 739 #define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) 740 #define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */ 741 #define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */ 742 #define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */ 743 #define RCU_USART0SRC_IRC16MDIV CFG2_USART0SEL(3) /*!< CK_USART0 select IRC16MDIV */ 744 745 /* LPUART clock source selection */ 746 #define CFG2_LPUARTSEL(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) 747 #define RCU_LPUARTSRC_CKAPB1 CFG2_LPUARTSEL(0) /*!< CK_LPUART select CK_APB1 */ 748 #define RCU_LPUARTSRC_CKSYS CFG2_LPUARTSEL(1) /*!< CK_LPUART select CK_SYS */ 749 #define RCU_LPUARTSRC_LXTAL CFG2_LPUARTSEL(2) /*!< CK_LPUART select LXTAL */ 750 #define RCU_LPUARTSRC_IRC16MDIV CFG2_LPUARTSEL(3) /*!< CK_LPUART select IRC16MDIV */ 751 752 /* USART1 clock source selection */ 753 #define CFG2_USART1SEL(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) 754 #define RCU_USART1SRC_CKAPB1 CFG2_USART1SEL(0) /*!< CK_USART1 select CK_APB1 */ 755 #define RCU_USART1SRC_CKSYS CFG2_USART1SEL(1) /*!< CK_USART1 select CK_SYS */ 756 #define RCU_USART1SRC_LXTAL CFG2_USART1SEL(2) /*!< CK_USART1 select LXTAL */ 757 #define RCU_USART1SRC_IRC16MDIV CFG2_USART1SEL(3) /*!< CK_USART1 select IRC16MDIV */ 758 759 /* USARTx(x=0,1) clock source selection */ 760 #define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) 761 #define RCU_USARTSRC_CKAPB CFG2_USART0SEL(0) /*!< CK_USART select CK_APB1/CK_APB2 */ 762 #define RCU_USARTSRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART select CK_SYS */ 763 #define RCU_USARTSRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART select LXTAL */ 764 #define RCU_USARTSRC_IRC16MDIV CFG2_USART0SEL(3) /*!< CK_USART select IRC16MDIV */ 765 766 /* I2Cx(x=0,1,2) clock source selection */ 767 #define CFG2_I2C0SEL(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U)) 768 #define RCU_I2CSRC_CKAPB1 CFG2_I2C0SEL(0) /*!< CK_I2C select CK_APB1 */ 769 #define RCU_I2CSRC_CKSYS CFG2_I2C0SEL(1) /*!< CK_I2C select CK_SYS */ 770 #define RCU_I2CSRC_IRC16MDIV CFG2_I2C0SEL(2) /*!< CK_I2C select IRC16MDIV */ 771 772 /* LPTIMER clock source selection */ 773 #define CFG2_LPTIMERSEL(regval) (BITS(9,10) & ((uint32_t)(regval) << 9U)) 774 #define RCU_LPTIMERSRC_CKAPB1 CFG2_LPTIMERSEL(0) /*!< CK_LPTIMER select CK_APB1 */ 775 #define RCU_LPTIMERSRC_IRC32K CFG2_LPTIMERSEL(1) /*!< CK_LPTIMER select CK_IRC32K */ 776 #define RCU_LPTIMERSRC_LXTAL CFG2_LPTIMERSEL(2) /*!< CK_LPTIMER select LXTAL */ 777 #define RCU_LPTIMERSRC_IRC16MDIV CFG2_LPTIMERSEL(3) /*!< CK_LPTIMER select IRC16MDIV */ 778 779 /* IRC16MDIV clock source selection */ 780 #define CFG2_IRC16MDIVSEL(regval) (BITS(18,20) & ((uint32_t)(regval) << 18U)) 781 #define RCU_IRC16MDIV_NONE CFG2_IRC16MDIVSEL(0) /*!< CK_IRC16MDIV select CK_IRC16M */ 782 #define RCU_IRC16MDIV_2 CFG2_IRC16MDIVSEL(4) /*!< CK_IRC16MDIV select CK_IRC16M divided by 2 */ 783 #define RCU_IRC16MDIV_4 CFG2_IRC16MDIVSEL(5) /*!< CK_IRC16MDIV select CK_IRC16M divided by 4 */ 784 #define RCU_IRC16MDIV_8 CFG2_IRC16MDIVSEL(6) /*!< CK_IRC16MDIV select CK_IRC16M divided by 8 */ 785 #define RCU_IRC16MDIV_16 CFG2_IRC16MDIVSEL(7) /*!< CK_IRC16MDIV select CK_IRC16M divided by 16 */ 786 787 /* USBD clock source selection */ 788 #define RCU_USBDSRC_IRC48M (uint32_t)0x00000000U /*!< CK_USBD select CK_IRC48M */ 789 #define RCU_USBDSRC_PLL RCU_CFG2_USBDSEL /*!< CK_USBD select CK_PLL */ 790 791 /* ADC clock source selection */ 792 #define RCU_ADCSRC_IRC16M (uint32_t)0x00000000U /*!< ADC clock source select */ 793 #define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */ 794 795 /* low power mode LDO voltage selection */ 796 #define RCU_LP_LDO_V_0_8 (uint32_t)0x00000000U /*!< LP_LDO output voltage 0.8V */ 797 #define RCU_LP_LDO_V_0_9 RCU_LPLDO_LPLDOVOS /*!< LP_LDO output voltage 0.9V */ 798 799 /* low power bandgap mode selection */ 800 #define LPB_LPBMSEL(regval) BITS(0,2) & ((uint32_t)(regval) << 0U)) 801 #define RCU_LPBM_32CLK LPB_LPBMSEL(3) /*!< The length of holding phase is 3.2ms, 32 clock cycles */ 802 #define RCU_LPBM_64CLK LPB_LPBMSEL(2) /*!< The length of holding phase is 6.4ms, 64 clock cycles */ 803 #define RCU_LPBM_128CLK LPB_LPBMSEL(1) /*!< The length of holding phase is 12.8ms, 128 clock cycles */ 804 #define RCU_LPBM_256CLK LPB_LPBMSEL(0) /*!< The length of holding phase is 25.6ms, 256 clock cycles */ 805 #define RCU_LPBM_512CLK LPB_LPBMSEL(7) /*!< The length of holding phase is 51.2ms, 512 clock cycles */ 806 #define RCU_LPBM_1024CLK LPB_LPBMSEL(6) /*!< The length of holding phase is 102.4ms, 1024 clock cycles */ 807 #define RCU_LPBM_2048CLK LPB_LPBMSEL(5) /*!< The length of holding phase is 204.8ms, 2048 clock cycles */ 808 809 /* function declarations */ 810 /* initialization, peripheral clock and reset configuration functions */ 811 /* deinitialize the RCU */ 812 void rcu_deinit(void); 813 /* enable the peripherals clock */ 814 void rcu_periph_clock_enable(rcu_periph_enum periph); 815 /* disable the peripherals clock */ 816 void rcu_periph_clock_disable(rcu_periph_enum periph); 817 /* enable the peripherals clock when sleep mode */ 818 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); 819 /* disable the peripherals clock when sleep mode */ 820 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); 821 /* reset the peripherals */ 822 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); 823 /* disable reset the peripheral */ 824 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); 825 /* reset the BKP */ 826 void rcu_bkp_reset_enable(void); 827 /* disable the BKP reset */ 828 void rcu_bkp_reset_disable(void); 829 830 /* system clock, AHB, APB1, APB2, ADC and clock out configuration functions */ 831 /* configure the system clock source */ 832 void rcu_system_clock_source_config(uint32_t ck_sys); 833 /* get the system clock source */ 834 uint32_t rcu_system_clock_source_get(void); 835 /* configure the AHB prescaler selection */ 836 void rcu_ahb_clock_config(uint32_t ck_ahb); 837 /* configure the APB1 prescaler selection */ 838 void rcu_apb1_clock_config(uint32_t ck_apb1); 839 /* configure the APB2 prescaler selection */ 840 void rcu_apb2_clock_config(uint32_t ck_apb2); 841 /* configure the ADC clock source and prescaler selection */ 842 void rcu_adc_clock_config(uint32_t ck_adc); 843 /* configure the CK_OUT clock source and divider */ 844 void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); 845 846 /* configure the PLL clock source selection and PLL multiply factor */ 847 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); 848 /* configure the USARTx(x=0,1) clock source selection */ 849 void rcu_usart_clock_config(usart_idx_enum usart_idx, uint32_t ck_usart); 850 /* configure the I2Cx(x=0,1,2) clock source selection */ 851 void rcu_i2c_clock_config(i2c_idx_enum i2c_idx, uint32_t ck_i2c); 852 /* configure the LPTIMER clock source selection */ 853 void rcu_lptimer_clock_config(uint32_t ck_lptimer); 854 /* configure the LPUART clock source selection */ 855 void rcu_lpuart_clock_config(uint32_t ck_lpuart); 856 /* configure the IRC16MDIV clock selection */ 857 void rcu_irc16mdiv_clock_config(uint32_t ck_irc16mdiv); 858 /* configure the USBD clock source selection */ 859 void rcu_usbd_clock_config(uint32_t ck_usbd); 860 /* configure the RTC clock source selection */ 861 void rcu_rtc_clock_config(uint32_t rtc_clock_source); 862 /* configure PLL source clocks pre-divider */ 863 void rcu_pll_source_ck_prediv_config(uint32_t pllsource_ck_prediv); 864 /* configure the LXTAL drive capability */ 865 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); 866 /* configure the low power mode LDO voltage selection */ 867 void rcu_lp_ldo_config(uint32_t lp_ldo_voltage); 868 /* configure low power bandgap mode selection */ 869 void rcu_lp_bandgap_config(uint32_t lp_bandgap_clock); 870 871 /* flag and interrupt functions */ 872 /* get the clock stabilization and periphral reset flags */ 873 FlagStatus rcu_flag_get(rcu_flag_enum flag); 874 /* clear the reset flag */ 875 void rcu_all_reset_flag_clear(void); 876 /* get the clock stabilization interrupt and ckm flags */ 877 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); 878 /* clear the interrupt flags */ 879 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); 880 /* enable the stabilization interrupt */ 881 void rcu_interrupt_enable(rcu_int_enum stab_int); 882 /* disable the stabilization interrupt */ 883 void rcu_interrupt_disable(rcu_int_enum stab_int); 884 885 /* oscillator configuration functions */ 886 /* wait until oscillator stabilization flags is SET */ 887 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); 888 /* turn on the oscillator */ 889 void rcu_osci_on(rcu_osci_type_enum osci); 890 /* turn off the oscillator */ 891 void rcu_osci_off(rcu_osci_type_enum osci); 892 /* enable the oscillator bypass mode */ 893 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); 894 /* disable the oscillator bypass mode */ 895 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); 896 /* enable the HXTAL clock monitor */ 897 void rcu_hxtal_clock_monitor_enable(void); 898 /* disable the HXTAL clock monitor */ 899 void rcu_hxtal_clock_monitor_disable(void); 900 /* enable the LXTAL clock monitor */ 901 void rcu_lxtal_clock_monitor_enable(void); 902 /* disable the LXTAL clock monitor */ 903 void rcu_lxtal_clock_monitor_disable(void); 904 905 /* set the IRC16M adjust value */ 906 void rcu_irc16m_adjust_value_set(uint8_t irc16m_adjval); 907 /* unlock the voltage key */ 908 void rcu_voltage_key_unlock(void); 909 910 /* get the system clock, bus and peripheral clock frequency */ 911 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); 912 913 #endif /* GD32L23X_RCU_H */ 914
