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Searched refs:MAC_PHY_CTL_PR (Results 1 – 4 of 4) sorted by relevance

/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_enet.h1118 #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!… macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_enet.h1094 #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!… macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_enet.c1604 … reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); in enet_phy_write_read()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_enet.c1612 … reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); in enet_phy_write_read()