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Searched refs:ENABLE (Results 1 – 25 of 32) sorted by relevance

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/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_syscfg.c155 if(ENABLE == newvalue) { in syscfg_adc_ch_remap_config()
163 if(ENABLE == newvalue) { in syscfg_adc_ch_remap_config()
171 if(ENABLE == newvalue) { in syscfg_adc_ch_remap_config()
179 if(ENABLE == newvalue) { in syscfg_adc_ch_remap_config()
Dgd32a50x_can.c162 if((uint8_t)ENABLE == can_parameter_init->local_priority_enable) { in can_init()
166 if((uint8_t)ENABLE == can_parameter_init->rx_private_filter_queue_enable) { in can_init()
174 if((uint32_t)ENABLE == can_parameter_init->protocol_exception_enable) { in can_init()
178 if((uint8_t)ENABLE == can_parameter_init->mb_tx_abort_enable) { in can_init()
233 ((can_parameter_struct *)p_struct)->mb_tx_abort_enable = (uint8_t)ENABLE; in can_struct_para_init()
252 ((can_fd_parameter_struct *)p_struct)->bitrate_switch_enable = (uint32_t)ENABLE; in can_struct_para_init()
554 if((uint32_t)ENABLE == can_fd_para_init->iso_can_fd_enable) { in can_fd_config()
558 if((uint32_t)ENABLE == can_fd_para_init->tdc_enable) { in can_fd_config()
562 if((uint32_t)ENABLE == can_fd_para_init->bitrate_switch_enable) { in can_fd_config()
672 if((uint8_t)ENABLE == can_fifo_para_init->dma_enable) { in can_rx_fifo_config()
Dgd32a50x_timer.c394 if(ENABLE == newvalue) { in timer_channel_control_shadow_config()
668 if(ENABLE == newvalue) { in timer_primary_output_config()
2492 if(ENABLE == newvalue) { in timer_channel_composite_pwm_mode_config()
2740 if(ENABLE == newvalue) { in timer_channel_break_control_config()
2762 if(ENABLE == newvalue) { in timer_channel_dead_time_config()
Dgd32a50x_adc.c678 if(ENABLE == newvalue){ in adc_watchdog1_channel_config()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_exmc.c86 exmc_norsram_init_struct->address_data_mux = ENABLE; in exmc_norsram_struct_para_init()
93 exmc_norsram_init_struct->memory_write = ENABLE; in exmc_norsram_struct_para_init()
94 exmc_norsram_init_struct->nwait_signal = ENABLE; in exmc_norsram_struct_para_init()
176 if(ENABLE == exmc_norsram_init_struct->extended_mode){ in exmc_norsram_init()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_exmc.c79 exmc_norsram_init_struct->address_data_mux = ENABLE; in exmc_norsram_struct_para_init()
83 exmc_norsram_init_struct->memory_write = ENABLE; in exmc_norsram_struct_para_init()
84 exmc_norsram_init_struct->nwait_signal = ENABLE; in exmc_norsram_struct_para_init()
Dgd32vf103_can.c184 if(ENABLE == can_parameter_init->time_triggered){ in can_init()
190 if(ENABLE == can_parameter_init->auto_bus_off_recovery){ in can_init()
196 if(ENABLE == can_parameter_init->auto_wake_up){ in can_init()
202 if(ENABLE == can_parameter_init->no_auto_retrans){ in can_init()
208 if(ENABLE == can_parameter_init->rec_fifo_overwrite){ in can_init()
214 if(ENABLE == can_parameter_init->trans_fifo_order){ in can_init()
305 if(ENABLE == can_filter_parameter_init->filter_enable){ in can_filter_init()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_exmc.c122 exmc_norsram_init_struct->address_data_mux = ENABLE; in exmc_norsram_struct_para_init()
129 exmc_norsram_init_struct->memory_write = ENABLE; in exmc_norsram_struct_para_init()
130 exmc_norsram_init_struct->nwait_signal = ENABLE; in exmc_norsram_struct_para_init()
227 if(ENABLE == exmc_norsram_init_struct->extended_mode){ in exmc_norsram_init()
424 if (ENABLE == newvalue){ in exmc_nand_ecc_config()
Dgd32e50x_can.c202 ((can_fdframe_struct*)p_struct)->excp_event_detect = ENABLE; in can_struct_para_init()
349 if(ENABLE == can_parameter_init->time_triggered){ in can_init()
355 if(ENABLE == can_parameter_init->auto_bus_off_recovery){ in can_init()
361 if(ENABLE == can_parameter_init->auto_wake_up){ in can_init()
367 if(ENABLE == can_parameter_init->auto_retrans){ in can_init()
373 if(ENABLE == can_parameter_init->rec_fifo_overwrite){ in can_init()
379 if(ENABLE == can_parameter_init->trans_fifo_order){ in can_init()
472 if(ENABLE == can_filter_parameter_init->filter_enable){ in can_filter_init()
511 can_filter.filter_enable = ENABLE; in can_filter_mask_mode_init()
679 if(ENABLE == can_fdframe_init->excp_event_detect){ in can_fd_init()
[all …]
Dgd32e50x_adc.c473 if(ENABLE == newvalue){ in adc_channel_differential_mode_config()
734 if(ENABLE == newvalue){ in adc_watchdog1_channel_config()
753 if(ENABLE == newvalue){ in adc_watchdog2_channel_config()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_exmc.c122 exmc_norsram_init_struct->address_data_mux = ENABLE; in exmc_norsram_struct_para_init()
129 exmc_norsram_init_struct->memory_write = ENABLE; in exmc_norsram_struct_para_init()
130 exmc_norsram_init_struct->nwait_signal = ENABLE; in exmc_norsram_struct_para_init()
213 if(ENABLE == exmc_norsram_init_struct->extended_mode){ in exmc_norsram_init()
505 if (ENABLE == newvalue){ in exmc_nand_ecc_config()
Dgd32f403_can.c184 if(ENABLE == can_parameter_init->time_triggered){ in can_init()
190 if(ENABLE == can_parameter_init->auto_bus_off_recovery){ in can_init()
196 if(ENABLE == can_parameter_init->auto_wake_up){ in can_init()
202 if(ENABLE == can_parameter_init->no_auto_retrans){ in can_init()
208 if(ENABLE == can_parameter_init->rec_fifo_overwrite){ in can_init()
214 if(ENABLE == can_parameter_init->trans_fifo_order){ in can_init()
305 if(ENABLE == can_filter_parameter_init->filter_enable){ in can_filter_init()
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_exmc.c150 exmc_norsram_init_struct->address_data_mux = ENABLE; in exmc_norsram_struct_para_init()
157 exmc_norsram_init_struct->memory_write = ENABLE; in exmc_norsram_struct_para_init()
158 exmc_norsram_init_struct->nwait_signal = ENABLE; in exmc_norsram_struct_para_init()
255 if(ENABLE == exmc_norsram_init_struct->extended_mode) { in exmc_norsram_init()
566 exmc_sdram_init_struct->write_protection = ENABLE; in exmc_sdram_struct_para_init()
769 if(ENABLE == newvalue) { in exmc_nand_ecc_config()
799 if(ENABLE == newvalue) { in exmc_sdram_readsample_enable()
886 if(ENABLE == newvalue) { in exmc_sdram_write_protection_config()
Dgd32f4xx_can.c83 ((can_parameter_struct *)p_struct)->auto_retrans = ENABLE; in can_struct_para_init()
86 ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = ENABLE; in can_struct_para_init()
185 if(ENABLE == can_parameter_init->time_triggered) { in can_init()
191 if(ENABLE == can_parameter_init->auto_bus_off_recovery) { in can_init()
197 if(ENABLE == can_parameter_init->auto_wake_up) { in can_init()
215 if(ENABLE == can_parameter_init->trans_fifo_order) { in can_init()
306 if(ENABLE == can_filter_parameter_init->filter_enable) { in can_filter_init()
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_slcd.c315 if(ENABLE == newvalue) { in slcd_com_seg_remap()
351 if(ENABLE == newvalue) { in slcd_high_drive_config()
Dgd32l23x_cau_aes.c400 while(ENABLE == cau_enable_state_get()) { in cau_aes_gcm()
632 while(ENABLE == cau_enable_state_get()) { in cau_aes_ccm()
Dgd32l23x_cau.c404 ret = ENABLE; in cau_enable_state_get()
/hal_gigadevice-latest/gd32vf103/riscv/include/
Dgd32vf103.h179 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; enumerator
/hal_gigadevice-latest/gd32f3x0/cmsis/gd/gd32f3x0/include/
Dgd32f3x0.h177 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; enumerator
/hal_gigadevice-latest/gd32f403/cmsis/gd/gd32f403/include/
Dgd32f403.h182 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; enumerator
/hal_gigadevice-latest/gd32e10x/cmsis/gd/gd32e10x/include/
Dgd32e10x.h190 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; enumerator
/hal_gigadevice-latest/gd32l23x/cmsis/gd/gd32l23x/include/
Dgd32l23x.h179 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; enumerator
/hal_gigadevice-latest/gd32a50x/cmsis/gd/gd32a50x/include/
Dgd32a50x.h184 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; enumerator
/hal_gigadevice-latest/gd32f4xx/cmsis/gd/gd32f4xx/include/
Dgd32f4xx.h290 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; enumerator
/hal_gigadevice-latest/gd32e50x/cmsis/gd/gd32e50x/include/
Dgd32e50x.h464 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; enumerator

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