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Searched refs:CTC_CTL1 (Results 1 – 12 of 12) sorted by relevance

/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_ctc.c135 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); in ctc_refsource_polarity_config()
136 CTC_CTL1 |= (uint32_t)polarity; in ctc_refsource_polarity_config()
149 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_USBSOFSEL); in ctc_usbsof_signal_select()
150 CTC_CTL1 |= (uint32_t)usbsof; in ctc_usbsof_signal_select()
165 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); in ctc_refsource_signal_select()
166 CTC_CTL1 |= (uint32_t)refs; in ctc_refsource_signal_select()
186 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); in ctc_refsource_prescaler_config()
187 CTC_CTL1 |= (uint32_t)prescaler; in ctc_refsource_prescaler_config()
199 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
200 CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); in ctc_clock_limit_value_config()
[all …]
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_ctc.c132 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); in ctc_refsource_polarity_config()
133 CTC_CTL1 |= (uint32_t)polarity; in ctc_refsource_polarity_config()
148 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); in ctc_refsource_signal_select()
149 CTC_CTL1 |= (uint32_t)refs; in ctc_refsource_signal_select()
169 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); in ctc_refsource_prescaler_config()
170 CTC_CTL1 |= (uint32_t)prescaler; in ctc_refsource_prescaler_config()
182 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
183 CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); in ctc_clock_limit_value_config()
195 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); in ctc_counter_reload_value_config()
196 CTC_CTL1 |= (uint32_t)reload_value; in ctc_counter_reload_value_config()
[all …]
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_ctc.c135 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); in ctc_refsource_polarity_config()
136 CTC_CTL1 |= (uint32_t)polarity; in ctc_refsource_polarity_config()
151 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); in ctc_refsource_signal_select()
152 CTC_CTL1 |= (uint32_t)refs; in ctc_refsource_signal_select()
172 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); in ctc_refsource_prescaler_config()
173 CTC_CTL1 |= (uint32_t)prescaler; in ctc_refsource_prescaler_config()
185 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
186 CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); in ctc_clock_limit_value_config()
198 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); in ctc_counter_reload_value_config()
199 CTC_CTL1 |= (uint32_t)reload_value; in ctc_counter_reload_value_config()
[all …]
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_ctc.c134 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); in ctc_refsource_polarity_config()
135 CTC_CTL1 |= (uint32_t)polarity; in ctc_refsource_polarity_config()
150 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); in ctc_refsource_signal_select()
151 CTC_CTL1 |= (uint32_t)refs; in ctc_refsource_signal_select()
171 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); in ctc_refsource_prescaler_config()
172 CTC_CTL1 |= (uint32_t)prescaler; in ctc_refsource_prescaler_config()
184 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
185 CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); in ctc_clock_limit_value_config()
197 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); in ctc_counter_reload_value_config()
198 CTC_CTL1 |= (uint32_t)reload_value; in ctc_counter_reload_value_config()
[all …]
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_ctc.c65 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); in ctc_refsource_polarity_config()
66 CTC_CTL1 |= (uint32_t)polarity; in ctc_refsource_polarity_config()
81 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); in ctc_refsource_signal_select()
82 CTC_CTL1 |= (uint32_t)refs; in ctc_refsource_signal_select()
102 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); in ctc_refsource_prescaler_config()
103 CTC_CTL1 |= (uint32_t)prescaler; in ctc_refsource_prescaler_config()
115 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
116 CTC_CTL1 |= CTL1_CKLIM(limit_value); in ctc_clock_limit_value_config()
128 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); in ctc_counter_reload_value_config()
129 CTC_CTL1 |= (uint32_t)reload_value; in ctc_counter_reload_value_config()
[all …]
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_ctc.c135 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); in ctc_refsource_polarity_config()
136 CTC_CTL1 |= (uint32_t)polarity; in ctc_refsource_polarity_config()
150 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); in ctc_refsource_signal_select()
151 CTC_CTL1 |= (uint32_t)refs; in ctc_refsource_signal_select()
171 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); in ctc_refsource_prescaler_config()
172 CTC_CTL1 |= (uint32_t)prescaler; in ctc_refsource_prescaler_config()
184 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); in ctc_clock_limit_value_config()
185 CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); in ctc_clock_limit_value_config()
197 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); in ctc_counter_reload_value_config()
198 CTC_CTL1 |= (uint32_t)reload_value; in ctc_counter_reload_value_config()
[all …]
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_ctc.h45 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_ctc.h47 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_ctc.h47 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ macro
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_ctc.h48 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_ctc.h48 #define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ macro
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_ctc.h47 #define CTC_CTL1 REG32(CTC + 0x00000004U) /*!< CTC control register 1 */ macro