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Searched refs:APB2_BUS_BASE (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-latest/gd32a50x/cmsis/gd/gd32a50x/include/
Dgd32a50x.h205 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ macro
222 #define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
223 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
224 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
225 #define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */
226 #define TRIGSEL_BASE (APB2_BUS_BASE + 0x00008400U) /*!< TRIGSEL base address */
227 #define CAN_BASE (APB2_BUS_BASE + 0x0000A000U) /*!< CAN base address */
/hal_gigadevice-latest/gd32vf103/riscv/include/
Dgd32vf103.h202 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address … macro
220 #define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address …
221 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address …
222 #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address …
223 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address …
/hal_gigadevice-latest/gd32f3x0/cmsis/gd/gd32f3x0/include/
Dgd32f3x0.h199 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ macro
215 #define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
216 #define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */
217 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
218 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
/hal_gigadevice-latest/gd32f403/cmsis/gd/gd32f403/include/
Dgd32f403.h205 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address … macro
224 #define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address …
225 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address …
226 #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address …
227 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address …
/hal_gigadevice-latest/gd32e10x/cmsis/gd/gd32e10x/include/
Dgd32e10x.h214 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address … macro
233 #define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address …
234 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address …
235 #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address …
236 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address …
/hal_gigadevice-latest/gd32l23x/cmsis/gd/gd32l23x/include/
Dgd32l23x.h199 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ macro
219 #define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
220 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
221 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
222 #define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */
/hal_gigadevice-latest/gd32f4xx/cmsis/gd/gd32f4xx/include/
Dgd32f4xx.h312 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address … macro
335 #define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address …
336 #define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address …
337 #define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address …
338 #define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address …
339 #define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address …
/hal_gigadevice-latest/gd32e50x/cmsis/gd/gd32e50x/include/
Dgd32e50x.h485 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ macro
507 #define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
508 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
509 #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
510 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
511 #define SHRTIMER_BASE (APB2_BUS_BASE + 0x00007400U) /*!< SHRTIMER base address */
512 #define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */