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Searched refs:APB1_BUS_BASE (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-latest/gd32l23x/cmsis/gd/gd32l23x/include/
Dgd32l23x.h198 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ macro
203 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
204 #define SLCD_BASE (APB1_BUS_BASE + 0x00002400U) /*!< LCD base address */
205 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
206 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
207 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
208 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
209 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
210 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
211 #define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
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/hal_gigadevice-latest/gd32f403/cmsis/gd/gd32f403/include/
Dgd32f403.h204 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address … macro
210 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address …
211 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address …
212 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address …
213 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address …
214 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address …
215 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address …
216 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address …
217 #define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address …
218 #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address …
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/hal_gigadevice-latest/gd32e10x/cmsis/gd/gd32e10x/include/
Dgd32e10x.h213 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address … macro
219 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address …
220 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address …
221 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address …
222 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address …
223 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address …
224 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address …
225 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address …
226 #define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address …
227 #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address …
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/hal_gigadevice-latest/gd32vf103/riscv/include/
Dgd32vf103.h201 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address … macro
207 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address …
208 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address …
209 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address …
210 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address …
211 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address …
212 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address …
213 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address …
214 #define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address …
215 #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address …
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/hal_gigadevice-latest/gd32f3x0/cmsis/gd/gd32f3x0/include/
Dgd32f3x0.h198 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ macro
203 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
204 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
205 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
206 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
207 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
208 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
209 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
210 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
211 #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
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/hal_gigadevice-latest/gd32a50x/cmsis/gd/gd32a50x/include/
Dgd32a50x.h204 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ macro
210 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
211 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
212 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
213 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
214 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
215 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
216 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
217 #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
218 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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/hal_gigadevice-latest/gd32f4xx/cmsis/gd/gd32f4xx/include/
Dgd32f4xx.h311 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address … macro
320 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address …
321 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address …
322 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address …
323 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address …
324 #define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address …
325 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address …
326 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address …
327 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address …
328 #define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address …
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/hal_gigadevice-latest/gd32e50x/cmsis/gd/gd32e50x/include/
Dgd32e50x.h484 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ macro
490 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
491 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
492 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
493 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
494 #define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S_add base address */
495 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
496 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
497 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
498 #define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
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