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Searched refs:AHB1_BUS_BASE (Results 1 – 8 of 8) sorted by relevance

/hal_gigadevice-latest/gd32f4xx/cmsis/gd/gd32f4xx/include/
Dgd32f4xx.h313 #define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address … macro
341 #define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address …
342 #define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address …
343 #define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address …
344 #define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address …
345 #define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address …
346 #define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address …
347 #define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address …
348 #define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address …
349 #define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address …
/hal_gigadevice-latest/gd32f3x0/cmsis/gd/gd32f3x0/include/
Dgd32f3x0.h200 #define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ macro
220 #define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
222 #define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
223 #define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
224 #define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
225 #define TSI_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< TSI base address */
226 #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE0000U) /*!< USBFS base address */
/hal_gigadevice-latest/gd32f403/cmsis/gd/gd32f403/include/
Dgd32f403.h206 #define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address … macro
230 #define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address …
231 #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address …
232 #define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address …
233 #define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address …
234 #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address …
235 #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address …
/hal_gigadevice-latest/gd32a50x/cmsis/gd/gd32a50x/include/
Dgd32a50x.h206 #define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ macro
230 #define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
231 #define DMAMUX_BASE (AHB1_BUS_BASE + 0x00000800U) /*!< DMAMUX base address */
232 #define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
233 #define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
234 #define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
235 #define MFCOM_BASE (AHB1_BUS_BASE + 0x00018400U) /*!< MFCOM base address */
/hal_gigadevice-latest/gd32vf103/riscv/include/
Dgd32vf103.h203 #define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address … macro
226 #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address …
227 #define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address …
228 #define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address …
229 #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address …
230 #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address …
/hal_gigadevice-latest/gd32e10x/cmsis/gd/gd32e10x/include/
Dgd32e10x.h215 #define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address … macro
239 #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address …
240 #define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address …
241 #define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address …
242 #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address …
243 #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address …
/hal_gigadevice-latest/gd32l23x/cmsis/gd/gd32l23x/include/
Dgd32l23x.h200 #define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ macro
224 #define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
226 #define DMAMUX_BASE (AHB1_BUS_BASE + 0x00000800U) /*!< DMA base address */
227 #define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
228 #define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
229 #define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
/hal_gigadevice-latest/gd32e50x/cmsis/gd/gd32e50x/include/
Dgd32e50x.h486 #define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ macro
515 #define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
516 #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
517 #define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
518 #define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
519 #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
520 #define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
521 #define TMU_BASE (AHB1_BUS_BASE + 0x00068000U) /*!< TMU base address */
522 #define USBHS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBHS base address */